A pcie interrupt-based data transmission method and system

Abstract

The application discloses a data transmission method and system based on PCIE interruption, wherein the data transmission method comprises the following steps: when an upper computer respectively receives interruption requests corresponding to different data packets sent by an FPGA, the upper computer performs data carrying operations of the data packets in a data storage unit; the upper computer respectively starts listening operations of A data packet and B data packet; in the listening process, the listening is started from timing listening after receiving the interruption request corresponding to the data packet, and when the interruption request is received within a preset listening duration, the listening duration is emptied, and the listening is reinitiated; when the interruption request is not received within the preset listening duration, the upper computer performs the carrying operation of the corresponding data packet after the timeout, and the listening is reinitiated after the listening duration is emptied. Through the listening of the interruption request corresponding to the data packet, the application can reliably perform data transmission and avoid data packet loss.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method and system based on PCIE interruption. Background Art

[0002] The FPGA (Field Programmable Gate Array) communicates with a host computer using PCIE (Peripheral Component Interconnect Express) technology to transmit data. After writing data to the data storage unit, the FPGA sends an interrupt request to the host computer. Upon receiving the interrupt request, the host computer removes the data from the data storage unit, completing the data transmission. However, in actual operation, the host computer software may not receive the interrupt request sent by the FPGA, resulting in packet loss during transmission. Summary of the Invention

[0003] The purpose of the embodiment of the present invention is to provide a data transmission method based on PCIE interruption, which can reliably transmit data and avoid data packet loss by monitoring the interrupt request of the corresponding data packet.

[0004] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0005] This application relates to a data transmission method based on PCIE interruption, comprising:

[0006] For data packet A and data packet B, when the host computer receives the interrupt request corresponding to different data packets sent by FPGA, it executes the data transfer operation of the corresponding data packet written into the data storage unit under the control of FPGA;

[0007] The host computer starts monitoring data packets A and B respectively;

[0008] During the monitoring process, the monitoring time starts from the time when the interrupt request of the corresponding data packet is received. When the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is restarted.

[0009] If no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time;

[0010] The data transmission includes data writing and data carrying, the FPGA writes the data storage unit in an AB data packet cross mode, the upper computer carries the corresponding data packet in an AB data packet cross mode, and the preset monitoring duration is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

[0011] In some embodiments of the present application, when the upper computer monitors the A data packet and the B data packet, two parallel first monitoring threads and second monitoring threads are triggered to start;

[0012] The first monitoring thread is used to monitor the A data packet, and the second monitoring thread is used to monitor the B data packet.

[0013] In some embodiments of the present application, during the monitoring process, a flag bit flag is set for different data respectively;

[0014] When the upper computer receives an interrupt request of the corresponding data packet, the flag is set to a first flag, and the upper computer performs a carrying operation of the corresponding data packet;

[0015] During the monitoring process, the following is performed:

[0016] S1: judging the flag bit flag, if it is a first flag bit, proceeding to S5, otherwise, proceeding to S2;

[0017] S2: judging whether an interrupt request is received within a preset monitoring duration, if yes, proceeding to S5, if no, proceeding to S3;

[0018] S3: judging whether the monitoring duration reaches the preset monitoring duration, if yes, proceeding to S4, if no, returning to S2;

[0019] S4: setting the flag to a second flag, and the upper computer performs a carrying operation of the corresponding data packet;

[0020] S5: clearing the monitoring duration, reinitiating the monitoring, and returning to S1.

[0021] In some embodiments of the present application, the FPGA controls the A data packet to be written into an A region of the data storage unit, and the B data packet to be written into a B region of the data storage unit;

[0022] The A data packet carried from the A region and the B data packet carried from the B region are cross-synthesized into complete data and stored in a buffer of the upper computer software;

[0023] When the size of the buffer reaches a specified size, the complete data is released from the buffer.

[0024] Compared with the prior art, the PCIE interrupt data transmission method has the following advantages and beneficial effects:

[0025] The host computer respectively listens to the interrupt request of the A data packet and the interrupt request of the B data packet, and judges whether there is a case that the host computer does not receive the interrupt request by whether the interrupt request is received within a preset listening duration, so that even if the interrupt request is not received within the preset listening duration, the data can be normally carried, the data packet loss phenomenon caused by not receiving the interrupt request is avoided, and the reliable transmission of data between the FPGA and the host computer is ensured.

[0026] The application also relates to a PCIE interrupt-based data transmission system, comprising:

[0027] a data acquisition unit for acquiring data;

[0028] an FPGA connected with the data acquisition unit, which outputs an interrupt request corresponding to an A data packet after the FPGA writes the A data packet acquired by the data acquisition unit into a data storage unit, and outputs an interrupt request corresponding to a B data packet after the FPGA writes the B data packet acquired by the data acquisition unit into the data storage unit, wherein the FPGA writes the data storage unit in an AB data packet cross mode;

[0029] a host computer connected with the FPGA through a PCIE bus, which performs a carrying operation of a corresponding data packet when receiving the interrupt request of the corresponding data packet sent by the FPGA, wherein the host computer carries the corresponding data packet in an AB data packet cross mode;

[0030] The host computer also respectively starts a listening operation of the A data packet and the B data packet;

[0031] In the listening process, the listening is started from receiving the interrupt request of the corresponding data packet, and the listening duration is cleared when the interrupt request is received within a preset listening duration, and the listening is reinitiated;

[0032] When the interrupt request is not received within the preset listening duration, the host computer performs the carrying operation of the corresponding data packet after the listening duration is cleared and the listening is reinitiated;

[0033] The preset listening duration is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

[0034] In some embodiments of the application, when the host computer listens to the A data packet and the B data packet, two parallel first listening threads and second listening threads are triggered and started;

[0035] The first monitoring thread is used for monitoring the A data packet, and the second monitoring thread is used for monitoring the B data packet.

[0036] In some embodiments of the application, during the monitoring process, a flag bit flag is set for different data respectively;

[0037] When the host computer receives an interrupt request corresponding to the data packet, the flag is set to a first flag, and the host computer performs a carrying operation on the corresponding data packet;

[0038] During the monitoring process, the following is performed:

[0039] S11: judging the flag bit flag, if it is a first flag bit, proceeding to S15, otherwise, proceeding to S12;

[0040] S12: judging whether an interrupt request is received when the monitoring duration is within a preset monitoring duration, if yes, proceeding to S15, if no, proceeding to S13;

[0041] S13: judging whether the monitoring duration reaches the preset monitoring duration, if yes, proceeding to S14, if no, returning to S12;

[0042] S14: setting the flag to a second flag bit, and the host computer performs a carrying operation on the corresponding data packet;

[0043] S15: clearing the monitoring duration, reinitiating the monitoring, and returning to S1.

[0044] In some embodiments of the application, the host computer further comprises:

[0045] a buffer, the FPGA controls the A data packet to be written into an A region of the data storage unit, and the B data packet to be written into a B region of the data storage unit, and the host computer carries the A data packet from the A region and the B data packet from the B region to cross and synthesize complete data and store the complete data in a buffer of the host computer software;

[0046] When the size of the buffer reaches a specified size, the complete data is released from the buffer.

[0047] Other features and advantages of the present application will become more apparent from the following detailed description of certain embodiments of the application, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described in the following are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0049] Figure 1 A schematic diagram of an embodiment of the PCIE interrupt-based data transmission system according to the present application is shown;

[0050] Figure 2 A schematic diagram of obtaining the time difference between adjacent interrupt requests is shown;

[0051] Figure 3 A flowchart of the host computer listening process in an embodiment of the PCIE interrupt-based data transmission method according to the present application is shown;

[0052] Figure 4 A schematic diagram of the host computer listening process in an embodiment of the PCIE interrupt-based data transmission method according to the present application is shown Figure 1 ;

[0053] Figure 5 A schematic diagram of the host computer listening process in an embodiment of the PCIE interrupt-based data transmission method according to the present application is shown Figure 2 ;

[0054] Figure 6 A flowchart of the A data packet transmission in an embodiment of the PCIE interrupt-based data transmission method according to the present application is shown;

[0055] Figure 7 A schematic diagram of the host computer data integration in an embodiment of the PCIE interrupt-based data transmission method according to the present application is shown.

[0056] Reference signs:

[0057] 100, data acquisition unit; 200, FPGA; 300, host computer; 400, data storage unit. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application.

[0059] Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application. In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0060] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixedly connected, or detachably connected, or integrally connected. For those skilled in the art, the specific meanings of the above terms in the present application can be understood in specific circumstances. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0061] The terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "multiple" is two or more.

[0062] In order to avoid the problem of packet loss caused by the fact that the host computer does not receive the interrupt request sent by the FPGA, the present application relates to a data transmission method based on PCIE interrupt, which, in the data transmission process, introduces a listening process of the interrupt request corresponding to the data packet, so as to ensure that the data in the data storage unit can be obtained when the host computer does not receive the interrupt request, and avoid the occurrence of packet loss.

[0063] Figure 1 A schematic diagram of a data transmission system based on PCIE interrupt is shown.

[0064] The data transmission method based on PCIE interrupt is carried out by using a data transmission system based on PCIE interrupt.

[0065] The data transmission system based on PCIE interrupt includes a data acquisition unit 100, an FPGA 200 and a host computer 300.

[0066] The data acquisition unit 100 is connected through the FPGA 200 by the PCIE bus, the data storage unit 400 can be set on the FPGA 200, or the data storage unit 400 is set independently of the FPGA 200 and connected with the FPGA 200.

[0067] As follows, the data transmission method will be described in combination with the data transmission system, and the specific description is as follows.

[0068] For A data packet and B data packet, the host computer 300 executes the data carrying operation of writing the data corresponding to the data packet in the data storage unit controlled by the FPGA when it receives the interrupt request corresponding to the different data packet sent by the FPGA 200 respectively.

[0069] The data transmission method includes data writing and data carrying.

[0070] The FPGA 200 collects data from the data collection unit 100 and writes the data into the data storage unit 400 in an AB data packet cross manner through a round-robin manner.

[0071] The FPGA 200 is connected with the host computer 300 through a PCIE bus.

[0072] The FPGA 200 writes the A data packet into the A region (for example, the address space is 0x00000000~0x10000000) of the data storage unit 400, and sends an interrupt request (referred to as interrupt request A) of the corresponding A data packet after the A data packet in the A region is written, to inform the host computer 300 to carry the A data packet from the A region.

[0073] The FPGA 200 continues to write the B data packet into the B region (for example, the address space is 0x10000000~0x20000000) of the data storage unit 400, and sends an interrupt request (referred to as interrupt request B) of the corresponding B data packet after the B data packet in the B region is written, to inform the host computer 300 to carry the B data packet from the B region.

[0074] The above-mentioned writing and carrying operations are cyclically executed to realize data transmission.

[0075] Referring to Figure 2 , a schematic diagram of the FPGA 200 sending an interrupt request is shown.

[0076] The FPGA 200 sends the interrupt request A and then sends the interrupt request B after a time interval difference of△t1, and thus the time interval difference between adjacent interrupt requests is recorded as:△t2,△t3,△t4,△t5,△t6 and△t7.

[0077] Referring to Figure 3 , a listening process of the host computer 300 is shown.

[0078] The host computer 300 starts the listening operation of the A data packet and the B data packet respectively.

[0079] The listening operation is started for the A data packet and the B data packet respectively, and the listening operation of the two kinds of data packets is executed in parallel and does not interfere with each other.

[0080] In some embodiments of the present application, a listening thread is triggered for the A data packet and the B data packet respectively, for example, a first listening thread is triggered for the A data packet, and a second listening thread is triggered for the B data packet, and the first listening thread and the second listening thread are executed in parallel.

[0081] In some embodiments of the present application, before the listening, a preset listening duration is set in advance, which is 2 times of the maximum time difference between the normal sending of the interrupt request A and the interrupt request B by the FPGA 200.

[0082] Referring to Figure 2 , Figure 4 and Figure 5 , the FPGA 200 sends the interrupt request A and the interrupt request B in cross, and selects the maximum time difference AtMax by recording the time difference between each two adjacent interrupt requests.

[0083] In the time period 2*AtMax from the receipt of the interrupt request A or B, the FPGA 200 will definitely send the interrupt request A or B, and as to whether the host computer 300 receives it, it is determined by the judgment, and when it is determined that the host computer 300 does not receive the interrupt request A or B, the host computer 300 should also handle the data when the time period 2*AtMax of the cyclic listening is reached, otherwise it will cause the phenomenon of packet loss of the host computer 300 due to the failure to receive the interrupt request.

[0084] In some embodiments of the present application, referring to Figure 3 , in the listening process of the A data packet, the listening is started from the receipt of the interrupt request A of the A data packet, and when the interrupt request A is received within the preset listening duration, the listening duration is cleared and the listening is re-initiated.

[0085] Referring to Figure 4 , the listening is started from the first interrupt request A on the left, and the second interrupt request A is received within 2*AtMax, which indicates that the host computer 300 will normally handle the data, at this time, the listening duration is cleared and the listening is re-initiated, that is, the time period 2*AtMax of the second cyclic listening is started.

[0086] Referring to Figure 5 , the listening is started from the first interrupt request A on the left, and the second interrupt request A is not received within 2*AtMax (that is, the interrupt request A shown by the dashed arrow in the middle Figure 4 ), when the time reaches 2*AtMax, the host computer 300 performs the handling operation of the A data packet (that is, the A data packet corresponding to the A area at this time will be handled), and the listening is re-initiated after the listening duration is cleared, that is, the time period 2*AtMax of the second cyclic listening is started.

[0087] Similarly, in the listening process of the B data packet, the listening is also started from the receipt of the interrupt request B of the B data packet, and when the interrupt request B is received within the preset listening duration, the listening duration is cleared and the listening is re-initiated.

[0088] If the interrupt request B is not received within the preset monitoring time, the host computer 300 performs the transport operation of the B data packet after timeout, and re-initiates monitoring after clearing the monitoring time.

[0089] In some embodiments of the present application, a monitoring timer may be started to obtain the monitoring duration, and clearing the monitoring duration means restarting the monitoring timer.

[0090] In some embodiments of the present application, in order to better monitor the interrupt request, flags are set corresponding to the A data packet and the B data packet respectively.

[0091] The data transmission processes of data packet A and data packet B are similar, so the data transmission process of data packet A is taken as an example for description.

[0092] When host computer 300 receives interrupt request A for data packet A, the flag at the listening point corresponding to interrupt request A is set to the first flag (e.g., the first flag is 1), and simultaneously, host computer 300 performs the corresponding data packet transfer operation. In other words, as long as host computer 300 receives an interrupt request, the flag at the listening point corresponding to the interrupt request is set to 1, and the corresponding data packet transfer operation is performed simultaneously.

[0093] See also Figure 6 , which shows that the host computer 300 performs the monitoring process of the A data packet, which is described in detail as follows.

[0094] S1: Determine the flag bit flag. If it is the first flag bit, proceed to S5; otherwise, proceed to S2.

[0095] As described above, during the monitoring process of the upper computer 300, if the upper computer 300 receives the interrupt request normally, the flag of the monitoring point position is 1. At this time, corresponding to the data transmission process, the upper computer 300 will normally perform the data transfer operation, and for the monitoring process, enter S5 to clear the monitoring time and re-initiate monitoring, that is, restart the monitoring timer and continue to monitor.

[0096] See also Figure 4 When the first interrupt request A on the far left is received by the host computer 300, the flag at the corresponding position is 1. In the corresponding data transmission process, the host computer 300 performs the data transfer operation. For the monitoring process, the monitoring time is cleared and the monitoring is re-initiated, that is, the first cycle monitoring time period 2*△tMax is started; when the second interrupt request A is received by the host computer 300, the flag at the corresponding position is 1. In the corresponding data transmission process, the host computer 300 performs the data transfer operation. For the monitoring process, the monitoring time is cleared and the monitoring is re-initiated, that is, the second cycle monitoring time period 2*△tMax is started.

[0097] If the flag is not the first flag, it means that the host computer 300 has not received the interrupt request A.

[0098] S2: Determine whether the interrupt request A is received within the preset listening duration. If yes, go to S5. If no, go to S3.

[0099] Referring to Figure 4 , when listening to the A data packet, after the first interrupt request A is listened to, the listening timer starts. When the second interrupt request A is listened to within the preset listening duration 2*△tMax, it means that the second interrupt request A is normally sent and received by the host computer 300 during the preset listening duration 2*△tMax. Thus, the data in this part will be normally carried by the host computer 300.

[0100] Corresponding to the first listening thread, the listening timer is restarted, and the preset listening duration is continuously maintained. That is, referring to Figure 4 , the second cycle listening time period 2*△tMax is started.

[0101] If the interrupt request A is not received within the preset listening duration, it means that the host computer 300 has not received the interrupt request A.

[0102] S3: Determine whether the listening duration reaches the preset listening duration. If yes, go to S4. If no, return to S2.

[0103] When the listening duration reaches the preset listening duration and no interrupt request A is received, it means that there is indeed a situation that the interrupt request A is not received by the host computer 300 during the preset listening duration. For example, referring to Figure 5 , when the listening duration reaches the first cycle listening time period 2*△tMax, the second interrupt request A shown by the dashed line is still not received Figure 5 . At this time, the packet is not avoided to be lost. The host computer 300 performs the carrying operation of the corresponding data packet after the timeout, and the flag is set to 0 to facilitate continuous listening. Then the listening timer is restarted, and the preset listening duration is continuously maintained. That is, referring to Figure 5 , the second cycle listening time period 2*△tMax is started.

[0104] When the listening duration has not reached the preset listening duration and no interrupt request A is received, it means that there may still be a situation that the interrupt request A is received during the preset listening duration. Therefore, it is returned to continue to determine whether the interrupt request A is received within the preset listening duration.

[0105] S4: The flag is set to the second flag, and the host computer 300 performs the carrying operation of the corresponding data packet.

[0106] When the interrupt request A is not monitored within the preset monitoring duration and the monitoring duration reaches the preset monitoring duration, at this time, the flag corresponding to the data monitoring point position where the monitoring duration reaches the preset monitoring duration is set as the second flag (for example, the second flag is 0), that is, the flag is set as the second flag.

[0107] Meanwhile, for the data transmission process, the host computer performs the carrying operation on the A data packet, so as to avoid the packet loss of the host computer 300 when the interrupt request A is not received.

[0108] S5: clear the monitoring duration, re-initiate monitoring, and return to S1.

[0109] In some embodiments of the present application, when the host computer 300 normally receives the interrupt request A (for example, see Figure 4 , when the first interrupt request A on the left is received), the monitoring timer is restarted, and the monitoring of the preset monitoring duration is continued.

[0110] In some embodiments of the present application, when the host computer 300 receives the interrupt request A within the preset monitoring duration (for example, see Figure 4 , when the second interrupt request A on the left is received), it indicates that the interrupt request A is also normally received during the preset monitoring duration, the monitoring timer is restarted, and the monitoring of the preset monitoring duration is continued.

[0111] In some embodiments of the present application, when the host computer 300 does not receive the interrupt request A within the preset monitoring duration and the time reaches the preset monitoring duration (for example, see Figure 5 , when the second interrupt request A shown by the dashed line is not received), at this time, the monitoring timer is restarted, and the monitoring of the preset monitoring duration is continued.

[0112] In some embodiments of the present application, since the FPGA 200 writes in the AB data packet cross manner, the host computer 300 also carries in the AB data packet cross manner, that is, the host computer 300 carries the A data packet, then carries the B data packet, and then carries the A data packet, and so on, until the reading is completed, and the ABAB... complete data in the AB data packet cross manner is formed, see Figure 7 .

[0113] In some embodiments of the present application, a buffer (not shown) is opened in the software of the host computer 300, and the data carried by the host computer 300 is placed in the buffer, and when the size of the buffer reaches the specified size, the data in the buffer is released.

[0114] The data transmission method disclosed by the application avoids the phenomenon that the host computer 300 cannot receive the interrupt request and packet loss by increasing interrupt monitoring on the basis of PCIE interrupt, and avoids data mutual adoption by monitoring A data packet and B data packet respectively.

[0115] The above examples are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing examples, the technical solutions recorded in the foregoing examples can still be modified or some technical features can be replaced by equivalents for ordinary skilled in the art; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions claimed by the present application.

Claims

1. A data transmission method based on PCIE interruption, characterized in that: include: For data packet A and data packet B, when the host computer receives the interrupt request corresponding to different data packets sent by FPGA, it executes the data transfer operation of the corresponding data packet in the data storage unit; The host computer triggers and starts a first listening thread for monitoring data packet A and a second listening thread for monitoring data packet B, respectively, wherein the first listening thread and the second listening thread are parallel; During the monitoring process, the monitoring time starts from the time when the interrupt request of the corresponding data packet is received. When the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is restarted. If no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; Among them, data transmission includes data writing and data transportation. The FPGA uses AB data packet cross-mode to write into the data storage unit, and the host computer uses AB data packet cross-mode to transport the corresponding data packet. The preset monitoring time is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

2. The data transmission method according to claim 1, wherein: During the monitoring process, flags are set for different data respectively; When the host computer receives the interrupt request of the corresponding data packet, the flag is set to the first flag, and the host computer performs the transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S1: Check the flag bit flag. If it is the first flag bit, go to S5. Otherwise, go to S2. S2: Determine whether an interrupt request is received within the preset monitoring time. If so, proceed to S5; if not, proceed to S3; S3: Determine whether the monitoring time reaches the preset monitoring time. If so, proceed to S4; if not, return to S2; S4: The flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S5: Clear the monitoring time, restart monitoring, and return to S1.

3. The data transmission method according to claim 1, wherein: The FPGA controls the writing of data packet A into area A of the data storage unit, and the writing of data packet B into area B of the data storage unit; The host computer combines the data packets A from area A and B from area B into complete data and stores them in the buffer of the host computer software. When the size of the buffer reaches a specified size, the complete data is released from the buffer.

4. A data transmission system based on PCIE interruption, characterized in that: include: A data acquisition unit, which is used to collect data; an FPGA connected to a data acquisition unit, configured to output an interrupt request corresponding to the A data packet after the FPGA writes the A data packet collected by the data acquisition unit into the data storage unit, and to output an interrupt request corresponding to the B data packet after the FPGA writes the B data packet collected by the data acquisition unit into the data storage unit, wherein the FPGA writes the A data packet into the data storage unit in an A-B data packet interleaving manner; A host computer is connected to the FPGA via a PCIE bus. When receiving an interrupt request for a corresponding data packet sent by the FPGA, the host computer performs a transport operation for the corresponding data packet. The host computer transports the corresponding data packet in an AB data packet crossover manner. The host computer also triggers and starts a first listening thread for monitoring data packet A and a second listening thread for monitoring data packet B, wherein the first listening thread and the second listening thread are parallel; During the monitoring process, the monitoring time starts from the time when the interrupt request of the corresponding data packet is received. When the interrupt request is received within the preset monitoring time, the monitoring time is cleared and the monitoring is restarted. If no interrupt request is received within the preset monitoring time, the host computer performs the corresponding data packet transfer operation after timeout, and re-initiates monitoring after clearing the monitoring time; The preset monitoring duration is twice the maximum time difference between adjacent interrupt requests normally sent by the FPGA.

5. The data transmission system according to claim 4, characterized in that During the monitoring process, flags are set for different data respectively; When the host computer receives the interrupt request of the corresponding data packet, the flag is set to the first flag, and the host computer performs the transport operation of the corresponding data packet; During the monitoring process, proceed as follows: S11: Determine the flag bit flag. If it is the first flag bit, proceed to S15; otherwise, proceed to S12. S12: Determine whether an interrupt request is received when the monitoring time is within the preset monitoring time. If so, proceed to S15; if not, proceed to S13; S13: Determine whether the monitoring time reaches the preset monitoring time. If so, proceed to S14; if not, return to S12; S14: The flag is set to the second flag bit, and the host computer performs the corresponding data packet transfer operation; S15: Clear the monitoring time, restart monitoring, and return to S1.

6. The data transmission system according to claim 4, characterized in that The host computer also includes: Buffer, FPGA controls the writing of data packet A into area A of the data storage unit, and data packet B into area B of the data storage unit. The A data packet carried from area A and the B data packet carried from area B by the host computer are cross-synthesized into complete data and stored in the buffer of the host computer software; When the size of the buffer reaches a specified size, the complete data is released from the buffer.

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