Compatible communication system and method and medium

Abstract

The invention discloses a compatible communication system and method and a medium, and the communication system comprises an IO interface module, an IO control module, an oversampling module, a first clock signal is subjected to 90-degree phase shift at a high transmission rate to form a second clock signal, sampling the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal respectively, and delaying the differential positive signal end or the differential negative signal end by 45 degrees; and the USB controller is based on a USB2.0 protocol and is used for data processing. According to the invention, three transmission rates of HS, FS and LS are realized, signals at a DP end and a DN end are delayed while phase shift processing is carried out on clock signals, quadruplicated frequency sampling at the HS transmission rate is realized, and the signal quality is effectively improved; an external PHY chip is not needed, the use cost is effectively reduced, the PHY chip is prevented from additionally occupying the space, the size of the USB equipment is reduced, and meanwhile the compatibility of the USB equipment can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of USB communication, and in particular relates to a compatible communication system, method and medium. Background Art

[0002] In the field of communication, USB2.0 (Universal Serial Bus 2.0) is an interface standard widely used between computers and electronic devices. It supports high-speed data transmission with a maximum transmission speed of up to 480Mbps. The USB2.0 interface is backward compatible and can be connected to earlier USB1.1 devices and transmit at a lower speed. In addition, USB2.0 also supports hot-swap function, allowing users to plug or unplug devices without turning off the power, providing a convenient connection and usage experience. Although USB3.0 and newer USB standards provide higher transmission speeds and better performance, USB2.0 still has a place in the market due to its wide compatibility and mature ecosystem. Many industrial-grade customers and consumer devices still use USB2.0 interfaces, especially in situations where high-speed data transmission is not particularly required.

[0003] FPGA chips have the characteristics of fast processing speed and flexible functions. They have great advantages in high-speed data acquisition and data transmission. Many data acquisition devices use FPGA as processor chips, but FPGA chips do not have their own USB2.0 data interface. In order to realize USB2.0 communication on devices using FPGA, it is necessary to use external physical layer chips, namely PHY chips, such as CYPRESS's CY7C68013A or FTDI's FT232 chips. These external PHY chips have a large number of IOs, and in addition to data IOs, there are many control IOs, so there are certain IO quantity requirements for FPGAs; at the same time, external PHY chips also increase costs. In addition, since the external PHY chip has a large number of IOs and a large size, for small USB devices, such as small camera systems, the external PHY will occupy additional camera size.

[0004] Chinese patent CN116418889A discloses a USB3.0 data transmission system and method based on FPGA. However, for USB devices, it is necessary to communicate with the computer system. For some earlier industrial computer systems, there are interfaces that only support USB2.0 but not USB3.0. Therefore, implementing USB2.0 can increase the compatibility of USB devices; at the same time, it can reduce costs and reduce the size of USB devices.

[0005] Therefore, in order to solve the above problems, the present invention provides a compatible communication system, method and medium. Summary of the invention

[0006] The purpose of the present invention is to overcome the above problems existing in the prior art and to provide a compatible communication system, method and medium.

[0007] In order to achieve the above technical objectives and the above technical effects, the present invention is implemented through the following technical solutions: A compatible communication system, comprising: The IO interface module includes a pull-up adjustment unit, a first data transceiver unit, and a second data transceiver unit, wherein the pull-up adjustment unit is used to adjust the pull-up resistance of the differential positive signal end and the differential negative signal end, the first data transceiver unit is used to transmit and receive high-speed data, and the second data transceiver unit is used to transmit and receive full-speed data or low-speed data; The IO control module includes a first communication mode and a second communication mode; the first communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the first data transceiver unit to transmit and receive high-speed data; the second communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the second data transceiver unit to transmit and receive full-speed data or low-speed data; An oversampling module, connected to the IO control module, for sampling and processing the data signal in the first communication mode or the second communication mode: for the first communication mode, for performing a 90° phase shift on the first clock signal to form a second clock signal, and for sampling the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal, respectively, and for delaying the differential positive signal end or the differential negative signal end by 45°; for the second communication mode, for sampling the differential positive signal end and the differential negative signal end based on the first clock signal; The USB controller is based on the USB2.0 protocol and is connected to the oversampling module and the IO control module for data processing.

[0008] Further, the pull-up adjustment unit includes: A differential positive signal pull-up interface, connected to the differential positive signal terminal through a first pull-up resistor, and used to adjust the pull-up resistor of the differential positive signal terminal; The differential negative signal pull-up interface is connected to the differential negative signal terminal through a second pull-up resistor and is used to adjust the pull-up resistor of the differential negative signal terminal.

[0009] Furthermore, the first data transceiver unit includes: A high-speed data receiving interface, connected to the differential positive signal terminal and the differential negative signal terminal respectively, for receiving high-speed data in the first communication mode; The high-speed data transmission interface is connected to the differential positive signal terminal and the differential negative signal terminal respectively, and is used for transmitting high-speed data in the first communication mode.

[0010] Furthermore, the second data transceiver unit includes: A first data transceiver interface, connected to the differential positive signal end, and used for transmitting and receiving full-speed data or low-speed data of the differential positive signal end in a second communication mode; The second data transceiver interface is connected to the differential negative signal end and is used to transmit and receive full-speed data or low-speed data of the differential negative signal end in the second communication mode.

[0011] Furthermore, it also includes: The NRZI decoding module is used for performing NRZI decoding on the sampled data from the oversampling module and sending the data to the USB controller; The NRZI encoding module is used to perform NRZI encoding on the data from the USB controller and send it to the IO control module.

[0012] Furthermore, it also includes a serial-to-parallel conversion module, which is used to perform 1:8 serial-to-parallel conversion on the sampled data from the oversampling module and send it to the NRZI decoding module.

[0013] Furthermore, it also includes a parallel-serial conversion module for performing 8:1 parallel-serial conversion on the data from the NRZI encoding module and sending the data to the IO control module.

[0014] Furthermore, the USB controller is also connected to an FPGA user interface.

[0015] The present invention also provides a compatibility communication method, comprising: The IO control module controls the IO interface module to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal to realize the first communication mode and the second communication mode; wherein, in the first communication mode, the first data transceiver unit is selected to transmit and receive high-speed data, and in the second communication mode, the second data transceiver unit is selected to transmit and receive full-speed data or low-speed data; In the first communication mode, the oversampling module performs a 90° phase shift on the first clock signal to form a second clock signal, and samples the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal, respectively, and delays the differential positive signal end or the differential negative signal end by 45°; In the second communication mode, the oversampling module samples the differential positive signal end and the differential negative signal end based on the first clock signal; The USB controller processes the sampling result from the oversampling module based on the USB2.0 protocol and feeds it back to the IO control module.

[0016] The present invention also provides a computer-readable storage medium, comprising a computer program, wherein the computer program implements the above communication method when executed by a processor.

[0017] The beneficial effects of the present invention are: (1) The present invention solves the problem of a large number of IOs in a traditional external PHY chip through an IO interface module. The present invention establishes data transmission with the DP terminal and the DN terminal of the USB bus through a pull-up adjustment unit, a first data transceiver unit, and a second data transceiver unit. Combined with the pull-up resistor adjustment control of the IO control module, three transmission rates of HS, FS, and LS are achieved. Under the premise of meeting the three transmission rates, the number of IOs is reduced, thereby reducing the IO requirements of the FPGA.

[0018] (2) The present invention delays the DP and DN signals while performing phase shifting processing on the clock signal, and finally samples the DP and DN signals respectively based on the two clock signals, thereby realizing sampling of four different phase relationships, that is, realizing quadruple frequency sampling at the HS transmission rate, and effectively improving the signal quality.

[0019] (3) The present invention realizes USB2.0 communication based on FPGA without the need for an external PHY chip, effectively reducing the cost of use, avoiding the extra space occupied by the PHY chip, and reducing the size of the USB device. At the same time, since no additional design and layout of the PHY chip is required, it helps to shorten the development cycle of the USB device.

[0020] (4) The present invention is based on the USB2.0 protocol, which is different from the USB3.0 design logic and can increase the compatibility of USB devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings: Figure 1 It is a system structure block diagram of the present invention; Figure 2 is a schematic diagram of oversampling in the present invention; Figure 3 It is a schematic diagram of NRZI encoding in the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] like Figure 1 As shown, this embodiment first provides a compatibility communication system, including: The IO interface module includes a pull-up adjustment unit, a first data transceiver unit and a second data transceiver unit. The pull-up adjustment unit is used to adjust the pull-up resistance of the differential positive signal end and the differential negative signal end. The first data transceiver unit is used to transmit and receive high-speed data, and the second data transceiver unit is used to transmit and receive full-speed data or low-speed data.

[0024] Since the USB2.0 interface supports three transmission rates: HS (High Speed, 480Mbps), FS (Full Speed, 12Mbps) and LS (Low Speed, 1.5Mbps), and uses half-duplex DP and DN data lines, the transmission level standard is different for each rate. Therefore, for FPGA, the following 6 groups of IO interfaces are used to receive and process USB2.0 DP and DN signals, as follows: As a specific implementation of the pull-up adjustment unit, its structure includes: The differential positive signal pull-up interface, namely the USB2_DP_PULLUP IO interface, is connected to the differential positive signal terminal, namely the DP terminal, through a first pull-up resistor, and is used to adjust the pull-up resistor of the differential positive signal terminal.

[0025] The differential negative signal pull-up interface, namely the USB2_DN_PULLUP IO interface, is connected to the differential negative signal terminal, namely the DN terminal, through the second pull-up resistor, and is used to adjust the pull-up resistor of the differential negative signal terminal.

[0026] Among them, the two IO interfaces USB2_DP_PULLUP and USB2_DN_PULLUP both use LVCMOS33 level, and the first pull-up resistor and the second pull-up resistor are 1.5KΩ resistors. When the computer communicates with the USB, it judges the device speed through the pull-up resistor on DP or DN. When USB2_DP_PULLUP is pulled up, the USB is HS (High Speed, 480Mbps) / FS (HighSpeed, 12Mbps), which can be judged by Chirp K signal and Chirp J signal. When USB2_DN_PULLUP is pulled up, the USB is LS (Low Speed, 1.5Mbps).

[0027] Chirp K signal and Chirp J signal are special signal states used for speed detection handshake when high-speed devices are connected to the USB host. These signal states are driven by current, and they form a specific voltage difference on the DP and DN data lines to facilitate the host to identify the speed capability of the device. In high-speed mode, when the device is ready to switch from full-speed mode to high-speed mode, it will generate a Chirp K signal on the DN line. The characteristic of this signal is that the voltage of the DP line is lower than the voltage of the DN line by a certain voltage value (usually 360mV). In contrast to the Chirp K signal, the Chirp J signal is generated on the D+ line, and its characteristic is that the voltage of the DP line is higher than the voltage of the DN line by a certain voltage value.

[0028] When a high-speed device is connected to a USB host, it first appears as a full-speed device and generates the SE0 signal during the reset process. After the reset is complete, the device will try to inform the host that it supports high-speed mode by sending a Chirp K signal; the host detects the device's Chirp K signal and responds with a series of Chirp K and Chirp J signal sequences to confirm the device's high-speed capability; after detecting the correct Chirp signal sequence, the device enters the high-speed preset state and completes the speed detection handshake process.

[0029] As a specific implementation of the first data transceiver unit, its structure includes: The high-speed data receiving interface, namely the USB2_HS_INPUT IO interface, is respectively connected to the differential positive signal terminal, namely the DP terminal, and the differential negative signal terminal, namely the DN terminal, for receiving high-speed data at the HS transmission rate; The high-speed data transmission interface, namely the USB2_HS_OUTPUT IO interface, is respectively connected to the differential positive signal terminal and the differential negative signal terminal, and is used for transmitting high-speed data at the HS transmission rate.

[0030] When the USB is at HS transmission rate, DP and DN are differential signals, so FPGA differential BUFFER is needed for data reception and transmission. However, for FPGA differential BUFFER, usually one differential BUFFER only supports reception or transmission, so two sets of differential BUFFERs USB2_HS_INPUT and USB2_HS_OUTPUT are used to realize high-speed data reception and transmission at HS transmission rate respectively.

[0031] As a specific implementation of the second data transceiver unit, its structure includes: The first data transceiver interface, namely USB2_FS / LS_DP_IO, is connected to the differential positive signal end and is used to transmit and receive full-speed data or low-speed data of the differential positive signal end at the FS / LS transmission rate; The second data transceiver interface, namely USB2_FS / LS_DN_IO, is connected to the differential negative signal end and is used for transmitting and receiving full-speed data or low-speed data of the differential negative signal end at the FS / LS transmission rate.

[0032] When the USB is at FS or LS transmission rate, for HS and LS data channels, the data is single-ended LVCMOS33 level, so two FPGA IO interfaces USB2_FS / LS_DN_IO and USB2_FS / LS_DP_IO are used to send and receive FS / LS data channels. FPGA single-ended supports receiving and sending data at the same time, so using one IO for DN and DP can realize data reception and transmission.

[0033] The IO control module includes a first communication mode and a second communication mode; the first communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the first data transceiver unit to transmit and receive high-speed data; the second communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the second data transceiver unit to transmit and receive full-speed data or low-speed data.

[0034] The first communication mode corresponds to the HS transmission rate, and the second communication mode corresponds to the FS / LS transmission rate.

[0035] The IO control module is mainly responsible for controlling the 6 groups of IO interfaces in the USB2.0 IO part, controlling the pull-up and pull-down resistors, and using the IO interface of the corresponding speed according to the speed selection. The pull-up resistor tells the computer that the USB device supports HS / FS / LS transmission rates, and sends and receives data at FS / LS transmission rates through USB2_FS / LS_DN_IO and USB2_FS / LS_DP_IO; and sends and receives data at HS transmission rates through USB2_HS_OUTPUT and USB2_HS_INPUT.

[0036] The oversampling module is connected to the IO control module and is used to sample and process the data signal in the first communication mode or the second communication mode: for the first communication mode, it is used to shift the first clock signal by 90° to form a second clock signal, and sample the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal respectively, and delay the differential positive signal end or the differential negative signal end by 45°; for the second communication mode, sample the differential positive signal end and the differential negative signal end based on the first clock signal.

[0037] For the data receiving end, the data signal received from the IO interface module first enters the oversampling module for data recovery. Usually, data recovery uses CDR technology, but this technology requires the use of devices such as VCO, which increases the complexity of the system. Therefore, in implementation, oversampling technology is used for data recovery.

[0038] For the second communication mode, that is, corresponding to the LS and FS transmission rates, the maximum rate is 12Mbps. The signals at the DN and DP ends can be oversampled directly through USB2_FS / LS_DN_IO and USB2_FS / LS_DP_IO, and then the sampling point at the data center is selected as the final sampling data.

[0039] For the first communication mode, that is, corresponding to the HS transmission rate, the rate is 480Mbps. If quadruple frequency is used, the clock needs to reach 960MHz, but usually FPGA cannot reach this rate, so it is impossible to directly use the multiplied clock for oversampling. Therefore, it is necessary to process the data before oversampling, such as Figure 2 As shown, first of all, for the differential buffer, there are two signals at the DP end and the DN end, and the phase difference is 180°, corresponding to DATA_DP and DATA_DN in the figure respectively. The result of four times oversampling is shown in DATA in the figure. In order to achieve oversampling, the DP / DN end signal is first delayed by 45 degrees, and then the DP / DN end data is sampled by the first clock signal CLK and the second clock signal CLK90 respectively. CLK90 is a clock of the same frequency generated by a 90° phase shift relative to CLK. By sampling the signals at the DP end and the DN end, the sampling of four phase relationships of 0°, 45°, 90° and 135° of a data is achieved within one clock cycle, and the clock used for sampling is 240MHz (equivalent to half of 480Mbps), thereby achieving four times oversampling of the data. For the sampled data, the sampling point closest to the data center can be selected as the final sampling data according to the sampled data jump result. Four times oversampling provides strong support for high-speed data transmission and precision measurement by improving signal quality and system performance.

[0040] CLK90 can be generated by using a clock management integrated circuit (IC) such as a phase-locked loop (PLL) or a digital delay-locked loop (DLL), so that multiple phase-shifted clock signals can be generated from a reference clock. The phase-locked loop (PLL) can generate a clock output with a 90-degree phase difference by adjusting the frequency divider or using an additional phase modulator, and the delay-locked loop (DLL) can align the input and output clock signals through a series of adjustable delay units to produce an output with a fixed phase offset. PLLs generally provide a wider frequency range and better locking performance, while DLLs may have advantages in terms of implementation simplicity and power consumption. PLLs and DLLs can also be used in combination to optimize performance.

[0041] The USB controller is based on the USB2.0 protocol and is connected to the oversampling module and the IO control module for data processing.

[0042] The USB controller is a USB 2.0 controller, and its main responsibility is to handle tasks related to the USB protocol, including the assembly and decomposition of data packets, the management of the protocol engine, and the communication with the host system. The USB controller implements these functions through an internal state machine and protocol stack to ensure that data can be correctly transmitted between the host and the peripheral according to the provisions of the USB protocol.

[0043] At the same time, the USB controller is also connected to the FPGA user interface for implementing endpoint definition and endpoint reading and writing.

[0044] Endpoint definition is to set the properties of the communication endpoint according to the requirements of USB2.0 protocol during the initialization of USB device. These properties include endpoint type (control, interrupt, bulk transfer or isochronous transfer), endpoint direction (input or output) and buffer size.

[0045] Endpoint reading and writing is the actual data exchange process after the endpoint definition is completed. Data can be transmitted through different transmission types such as control, interrupt, bulk transfer or isochronous transfer. In FPGA, endpoint reading and writing usually involves serialization and deserialization of data, as well as the processing of clock domain crossing. The logic design inside the FPGA is used to process the data packet format specified by the USB2.0 protocol and ensure that the data is sent or received at the correct time point. For example, the slave FIFO method can be used to achieve fast data reading and writing to improve data transmission efficiency.

[0046] Since USB2.0 data adopts NRZI encoding, the over-sampled data needs to be decoded. Specifically, the sampled data from the over-sampling module is NRZI-decoded by the NRZI decoding module and sent to the USB controller.

[0047] The NRZI encoding method of USB2.0 is as follows Figure 3As shown, for oversampled data, the NRZI data at two adjacent moments is judged, and the level flip represents logic 0, and the level unchanged represents logic 1. At the same time, because USB2.0 will force data 0 to be inserted during data transmission, that is, if there are 6 consecutive 1s in the data to be transmitted, a 0 will be forced to be inserted after the 6th 1 before sending, so that the transmitted signal is forced to flip. Therefore, in decoding, delete the 0 after 6 consecutive 1s.

[0048] For the USB transmitter, the data from the USB controller is NRZI-encoded by the NRZI encoding module and sent to the IO control module.

[0049] Encoding method such as Figure 3 As shown in the figure, data 0 is encoded as a level flip, while data 1 remains unchanged. If 6 consecutive 1s are encountered, a 0 is inserted after the 6th 1.

[0050] For the sampling points obtained by oversampling, the sampling data from the oversampling module can also be converted into 1:8 serial-to-parallel through the serial-to-parallel conversion module and sent to the NRZI decoding module.

[0051] For the NRZI-encoded data, the parallel-serial conversion module can also perform 8:1 parallel-to-serial conversion on the data from the NRZI encoding module and send it to the IO control module. The serialized data is transmitted to the USB bus through the IO control module.

[0052] A second aspect of the present invention further provides a compatibility communication method, comprising: The IO control module controls the IO interface module to adjust the pull-up resistors of the differential positive signal end and the differential negative signal end to realize the first communication mode and the second communication mode; wherein, in the first communication mode, the first data transceiver unit is selected to transmit and receive high-speed data, and in the second communication mode, the second data transceiver unit is selected to transmit and receive full-speed data or low-speed data.

[0053] In the first communication mode, the oversampling module performs a 90° phase shift on the first clock signal to form a second clock signal, and samples the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal, respectively, and delays the differential positive signal end or the differential negative signal end by 45°.

[0054] In the second communication mode, the oversampling module samples the differential positive signal terminal and the differential negative signal terminal based on the first clock signal.

[0055] The USB controller processes the sampling result from the oversampling module based on the USB2.0 protocol and feeds it back to the IO control module.

[0056] In order to further improve the system performance, the communication method also includes a NRZI decoding module, a NRZI encoding module, a serial-to-parallel conversion module, and a specific processing process of the parallel-to-serial conversion module, wherein: The serial-to-parallel conversion module performs 1:8 serial-to-parallel conversion on the sampled data from the oversampling module and sends it to the NRZI decoding module; the NRZI decoding module performs NRZI decoding on the data from the serial-to-parallel conversion module and sends it to the USB controller; the NRZI encoding module is used to perform NRZI encoding on the data from the USB controller and send it to the parallel-to-serial conversion module; the parallel-to-serial conversion module performs 8:1 parallel-to-serial conversion on the data from the NRZI encoding module and sends it to the IO control module.

[0057] A third aspect of the present invention further provides a computer-readable storage medium, comprising a computer program, wherein the computer program implements the above communication method when executed by a processor.

[0058] In practical applications, the computer-readable storage medium may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device.

[0059] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, which carry computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0060] The program code embodied on the computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0061] Computer program code for performing the operation of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0062] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0063] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, and these changes and improvements all fall within the scope of the present invention to be protected.

Claims

1. A compatible communication system, characterized in that: include: The IO interface module includes a pull-up adjustment unit, a first data transceiver unit, and a second data transceiver unit, wherein the pull-up adjustment unit is used to adjust the pull-up resistance of the differential positive signal end and the differential negative signal end, the first data transceiver unit is used to transmit and receive high-speed data, and the second data transceiver unit is used to transmit and receive full-speed data or low-speed data; The IO control module includes a first communication mode and a second communication mode; the first communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the first data transceiver unit to transmit and receive high-speed data; the second communication mode is used to control the pull-up adjustment unit to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal, and select the second data transceiver unit to transmit and receive full-speed data or low-speed data; An oversampling module, connected to the IO control module, for sampling and processing the data signal in the first communication mode or the second communication mode: for the first communication mode, for performing a 90° phase shift on the first clock signal to form a second clock signal, and for sampling the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal, respectively, and for delaying the differential positive signal end or the differential negative signal end by 45°; for the second communication mode, for sampling the differential positive signal end and the differential negative signal end based on the first clock signal; The USB controller is based on the USB2.0 protocol and is connected to the oversampling module and the IO control module for data processing.

2. A compatible communication system according to claim 1, characterized in that: The pull-up adjustment unit includes: A differential positive signal pull-up interface, connected to the differential positive signal terminal through a first pull-up resistor, and used to adjust the pull-up resistor of the differential positive signal terminal; The differential negative signal pull-up interface is connected to the differential negative signal terminal through a second pull-up resistor and is used to adjust the pull-up resistor of the differential negative signal terminal.

3. A compatible communication system according to claim 2, characterized in that: The first data transceiver unit includes: A high-speed data receiving interface, connected to the differential positive signal terminal and the differential negative signal terminal respectively, for receiving high-speed data in the first communication mode; The high-speed data transmission interface is connected to the differential positive signal terminal and the differential negative signal terminal respectively, and is used for transmitting high-speed data in the first communication mode.

4. A compatible communication system according to claim 3, characterized in that: The second data transceiver unit includes: A first data transceiver interface, connected to the differential positive signal end, and used for transmitting and receiving full-speed data or low-speed data of the differential positive signal end in a second communication mode; The second data transceiver interface is connected to the differential negative signal end and is used to transmit and receive full-speed data or low-speed data of the differential negative signal end in the second communication mode.

5. A compatible communication system according to any one of claims 1 to 4, characterized in that: Also includes: The NRZI decoding module is used for performing NRZI decoding on the sampled data from the oversampling module and sending the data to the USB controller; The NRZI encoding module is used to perform NRZI encoding on the data from the USB controller and send it to the IO control module.

6. A compatible communication system according to claim 5, characterized in that: It also includes a serial-to-parallel conversion module for performing 1:8 serial-to-parallel conversion on the sampled data from the oversampling module and sending the data to the NRZI decoding module.

7. A compatible communication system according to claim 6, characterized in that: It also includes a parallel-to-serial conversion module for performing 8:1 parallel-to-serial conversion on the data from the NRZI encoding module and sending the data to the IO control module.

8. A compatible communication system according to claim 7, characterized in that: The USB controller is also connected to the FPGA user interface.

9. A compatibility communication method, characterized in that: include: The IO control module controls the IO interface module to adjust the pull-up resistors of the differential positive signal terminal and the differential negative signal terminal to realize the first communication mode and the second communication mode; wherein, in the first communication mode, the first data transceiver unit is selected to transmit and receive high-speed data, and in the second communication mode, the second data transceiver unit is selected to transmit and receive full-speed data or low-speed data; In the first communication mode, the oversampling module performs a 90° phase shift on the first clock signal to form a second clock signal, and samples the differential positive signal end and the differential negative signal end based on the first clock signal and the second clock signal, respectively, and delays the differential positive signal end or the differential negative signal end by 45°; In the second communication mode, the oversampling module samples the differential positive signal end and the differential negative signal end based on the first clock signal; The USB controller processes the sampling result from the oversampling module based on the USB2.0 protocol and feeds it back to the IO control module.

10. A computer-readable storage medium comprising a computer program, characterized in that: When the computer program is executed by a processor, the communication method as claimed in claim 9 is implemented.

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