Timing optimization method and electronic device

Abstract

The application provides a timing optimization method and an electronic device. The method comprises: obtaining a timing report and a netlist, and determining a worst timing path and a logic stage number of the worst timing path from the timing report; determining an initial primitive relationship chain according to the worst timing path, the logic stage number of the worst timing path, a connection relationship between primitives in the netlist, and an expected logic stage number; updating the initial primitive relationship chain according to a preset register in the initial primitive relationship chain, the expected logic stage number, the worst timing path, the logic stage number of the worst timing path, and the connection relationship between primitives in the netlist, to obtain an updated primitive relationship chain; determining whether a timing delay of the updated primitive relationship chain meets a preset condition, and if yes, taking the updated primitive relationship chain as a target primitive relationship chain. The timing delay of the timing path can be improved, and the timing path is optimized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FPGA, in particular to a timing optimization method and an electronic device. BACKGROUND

[0002] Timing report of FPGA (Field-Programmable Gate Array) is an indispensable part in the process of FPGA design and verification. The timing report provides detailed information about all paths in the design, including the delay of each path, the slack and the violated timing constraints, etc. These information is crucial to ensure that the FPGA design works normally at the target frequency. Therefore, timing analysis is not only a necessary step to ensure the correctness of the design, but also an important means to improve the performance of the design. With the continuous expansion and complexity of the application field of FPGA, the requirement for the performance of the design is also getting higher and higher. Therefore, how to optimize the timing of FPGA has become an important issue.

[0003] In the prior art, the method for improving timing generally adopts timing constraint optimization, logic optimization, clock distribution, signal synchronization and asynchronous processing, etc. However, for scenarios such as large multiplication decomposition, division, multiplier cascade, long chain cascade of arithmetic logic unit (ALU) and cascade of burst pipelined synchronous static RAM (BSRAM), the above methods cannot provide a good timing solution. SUMMARY

[0004] The present application aims at the deficiencies in the prior art, and provides a timing optimization method and an electronic device to optimize the timing path.

[0005] To achieve the above object, the technical solutions adopted by the embodiments of the present application are as follows:

[0006] In a first aspect, the embodiments of the present application provide a timing optimization method, which comprises:

[0007] obtaining a timing report and a netlist, and determining a worst timing path and the number of logic stages of the worst timing path from the timing report, wherein the timing report comprises at least one timing path, and the worst timing path is a path without a register;

[0008] determining an initial primitive relationship chain according to the worst timing path, the number of logic stages of the worst timing path, the connection relationship between each primitive in the netlist and the expected number of logic stages, wherein the initial primitive relationship chain comprises at least one preset register, and the preset register is a register with a fan-out of 1.

[0009] updating the initial primitive relationship chain according to the preset registers, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between primitives in the netlist, to obtain an updated primitive relationship chain;

[0010] determining whether the timing delay of the updated primitive relationship chain meets a preset condition, and if so, taking the updated primitive relationship chain as a target primitive relationship chain.

[0011] Optionally, the initial primitive relationship chain is determined according to the worst timing path, the number of logic stages of the worst timing path, the connection relationship between primitives in the netlist, and the expected number of logic stages, comprising:

[0012] determining the total number of moves of the preset registers according to the number of logic stages of the worst timing path and the expected number of logic stages;

[0013] determining the initial primitive relationship chain according to the total number of moves of the preset registers, the connection relationship between primitives in the netlist, and the head primitive and the tail primitive in the worst timing path.

[0014] Optionally, the initial primitive relationship chain is determined according to the number of preset registers, the connection relationship between primitives in the netlist, and the head primitive and the tail primitive in the worst timing path, comprising:

[0015] A1: taking the worst timing path as an initial candidate path and an initial pursuit path;

[0016] B1: determining whether there is a new first candidate path or a new first pursuit path according to the tail primitive, the connection relationship between primitives in the netlist, and the total number of moves of the preset registers, and if so, taking the new first candidate path or the new first pursuit path as a first initial relationship chain;

[0017] C1: determining whether there is a new second candidate path or a new second pursuit path according to the head primitive, the connection relationship between primitives in the netlist, and the total number of moves of the preset registers, and if so, taking the new second candidate path or the new second pursuit path as a second initial relationship chain;

[0018] D1: obtaining the initial primitive relationship chain according to the first initial relationship chain and / or the second initial relationship chain, and stopping the loop;

[0019] E1: if the new first alternative path, the new first pursuing path, the new second alternative path and the new second pursuing path do not exist, then re-determine a new total number of movements of the preset register, and re-perform steps B1-E1 according to the new total number of movements until a preset loop end condition is reached.

[0020] Optionally, the determining whether the new first alternative path or the new first pursuing path exists according to the tail primitive, the connection relationship between the primitives in the netlist and the total number of movements of the preset register comprises:

[0021] taking the tail primitive as a first starting point, traversing each register in the netlist according to the connection relationship between the primitives in the netlist, and determining whether the current register traversed is the preset register;

[0022] if the current register is the preset register, adding the current register and a path in a module where the current register is located to the initial pursuing path to obtain a new first pursuing path, and continuing to traverse a next register of the current register until a first traversal end condition is met, and taking the new first pursuing path when the first traversal end condition is met as the first initial relationship chain, the first traversal end condition being that a number of the preset registers traversed is equal to the total number of movements of the preset register or the current register being a top layer port;

[0023] if the current register is not the preset register, determining whether the current register meets the first traversal end condition;

[0024] if the first traversal end condition is not met, continuing to traverse the next register of the current register, and determining whether the preset register exists after the current register when the first traversal end condition is met;

[0025] if the preset register exists after the current register, updating the initial alternative path according to the preset register to obtain a new first alternative path.

[0026] Optionally, the updating the initial alternative path according to the preset register comprises:

[0027] adding a path in a module where the preset register is located and each primitive before the preset register to the initial alternative path.

[0028] Optionally, the updating the initial primitive relationship chain according to the preset registers in the initial primitive relationship chain, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between primitives in the netlist, to obtain an updated primitive relationship chain, comprises:

[0029] A2: starting from the head of the initial primitive relationship chain, determining the number of logic stages between two adjacent groups of preset registers in the initial primitive relationship chain according to the connection relationship between primitives in the netlist;

[0030] B2: determining whether the intermediate preset register of the two adjacent groups of preset registers meets the moving condition according to the number of logic stages and the preset number of logic stages;

[0031] C2: if it is determined that the moving condition is met, determining a target primitive according to the preset number of logic stages and the worst timing path, moving the intermediate preset register to before the target primitive, and determining whether the intermediate preset register is successfully moved according to the number of logic stages between the target primitive and the tail primitive of the worst timing path;

[0032] D2: if the moving condition is not met or the intermediate register is not successfully moved, updating the intermediate preset register to the head of the initial primitive relationship chain to obtain a new head, and re-executing step A2 until the preset registers in the initial primitive relationship chain are traversed and it is determined whether a new primitive chain is obtained after the traversal is completed;

[0033] E2: if a new primitive chain is obtained after the traversal is completed, taking the new primitive chain obtained after the traversal is completed as the updated primitive relationship chain;

[0034] F2: if no new primitive chain is obtained after the traversal is completed, determining a new preset number of logic stages, and returning to execute step A2 according to the new preset number of logic stages until iteration is completed.

[0035] Optionally, the two adjacent groups of preset registers comprise a first preset register, a second preset register, and a third preset register, and the second preset register is an intermediate preset register.

[0036] The determining the number of logic stages between two adjacent groups of preset registers in the initial primitive relationship chain according to the connection relationship between primitives in the netlist comprises:

[0037] obtaining a first number of logic stages between the first preset register and the second preset register from the netlist;

[0038] obtaining a second number of logic stages between the second preset register and the third preset register from the netlist;

[0039] adding the first number of logic levels and the second number of logic levels to obtain a sum of the number of logic levels.

[0040] Optionally, the determining whether the intermediate preset register of the two adjacent preset registers meets the moving condition according to the sum of the number of logic levels and the preset number of logic levels comprises:

[0041] If the sum of the number of logic levels is less than or equal to the preset number of logic levels, it is determined that the intermediate preset register of the two adjacent preset registers meets the moving condition.

[0042] Optionally, the determining the target primitive according to the preset number of logic levels and the worst timing path comprises:

[0043] starting from a head primitive of the worst timing path, determining a primitive between the head primitive of the worst timing path and a primitive with the preset number of logic levels as the target primitive.

[0044] In a second aspect, an embodiment of the present application further provides a timing optimization device, which comprises:

[0045] an obtaining module, configured to obtain a timing report and a netlist, and determine a worst timing path and a number of logic levels of the worst timing path from the timing report, the timing report comprising at least one timing path, and the worst timing path being a path without a register;

[0046] a determining module, configured to determine an initial primitive relationship chain according to the worst timing path, the number of logic levels of the worst timing path, a connection relationship between primitives in the netlist and an expected number of logic levels, the initial primitive relationship chain comprising at least one preset register, and the preset register being a register with a fan-out of 1;

[0047] an updating module, configured to update the initial primitive relationship chain according to the preset register in the initial primitive relationship chain, the expected number of logic levels, the worst timing path, the number of logic levels of the worst timing path and the connection relationship between the primitives in the netlist, to obtain an updated primitive relationship chain;

[0048] the determining module, configured to determine whether a timing delay of the updated primitive relationship chain meets a preset condition, and if so, to determine the updated primitive relationship chain as a target primitive relationship chain.

[0049] Optionally, the determining module is specifically configured to:

[0050] determine a total number of moves of the preset register according to the number of logic levels of the worst timing path and the expected number of logic levels;

[0051] determine the initial primitive relationship chain according to the head primitive, the connection relationship between the primitives in the netlist, and the total number of movements of the preset register.

[0052] Optionally, the determining module is specifically configured to:

[0053] A1: taking the worst timing path as an initial alternative path and an initial pursuit path;

[0054] B1: determining whether there is a new first alternative path or a new first pursuit path according to the tail primitive, the connection relationship between the primitives in the netlist, and the total number of movements of the preset register, and taking the new first alternative path or the new first pursuit path as a first initial relationship chain if there is;

[0055] C1: determining whether there is a new second alternative path or a new second pursuit path according to the head primitive, the connection relationship between the primitives in the netlist, and the total number of movements of the preset register, and taking the new second alternative path or the new second pursuit path as a second initial relationship chain if there is;

[0056] D1: obtaining the initial primitive relationship chain according to the first initial relationship chain and / or the second initial relationship chain, and stopping the loop;

[0057] E1: if the new first alternative path, the new first pursuit path, the new second alternative path, and the new second pursuit path all do not exist, then re-determining a new total number of movements of the preset register, and re-executing steps B1-E1 according to the new total number of movements until a preset loop end condition is reached.

[0058] Optionally, the determining module is specifically configured to:

[0059] taking the tail primitive as a first starting point, traversing each register in the netlist according to the connection relationship between the primitives in the netlist, determining whether the current register traversed is the preset register for the current register;

[0060] if the current register is the preset register, adding the current register and a path in a module where the current register is located to the initial pursuit path to obtain a new first pursuit path, and continuing to traverse a next register of the current register until a first traversal end condition is met, and taking the new first pursuit path when the first traversal end condition is met as the first initial relationship chain, the first traversal end condition being that the number of the preset registers traversed is equal to the total number of movements of the preset register or the current register being a top-level port;

[0061] If the current register is not the preset register, it is determined whether the current register satisfies a first traversal end condition;

[0062] If the first traversal end condition is not satisfied, a next register of the current register is continuously traversed, and it is determined whether there is the preset register after the current register when the first traversal end condition is satisfied;

[0063] If the preset register exists after the current register, the initial candidate path is updated according to the preset register to obtain a new first candidate path.

[0064] Optionally, the updating module is specifically configured to:

[0065] add a path in a module where the preset register is located and each primitive before the preset register to the initial candidate path.

[0066] Optionally, the updating module is specifically configured to:

[0067] A2: starting from a chain head in the initial primitive relationship chain, determining a logic level number between adjacent two groups of preset registers in the initial primitive relationship chain according to a connection relationship between each primitive in the netlist;

[0068] B2: determining whether an intermediate preset register of the adjacent two groups of preset registers satisfies a moving condition according to the logic level number and the preset logic level number;

[0069] C2: if it is determined that the moving condition is satisfied, determining a target primitive according to the preset logic level number and the worst timing path, moving the intermediate preset register to before the target primitive, and determining whether the intermediate preset register is successfully moved according to a logic level number between the target primitive and a tail primitive of the worst timing path;

[0070] D2: if the moving condition is not satisfied or the intermediate register is not successfully moved, updating the intermediate preset register to a chain head of the initial primitive relationship chain to obtain a new chain head, and re-executing step A2 until preset registers in the initial primitive relationship chain are traversed and it is determined whether a new primitive chain is obtained after the traversal is completed;

[0071] E2: if the new primitive chain is obtained after the traversal is completed, the new primitive chain obtained after the traversal is completed is taken as the updated primitive chain;

[0072] F2: if the new primitive chain is not obtained after the traversal is completed, a new preset logic level number is determined, and step A2 is executed according to the new preset logic level number until iteration is ended.

[0073] Optionally, the two adjacent groups of preset registers comprise: a first preset register, a second preset register, and a third preset register, and the second preset register is an intermediate preset register.

[0074] The updating module is specifically configured to:

[0075] obtain, from the netlist, a first number of logic levels between the first preset register and the second preset register;

[0076] obtain, from the netlist, a second number of logic levels between the second preset register and the third preset register;

[0077] add the first number of logic levels and the second number of logic levels to obtain a total number of logic levels.

[0078] Optionally, the updating module is specifically configured to:

[0079] if the total number of logic levels is less than or equal to the preset number of logic levels, determine that an intermediate preset register of the two adjacent groups of preset registers satisfies the moving condition.

[0080] Optionally, the updating module is specifically configured to:

[0081] start from a head primitive of the worst timing path, and take a primitive between the head primitive of the worst timing path and the intermediate preset register as the target primitive, where a number of logic levels of the target primitive is the preset number of logic levels.

[0082] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a processor, a storage medium, and a bus, the storage medium stores program instructions executable by the processor, when an application program runs, the processor and the storage medium communicate through the bus, and the processor executes the program instructions to execute steps of the timing optimization method in the first aspect.

[0083] In a fourth aspect, an embodiment of the present application further provides a computer readable storage medium, the computer readable storage medium stores a computer program, and the computer program reads and executes steps of the timing optimization method in the first aspect.

[0084] The present application has the following beneficial effects:

[0085] The timing optimization method and the electronic device provided by the application, by calling relationship analysis according to the worst timing path determined by the acquired timing report, the logical level number of the worst timing path, the connection relationship between each primitive in the netlist and the expected logical level number, the initial primitive relationship chain containing the register with the fan-out of 1 is determined first, then the register with the fan-out of 1 is moved according to the preset register in the initial primitive relationship chain, the expected logical level number, the worst timing path, the logical level number of the worst timing path and the connection relationship between each primitive in the netlist, so as to update the initial primitive relationship chain, obtain the updated primitive relationship chain, update the initial primitive relationship chain by moving the register with the fan-out of 1 in the initial primitive relationship chain, and determine whether the timing delay of the updated primitive relationship chain meets the preset condition, if yes, the updated primitive relationship chain is taken as the target primitive relationship chain, so as to optimize the timing path. By moving the register with the fan-out of 1, the timing delay of the timing path can be improved, so as to optimize the timing path. The timing of the scenarios such as large multiplication decomposition, division, multiplier cascade, ALU long chain cascade and BSRAM cascade can be well optimized, and the user design quality is improved. BRIEF DESCRIPTION OF DRAWINGS

[0086] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0087] Figure 1 The flowchart of the timing optimization method provided by the embodiment of the application;

[0088] Figure 2 The schematic diagram of the worst timing path provided by the embodiment of the application;

[0089] Figure 3 The flowchart of the method for determining the initial primitive relationship chain improved by the embodiment of the application;

[0090] Figure 4 The flowchart of another method for determining the initial primitive relationship chain provided by the embodiment of the application;

[0091] Figure 5 The schematic diagram of the initial primitive relationship chain provided by the embodiment of the application;

[0092] Figure 6 The flowchart of another method for determining the initial primitive relationship chain provided by the embodiment of the application;

[0093] Figure 7 A flowchart of a method for determining an updated primitive relationship chain provided by an embodiment of the present application is shown in FIG. 6.

[0094] Figure 8 A schematic diagram of an updated primitive relationship chain provided by an embodiment of the present application is shown in FIG. 7.

[0095] Figure 9 A flowchart of another method for determining an updated primitive relationship chain provided by an embodiment of the present application is shown in FIG. 8.

[0096] Figure 10 A device schematic diagram of a timing optimization method provided by an embodiment of the present application is shown in FIG. 9.

[0097] Figure 11 A structural block diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 10. DETAILED DESCRIPTION

[0098] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application are only intended to illustrate and describe the present application, and are not intended to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn according to the actual proportions. The flowchart shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can not be implemented in sequence, and the steps without logical context relationship can be reversed in sequence or implemented simultaneously. In addition, one or more other operations can be added to the flowchart or removed from the flowchart by those skilled in the art under the guidance of the content of the present application.

[0099] In addition, the described embodiments are only some of the embodiments of the present application, not all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0100] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0101] Optionally, the timing optimization method provided in the embodiments of the present application is applied to an electronic device, which can be a terminal device with computing processing capability and display function, such as a mobile phone, a tablet computer, a notebook computer, a palm computer, a desktop computer, or a server. The timing optimization method can be applied to an application program in the terminal device, such as an APP (application) of a mobile phone or an application system on a computer.

[0102] The specific implementation process of the timing optimization provided in the embodiments of the present application is explained below.

[0103] Figure 1 A flowchart of a timing optimization method provided in the embodiments of the present application is shown in FIG. 1. The execution subject of the method is an electronic device as described above. As shown in FIG. 1, the method includes the following steps. Figure 1

[0104] In S101, a timing report and a netlist are obtained, and a worst timing path and a logic level number of the worst timing path are determined from the timing report.

[0105] The timing report can include at least one timing path, and the worst timing path is a path that does not include a register. The worst timing path can be, for example, the timing path of "ALU chain-Logic chain-DSP" as shown in FIG. 2, which does not include a register. The logic level number of the worst timing path, level_worst, can be 31, for example. Figure 2

[0106] Specifically, the timing report and the netlist can be generated based on user input design information. The netlist can include a plurality of primitives and an association relationship between the primitives, where the primitives can be registers, ALUs, Logics, DSPs, and the like, and there is a logic relationship between the primitives. For example, the ALU chain in FIG. 2 can include ALU1→ALU2→ALU3→ALU4, where ALU1, ALU2, ALU3, and ALU4 are different primitives. The logic relationship between ALU2 and ALU1 and ALU3 is that the output of ALU1 is the input of ALU2, the output of ALU2 is the input of ALU3, and the logic level number of ALU1 to ALU3 is 2. Figure 2

[0107] In S102, an initial primitive relationship chain is determined according to the worst timing path, the logic level number of the worst timing path, the connection relationship between the primitives in the netlist, and an expected logic level number.

[0108] The initial primitive relationship chain includes at least one preset register, where the preset register refers to a register with a fan-out of 1.

[0109] ​​​The expected logic level can be used to guide the movement of the registers in the netlist and the breaking of the chain when the modules such as DSP, ALU, Block RAM, logic, etc. are cascaded. The expected logic level can be set in advance according to the actual situation. Meanwhile, the preset iteration number Iteration_num, the logic level iteration value Iteration_level, the clock frequency iteration value Iteration_fmax and the user's expected maximum clock frequency fmax can also be configured in advance. The preset iteration number refers to the number of iterations of the timing optimization method. The clock frequency iteration value can be used to update the user's expected maximum clock frequency each time. The logic level iteration value can be used to update the user's expected logic level each time.

[0110] Optionally, the initial primitive relationship chain containing the register with a fan-out of 1 can be determined using a preset method according to the worst timing path, the logic level of the worst timing path, the connection relationship between the primitives in the netlist and the expected logic level.

[0111] S103, updating the initial primitive relationship chain according to the preset register in the initial primitive relationship chain, the expected logic level, the worst timing path, the logic level of the worst timing path and the connection relationship between the primitives in the netlist, to obtain an updated primitive relationship chain.

[0112] Specifically, the register with a fan-out of 1 in the initial primitive relationship chain can be moved using a preset method according to the preset register in the initial primitive relationship chain, the expected logic level, the worst timing path, the logic level of the worst timing path and the connection relationship between the primitives in the netlist. Specifically, the breaking of the chain of the cascaded modules such as DSP, ALU, Block RAM, logic, etc. in the netlist can be performed by moving the register with a fan-out of 1, so as to update the timing delay of the initial primitive relationship chain and obtain an updated primitive relationship chain. The updated primitive relationship chain is the relationship chain after the movement of the register with a fan-out of 1.

[0113] S104, determining whether the timing delay of the updated primitive relationship chain meets a preset condition.

[0114] If the preset condition is met, S105 is performed; if the preset condition is not met, S106 is performed.

[0115] The preset condition refers to that the difference between the timing delay of the updated primitive relationship chain and the expected maximum clock frequency fmax is less than a preset threshold value, or the timing delay of the updated primitive relationship chain is much greater than the expected maximum clock frequency fmax.

[0116] The new expected maximum clock frequency fmax s = (fmax s-1) Iteration fmax, where s is the iteration number, Iteration fmax is the clock frequency iteration value, fmax s is the new expected clock frequency maximum value for the next iteration of the current iteration, fmax s-1 is the expected clock frequency maximum value for the current iteration.

[0117] S105, update the initial primitive relationship chain as the target primitive relationship chain.

[0118] S106, determine whether the preset iteration number is reached.

[0119] If the preset iteration number is not reached, perform the following S107; if the iteration number reaches the preset iteration number, perform the following S108.

[0120] S107, update the expected clock frequency maximum value fmax and the expected logic stage number, and return to perform S102.

[0121] S108, feedback the update failure.

[0122] In the embodiment, the initial primitive relationship chain containing the fan-out-1 register is determined by analyzing the calling relationship according to the worst timing path determined by the timing report obtained, the logic stage number of the worst timing path, the connection relationship between each primitive in the netlist, and the expected logic stage number. Then, the fan-out-1 register is moved according to the preset register in the initial primitive relationship chain, the expected logic stage number, the worst timing path, the logic stage number of the worst timing path, and the connection relationship between each primitive in the netlist, so as to update the initial primitive relationship chain, obtain the updated primitive relationship chain, update the initial primitive relationship chain by moving the fan-out-1 register in the initial primitive relationship chain, and determine whether the timing delay of the updated primitive relationship chain meets the preset condition. If it meets, the updated primitive relationship chain is taken as the target primitive relationship chain, so as to optimize the timing path. By moving the fan-out-1 register, the timing delay of the timing path can be improved, so as to optimize the timing path. The timing of scenarios such as large multiplication decomposition, division, multiplier cascade, ALU long chain cascade, and BSRAM cascade can be well optimized, and the timing of user design is improved.

[0123] Figure 3 is a flow diagram of a method for determining an initial primitive relationship chain improved by the embodiment of the application, as Figure 3 shown above, the initial primitive relationship chain in S102 above can be determined according to the worst timing path, the logic stage number of the worst timing path, the connection relationship between each primitive in the netlist, and the expected logic stage number, which can include:

[0124] S201, determining a total number of preset register movements according to the logic level number of the worst timing path and the expected logic level number.

[0125] Specifically, the total number of preset register movements is denoted by N for example, N = 2 * (levelworst / (logic level)), wherein levelworst is the logic level number of the worst timing path, and logic level is the expected logic level number, and the division is calculated by taking the upper value, for example, when the logic level number of the worst timing path levelworst = 31 and the expected logic level number logic level = 10, then N = 8.

[0126] S202, determining an initial primitive relationship chain according to the total number of preset register movements, the connection relationship between primitives in the netlist, and the head primitive and the tail primitive in the worst timing path.

[0127] As shown in the worst timing path in the Figure 2 , the head primitive in the worst timing path can be ALU1 in the ALU chain for example, and the tail primitive is DSP.

[0128] Figure 4 The flowchart of another method for determining an initial primitive relationship chain provided by the embodiment of the present application is shown in Figure 4 , and the determination of the initial primitive relationship chain in S202 according to the total number of preset register movements, the connection relationship between primitives in the netlist, and the head primitive and the tail primitive in the worst timing path can include:

[0129] S301, taking the worst timing path as an initial candidate path and an initial pursuit path.

[0130] S302, determining whether there is a new first candidate path or a new first pursuit path according to the tail primitive, the connection relationship between primitives in the netlist, and the total number of preset register movements.

[0131] Optionally, if there is a new first candidate path or a new first pursuit path, S303 is performed. If there is no new first candidate path or new first pursuit path, S304 is performed.

[0132] S303, taking the new first candidate path or the new first pursuit path as a first initial relationship chain.

[0133] Specifically, if the new first alternative path and the new first pursuit path exist, only the new first pursuit path is taken as the first initial relationship chain; if the new first alternative path exists and the new first pursuit path does not exist, the new first alternative path is taken as the first initial relationship chain; if the new first alternative path does not exist and only the new first pursuit path exists, the new first pursuit path is taken as the first initial relationship chain.

[0134] S304, determining whether the new second alternative path or the new second pursuit path exists according to the header primitive, the connection relationship between the primitives in the netlist, and the total number of preset register movements.

[0135] Optionally, if the new second alternative path or the new second pursuit path exists, the following S305 is performed; if the new second alternative path or the new second pursuit path does not exist, the following S307 is performed.

[0136] Optionally, as known from the foregoing, the total number of preset register movements N = 2 * (levelworst / (logic level)), the iteration number s of the first iteration is 1, the iteration number s of the second iteration is 2, the iteration number s of the third iteration is 3, and so on. The new total number of preset register movements is determined, that is, the total number of preset register movements in the next iteration of the current iteration. Before the new total number of preset register movements is determined, the new expected logic level needs to be determined, and the new expected logic level logic level s = (logic level s-1 )+Iteration_level, wherein s is the iteration number, Iteration_level is the logic level iteration value, logic level s is the new expected logic level in the next iteration of the current iteration, logic level s-1 is the expected logic level in the current iteration, and the new total number of preset register movements N s = 2 * (levelworst / (logic level s )).

[0137] S305, taking the new second alternative path or the new second pursuit path as the second initial relationship chain.

[0138] Specifically, if the new second alternative path and the new second pursuit path exist, only the new second pursuit path is taken as the second initial relationship chain; if the new second alternative path exists and the new second pursuit path does not exist, the new second alternative path is taken as the second initial relationship chain; if the new second alternative path does not exist and only the new second pursuit path exists, the new second pursuit path is taken as the second initial relationship chain.

[0139] S306: Obtain an initial primitive relationship chain according to the first initial relationship chain and / or the second initial relationship chain, and stop the loop.

[0140] Optionally, if there is a first initial relationship chain and a second initial relationship chain, both the first initial relationship chain and the second initial relationship chain are used as the initial primitive relationship chain. Since both the first initial relationship chain and the second initial relationship chain contain the worst timing path, the initial primitive relationship chain obtained is obtained by merging the worst timing paths that overlap in the first initial relationship chain and the second initial relationship chain to obtain the initial primitive relationship chain. Figure 5 As shown, the first initial relationship chain is "ALU chain in the worst timing path - Logic chain in the worst timing path - DSP in the worst timing path - register F1 with fan-out 1 - ALU chain - register F2 with fan-out 1", and the second initial relationship chain is "register F6 with fan-out 1 - Logic chain - register F5 with fan-out 1 - Logic chain - register F4 with fan-out 1 - Logic chain - register F3 with fan-out 1 - ALU chain in the worst timing path - Logic chain in the worst timing path - D in the worst timing path SP", the initial primitive relationship chain is "register F6 with fan-out 1-Logic chain-register F5 with fan-out 1-Logic chain-register F4 with fan-out 1-Logic chain-register F3 with fan-out 1-ALU chain in the worst timing path-Logic chain in the worst timing path-DSP in the worst timing path-register F1 with fan-out 1-ALU chain-register F2 with fan-out 1", among which, register F6 with fan-out 1 is the head of the initial primitive relationship chain, and register F2 with fan-out 1 is the tail of the initial primitive relationship chain.

[0141] Optionally, if only the first initial relationship chain exists, the first initial relationship chain is used as the initial primitive relationship chain; if only the second initial relationship chain exists, the second initial relationship chain is used as the initial primitive relationship chain.

[0142] S307: Determine whether the preset number of iterations has been reached.

[0143] If the preset number of iterations is not reached, the new total number of moves of the preset register is determined, and the process returns to S302 to S304. If the preset number of iterations is reached, the process ends.

[0144] Figure 6 A flowchart of another method for determining an initial primitive relationship chain provided in an embodiment of the present application is shown as follows: Figure 6As shown, the determining, in S302, whether there is a new first candidate path or a new first pursuit path according to the tail primitive, the connection relationship between each primitive in the netlist, and the total number of preset registers can include:

[0145] S401, taking the tail primitive as a first starting point, traversing each register in the netlist according to the connection relationship between each primitive in the netlist.

[0146] For example, as shown in the initial primitive relationship chain in Figure 5 , taking the tail primitive "DSP" of the worst timing path as the first starting point, the registers in the netlist are traversed backward.

[0147] S402, determining whether the current register traversed is a preset register.

[0148] Optionally, if the current register is a preset register, i.e., the current register is a register with a fan-out of 1, then S403 is performed; if the current register is not a preset register, then S406 is performed.

[0149] S403, adding the current register and the path in the module where the current register is located to the initial pursuit path to obtain a new first pursuit path.

[0150] The module where the current register is located and the path in the module where the current register is located can be obtained from the netlist. For example, when the current register is a register F1 with a fan-out of 1, the register F1 with a fan-out of 1 and the path in the module where the register F1 with a fan-out of 1 is located are added to the initial pursuit path to obtain a new first pursuit path.

[0151] S404, determining whether a first traversal end condition is met.

[0152] Optionally, if the first traversal end condition is met, then S405 is performed; if the first traversal end condition is not met, then S402 is returned to be executed.

[0153] The first traversal end condition is that the number of preset registers traversed is equal to the total number of preset registers or the current register is a top-level port. The current register being a top-level port can include that the current register being a register with a fan-out of 1 is a top-level port or is not a register with a fan-out of 1, i.e., if the current register traversed is determined to be a top-level port, then the tail primitive traversal ends and no other register is traversed.

[0154] S405, taking the new first pursuit path when the first traversal end condition is met as a first initial relationship chain.

[0155] For example, if the first traversal end condition is met when the register F2 with a fan-out of 1 is reached, the new first pursuit path obtained when the register F2 with a fan-out of 1 is reached is taken as the first initial relationship chain.

[0156] S406, determining whether the current register meets the first traversal end condition.

[0157] Optionally, if the current register is not a register with a fan-out of 1, it is determined whether the current register meets the first traversal end condition. If yes, the traversal is ended, and there is no new first alternative path; if not, the next register of the current register is continued to be traversed, and S407 is performed.

[0158] Specifically, if the current register is a top layer port or the number of iterations is reached, the tail primitive ends the traversal; if it is determined that the current register is not a top layer port and the number of iterations is not reached, S407 is performed.

[0159] S407, determining whether there is a preset register after the current register when the first traversal end condition is met.

[0160] Optionally, if there is a preset register after the current register when the first traversal end condition is met, S408 is performed; if there is no preset register after the current register when the first traversal end condition is met, there is no new first alternative path.

[0161] Specifically, if the current register is not a top layer port, the next register of the current register is continued to be traversed.

[0162] S408, updating the initial alternative path according to the preset register to obtain a new first alternative path.

[0163] Specifically, the path in the module where the preset register is located and each primitive before the preset register can be added to the initial alternative path.

[0164] It is worth noting that the process of determining whether there is a new second alternative path or a new second pursuit path according to the head primitive, the connection relationship between each primitive in the netlist, and the total number of movements of the preset register in S304 is similar to that in S303. Specifically, each register is traversed starting from the head primitive as a starting point, thereby obtaining a new second alternative path or a new second pursuit path.

[0165] Figure 7 A flowchart of a method for determining an updated primitive relationship chain provided by an embodiment of the present application is shown in FIG. 4. Figure 7As shown, the initial primitive relationship chain is updated according to the preset registers in the initial primitive relationship chain, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between primitives in the netlist in S103 above, to obtain an updated primitive relationship chain, which can include:

[0166] S501, starting from the head of the initial primitive relationship chain, determining the number of logic stages between two adjacent groups of preset registers in the initial primitive relationship chain according to the connection relationship between primitives in the netlist.

[0167] For example, taking the initial primitive relationship chain in Figure 5 as an example, the head of the initial primitive relationship chain is the register F6 with a fan-out of 1. The two adjacent groups of preset registers are: the register F6 with a fan-out of 1 and the register F5 with a fan-out of 1, and the register F5 with a fan-out of 1 and the register F4 with a fan-out of 1. Then, the sum of the number of logic stages between the register F6 with a fan-out of 1 and the register F5 with a fan-out of 1 and the number of logic stages between the register F5 with a fan-out of 1 and the register F4 with a fan-out of 1 can be determined according to the connection relationship between primitives in the netlist using a preset method.

[0168] S502, determining whether the intermediate preset register of the two adjacent groups of preset registers meets the moving condition according to the number of logic stages and the preset number of logic stages.

[0169] Optionally, if the intermediate preset register meets the moving condition, S503 is performed; if the intermediate preset register does not meet the moving condition, S505 is performed.

[0170] For example, for the two adjacent groups of preset registers: the register F6 with a fan-out of 1 and the register F5 with a fan-out of 1, and the register F5 with a fan-out of 1 and the register F4 with a fan-out of 1, the intermediate preset register is the register F5 with a fan-out of 1, and it is determined whether the register F5 with a fan-out of 1 meets the moving condition.

[0171] S503, determining a target primitive according to the preset number of logic stages and the worst timing path, and moving the intermediate preset register to before the target primitive.

[0172] Wherein, the determined target primitive is the primitive in the worst timing path, and the intermediate preset register is moved to before the target primitive, so that the output of the intermediate preset register is the input of the target primitive.

[0173] For example, continuing with Figure 5For example, if the determined target primitive is a Logic chain, the intermediate preset register, i.e., the register F5 with a fan-out of 1, is moved before the Logic connection, and the output of the register F5 with a fan-out of 1 is the input of the Logic connection. The initial primitive relationship chain after the movement is as shown in Figure 8 .

[0174] S504, determining whether the intermediate preset register is successfully moved according to the number of logic levels between the target primitive and the tail primitive of the worst timing path.

[0175] Optionally, after the intermediate preset register is moved, it is further determined whether the intermediate preset register is successfully moved according to the number of logic levels between the target primitive and the tail of the worst timing path using a preset method. If the movement is successful, the intermediate preset register is moved between the target primitives, and the netlist is updated, i.e., the connection relationship between the primitives in the netlist is updated, the iteration is ended, and the updated primitive chain is obtained. If the movement is not successful, the following S505 is performed.

[0176] S505, determining whether the preset register in the initial primitive relationship chain is iterated completely.

[0177] Optionally, if the iteration is completed, the following S507 is performed; if the iteration is not completed, the S506 is performed.

[0178] S506, updating the intermediate preset register as the head of the initial primitive relationship chain to obtain a new head, and performing the S501 again.

[0179] S507, determining whether a new primitive chain is obtained.

[0180] Optionally, if the new primitive chain is obtained, the following S508 is performed; if the iteration is completed but the new primitive chain is not obtained, the following S509 is performed.

[0181] S508, taking the new primitive chain obtained after the iteration as the updated primitive chain.

[0182] S509, determining whether the iteration number is reached.

[0183] If the iteration number is reached, the iteration is ended; if the iteration number is not reached, a new expected number of logic levels is determined, and the S501 is performed again.

[0184] Figure 9 Another method for determining the updated primitive relationship chain provided by the embodiment of the present application is shown in the flowchart as shown in Figure 9 . In the S501, the head of the initial primitive relationship chain is taken as the starting point, and the number of logic levels between the two adjacent preset registers in the initial primitive relationship chain is determined according to the connection relationship between the primitives in the netlist.

[0185] S601, obtaining a first logic level number between the first preset register and a second preset register from the netlist.

[0186] For example, as shown in the initial primitive relationship chain, the first preset register can be the register F6 with a fanout of 1, and the second preset register can be the register F5 with a fanout of 1. Then the first logic level number level_1 between the register F6 with a fanout of 1 and the register F5 with a fanout of 1 can be obtained from the netlist. Figure 5

[0187] S602, obtaining a second logic level number between the second preset register and a third preset register from the netlist.

[0188] For example, the third preset register is the register F4 with a fanout of 1. Then the first logic level number level_2 between the register F5 with a fanout of 1 and the register F4 with a fanout of 1 can be obtained from the netlist.

[0189] S603, adding the first logic level number and the second logic level number to obtain a logic level number sum.

[0190] For example, the logic level number sum level_sim = level_1 + level_2.

[0191] Optionally, the determining, in S502, whether the intermediate preset register between the two adjacent preset registers meets the moving condition according to the logic level number sum and the preset logic level number can include:

[0192] Specifically, if the logic level number sum is less than or equal to the preset logic level number, it is determined that the intermediate preset register between the two adjacent preset registers meets the moving condition, such as level_sim ≤ logic level. If the logic level number sum is greater than the preset logic level number, the intermediate preset register between the two adjacent preset registers does not meet the moving condition.

[0193] Optionally, the determining, in S503, the target primitive according to the preset logic level number and the worst timing path can include:

[0194] Specifically, the primitive with a logic level number between the first primitive of the worst timing path and the target primitive being the preset logic level number can be taken as the target primitive.

[0195] Figure 10 A device schematic diagram of a timing optimization method provided by an embodiment of the present application is shown in FIG. 6. As shown in FIG. 6, the device includes: Figure 10

[0196] ​​The acquisition module 701 is configured to acquire a timing report and a netlist, and determine a worst timing path and a number of logic stages of the worst timing path from the timing report, the timing report including at least one timing path, and the worst timing path being a path without a register;

[0197] The determination module 702 is configured to determine an initial primitive relationship chain according to the worst timing path, the number of logic stages of the worst timing path, a connection relationship between primitives in the netlist, and an expected number of logic stages, the initial primitive relationship chain including at least one preset register, and the preset register being a register with a fan-out of 1.

[0198] The update module 703 is configured to update the initial primitive relationship chain according to the preset register in the initial primitive relationship chain, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between primitives in the netlist, to obtain an updated primitive relationship chain.

[0199] The determination module 702 is configured to determine whether a timing delay of the updated primitive relationship chain meets a preset condition, and if so, take the updated primitive relationship chain as a target primitive relationship chain.

[0200] Optionally, the determination module 702 is specifically configured to:

[0201] determine a total number of movements of the preset register according to the number of logic stages of the worst timing path and the expected number of logic stages;

[0202] determine the initial primitive relationship chain according to the total number of movements of the preset register, the connection relationship between primitives in the netlist, and a head primitive and a tail primitive in the worst timing path.

[0203] Optionally, the determination module 702 is specifically configured to:

[0204] A1: take the worst timing path as an initial alternative path and an initial pursuit path;

[0205] B1: determine whether there is a new first alternative path or a new first pursuit path according to the tail primitive, the connection relationship between primitives in the netlist, and the total number of movements of the preset register, and if so, take the new first alternative path or the new first pursuit path as a first initial relationship chain.

[0206] C1: determining whether a new second alternative path or a new second pursuit path exists according to the header primitive, the connection relationship between the primitives in the netlist, and the total number of movements of the preset register, and if the new second alternative path or the new second pursuit path exists, taking the new second alternative path or the new second pursuit path as a second initial relationship chain;

[0207] D1: obtaining the initial primitive relationship chain according to the first initial relationship chain and / or the second initial relationship chain, and stopping the loop;

[0208] E1: if the new first alternative path, the new first pursuit path, the new second alternative path, and the new second pursuit path all do not exist, re-determining a new total number of movements of the preset register, and re-executing steps B1-E1 according to the new total number of movements until a preset loop end condition is reached.

[0209] Optionally, the determination module 702 is specifically configured to:

[0210] take the tail primitive as a first starting point, traverse each register in the netlist according to the connection relationship between the primitives in the netlist, and determine whether the current register is the preset register for the current register traversed;

[0211] if the current register is the preset register, add the current register and a path in a module in which the current register is located to the initial pursuit path to obtain a new first pursuit path, and continue to traverse a next register of the current register until a first traversal end condition is met, and take the new first pursuit path when the first traversal end condition is met as the first initial relationship chain, the first traversal end condition being that the number of the preset registers traversed is equal to the total number of movements of the preset register or the current register being a top layer port;

[0212] if the current register is not the preset register, determine whether the current register meets the first traversal end condition;

[0213] if the first traversal end condition is not met, continue to traverse the next register of the current register, and determine whether the preset register exists after the current register when the first traversal end condition is met;

[0214] if the preset register exists after the current register, update the initial alternative path according to the preset register to obtain a new first alternative path.

[0215] Optionally, the update module 703 is specifically configured to:

[0216] add the path in the module where the preset register is located and each primitive before the preset register to the initial candidate path.

[0217] Optionally, the updating module 703 is specifically used for:

[0218] A2: starting from the head of the initial primitive relationship chain, determining the number of logic stages between two adjacent groups of preset registers in the initial primitive relationship chain according to the connection relationship between each primitive in the netlist;

[0219] B2: determining whether an intermediate preset register of the two adjacent groups of preset registers meets a moving condition according to the number of logic stages and the preset number of logic stages;

[0220] C2: if it is determined that the moving condition is met, determining a target primitive according to the preset number of logic stages and the worst timing path, moving the intermediate preset register to before the target primitive, and determining whether the intermediate preset register is successfully moved according to the number of logic stages between the target primitive and a tail primitive of the worst timing path;

[0221] D2: if the moving condition is not met or the intermediate register is not successfully moved, updating the intermediate preset register to the head of the initial primitive relationship chain to obtain a new head, re-executing step A2 until the preset registers in the initial primitive relationship chain are traversed completely, and determining whether a new primitive chain is obtained after the traversal is completed;

[0222] E2: if the new primitive chain is obtained after the traversal is completed, taking the new primitive chain obtained after the traversal is completed as the updated primitive chain;

[0223] F2: if the new primitive chain is not obtained after the traversal is completed, determining a new preset number of logic stages, and returning to execute step A2 according to the new preset number of logic stages until iteration is completed.

[0224] Optionally, the two adjacent groups of preset registers include a first preset register, a second preset register and a third preset register, and the second preset register is an intermediate preset register.

[0225] The updating module 703 is specifically used for:

[0226] obtaining a first number of logic stages between the first preset register and the second preset register from the netlist;

[0227] obtaining a second number of logic stages between the second preset register and the third preset register from the netlist;

[0228] The first logic level number and the second logic level number are added to obtain the logic level sum.

[0229] Optionally, the updating module 703 is specifically configured to:

[0230] If the sum of the number of logic levels is less than or equal to the preset number of logic levels, it is determined that the middle preset register of the two adjacent groups of preset registers meets the shift condition.

[0231] Optionally, the updating module 703 is specifically configured to:

[0232] Taking the head primitive of the worst timing path as a starting point, a primitive whose logic level between the head primitive of the worst timing path and the preset logic level is used as the target primitive.

[0233] Figure 11 This is a structural block diagram of an electronic device 800 provided in an embodiment of the present application. Figure 11 As shown, the electronic device may include: a processor 801 and a memory 802.

[0234] Optionally, a bus 803 may also be included, wherein the memory 802 is used to store machine-readable instructions executable by the processor 801. When the electronic device 800 is running, the processor 801 communicates with the memory 802 through the bus 803. When the machine-readable instructions are executed by the processor 801, the method steps in the above method embodiment are performed.

[0235] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method steps in the above-mentioned timing optimization method embodiment are executed.

[0236] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0237] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. When the functions are realized in the form of software function units and sold or used as an independent product, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the parts that essentially contribute to the prior art or the parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0238] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A timing optimization method, characterized by, The method comprises: acquiring a timing report and a netlist, and determining a worst timing path and a number of logic stages of the worst timing path from the timing report, the timing report comprising at least one timing path, the worst timing path being a path not containing a register; determining an initial primitive relationship chain according to the worst timing path, the number of logic stages of the worst timing path, a connection relationship between primitives in the netlist, and an expected number of logic stages, the initial primitive relationship chain comprising at least one preset register, the preset register being a register with a fan-out of 1; updating the initial primitive relationship chain according to the preset register in the initial primitive relationship chain, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between primitives in the netlist, to obtain an updated primitive relationship chain; determining whether a timing delay of the updated primitive relationship chain meets a preset condition, and if so, taking the updated primitive relationship chain as a target primitive relationship chain.

2. The timing optimization method of claim 1, wherein, The determining of the initial primitive relationship chain according to the worst timing path, the number of logic stages of the worst timing path, the connection relationship between primitives in the netlist, and the expected number of logic stages comprises: determining a total number of movements of the preset register according to the number of logic stages of the worst timing path and the expected number of logic stages; determining the initial primitive relationship chain according to the total number of movements of the preset register, the connection relationship between primitives in the netlist, and a head primitive and a tail primitive in the worst timing path.

3. The timing optimization method of claim 2, wherein, The determining of the initial primitive relationship chain according to the number of preset registers, the connection relationship between primitives in the netlist, and the head primitive and the tail primitive in the worst timing path comprises: A1: taking the worst timing path as an initial candidate path and an initial pursuit path; B1: determining whether there is a new first candidate path or a new first pursuit path according to the tail primitive, the connection relationship between primitives in the netlist, and the total number of movements of the preset register, and if so, taking the new first candidate path or the new first pursuit path as a first initial relationship chain; C1: determining whether there is a new second candidate path or a new second pursuit path according to the head primitive, the connection relationship between primitives in the netlist, and the total number of movements of the preset register, and if so, taking the new second candidate path or the new second pursuit path as a second initial relationship chain; D1: obtaining the initial primitive relationship chain according to the first initial relationship chain and / or the second initial relationship chain, and stopping the loop; E1: if there is no new first candidate path, no new first pursuit path, no new second candidate path, and no new second pursuit path, then re-determining a new total number of movements of the preset register, and re-executing steps B1-E1 according to the new total number of movements until a preset loop end condition is reached.

4. The timing optimization method of claim 3, wherein, The determining whether there is a new first alternative path or a new first pursuit path according to the tail primitive, the connection relationship between the primitives in the netlist, and the total number of preset registers includes: Taking the tail primitive as a first starting point, traversing each register in the netlist according to the connection relationship between the primitives in the netlist, and determining whether the current register traversed is the preset register; If the current register is the preset register, adding the current register and the path in the module where the current register is located to the initial pursuit path to obtain a new first pursuit path, and continuing to traverse the next register of the current register until a first traversal end condition is met, and taking the new first pursuit path when the first traversal end condition is met as the first initial relationship chain, the first traversal end condition being that the number of the preset registers traversed is equal to the total number of the preset registers or the current register is a top-level port; If the current register is not the preset register, determining whether the current register meets the first traversal end condition; If the first traversal end condition is not met, continuing to traverse the next register of the current register, and determining whether there is a preset register after the current register when the first traversal end condition is met; If there is a preset register after the current register, updating the initial alternative path according to the preset register to obtain a new first alternative path.

5. The timing optimization method of claim 4, wherein, The updating the initial alternative path according to the preset register includes: Adding the path in the module where the preset register is located and each primitive before the preset register to the initial alternative path.

6. The timing optimization method of claim 1, wherein, The updating the initial primitive relationship chain according to the preset register in the initial primitive relationship chain, the expected number of logic stages, the worst timing path, the number of logic stages of the worst timing path, and the connection relationship between the primitives in the netlist to obtain an updated primitive relationship chain includes: A2: Taking the head of the initial primitive relationship chain as a starting point, determining the number of logic stages between two adjacent groups of preset registers in the initial primitive relationship chain according to the connection relationship between the primitives in the netlist; B2: Determining whether an intermediate preset register between the two adjacent groups of preset registers meets a moving condition according to the number of logic stages and the preset number of logic stages; C2: If it is determined that the moving condition is met, determining a target primitive according to the preset number of logic stages and the worst timing path, moving the intermediate preset register to before the target primitive, and determining whether the intermediate preset register is successfully moved according to the number of logic stages between the target primitive and the tail primitive of the worst timing path; D2: if the moving condition is not met or the intermediate preset register is not moved successfully, updating the intermediate preset register as a head of the initial primitive relationship chain to obtain a new head, re-executing step A2 until preset registers in the initial primitive relationship chain are traversed completely and it is determined whether a new primitive chain is obtained after the traversal is completed; E2: if the new primitive chain is obtained after the traversal is completed, taking the new primitive chain obtained after the traversal is completed as the updated primitive chain; F2: if the new primitive chain is not obtained after the traversal is completed, determining a new preset logic level number, and returning to execute step A2 according to the new preset logic level number until iteration is completed.

7. The timing optimization method of claim 6, wherein, The adjacent two groups of preset registers comprise a first preset register, a second preset register and a third preset register, and the second preset register is an intermediate preset register; The method further comprises the following steps of: obtaining a first logic level number between the first preset register and the second preset register from the netlist; obtaining a second logic level number between the second preset register and the third preset register from the netlist; adding the first logic level number and the second logic level number to obtain the logic level number sum.

8. The timing optimization method of claim 6, wherein, The method further comprises the following steps of: if the logic level number sum is less than or equal to the preset logic level number, determining that the intermediate preset register of the adjacent two groups of preset registers meets the moving condition.

9. The timing optimization method of claim 6, wherein, The method further comprises the following steps of: taking a primitive with a logic level number between a head primitive of the worst timing path and the primitive as the preset logic level number as the target primitive.

10. An electronic device, comprising: The method further comprises the following steps of: a memory and a processor, the memory storing a computer program executable by the processor, and the processor implementing the steps of the timing optimization method according to any one of claims 1-9 when executing the computer program.

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