Chip BGA coplanarity measurement method, electronic equipment and medium

Abstract

The invention discloses a chip BGA coplanarity measurement method, electronic equipment and a medium, and the method comprises the steps: obtaining chip BGA packaging height map data, and segmenting a chip BGA in a height map; the solder balls in the obtained chip BGA are segmented; performing coplanarity measurement on the segmented solder ball data through a dynamic plane fitting algorithm to obtain a measurement result, the measurement result including a coplanarity deviation value, a warping degree and a packaging overall height; according to the method, morphological parameters are dynamically adjusted, principal component analysis noise evaluation is introduced, and the plane fitting algorithm is optimized, so that the precision, efficiency and adaptability of chip BGA coplanarity measurement are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and in particular to a chip BGA coplanarity measurement method, electronic equipment and a medium. Background Art

[0002] With the rapid development of electronic manufacturing technology, ball grid array (BGA) packaging has been widely used in the field of integrated circuits due to its high density and high performance. However, the quality of BGA packaging directly affects the reliability and performance of electronic equipment, among which coplanarity and warpage are key measurement indicators. Traditional measurement methods usually rely on manual visual inspection or simple image processing technology, which has the problems of low efficiency and insufficient accuracy, and it is difficult to meet the needs of modern high-precision manufacturing.

[0003] In recent years, automatic measurement technology based on height maps has gradually become mainstream. By collecting height map data of BGA packages and combining image processing and machine learning algorithms, efficient and accurate measurement of coplanarity and warpage can be achieved.

[0004] For example, a Chinese patent document with publication number CN113052797A and application number: 2021102495776 discloses a BGA solder ball three-dimensional detection method based on deep image processing. The method uses machine vision technology to convert the collected chip point cloud into a depth map using point cloud and image processing technology, and then performs chip solder ball detection and analysis. However, this method analyzes and processes the acquired image through a fixed image processing process, and still has deficiencies in processing complex noise and dynamically adjusting parameters. It cannot be adjusted according to the specific chip situation, resulting in poor stability and adaptability of the measurement results. Summary of the invention

[0005] Technical purpose: In view of the shortcomings of existing chip BGA coplanarity detection, the present invention discloses a chip BGA coplanarity measurement method, electronic equipment and medium based on height map and dynamic plane fitting, which can adapt to different noise levels and scenarios and perform efficient detection and processing on chips.

[0006] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution: A chip BGA coplanarity measurement method, characterized by comprising the steps of: Step A, obtaining a chip BGA package height map; Step B, segmenting the chip BGA in the package height diagram; Step C, then dividing the solder balls in the obtained chip BGA; Step D: perform coplanarity measurement on the segmented solder ball data through a dynamic plane fitting algorithm, determine the reference plane for coplanarity measurement according to the position of the solder ball vertices in the segmented solder ball data, and perform coplanarity analysis by calculating the distance from the solder ball to the plane to obtain measurement results, which include coplanarity deviation value, warpage and overall package height.

[0007] Preferably, in step D of the present invention, the process of determining the reference plane for coplanarity measurement includes: Traverse all solder ball combinations in the solder ball set arranged in descending order of height, prioritize the solder ball with the highest height and group three solder balls together, make collinearity judgment for the solder balls in the same group, and select non-collinear solder balls for plane equation calculation and centroid inclusion verification; for multiple groups of solder balls that meet the conditions, take the plane determined by the group of solder balls with the worst coplanarity as the installation plane; if there is no installation plane, obtain the regression plane through weighted least squares regression plane fitting, and take the regression plane as the reference plane.

[0008] Preferably, the process of performing collinearity judgment on the same group of solder balls of the present invention includes: calculating the projection vector of the solder ball on the XY plane according to the coordinates of the solder ball, and performing collinearity judgment by vector cross product.

[0009] Preferably, the weighted least squares regression plane fitting process of the present invention includes: assigning a weight to each solder ball, the weight value is positively correlated with the height, and constructing a weighted point cloud matrix: , ,in, For the The weight value of each solder ball is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of weight changes with height; For the The vertical height of the top of the solder ball; It is the minimum value of all solder ball heights; For the The three-dimensional coordinates of the solder ball are =( , , ); is the mean vector of all solder ball coordinates, that is , n is the number of solder balls; calculate the main direction through singular value decomposition (SVD), take the vector corresponding to the minimum singular value as the normal vector a; translate the plane to make it pass through the solder ball with the highest height among all solder balls ,Right now , and use this plane as the regression plane.

[0010] Preferably, in step B of the present invention, the height map data pixel values ​​are first converted into a real height value matrix , , To encapsulate height map data, is the package height map depth, Conversion parameters for line laser measuring instruments that collect package height maps; Then the real height value matrix Perform PCA dimensionality reduction, extract the first two principal components, reconstruct the image and calculate the residual variance, and dynamically adjust the morphological parameters according to the residual variance; The chip BGA of the package height map is segmented using a chip area segmentation method with adaptive noise suppression.

[0011] Preferably, the process of reducing the dimension of the real height value matrix and adjusting the morphological parameters of the present invention includes: Step B1: Matrix the real height value Centralize and get the matrix ,in is the mean vector of all solder ball coordinates; Perform singular value decomposition to obtain the principal component direction; extract the first two principal components and reconstruct the height map matrix after dimensionality reduction ; Then calculate the residual variance; , where N is the total number of pixels in the packed height map; The noise scene is divided by setting a noise threshold, and each divided noise scene corresponds to a corresponding morphological parameter. Step B2: Compare the calculated residual variance with a preset threshold to determine the noise scene, and select corresponding morphological parameters according to the corresponding noise scene; the morphological parameters include a morphological kernel size and an iteration number; Step B3, then calculate the true height value matrix The median value ,according to With Tolerance Generate a binary mask: ; Tolerance Get the maximum value of the real height value matrix height ,Right now ; Step B4: Finally, the binary mask is subjected to morphological closing and opening operations using the morphological parameters determined in step B2 to eliminate noise and retain the complete chip area, thereby obtaining a height map of the segmented chip area.

[0012] Preferably, in step C of the present invention, the process of segmenting the solder balls in the chip BGA includes: Step C1, performing bilateral filtering on the chip area height map formed after segmentation to remove noise; Step C2: According to the height threshold Generate binary solder balls: ; in is the real height value matrix The height of the corresponding pixel in for , and The real height value matrix The mean and standard deviation of Step C3: Perform morphological closing and opening operations with a kernel size of 3×3 to fill the internal voids of the solder balls, remove small noise points, smooth the contours, and retain the complete solder ball area; extract the solder ball contours through connected domain analysis, and select valid solder balls based on area and roundness: ; Only regions with a roundness greater than the roundness threshold and an area greater than the area threshold are retained as valid solder balls.

[0013] The present invention discloses an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program so that the device executes the above-mentioned chip BGA coplanarity measurement method.

[0014] The present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, a device executing the computer program implements the above-mentioned chip BGA coplanarity measurement method.

[0015] Beneficial effects: The chip BGA coplanarity measurement method, electronic device and medium disclosed in the present invention have the following beneficial effects: 1. When segmenting the package height map, the present invention dynamically adjusts the morphological parameters according to the noise scene, and uses dynamic plane fitting to adapt to different noise levels and scene requirements, thereby ensuring the stability of the measurement results.

[0016] 2. The present invention can determine the corresponding coplanarity measurement plane according to different package height map conditions through dynamic plane fitting, thereby effectively ensuring the coplanarity and warpage measurement accuracy of the BGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0018] Figure 1 is a flow chart of the coplanarity measurement method of the present invention; Figure 2This is the collected chip BGA package height map; Figure 3 This is a schematic diagram of the result of segmenting the chip BGA; Figure 4 This is a schematic diagram of a chip BGA after segmentation; Figure 5 This is a schematic diagram of the solder ball segmentation results on a chip BGA; Figure 6 Schematic diagram of the chip BGA installation plane Figure 7 Schematic diagram of the regression fitting plane of chip BGA Figure 8 Schematic diagram of the correlation between the chip BGA mounting plane and the regression fitting plane. DETAILED DESCRIPTION

[0019] Reference will now be made in detail to embodiments of the present disclosure, one or more examples of which are set forth herein below. Each embodiment and example is provided by way of explanation of the apparatus, composition and materials of the present disclosure, rather than limitation. On the contrary, the following description provides a convenient illustration of an exemplary embodiment for implementing the present disclosure. In fact, it will be clear to those skilled in the art that various modifications and variations may be made in the teachings of the present disclosure without departing from the scope or spirit of the present disclosure.

[0020] like Figure 1 As shown, the present invention discloses a chip BGA coplanarity measurement method, which is characterized by comprising the steps of: Step A, obtaining a chip BGA package height map; The present invention uses a line laser measuring instrument to obtain the chip BGA package height map data. Figure 1 The figure below is an example of the chip BGA package height map collected. The chip BGA package height size is 3200×12000, and its depth is 16 bits, that is, the pixel value is between [0, 32767].

[0021] Step B, segment the chip BGA in the package height map; when segmenting the chip BGA, first convert the height map data pixel value into a real height value matrix , , To encapsulate height map data, is the package height map depth, is the conversion parameter of the line laser measuring instrument for collecting the package height map, which is set to 1.6 in this embodiment, and the height unit of the real height value matrix H is mm; Then, PCA dimension reduction is performed on the true height value matrix H, the first two principal components are extracted, the image is reconstructed and the residual variance is calculated, and the morphological parameters are dynamically adjusted according to the residual variance; The chip PGA of the package height map is segmented by using the chip area segmentation method with adaptive noise suppression. During segmentation, the influence of the noise scene on the segmentation result is considered, so that it can automatically adjust itself according to the set segmentation process.

[0022] The process of reducing the dimension of the real height value matrix and adjusting the morphological parameters of the present invention includes: Step B1: Matrix the real height value Centralize and get the matrix ,in is the mean vector of all solder ball coordinates; Perform singular value decomposition to obtain the principal component direction; extract the first two principal components and reconstruct the height map matrix after dimensionality reduction ; Then calculate the residual variance; , where N is the total number of pixels in the package height map, and N is numerically the product of the number of pixels in the height and width directions of the package height map; The noise scene is divided by setting a noise threshold, and each divided noise scene corresponds to a corresponding morphological parameter. Step B2: Compare the calculated residual variance with a preset threshold to determine the noise scene, and select corresponding morphological parameters according to the corresponding noise scene; the morphological parameters include a morphological kernel size and an iteration number; Specifically, the noise threshold can be obtained and set through experimental data, and the number of divisions can be adjusted according to the measurement accuracy. In the embodiment of the present invention, two groups of thresholds are set to divide the noise scene into three levels: low, medium and high. Threshold 1 = 0.001, threshold 2 = 0.01; if , it is judged as a low-noise scene, the morphological kernel size is set to 3×3, and the number of iterations is 2; if , it is judged as a medium noise scene, the morphological kernel size is set to 5×5, and the number of iterations is 3; if , it is determined to be a high noise scene, the morphological kernel size is set to 7×7, and the number of iterations is set to 4.

[0023] Step B3: Calculate the true height value matrix The median value ,according to With Tolerance Generate a binary mask: ; Tolerance Get the maximum value of the real height value matrix height ,Right now , in the present invention, the tolerance .

[0024] Step B4: Finally, the binary mask is subjected to morphological closing and opening operations using the morphological parameters determined in step B2 to eliminate noise and retain the complete chip area, and obtain a height map of the segmented chip area to form the following: Figure 3 The segmentation result is shown.

[0025] Step C, then dividing the solder balls in the obtained chip BGA; The process of segmenting the solder balls in the chip BGA includes: Step C1, performing bilateral filtering on the chip area height map formed after segmentation to remove noise; Step C2: According to the height threshold Generate binary solder balls: ; in is the real height value matrix The height of the corresponding pixel in for , and The real height value matrix The mean and standard deviation of Step C3: Perform morphological closing and opening operations with a kernel size of 3×3 to fill the internal voids of the solder balls, remove small noise points, smooth the contours, and retain the complete solder ball area; extract the solder ball contours through connected domain analysis, and select valid solder balls based on area and roundness: ; Only areas with a roundness greater than the roundness threshold and an area greater than the area threshold are retained as valid solder balls. The roundness threshold and the area threshold are set according to requirements. In this embodiment, the roundness threshold is set to 0.7, and the area threshold is 70% of the nominal solder ball size.

[0026] Step D: perform coplanarity measurement on the segmented solder ball data through a dynamic plane fitting algorithm, determine the reference plane for coplanarity measurement according to the position of the solder ball vertices in the segmented solder ball data, and perform coplanarity analysis by calculating the distance from the solder ball to the plane to obtain measurement results, which include coplanarity deviation value, warpage and overall package height.

[0027] In step D of the present invention, the process of determining the reference plane for coplanarity measurement includes: Traverse all solder ball combinations in the solder ball set arranged in descending order of height, and prioritize the solder ball with the highest height, and group three solder balls together. Perform collinearity judgment on the solder balls in the same group, and select non-collinear solder balls for plane equation calculation and centroid inclusion verification. The purpose of the centroid inclusion verification is to ensure that the plane formed by the selected three solder ball vertices can simulate the stable placement state of the chip on the ideal plane, that is, the projection of the triangle formed by the three points on the XY plane must include the projection of the centroid of the chip as a whole. The conventional verification method is: calculate the XY coordinate projection of the chip's centroid and the XY coordinate projection of the selected three solder ball vertices, and then use the judgment algorithm of the point inside the triangle, such as or the cross product method to determine whether the centroid projection falls inside the triangle formed by the three-point projection (excluding the boundary); for multiple groups of solder balls that meet the conditions, use the plane determined by the group of solder balls with the worst coplanarity as the installation plane, Figure 6 This is a plan view obtained using the installation plane method.

[0028] The process of judging the collinearity of the solder balls in the same group includes: calculating the projection vector of the solder ball on the XY plane according to the coordinates of the solder ball, and judging the collinearity by the vector cross product. Assume that the coordinates of the three solder balls in the height map coordinate system are ( , , ), ( , , ), ( , , ); Calculate the projection vector of the three points on the XY plane and ; Collinearity is determined by the absolute value of the cross product. If ,Right now and If they are collinear, then skip this combination, where is a minimum value; in this way, the solder ball that meets the requirements is selected and the installation plane is determined.

[0029] In the case where there is no installation plane, the regression plane is obtained by weighted least squares regression plane fitting, and the regression plane is used as the reference plane; the weighted least squares regression plane fitting process of the present invention includes: assigning a weight to each solder ball, the weight value is positively correlated with the height, and constructing a weighted point cloud matrix: , ,in, For the The weight value of each solder ball is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of weight changes with height; For the The vertical height of the top of the solder ball; It is the minimum value of all solder ball heights; For the The three-dimensional coordinates of the solder ball are =( , , ); is the mean vector of all solder ball coordinates, that is , n is the number of solder balls; calculate the main direction through singular value decomposition (SVD), take the vector corresponding to the minimum singular value as the normal vector a; translate the plane to make it pass through the solder ball with the highest height among all solder balls ,Right now , taking this plane as the regression plane, Figure 7 is a plane diagram obtained by using the regression plane method. Figure 8 As shown in the figure, it is the correlation between the two planes obtained by simultaneously confirming the mounting plane and the regression plane for the same chip BGA height map. It can be seen from the figure that the coplanarity calculated using the mounting plane and the regression plane method is statistically consistent and interchangeable. Therefore, when the chip BGA height map does not have a mounting plane, the regression plane can be used instead of the mounting plane for coplanarity measurement and analysis.

[0030] After obtaining the corresponding reference plane, calculate the vertical distance from the solder ball to the corresponding reference plane, and calculate the vertical distance from the solder ball to the corresponding reference plane. The total number of solder balls on the chip BGA, assuming the reference plane expression is , solder ball The perpendicular distance to the reference plane is: ; Coplanarity is defined as the difference between the maximum and minimum perpendicular distances, that is: ; In this way, coplanarity analysis can be performed based on the calculation results.

[0031] When calculating the chip BGA warpage, the sampling ratio is dynamically determined based on the total number of solder balls: ; Where n is the total number of solder balls on the chip BGA. After Solder balls, warpage is calculated by the following formula: .

[0032] The overall package height of the chip BGA is the height of the solder ball with the largest vertical distance from the substrate among all the solder balls.

[0033] The present invention also discloses an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program, so that the device executes the above-mentioned chip BGA coplanarity measurement method.

[0034] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed, a device executing the computer program implements the above-mentioned chip BGA coplanarity measurement method.

[0035] Through the description of the above implementation methods, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above-mentioned embodiment method can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium, and the memory can be various types of memory, which can be a random access memory, a read-only memory, a flash memory, etc., such as a read-only memory (ROM) / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0036] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A chip BGA coplanarity measurement method, characterized in that: Includes steps: Step A, obtaining a chip BGA package height map; Step B, segmenting the chip BGA in the package height diagram; Step C, then dividing the solder balls in the obtained chip BGA; Step D: perform coplanarity measurement on the segmented solder ball data through a dynamic plane fitting algorithm, determine the reference plane for coplanarity measurement according to the position of the solder ball vertices in the segmented solder ball data, and perform coplanarity analysis by calculating the distance from the solder ball to the plane to obtain measurement results, which include coplanarity deviation value, warpage and overall package height.

2. A chip BGA coplanarity measurement method according to claim 1, characterized in that: In step D, the process of determining the reference plane for coplanarity measurement includes: Traverse all solder ball combinations in the solder ball set arranged in descending order of height, prioritize the solder ball with the highest height and group three solder balls together, make collinearity judgment for the solder balls in the same group, and select non-collinear solder balls for plane equation calculation and centroid inclusion verification; for multiple groups of solder balls that meet the conditions, take the plane determined by the group of solder balls with the worst coplanarity as the installation plane; if there is no installation plane, obtain the regression plane through weighted least squares regression plane fitting, and take the regression plane as the reference plane.

3. A chip BGA coplanarity measurement method according to claim 2, characterized in that: The process of judging the collinearity of the solder balls in the same group includes: calculating the projection vector of the solder balls on the XY plane according to the coordinates of the solder balls, and judging the collinearity by the vector cross product.

4. A chip BGA coplanarity measurement method according to claim 2, characterized in that: The weighted least squares regression plane fitting process includes: assigning a weight to each solder ball, the weight value is positively correlated with the height, and constructing a weighted point cloud matrix: , ,in, For the The weight value of each solder ball is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of weight changes with height; For the The vertical height of the top of the solder ball; It is the minimum value of all solder ball heights; For the The three-dimensional coordinates of the solder ball are =( , , ); is the mean vector of all solder ball coordinates, that is , n is the number of solder balls; calculate the main direction through singular value decomposition (SVD), take the vector corresponding to the minimum singular value as the normal vector a; translate the plane so that it passes through the solder ball with the highest height among all solder balls ,Right now , and use this plane as the regression plane.

5. A chip BGA coplanarity measurement method according to claim 1, characterized in that: In step B, the height map data pixel values ​​are first converted into a real height value matrix , , To encapsulate height map data, is the package height map depth, Conversion parameters for line laser measuring instruments that collect package height maps; Then the real height value matrix Perform PCA dimensionality reduction, extract the first two principal components, reconstruct the image and calculate the residual variance, and dynamically adjust the morphological parameters according to the residual variance; The chip BGA of the package height map is segmented using a chip area segmentation method with adaptive noise suppression.

6. A chip BGA coplanarity measurement method according to claim 5, characterized in that: The process of reducing the dimension of the true height value matrix and adjusting the morphological parameters includes: Step B1: Matrix the real height value Centralize and get the matrix ,in is the mean vector of all solder ball coordinates; Perform singular value decomposition to obtain the principal component direction; extract the first two principal components and reconstruct the height map matrix after dimensionality reduction ; Then calculate the residual variance; , where N is the total number of pixels in the packed height map; The noise threshold is set to divide the noise scene, and each divided noise scene corresponds to the corresponding morphological parameters. Step B2: Compare the calculated residual variance with a preset threshold value to determine the noise scene, and select corresponding morphological parameters according to the corresponding noise scene; the morphological parameters include morphological kernel size and number of iterations; Step B3, then calculate the true height value matrix The median value of ,according to With tolerance Generate a binary mask: ; Tolerance Get the maximum value of the real height value matrix height ,Right now ; Step B4: Finally, the binary mask is subjected to morphological closing and opening operations using the morphological parameters determined in step B2 to eliminate noise and retain the complete chip area, thereby obtaining a height map of the segmented chip area.

7. A chip BGA coplanarity measurement method according to claim 1, characterized in that: In step C, the process of segmenting the solder balls in the chip BGA includes: Step C1, performing bilateral filtering on the chip area height map formed after segmentation to remove noise; Step C2: According to the height threshold Generate binary solder balls: ; in is the real height value matrix The height of the corresponding pixel in for , and The real height value matrix The mean and standard deviation of Step C3: Perform morphological closing and opening operations with a kernel size of 3×3 to fill the internal voids of the solder balls, remove small noise points, smooth the contours, and retain the complete solder ball area; extract the solder ball contours through connected domain analysis, and select valid solder balls based on area and roundness: ； Only regions with a roundness greater than the roundness threshold and an area greater than the area threshold are retained as valid solder balls.

8. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program so that the device executes the chip BGA coplanarity measurement method described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program. When the computer program is executed, a device executing the computer program implements a chip BGA coplanarity measurement method according to any one of claims 1 to 7.

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