Display method, video memory construction method and electronic equipment

Abstract

The embodiment of the invention provides a display method, a video memory construction method and electronic equipment, and the method comprises the steps: obtaining a current video memory descriptor, and obtaining the display data of a current frame image from a current video memory region when the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory region, and transmitting the display data of the current frame image to a display to display the image. The display of each frame of image is realized by using the function of the video memory descriptor through the hardware of the video memory controller, and the memory operation can be directly carried out on the hardware level without consuming processor resources, so that the overall overhead of the system is reduced. When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, the video memory controller acquires the display data of the current frame image corresponding to the current video memory descriptor, and the processor does not need to update the video memory address to the video memory controller, so that the overhead of the processor is further reduced; therefore, the processor can process the image more efficiently, and the image display efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to a display method, a video memory construction method and an electronic device. Background Art

[0002] As the performance requirements of embedded product systems continue to increase, more and more products are adding display screens. In the face of complex display tasks, the requirements for display performance are also getting higher and higher. In order to improve display efficiency, double buffers can be used to alternately draw and display images. While the video memory controller reads the display data of the current frame in the front buffer, the processor prepares the display data of the next frame in the back buffer.

[0003] Currently, the two buffers are mainly allocated and managed through software methods, for example, determining the size, location, and switching time of the buffers.

[0004] However, due to the limited number of video memory areas, the video memory areas need to be frequently allocated and released. Software management requires additional processor resources to perform memory management tasks, increasing processor overhead. In addition, after the current frame is displayed, the video memory controller needs to wait for the processor to update the new video memory address to the video memory controller before displaying the next frame of the image. The processor needs to calculate and update the video memory address, further increasing processor overhead. The increase in processor overhead will affect the image processing speed and image display efficiency. Summary of the invention

[0005] Embodiments of the present application provide a display method, a video memory construction method, and an electronic device to improve image display efficiency.

[0006] In a first aspect, an embodiment of the present application provides a display method, which is used in a video memory controller, and the method includes:

[0007] Obtaining a current video memory descriptor, wherein the current video memory descriptor is used to indicate whether display data of a current frame image is written into a current video memory area corresponding to the current video memory descriptor;

[0008] When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, acquiring the display data of the current frame image from the current video memory area;

[0009] The display data of the current frame image is transmitted to a display so as to display the current frame image on the display.

[0010] In a possible implementation, the current video memory descriptor includes a home bit;

[0011] When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, acquiring the display data of the current frame image from the current video memory area includes:

[0012] When the belonging bit indicates that the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor, the display data of the current frame image is obtained from the current video memory area.

[0013] In a possible implementation, the current video memory descriptor further includes a third video memory descriptor;

[0014] The method further comprises:

[0015] After the current frame image is displayed for a preset time, a video memory descriptor of a next frame image is obtained according to the third video memory descriptor.

[0016] In a possible implementation, the current video memory descriptor includes a mode bit;

[0017] The step of obtaining a video memory descriptor of a next frame of image according to the third video memory descriptor includes:

[0018] When the mode bit indicates that the video memory mode is chain video memory, the address of the video memory descriptor of the next frame image is obtained according to the third video memory description word;

[0019] When the mode bit indicates that the video memory mode is a ring video memory, a fixed offset is obtained according to the third video memory description word, and an address of a video memory descriptor of the next frame image is obtained according to the address of the current video memory descriptor and the fixed offset;

[0020] The video memory descriptor of the next frame image is obtained according to the address of the video memory descriptor of the next frame image.

[0021] In a possible implementation, the current video memory descriptor includes a display bit;

[0022] The step of acquiring a fixed offset according to the third video memory descriptor, and acquiring an address of a video memory descriptor of a next frame of image according to the address of the current video memory descriptor and the fixed offset, comprises:

[0023] When the display bit indicates that the current video memory descriptor is not the last video memory descriptor, a fixed offset is obtained according to the third video memory descriptor, and the address of the video memory descriptor of the next frame image is obtained according to the address of the current video memory descriptor and the fixed offset.

[0024] In a possible implementation, the method further includes:

[0025] When the display bit indicates that the current video memory descriptor is the last video memory descriptor, the address of the first video memory descriptor is obtained from the register as the address of the video memory descriptor of the next frame of image.

[0026] In a possible implementation, the current video memory descriptor includes a first video memory descriptor word;

[0027] The home bit, the mode bit and the display bit are located in the first video memory description word.

[0028] In a possible implementation, the current video memory descriptor includes a second video memory descriptor word;

[0029] Acquiring display data of the current frame image from the current display memory area includes:

[0030] Acquire the address of the current video memory area corresponding to the current video memory descriptor according to the second video memory description word;

[0031] The display data of the current frame image is obtained from the address of the current display memory area.

[0032] In a possible implementation, the method further includes:

[0033] After the current frame image is displayed for a preset time, the belonging bit is modified to a first value, so that the current video memory area is allowed to be updated with display data.

[0034] In a second aspect, the present application provides a method for constructing a video memory, the method being used for a processor, the method comprising:

[0035] Write the display data of the current frame image into the current video memory area corresponding to the current video memory descriptor;

[0036] The current video memory descriptor is controlled to indicate that the display data of the current frame image has been completely written into the current video memory area, so that the video memory controller obtains the display data of the current frame image from the current video memory area and controls the display to display the current frame image.

[0037] In a possible implementation, the method further includes:

[0038] Assign a corresponding video memory descriptor to each video memory area.

[0039] In a possible implementation, the current video memory descriptor includes a home bit;

[0040] The controlling the current display memory descriptor to indicate that the display data of the current frame image has been completely written into the current display memory area includes:

[0041] The home bit is modified to a first value.

[0042] In a possible implementation, the method further includes:

[0043] When the belonging bit is a second value, the display data of the current display memory area is updated.

[0044] In a third aspect, an electronic device includes: a display, a processor, a video memory controller, and a memory, wherein the memory includes a plurality of video memory areas;

[0045] The processor is used to execute the method according to the second aspect;

[0046] The video memory controller is used to execute the method described in the first aspect so that the display displays each frame of image.

[0047] The display method, video memory construction method and electronic device provided by the embodiments of the present application obtain the current video memory descriptor, which is used to indicate whether the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor. When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, the display data of the current frame image is obtained from the current video memory area, and the display data of the current frame image is transmitted to the display to display the current frame image on the display. The display of each frame image is realized by using the function of the video memory descriptor through the hardware of the video memory controller, and memory operations can be performed directly at the hardware level without consuming processor resources, thereby reducing the overall overhead of the system. And when the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, the video memory controller obtains the display data of the current frame image corresponding to the current video memory descriptor, and there is no need for the processor to update the video memory address to the video memory controller, further reducing the processor's overhead, so that the processor can process the image more efficiently and improve the image display efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0049] Figure 1 A schematic diagram of a flow chart of a display method provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of a flow chart of a display method provided in another embodiment of the present application;

[0051] Figure 3 A flowchart of a display method provided in yet another embodiment of the present application;

[0052] Figure 4A schematic diagram of a flow chart of a method for constructing a video memory according to an embodiment of the present application;

[0053] Figure 5 A schematic diagram of the correspondence between a video memory descriptor and a video memory area provided in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of the correspondence between a video memory descriptor and a video memory area provided in another embodiment of the present application;

[0055] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application.

[0056] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0057] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0058] As described in the background art, since the number of video memory areas is limited, it is necessary to frequently allocate and release video memory areas. To allocate and release video memory areas through software methods, the processor needs to perform memory management tasks. In addition, after the processor writes display data into the video memory area, the processor needs to calculate and update the video memory address, further increasing the processor overhead. The increase in processor overhead will affect the image processing speed and image display efficiency.

[0059] To this end, the present application provides a display method, which realizes the display of each frame image through the function of the video memory descriptor using the video memory controller, a hardware, and can directly perform memory operations at the hardware level, without consuming processor resources, thereby reducing the processor's overhead. When the current video memory descriptor indicates that the display data of the current frame image is written to the current video memory area, the video memory controller obtains the display data of the current frame image corresponding to the current video memory descriptor, without the processor updating the video memory address to the video memory controller, further reducing the processor's overhead, so that the processor can process the image more efficiently, and improve the image display efficiency.

[0060] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0061] Figure 1 A flow chart of the display method provided in this application, such as Figure 1 As shown, with the video memory controller as the execution subject, the method may include:

[0062] S101. Obtain a current video memory descriptor, where the current video memory descriptor is used to indicate whether display data of a current frame image is written into a current video memory area corresponding to the current video memory descriptor.

[0063] In some embodiments, the current video memory descriptor includes an ownership (OWN) bit, which is used to indicate whether the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor. It can also be understood that the ownership bit is used to indicate whether the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller.

[0064] Specifically, the ownership bit is used to indicate that the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor, that is, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller, and the video memory controller can obtain display data from the current video memory area. The ownership bit is used to indicate that the display data of the current frame image is not all written into the current video memory area corresponding to the current video memory descriptor, that is, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the processor, and the video memory controller temporarily does not obtain display data from the current video memory area.

[0065] For example, when the ownership bit is a first value, the ownership bit is used to indicate that the display data of the current frame image has been completely written into the current video memory area corresponding to the current video memory descriptor, that is, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller; when the ownership bit is a second value, the ownership bit is used to indicate that the display data of the current frame image has not been completely written into the current video memory area corresponding to the current video memory descriptor, that is, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the processor.

[0066] The first value may be, for example, 1, and the second value may be, for example, 0, that is, when the ownership bit is 1, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller, and the display data in the current video memory area corresponding to the current descriptor is valid data to be displayed; when the ownership bit is 0, the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the processor, and the display data in the current video memory area corresponding to the current video memory descriptor is invalid data. The first value may also be 0, and the second value may be 1.

[0067] It should be noted that there are two main methods for implementing video memory, one is chain video memory and the other is ring video memory.

[0068] Since the video memory controller needs to frequently access the video memory descriptors, in order to improve the efficiency of the video memory controller accessing the video memory descriptors, the video memory descriptors can be placed in the random access memory (RAM). When the number of video memory descriptors is large and the space occupied is large, and the space of the random access memory is limited or discontinuous, linked video memory can be used. Linked video memory allows the video memory descriptors to be stored in different memory blocks in a dispersed manner without the need for continuous memory space, thereby making more efficient use of limited random access memory resources.

[0069] Ring memory searches for the next memory descriptor by offsetting fixed bytes, while chain memory needs to access the contents of the memory descriptor to determine the address of the next memory descriptor and then access it. Therefore, ring memory consumes less time and has high efficiency.

[0070] Therefore, in some embodiments, the current video memory descriptor may include a mode (Second Address Chained, SAC) bit, and the mode bit is used to indicate whether the video memory mode is chained video memory or ring video memory. For example, when the mode bit is a first value, the mode bit is used to indicate that the video memory mode is chained video memory, and when the mode bit is a second value, the mode bit is used to indicate that the video memory mode is ring video memory.

[0071] In a specific implementation, the current video memory descriptor includes a display bit, and the display bit is used to indicate whether the current video memory descriptor is the last video memory descriptor.

[0072] In some examples, the current video memory descriptor may include a first video memory descriptor word, and the home bit, the mode bit, and the display bit are located in the first video memory descriptor word.

[0073] In other examples, the home bit, mode bit, and display bit may also be located in other video memory descriptor words.

[0074] Table 1

[0075]

[0076] In some specific implementations, as shown in Table 1, the first video memory description word may also include any of the following bits:

[0077] Display interrupt enable (DIE) bit: used to enable frame display interrupt. If this bit is set to 1 and the video memory controller turns on the frame display end interrupt, the video memory controller will trigger the video memory controller frame display end interrupt after displaying the frame image pointed to by the descriptor. The frame display end interrupt (Frame End Interrupt) is an interrupt signal sent by the display controller to the processor after completing the display of a frame of image. The interrupt signal is used to notify the processor that the display of the current frame has been completed and the next operation can be performed.

[0078] Mode (second address chained, SAC) bit: used to configure the video memory mode. When this bit is set to 1, the video memory mode is configured as chained video memory, and the third video memory descriptor word points to the address of the next video memory descriptor; when this bit is set to 0, the video memory mode is configured as ring video memory, and the third video memory descriptor word is invalid or indicates a fixed offset.

[0079] Display end of ring (DER) bit: used to indicate the last descriptor in ring memory mode. When this bit is 1, it means that the current descriptor is the last one in the ring memory. When LCDC reads the last memory space of the ring memory, it will jump to the first memory space to check the descriptor word, and then cycle.

[0080] Data pixels sequence (DPS) bit: used to configure the big-endian and little-endian format of pixel data.

[0081] Pixel alpha mode (PAM) bit: used to configure the pixel transparency mode of the video memory area pointed to by the current descriptor. When this bit is set to 1, the pixel transparency is determined by the ABV[23:16] bit field. When it is set to 0, the pixel transparency is determined by the transparency value of each pixel.

[0082] Transparency enable (apha mode enable, AME) bit: used to enable image transparency. When this bit is set to 1, image transparency display is enabled.

[0083] Byte order (pixels alpha swap, PAS) bit: used to configure the byte order of the ARGB pixel format. When this bit is set to 1, it is the ARBG format, and when it is cleared to 0, it is the RGBA format. Among them, the ARGB format represents the order of Alpha (transparency), Red (red), Green (green), and Blue (blue) channels. The RGBA format represents the order of Red (red), Green (green), Blue (blue), and Alpha (transparency) channels.

[0084] Alpha blending value (ABV) bit: used to configure the transparency value.

[0085] Pixel format (image data format, IDF) bit: used to configure the pixel format of the image, for example, it can be as follows:

[0086] 000: ARGB888

[0087] 001: RGB888 / 666

[0088] 010: RGB565

[0089] 011: RGB555

[0090] 100:8BPP

[0091] 101:4BPP

[0092] 110:2BPP

[0093] 111:1BPP.

[0094] For example, as shown in Table 1, a reserved bit may also be included, which is used to assign a corresponding meaning to the bit according to actual conditions.

[0095] In some embodiments, the current memory descriptor includes a second memory descriptor word, which is used to indicate the address of the current memory area corresponding to the current memory descriptor. The second memory descriptor word may include a display buffer address pointer (DBAP, DBAP) bit.

[0096] Table 2

[0097]

[0098] As shown in Table 2, the video memory region address pointing bit is used to point to the address of the video memory region corresponding to the current video memory descriptor.

[0099] In some embodiments, the current video memory descriptor includes a third video memory descriptor word, which is used to indicate the address of the next video memory descriptor when the video memory mode is chained video memory. The third video memory descriptor word may, for example, include a Next Discreption Address Pointer (NDAP).

[0100] Table 3

[0101]

[0102] As shown in Table 3, the next descriptor address pointer bit is used to indicate the address of the next video memory descriptor. The third video memory descriptor can also be used to indicate a fixed offset when the video memory mode is a ring video memory.

[0103] In other embodiments, the third video memory descriptor is invalid when the video memory mode is ring video memory, and the video memory controller can obtain and store a fixed offset in advance, and obtain the address of the next video memory descriptor according to the fixed offset and the address of the current video memory descriptor.

[0104] In some embodiments, when the current video memory descriptor is the first video memory descriptor, the first address of the first video memory descriptor can be obtained from the register.

[0105] In actual applications, before enabling the video memory controller, the user can initialize each video memory descriptor in advance according to the meaning of each bit field of the descriptor as needed.

[0106] S102 . When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, the display data of the current frame image is obtained from the current video memory area.

[0107] In some embodiments, when the attribution bit in the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor, the display data of the current frame image is obtained from the current video memory area. When the attribution bit in the current video memory descriptor indicates that the display data of the current frame image is not fully written into the current video memory area corresponding to the current video memory descriptor, the video memory controller can stop working and continue to control the display to display the previous frame image until the processor modifies the attribution bit of the current video memory descriptor to indicate that the display data of the current frame image is fully written into the current video memory area, and then obtains the display data of the current frame image from the current video memory area. The ownership of the current video memory area is managed according to the attribution bit to ensure that the video memory controller will not access the unprepared display data in the current video memory area before the processor completely writes the display data into the current video memory area. In the case of multi-tasking or abnormal planning in the system, buffer space is provided for the display control of the video memory controller, reducing the risk of display frame drops in the display control of the video memory controller and reducing system interruption overhead.

[0108] In some embodiments, when the current video memory descriptor indicates that the display data of the current frame image is written to the current video memory area, the address of the current video memory area corresponding to the current video memory descriptor can be obtained according to the second video memory descriptor in the current video memory descriptor, and the display data of the current frame image can be obtained from the address of the current video memory area, thereby enabling the display data of the current frame image to be obtained more quickly.

[0109] S103: Transmit the display data of the current frame image to the display, so as to display the current frame image on the display.

[0110] In this embodiment, after the display memory controller obtains the display data of the current frame image, it transmits the display data of the current frame image to the display so that the current frame image can be displayed on the display. For example, the display data can be output to an externally connected display interface.

[0111] The display method provided by the present application realizes the display of each frame image by using the function of the video memory descriptor through the video memory controller, which is hardware, and can directly perform memory operations at the hardware level without consuming processor resources, thereby reducing the overall system overhead. Moreover, when the current video memory descriptor indicates that the display data of the current frame image is written to the current video memory area, the video memory controller obtains the display data of the current frame image corresponding to the current video memory descriptor, without the need for the processor to update the video memory address to the video memory controller, further reducing the processor overhead, enabling the processor to process the image more efficiently, and improving the image display efficiency.

[0112] Figure 2 A flow chart of a display method provided in another embodiment of the present application is shown in FIG. Figure 2 As shown, after step S103, the following steps are also included:

[0113] S104 . After the current frame image is displayed for a preset time, a video memory descriptor of the next frame image is obtained according to the third video memory descriptor.

[0114] For example, the preset time may be determined according to the display time required for the frame image.

[0115] In some examples, when the mode bit in the current video memory descriptor indicates that the video memory mode is chain video memory, the address of the video memory descriptor of the next frame image is obtained according to the third video memory descriptor in the current video memory descriptor; when the mode bit in the current video memory descriptor indicates that the video memory mode is ring video memory, the fixed offset is obtained according to the third video memory descriptor, and the address of the video memory descriptor of the next frame image is obtained according to the address of the video memory descriptor of the next frame image and the fixed offset. Then, the video memory descriptor of the next frame image is obtained according to the address of the video memory descriptor of the next frame image, so that the display data of the next frame image can be obtained.

[0116] For example, the first address of the video memory descriptor of the next frame image can be determined based on the first address of the current video memory descriptor and the address bits required by the current video memory descriptor, and the address of the video memory descriptor of the next frame image can be determined based on the first address of the video memory descriptor of the next frame image and the address bits required by the video memory descriptor of the next frame image.

[0117] In a specific implementation, the current video memory descriptor includes a display bit, and the display bit is used to indicate whether the current video memory descriptor is the last video memory descriptor. When the display bit indicates that the current video memory descriptor is not the last video memory descriptor, a fixed offset is obtained according to a third video memory descriptor word, and the address of the video memory descriptor of the next frame image is obtained according to the address of the current video memory descriptor and the fixed offset.

[0118] In a specific implementation, when the display bit indicates that the current video memory descriptor is the last video memory descriptor, the address of the first video memory descriptor is obtained from the register as the address of the video memory descriptor of the next frame of image.

[0119] For example, the display bit may be located in the first display memory description word.

[0120] In some embodiments, after the current frame image is displayed for a preset time, the belonging bit is modified to a first value so that the current display area allows the display data to be updated. At this time, the processor can update the display data of the current video memory area.

[0121] The display method provided by the present application obtains the video memory descriptor of the next frame image according to the third video memory descriptor after the current frame image is displayed for a preset time, that is, after the current frame image is displayed, so that the display data of the next frame image can be obtained according to the video memory descriptor of the next frame image, thereby being able to display the next frame image.

[0122] Figure 3 A flow chart of a display method provided in another embodiment of the present application is shown in FIG. Figure 3 As shown, with the display controller as the execution subject, the display method provided in this embodiment may include:

[0123] S201: The video memory controller obtains a current video memory descriptor.

[0124] For example, when the current video memory descriptor is the first video memory descriptor, the address of the first video memory descriptor can be obtained from the register. When the current video memory descriptor is not the first video memory descriptor, the current video memory descriptor is obtained according to the previous video memory descriptor.

[0125] For example, the address of the video memory descriptor may be user-configurable.

[0126] S202: Determine whether the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller.

[0127] For example, the state of the ownership bit in the first video memory descriptor in the current video memory descriptor can be determined. When the ownership bit is a first value, it indicates that the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the video memory controller, that is, the processor has written all the display data of the current frame image into the video memory area corresponding to the current video memory descriptor. When the ownership bit is a second value, it indicates that the ownership of the current video memory area corresponding to the current video memory descriptor belongs to the processor. At this time, the processor has not written all the display data of the current frame image into the current video memory area corresponding to the current video memory descriptor. The video memory controller can stop working until the processor gives the ownership of the current video memory area to the video memory controller.

[0128] For example, when the first value is 1, the second value is 0; when the first value is 0, the second value is 1.

[0129] For example, the processor modifies the ownership bit to a first value, indicating that the processor gives the ownership right of the current video memory region to the video memory controller.

[0130] If yes, go to step S203, if no, go to step S209.

[0131] S203 , obtaining the address of the current video memory area according to the second video memory description word in the current video memory descriptor, and obtaining display data of the current frame image according to the address of the current video memory area.

[0132] S204: Send the display data of the current frame image to the display, so as to display the display data of the current frame image on the display.

[0133] S205: After the current frame image is displayed, the video memory controller returns the ownership of the current video memory area to the processor, and determines whether the video memory mode is chain video memory or ring video memory according to the mode bit in the current video memory descriptor.

[0134] For example, the video memory controller may modify the ownership bit to 0 to return the ownership of the current video memory region to the processor.

[0135] For example, when the mode bit in the current video memory descriptor is 1, the video memory mode is chain video memory, when the mode bit in the current video memory descriptor is 0, the video memory mode is ring video memory, or, when the mode bit is 0, the video memory mode is chain video memory, when the mode bit is 1, the video memory mode is ring video memory.

[0136] When the mode bit in the current video memory descriptor indicates that the video memory mode is chain video memory, step S206 is executed; when the mode bit in the current video memory descriptor indicates that the video memory mode is ring video memory, step S207 is executed.

[0137] S206: When the video memory mode is chained video memory, the video memory controller obtains the address of the next video memory descriptor according to the third video memory descriptor in the current video memory descriptor, and returns the ownership of the current video memory descriptor to the processor.

[0138] Then, step S202 may be continued to be executed to sequentially display the image data corresponding to each display descriptor.

[0139] It should be noted that after the ownership of the current video memory descriptor is returned to the processor, the processor can update the display data in the current video memory area corresponding to the current video memory descriptor.

[0140] In this embodiment, after the current frame image is displayed, the ownership of the current descriptor will be returned to the processor, and the address of the next video memory descriptor will be determined based on the third video memory descriptor. By continuing to execute step S202, the address of the video memory area where the display data of the next frame image is located can be obtained, and then the display data of the next frame image can be obtained and the next frame image can be displayed.

[0141] It should be noted that when the video memory controller traverses to the last video memory descriptor in the chain, the third video memory descriptor word of the last video memory descriptor points to the address of the first descriptor, so that the video memory controller can continue to traverse from the first video memory descriptor.

[0142] S207: When the video memory mode is the ring video memory, the video memory controller returns the ownership of the current video memory descriptor to the processor, and determines whether the current video memory descriptor is the last video memory descriptor.

[0143] If yes, go to step S208, if no, go to step S209.

[0144] S208. When the current video memory descriptor is the last video memory descriptor, obtain the first video memory descriptor from the register as the next video memory descriptor.

[0145] Then, execute step S202.

[0146] In this embodiment, after the current frame image is displayed, the ownership of the current descriptor will be returned to the processor, and a fixed offset will be added to the address of the current descriptor to determine the address of the next video memory descriptor, and step S202 can be continued to obtain the address of the video memory area where the display data of the next frame image is located, and then the display data of the next frame image is obtained and the next frame image is displayed. When the last video memory descriptor of the ring video memory is traversed, the video memory descriptor starts to traverse again from the first video memory descriptor.

[0147] S209: When the current video memory descriptor is not the last video memory descriptor, add a fixed offset to the first address of the current video memory descriptor to obtain the address of the next video memory descriptor.

[0148] For example, the fixed offset may be the three video memory description words mentioned above, namely, the first video memory description word, the second video memory description word and the third video memory description word.

[0149] Then, step 202 is executed to sequentially display the image data corresponding to each display descriptor.

[0150] S210: The video memory controller stops working until the processor gives the ownership of the current video memory area to the video memory controller.

[0151] Then, execute step S203.

[0152] It should be noted that after the last frame of image is displayed, step S202 is stopped.

[0153] In the data processing method provided in the embodiment of the present application, the video memory controller displays the frame images pointed to by each video memory descriptor in sequence, and the processor only needs to continuously update each video memory area. Compared with the multi-buffer mechanism implemented by software, the processor does not need to determine when the video memory controller has finished displaying, nor does it need to configure the address of the video memory space each time, thereby improving display efficiency.

[0154] Figure 4 A flowchart of a method for constructing a video memory according to an embodiment of the present application is shown in FIG. Figure 4 As shown, with the processor as the execution subject, the video memory construction method of this embodiment includes the following steps:

[0155] S301, writing display data of the current frame image into the current video memory area corresponding to the current video memory descriptor.

[0156] S302: Control the current video memory descriptor to indicate that the display data of the current frame image has been written into the current video memory area, so that the video memory controller obtains the display data of the current frame image from the current video memory area and controls the display to display the current frame image.

[0157] In some embodiments, a corresponding video memory descriptor may be allocated to each video memory region, so that display data may be obtained from the corresponding video memory region based on the video memory descriptor.

[0158] The video memory descriptor may include a first video memory descriptor, a second video memory descriptor, and a third video memory descriptor. The first video memory descriptor includes a home bit, a mode bit, and a display bit. The home bit is used to indicate whether the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor. The mode bit is used to indicate whether the video memory mode is chain video memory or ring video memory. The display bit is used to indicate whether the current video memory descriptor is the last video memory descriptor.

[0159] When the mode bit indicates that the video memory mode is chain video memory, the third video memory description word is used to indicate the address of the next descriptor. When the mode bit indicates that the video memory mode is ring video memory, the third video memory description word is invalid.

[0160] For example, Figure 5 and Figure 6 As shown, Figure 5 This is a schematic diagram of chained video memory. Figure 6 The schematic diagram of the ring memory is shown in Figure 1. Figure 5 The previous video memory descriptor points to the next video memory descriptor. Figure 6 There is no pointing relationship between the video memory descriptors.

[0161] In some embodiments, the current video memory descriptor includes a home bit, and the home bit can be modified to a second value to indicate that the display data of the current frame has been completely written into the current video memory area.

[0162] In some embodiments, after display data of the current frame image is displayed, the video memory controller modifies the home bit to a second value to indicate that the current video memory area allows the display data to be updated. When the home bit is the second value, the processor can update the display data of the current video memory area.

[0163] In actual applications, the processor can first fill the display data in each video memory area in the memory and update the corresponding video memory descriptor in the initialization phase, and then the processor can configure the information of the video memory descriptor in the register. Then the video memory controller can be enabled, and after the video memory controller is enabled, the address of the first video memory descriptor can be obtained from the register.

[0164] The video memory construction method provided in the present application enables the processor to update the display data in the video memory area corresponding to the video memory descriptor to realize the display of multiple frames of images.

[0165] The present application also provides an electronic device, such as Figure 7 As shown, it includes: a display 703, a processor 701, a video memory controller 702 and a memory 704, and the memory 704 includes multiple video memory areas;

[0166] Processor 701, used to execute the above-mentioned video memory construction method;

[0167] The video memory controller 702 is used to execute the above display method to display each frame of image on the display 703 .

[0168] For example, each video memory region has a corresponding video memory descriptor. For example, n video memory regions are included, which correspond to one of video memory descriptor 0 to video memory descriptor n in sequence.

[0169] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0170] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0171] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0172] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0173] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0174] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0175] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0176] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0177] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0178] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A display method, characterized in that: The method is used for a video memory controller, and the method comprises: Obtaining a current video memory descriptor, wherein the current video memory descriptor is used to indicate whether display data of a current frame image is written into a current video memory area corresponding to the current video memory descriptor; When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, acquiring the display data of the current frame image from the current video memory area; The display data of the current frame image is transmitted to a display so as to display the current frame image on the display.

2. The method according to claim 1, characterized in that The current video memory descriptor includes a home bit; When the current video memory descriptor indicates that the display data of the current frame image is written into the current video memory area, acquiring the display data of the current frame image from the current video memory area includes: When the belonging bit indicates that the display data of the current frame image is written into the current video memory area corresponding to the current video memory descriptor, the display data of the current frame image is obtained from the current video memory area.

3. The method according to claim 2, characterized in that The current video memory descriptor also includes a third video memory description word; The method further comprises: After the current frame image is displayed for a preset time, a video memory descriptor of a next frame image is obtained according to the third video memory descriptor.

4. The method according to claim 3, characterized in that The current video memory descriptor includes a mode bit; The step of obtaining a video memory descriptor of a next frame of image according to the third video memory descriptor includes: When the mode bit indicates that the video memory mode is chain video memory, the address of the video memory descriptor of the next frame image is obtained according to the third video memory description word; When the mode bit indicates that the video memory mode is a ring video memory, a fixed offset is obtained according to the third video memory description word, and an address of a video memory descriptor of the next frame image is obtained according to the address of the current video memory descriptor and the fixed offset; The video memory descriptor of the next frame image is obtained according to the address of the video memory descriptor of the next frame image.

5. The method according to claim 4, characterized in that The current video memory descriptor includes display bits; The step of acquiring a fixed offset according to the third video memory descriptor, and acquiring an address of a video memory descriptor of a next frame of image according to the address of the current video memory descriptor and the fixed offset, comprises: When the display bit indicates that the current video memory descriptor is not the last video memory descriptor, a fixed offset is obtained according to the third video memory descriptor, and the address of the video memory descriptor of the next frame image is obtained according to the address of the current video memory descriptor and the fixed offset.

6. The method according to claim 5, characterized in that The method further comprises: When the display bit indicates that the current video memory descriptor is the last video memory descriptor, the address of the first video memory descriptor is obtained from the register as the address of the video memory descriptor of the next frame of image.

7. The method according to claim 6, characterized in that The current video memory descriptor includes a first video memory descriptor word; The home bit, the mode bit and the display bit are located in the first video memory description word.

8. The method according to claim 1, characterized in that The current video memory descriptor includes a second video memory descriptor word; Acquiring display data of the current frame image from the current display memory area includes: Acquire the address of the current video memory area corresponding to the current video memory descriptor according to the second video memory description word; The display data of the current frame image is obtained from the address of the current display memory area.

9. The method according to any one of claims 2 to 7, characterized in that: The method further comprises: After the current frame image is displayed for a preset time, the belonging bit is modified to a first value, so that the current video memory area is allowed to be updated with display data.

10. A method for constructing video memory, characterized in that: The method is used for a processor, and the method comprises: Write the display data of the current frame image into the current video memory area corresponding to the current video memory descriptor; The current video memory descriptor is controlled to indicate that the display data of the current frame image has been completely written into the current video memory area, so that the video memory controller obtains the display data of the current frame image from the current video memory area and controls the display to display the current frame image.

11. The method according to claim 10, characterized in that The method further comprises: Assign a corresponding video memory descriptor to each video memory area.

12. The method according to claim 10, characterized in that The current video memory descriptor includes a home bit; The controlling the current display memory descriptor to indicate that the display data of the current frame image has been completely written into the current display memory area includes: The home bit is modified to a first value.

13. The method according to claim 12, characterized in that The method further comprises: When the belonging bit is a second value, the display data of the current display memory area is updated.

14. An electronic device, characterized in that: include: A display, a processor, a video memory controller and a memory, wherein the memory includes a plurality of video memory areas; The processor is configured to execute the method of any one of claims 10 to 13; The video memory controller is used to execute the method described in any one of claims 1 to 9, so that the display displays each frame of image.

Images