Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The display panel comprises a plurality of sub-pixels, each of which comprises a light emitting element and a pixel circuit electrically connected to each other. The pixel circuit comprises a driving transistor for generating a driving current according to a data signal to drive the light emitting element to emit light. A gate of the driving transistor is electrically connected to a first node or connected to the first node through a first capacitor. The pixel circuit further comprises a data write transistor and a first reset transistor electrically connected to the first node and used for transmitting the data signal and a first reset signal. The driving transistor is an oxide transistor, so as to reduce power consumption of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display panels and their driving methods. Background Technology

[0002] AMOLED (Active-Matrix Organic Light-Emitting Diode) display panels have advantages such as fast response speed, high contrast, and wide viewing angle.

[0003] In AMOLED display panels, the driving transistors in the traditional pixel circuits are generally LTPS TFT (Low Temperature Poly-Silicon) transistors, which leads to disadvantages such as high power consumption in AMOLED display panels. Summary of the Invention

[0004] This invention provides a display panel and a driving method thereof to reduce the power consumption of AMOLED display panels.

[0005] This invention provides a display panel including a plurality of sub-pixels. Each sub-pixel includes an electrically connected light-emitting element and a pixel circuit. The pixel circuit includes:

[0006] A driving transistor is used to generate a driving current according to a data signal to drive the light-emitting element to emit light. The driving transistor is an oxide transistor, and the gate of the driving transistor is electrically connected to a first node or connected to the first node through a first capacitor.

[0007] A data writing transistor is electrically connected to the first node for transmitting the data signal;

[0008] The first reset transistor is electrically connected to the first node and is used to transmit the first reset signal.

[0009] This invention also provides a driving method for a display panel, applied to any of the display panels described above, comprising:

[0010] The first reset transistor is turned on so that it transmits the first reset signal to the first node.

[0011] The data writing transistor is controlled to turn on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, thereby turning on the driving transistor;

[0012] The driving transistor is controlled to generate a driving current according to the data signal to drive the light-emitting element to emit light.

[0013] This invention provides a display panel and its driving method, comprising a plurality of sub-pixels. Each sub-pixel includes an electrically connected light-emitting element and a pixel circuit. The pixel circuit includes a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light. The gate of the driving transistor is electrically connected to a first node or connected to the first node through a first capacitor. The pixel circuit also includes a data writing transistor and a first reset transistor electrically connected to the first node and respectively used to transmit the data signal and a first reset signal. The driving transistor is an oxide transistor, which at least reduces the power consumption of the display panel. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the display panel architecture provided in an embodiment of the present invention.

[0015] Figure 2 and Figure 3 This is a schematic diagram of the pixel circuit provided in an embodiment of the present invention.

[0016] Figure 4 A flowchart of a display panel driving method provided in an embodiment of the present invention.

[0017] Figure 5 and Figure 6 They are respectively Figure 2 and Figure 3 The waveform diagram of some signals in the pixel circuit. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In this document, the source and drain of a transistor are not distinguished and can be interchanged. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the attached drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] The present invention provides a display panel, which includes, but is not limited to, the following embodiments and combinations thereof.

[0022] In some embodiments, combined with Figures 1 to 3 As shown, the display panel 100 includes a plurality of sub-pixels 101. Each sub-pixel 101 includes an electrically connected light-emitting element Di and a pixel circuit 1011. The pixel circuit 1011 includes: a driving transistor T1, used to generate a driving current according to a data signal Data to drive the light-emitting element Di to emit light. The driving transistor T1 is an oxide transistor, and the gate of the driving transistor T1 is electrically connected to a first node P (not shown in this case) or connected to the first node P through a first capacitor C1; a data writing transistor T7, electrically connected to the first node P, used to transmit the data signal Data; and a first reset transistor T8, electrically connected to the first node P, used to transmit a first reset signal VI1.

[0023] The display panel 100 can be a self-emissive display panel, that is, the display panel 100 displays images through the self-emissive light-emitting element Di in the sub-pixel 101.

[0024] Specifically, such as Figure 1 As shown, the display panel 100 may further include cascaded multi-stage gate driving units (forming a gate driving circuit 102); a timing controller 201, each of the gate driving units being electrically connected between the timing controller 201 and the corresponding plurality of pixel circuits 1011, for outputting a gate signal Gate transmitted to the corresponding plurality of pixel circuits 1011; and at least one source driver 202, each of the source drivers 202 being electrically connected between the timing controller 201 and the corresponding plurality of pixel circuits 1011, for outputting the aforementioned data signal Data transmitted to the corresponding plurality of pixel circuits 1011. The display panel 100 may include an electrically connected panel body 10 and a driving chip 20. The panel body 10 has the aforementioned gate driving circuit 102 and a plurality of sub-pixels 101 disposed on its substrate, and the driving chip 20 may include the timing controller 201 and the source driver 202.

[0025] For ease of description, this example uses multiple sub-pixel 101 arrays arranged in n rows and m columns (n ​​and m are both positive integers).

[0026] The gate drive circuit 102 may include at least n levels of gate drive units, such as Figure 1 As shown, each gate driving unit outputs a corresponding gate signal Gate according to the first control signal provided by the timing controller 201. The n-level gate signals are transmitted to the n-row sub-pixels 101 through n gate lines (GL1 to GLn). The n gate pulses in the n-level gate signals used to turn on the n-row sub-pixels 101 can be arranged sequentially on the time axis to turn on multiple rows of sub-pixels 101 in sequence.

[0027] The source driver 202 can generate m data signals Data through m data lines (DL1 to DLm) to output to m columns of sub-pixels 101 respectively according to the second control signal provided by the timing controller 201. Each data signal Data can include n data voltages corresponding to n sub-pixels 101 in the same column. When each row of sub-pixels 101 is turned on, the multiple data lines receive multiple data voltages of multiple sub-pixels 101 in that row, so that the multiple data voltages act on the multiple sub-pixels 101 in that row to realize the light emission of multiple light-emitting elements Di in the multiple sub-pixels 101 in that row. In this way, the light-emitting elements Di of all rows can be controlled to emit light in sequence to present a complete picture.

[0028] As discussed above, in this embodiment, the data writing transistor T7 in each pixel circuit 1011 transmits a data signal Data to the gate of the driving transistor T1 through the first node P. The driving transistor T1 then generates a corresponding driving current based on the data voltage in the data signal Data to drive the corresponding light-emitting element Di to emit light. The gate signal Gate of each stage can act on, but is not limited to, the data writing transistor T7 and the first reset transistor T8 in the corresponding row of pixel circuits 1011, to achieve at least one of transmitting the data signal Data to the gate of the driving transistor T1 during a corresponding time period or generating a corresponding driving current during a corresponding time period.

[0029] Understandably, in this embodiment, the driving transistor T1 used to generate the driving current is an oxide transistor. On the one hand, it has a low leakage rate, which reduces the potential change of its gate due to leakage, thus reducing the risk of screen flicker. On the other hand, the threshold voltage of the driving transistor T1 has a small hysteresis effect, which improves the afterimage phenomenon. Furthermore, the operating voltage of the driving transistor T1 is small, which reduces the power consumption of the display panel 100. Moreover, the oxide transistor has high process uniformity, which improves the uniformity of the screen display.

[0030] In some embodiments, such as Figure 2 As shown, both the data writing transistor T7 and the first reset transistor T8 are oxide transistors. As discussed above, since both the data writing transistor T7 and the first reset transistor T8 are directly or indirectly connected to the gate of the driving transistor T1 through the first node P, they affect the potential of the gate of the driving transistor T1 by influencing the potential of the first node P, thus affecting the magnitude of the driving current. Similarly, to reduce the significant leakage of charge from the first node P through at least one of the data writing transistor T7 and the first reset transistor T8, this embodiment also uses oxide transistors for both, thereby reducing the impact on the luminous brightness of the light-emitting element Di.

[0031] In some embodiments, such as Figure 3 As shown, both the data writing transistor T7 and the first reset transistor T8 are low-temperature polysilicon transistors. It is understood that in this embodiment, considering that the driving transistor T1 already has a low leakage rate, and further considering the high electron mobility of low-temperature polysilicon (i.e., electrons move faster between the two), both the data writing transistor T7 and the first reset transistor T8 are set to be low-temperature polysilicon, thereby accelerating the transmission speed of the data signal Data and the first reset signal VI1 to the first node P, and thus accelerating the response speed of the display panel 100.

[0032] Based on this, such as Figure 3 As shown, the pixel circuit 1011 further includes a transfer transistor T9, electrically connected between the data writing transistor T7, the first reset transistor T8, and the first node P. The transfer transistor T9 is an oxide transistor. It is understood that, based on the fact that both the data writing transistor T7 and the first reset transistor T8 are low-temperature polysilicon, a transfer transistor T9, an oxide transistor, is further configured between them and the first node P. Since the transfer transistor T9 has a low leakage rate, it can also reduce the risk of significant charge leakage from the first node P through at least one of the data writing transistor T7 and the first reset transistor T8.

[0033] Of course, one of the data writing transistor T7 and the first reset transistor T8 can be an oxide transistor, and the other can be a low-temperature polysilicon transistor. As discussed above, having an oxide transistor in either T7 or T8 can prevent significant charge leakage from the first node P through its path, while having a low-temperature polysilicon transistor in either T7 or T8 can accelerate the transmission of the data signal Data or the first reset signal VI1 to the first node P, thereby speeding up the response of the display panel 100.

[0034] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a compensation transistor T3, electrically connected between the gate of the driving transistor T1 and one of the source and drain of the driving transistor T1; and a second reset transistor T4, electrically connected to one of the anode and cathode of the light-emitting element Di, for transmitting a second reset signal VI2 to one of the anode and cathode of the light-emitting element Di; wherein at least one of the compensation transistor T3 and the second reset transistor T4 is an oxide transistor.

[0035] Since the compensation transistor T3 is electrically connected between the gate and one of the source and drain of the driving transistor T1 (taking the case where the compensation transistor T3 is electrically connected to the drain of the driving transistor T1 as an example), the charge between the gate and source of the driving transistor T1 will be transferred through the compensation transistor T3, thus changing their potentials and affecting the magnitude of the driving current. Furthermore, since the second reset transistor T4 is electrically connected to one of the anode and cathode of the light-emitting element Di (taking the case where the second reset transistor T4 is electrically connected to the anode of the light-emitting element Di as an example), the charge at the anode of the light-emitting element Di will also leak through the second reset transistor T4, thus affecting the anode potential of the light-emitting element Di and consequently affecting the brightness of the light-emitting element Di.

[0036] Therefore, in this embodiment, at least one of the compensation transistor T3 and the second reset transistor T4 is set as an oxide transistor, which can reduce the potential change of at least one of the gate, source and drain of the driving transistor T1, thereby reducing the impact on the brightness of the light-emitting element Di.

[0037] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes a second capacitor C2, the first plate of which is electrically connected to a first power line (for transmitting a first power signal VDD), and the second plate of which is electrically connected to the first node P. The first power signal VDD transmitted by the first power line is a constant voltage signal; therefore, when the first node P is in a floating state, the second capacitor C2 can maintain the stability of the potential of the first node P.

[0038] Specifically, when the pixel circuit 1011 includes a first capacitor C1, such as Figure 2 and Figure 3As shown, the first capacitor C1 can be used to maintain the stability of the voltage difference between the first node P and the gate of the driving transistor T1 (i.e., the second node Q). When the potential of one of them changes, due to the voltage stabilization effect of the first capacitor C1, or what can be understood as the coupling effect, the potential of the other one will also change in the same way. When the pixel circuit 1011 does not include the first capacitor C1, it differs from... Figure 2 and Figure 3 As shown, the potentials of the second node Q and the first node P are the same. At this time, the data signal Data and the first reset signal VI1 can be directly transmitted to the gate of the driving transistor T1, and the second capacitor C2 can also directly maintain the stability of the potential of the second node Q.

[0039] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes: a first switching transistor T6, electrically connected between the source and drain of the driving transistor T1 and the anode and cathode of the light-emitting element Di; and a third reset transistor T2, electrically connected between the source and drain of the driving transistor T1 and the first switching transistor T6, for transmitting a third reset signal VI3 to the source and drain of the driving transistor T1. The example provided illustrates this by having the first switching transistor T6 and the third reset transistor T2 electrically connected to the source of the driving transistor T1.

[0040] Understandably, in this embodiment, by setting a first switching transistor T6 between the light-emitting element Di and the driving transistor T1, the potential of the drain of the driving transistor T1 and the potential of the anode of the light-emitting element Di can be isolated when the first switching transistor T6 is turned off, thereby reducing interference between the two. Specifically, when the second reset transistor T4 resets the anode of the light-emitting element Di through the second reset signal VI2, and when the third reset transistor T2 resets the drain of the driving transistor T1 through the third reset signal VI3, the first switching transistor T6 can be turned off; after the data signal Data is written to the driving transistor T1, the first switching transistor T6 can be turned on to allow the driving transistor T1 to generate the aforementioned driving current.

[0041] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes a second switching transistor T5, electrically connected between the source and drain of the driving transistor T1 and the first power line (for transmitting the first power signal VDD). Based on the above illustration of the connection relationship between the source and drain of the driving transistor T1, it can be assumed that the second switching transistor T5 is electrically connected to the drain of the driving transistor T1, that is, the second switching transistor T5 and the compensation transistor T3 are electrically connected.

[0042] Similarly, since the second switching transistor T5 is electrically connected between the source of the driving transistor T1 and the first power supply line, the potential between the first power supply line and the source of the driving transistor T1 can be isolated when the second switching transistor T5 is turned off, thereby reducing interference between them. Specifically, the second reset transistor T4 can reset the anode of the light-emitting element Di through the second reset signal VI2, and the third reset transistor T2 can reset the drain of the driving transistor T1 through the third reset signal VI3, and the first switching transistor T6 can be turned off in both cases; after the data signal Data is written to the driving transistor T1, the first switching transistor T6 can be turned on to make the driving transistor T1 generate the aforementioned driving current.

[0043] In some embodiments, such as Figure 2 and Figure 3 As shown, the pixel circuit 1011 further includes a storage capacitor Cst, the first plate of which is electrically connected to the gate of the driving transistor T1, and the second plate of which is electrically connected to one of the anode and cathode of the light-emitting element Di. Based on the above illustration of the connection relationship between the anode and cathode of the light-emitting element Di, it can be assumed here that the second plate of the storage capacitor Cst is electrically connected to the anode of the light-emitting element Di.

[0044] Similarly, since the two ends of the storage capacitor Cst are electrically connected to the second node Q and the third node C (i.e. the anode of the light-emitting element Di), the storage capacitor Cst is used to maintain the stability of the voltage difference between the second node Q and the third node C. Since neither the second node Q nor the third node C is constantly connected to the constant voltage signal, when both are floating, a change in the potential of one of them will cause a change in the potential of the other.

[0045] To better illustrate the light-emitting principle of the display panel 100 and its sub-pixels 101, the present invention also provides a driving method for the display panel, applicable to any of the display panels 100 described above, such as... Figure 4 As shown, including but not limited to the following steps.

[0046] S1, control the first reset transistor to turn on, so that the first reset transistor transmits the first reset signal to the first node.

[0047] Specifically, in Figure 2 In the process, the first reset transistor T8 can be controlled to turn on so that the first reset signal VI1 is transmitted to the first node P to reset it; in Figure 3In this configuration, both the first reset transistor T8 and the transmission transistor T9 can be turned on to transmit the first reset signal VI1 to the first node P for resetting it. Resetting the first node P releases any residual charge within it.

[0048] S2, control the data writing transistor to turn on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, so that the driving transistor turns on.

[0049] Specifically, in Figure 2 In the process, the data writing transistor T7 can be turned on to transmit the data signal Data to the first node P and then to the gate of the driving transistor T1 through the coupling effect of the first capacitor C1; Figure 3 In this process, both the data writing transistor T7 and the transmission transistor T9 can be turned on to transmit the data signal Data to the gate of the driving transistor T1 so that the driving transistor T1 can be turned on.

[0050] S3, control the driving transistor to generate a driving current according to the data signal to drive the light-emitting element to emit light.

[0051] As can be seen from the above discussion, when the pixel circuit 1011 includes at least one of the first switching transistor T6 and the second switching transistor T5, it is necessary to control its conduction in order to form a path between the first power line and the cathode of the light-emitting element Di. At this time, the driving transistor T1 can generate a driving current according to the data signal to drive the light-emitting element Di to emit light.

[0052] To better illustrate the display panel described above, here is a brief explanation. Figure 2 and Figure 3 The operating stages of the i-th row of sub-pixels 101 in the circuit diagrams of the two types of sub-pixels 101 are described respectively, where i is a positive integer greater than 0 and less than or equal to n-1. For ease of explanation, this invention uses N-type oxide transistors and P-type low-temperature polysilicon transistors as examples. Figure 2 In this configuration, the driving transistor T1, data writing transistor T7, first reset transistor T8, compensation transistor T3, and second reset transistor T4 are all N-type transistors, while the first switching transistor T6, third reset transistor T2, and second switching transistor T5 are all P-type transistors. For example... Figure 3 The driving transistor T1, compensation transistor T3, and second reset transistor T4 are all N-type transistors, while the first switching transistor T6, third reset transistor T2, second switching transistor T5, data writing transistor T7, and first reset transistor T8 are all P-type transistors.

[0053] Combination Figure 2 and Figure 5 As shown, Figure 2 The sub-pixel 101 shown may include, but is not limited to, the following working stages:

[0054] In stage t1, the first gate signal EM1[i], the second gate signal Nscan2[i], and the third gate signal Nscan1[i] are all at their corresponding effective potentials, thereby controlling the second switching transistor T5, the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to all be turned on. The first power supply signal VDD is transmitted to the drain of the driving transistor T1, and then transmitted to the gate of the driving transistor T1 through the compensation transistor T3. The second reset signal VI2 is transmitted to the third node C to reset it, and the first reset signal VI1 is transmitted to the first node P to reset it.

[0055] That is, step S1 above may include, but is not limited to, the following steps:

[0056] S11, control the first reset transistor, the compensation transistor and the second switching transistor to be turned on, the first reset signal is transmitted to the first node, and the first power signal output by the first power line is transmitted to the drain and gate of the driving transistor;

[0057] Referring to the discussion of stage t1, the first reset transistor T8 is turned on, causing the first reset signal VI1 to be transmitted to the first node P to reset it. The second switching transistor T5 and the compensation transistor T3 are both turned on, causing the first power supply signal VDD to be transmitted to the drain and gate of the driving transistor T1. The second switching transistor T5;

[0058] Furthermore, step S1 above may also include, but is not limited to, the following steps:

[0059] S12, control the second reset transistor to turn on, and transmit the second reset signal to one of the anode and cathode of the light-emitting element;

[0060] As can be seen from the discussion of stage t1, the second reset transistor T4 is turned on, which causes the second reset signal VI2 to be transmitted to the third node C to reset it;

[0061] In stage t2, the second gate signal Nscan2[i], the third gate signal Nscan1[i], and the fourth gate signal Pscan1[i] are all effective potentials, thereby controlling the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to continue to conduct, and the third reset transistor T2 to conduct. Therefore, the first node P, the second node Q, and the third node C are maintained at their previous reset voltages. At the same time, the source of the driving transistor T1 is reset by the third reset signal VI3 so that the gate-source voltage of the driving transistor T1 is greater than its threshold voltage Vth. Therefore, the driving transistor T1 is turned on. The third reset signal VI3 charges the second node Q through the driving transistor T1 and the compensation transistor T3 to reduce its potential until the driving transistor T1 is turned off. At this time, the voltage VQ of the second node Q is VI3 + Vth.

[0062] That is, the steps between steps S1 and S2 may include, but are not limited to, the following:

[0063] S13, control the third reset transistor to turn on, and transmit the third reset signal to the other of the source and drain of the driving transistor to turn on the driving transistor. The potential of the gate of the driving transistor is reduced by the third reset signal until the driving transistor is turned off.

[0064] As can be seen from the discussion of stage t2, when the third reset transistor T2 is turned on, the source of the driving transistor T1 is reset by the third reset signal VI3. After the driving transistor T1 is turned on, the voltage VQ of the second node decreases until the driving transistor T1 is turned off. When the voltage VQ of the second node is VI3+Vth.

[0065] In stage t3, the third gate signal Nscan1[i] and the fifth gate signal Nscan3[i] are both effective potentials, thereby controlling the second reset transistor T4 to continue to conduct, and the data writing transistor T7 to conduct, and the data signal Data is transmitted to the first node P. The voltage of the first node P jumps from VI1 to Data. Since the potential of the third node C is maintained at VI2, through the coupling effect of the first capacitor C1, the voltage of the second node Q also jumps in the corresponding proportion of "Data-VI1" according to the series voltage division of the capacitors on the basis of the original VI3+Vth. Therefore, the voltage VQ of the second node Q is VI3+Vth+(Data-VI1)*C10 / (Cst0+C10), where C10 and Cst0 are the capacitance values ​​of the first capacitor C1 and the storage capacitor Cst, respectively.

[0066] That is, based on step S13, step S2 above may include, but is not limited to, the following steps:

[0067] S21, control the data writing transistor to turn on, the data signal is transmitted to the first node, and through the coupling effect of the first capacitor, the potential of the gate of the driving transistor undergoes a corresponding jump;

[0068] As can be seen from the discussion of stage t3, when the data writing transistor T7 is turned on, the voltage VQ of the second node Q becomes VI3+Vth+(Data-VI1)*C10 / (Cst0+C10) through the coupling effect of the first capacitor C1.

[0069] In stage t4, the first gate signal EM1[i] and the sixth gate signal EM2[i] are both at their corresponding effective potentials, thereby controlling the second switching transistor T5 and the first switching transistor T6 to conduct. A path is formed between the first power line and the cathode of the light-emitting element Di. At this time, the source voltage of the driving transistor T1 is approximately the voltage of the third node C, that is, the gate-source voltage of the driving transistor T1 is VQ-VC=VI3+Vth+(Data-VI1)*C10 / (Cst0+C10)-VI2, and the driving current generated by the driving transistor T1 is I=k×(Vgs-Vth). 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 Since the driving current is independent of Vth, Vth compensation function is achieved.

[0070] That is, step S3 above may include, but is not limited to, the following steps:

[0071] S31, control both the first switching transistor and the second switching transistor to be turned on, forming a path for the drive current to flow between the first power line and the other of the anode and cathode of the light-emitting element;

[0072] As discussed in stage t4, when the second switching transistor T5 and the first switching transistor T6 are turned on, a drive current I = k × (Vgs - Vth) can be generated. 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 .

[0073] Combination Figure 3 and Figure 6 As shown, Figure 3 The sub-pixel 101 shown may include, but is not limited to, the following working stages:

[0074] In stage t1', the first gate signal EM1[i], the seventh gate signal Pscan3[i], and the third gate signal Nscan1[i] are all at their corresponding effective potentials, thereby controlling the second switching transistor T5, the first reset transistor T8, the compensation transistor T3, the second reset transistor T4, and the transmission transistor T9 to be turned on. Similarly, in stage t1, the first power supply signal VDD is transmitted to the drain and gate of the driving transistor T1, the second reset signal VI2 is transmitted to the third node C to reset it, and the first reset signal VI1 is transmitted to the first node P to reset it.

[0075] That is, at least based on step S11, the above step S1 may also include, but is not limited to, the following steps:

[0076] S14, control both the first reset transistor and the transmission transistor to be turned on, and transmit the first reset signal to the first node;

[0077] As can be seen from the discussion of stage t1', the difference from stage t1 is that, due to the setting of transmission transistor T9, transmission transistor T9 is also turned on at this time, so that the first reset signal VI1 can be transmitted to the first node P to reset it.

[0078] The first reset transistor T8 is turned on, causing the first reset signal VI1 to be transmitted to the first node P to reset it. The second switching transistor T5 and the compensation transistor T3 are both turned on, causing the first power supply signal VDD to be transmitted to the drain and gate of the driving transistor T1. The second switching transistor T5;

[0079] In stage t2', the seventh gate signal Pscan3[i], the third gate signal Nscan1[i], and the fourth gate signal Pscan1[i] are all effective potentials, thereby controlling the first reset transistor T8, the compensation transistor T3, and the second reset transistor T4 to continue to conduct, and the third reset transistor T2 to conduct. Similarly, in stage t2, the voltage VQ of the second node Q is VI3+Vth.

[0080] In stage t3', the third gate signal Nscan1[i] and the eighth gate signal Pscan2[i] are both effective potentials, thereby controlling the second reset transistor T4 to continue to conduct, and the data writing transistor T7 and the transmission transistor T9 are both conducted. Similarly, in stage t3, the voltage VQ of the second node Q is VI3+Vth+(Data-VI1)*C10 / (Cst0+C10).

[0081] That is, at least based on step S11, the data writing transistor T7 and the first reset transistor T8 are both low-temperature polysilicon transistors, and the transmission transistor T9 is an oxide transistor. Step S2 may also include, but is not limited to, the following steps:

[0082] S22, both the first reset transistor and the transmission transistor are turned on, and the first reset signal is transmitted to the first node;

[0083] As can be seen from the discussion of stage t3', the difference from stage t3 is that, due to the setting of transmission transistor T9, transmission transistor T9 is also turned on at this time, so that the data signal Data can be transmitted to the first node P;

[0084] In stage t4', the first gate signal EM1[i] and the sixth gate signal EM2[i] are both at their corresponding effective potentials, thereby controlling the second switching transistor T5 and the first switching transistor T6 to turn on. Similarly, in stage t4, the driving current I generated by the driving transistor T1 is I = k × (Vgs - Vth). 2 =k×[VI3+(Data-VI1)×C10 / (Cst0+C10)-VI2] 2 Since the driving current is independent of Vth, Vth compensation is achieved.

[0085] It should be noted that this invention is illustrated only by the example that all gate signals other than the fifth gate signal Nscan3[i] or the eighth gate signal Pscan2[i] acting on the data writing transistor T7 are at least one-to-two. For example Figure 5 As shown, sub-pixels 101 in the i-th row and 101 in the i+1-th row, which are respectively affected by the fifth gate signal Nscan3[i] of the i-th level and the fifth gate signal Nscan3[i+1] of the i-th level, are both affected by the same set of first gate signals EM1[i], sixth gate signal EM2[i], second gate signal Nscan2[i], third gate signal Nscan1[i], and fourth gate signal Pscan1[i]. For example... Figure 6 As shown, the i-th row sub-pixel 101 and the i+1-th row sub-pixel 101, which are respectively acted by the i-th level eighth gate signal Pscan2[i] and the i+1 level eighth gate signal Pscan2[i+1], are both acted by the same set of first gate signal EM1[i], sixth gate signal EM2[i], seventh gate signal Pscan3[i], third gate signal Nscan1[i], and fourth gate signal Pscan1[i].

[0086] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display panel, characterized in that, It includes multiple sub-pixels, each sub-pixel comprising an electrically connected light-emitting element and a pixel circuit, the pixel circuit comprising: A driving transistor is used to generate a driving current according to a data signal to drive the light-emitting element to emit light. The driving transistor is an oxide transistor, and the gate of the driving transistor is electrically connected to a first node or connected to the first node through a first capacitor. A data writing transistor is electrically connected to the first node for transmitting the data signal; The first reset transistor is electrically connected to the first node and is used to transmit the first reset signal; A compensation transistor is electrically connected between the gate of the driving transistor and one of the source or drain of the driving transistor. The second switching transistor is electrically connected between one of the source and drain of the driving transistor and the first power supply line. The second reset transistor is electrically connected to one of the anode and cathode of the light-emitting element; The third reset transistor is electrically connected to the other of the source and drain of the driving transistor; Specifically, when the first reset transistor, the compensation transistor, the second switching transistor, and the second reset transistor are all turned on, the first reset signal is transmitted to the first node, the first power signal output from the first power line is transmitted to the drain and gate of the driving transistor, and the second reset signal is transmitted to one of the anode and cathode of the light-emitting element; during the period between controlling the first reset transistor to turn on and controlling the data writing transistor to turn on, the third reset transistor is controlled to turn on, and the third reset signal is transmitted to the other of the source and drain of the driving transistor to turn on the driving transistor, and the potential of the gate of the driving transistor is raised by the third reset signal until the driving transistor is turned off.

2. The display panel according to claim 1, characterized in that, Both the data writing transistor and the first reset transistor are oxide transistors.

3. The display panel according to claim 1, characterized in that, Both the data writing transistor and the first reset transistor are low-temperature polycrystalline silicon transistors.

4. The display panel according to claim 3, characterized in that, The pixel circuit also includes: A transmission transistor is electrically connected between the data write transistor, the first reset transistor, and the first node, and the transmission transistor is an oxide transistor.

5. The display panel according to any one of claims 1 to 4, characterized in that, At least one of the compensation transistor and the second reset transistor is an oxide transistor.

6. The display panel according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes: The second capacitor has its first plate electrically connected to the first power line and its second plate electrically connected to the first node.

7. The display panel according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes: The first switching transistor is electrically connected between the source and drain of the driving transistor and the anode and cathode of the light-emitting element. The third reset transistor is electrically connected to the other of the source and drain of the driving transistor and the first switching transistor, and the third reset transistor is used to transmit a third reset signal to the other of the source and drain of the driving transistor.

8. The display panel according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes: A storage capacitor, wherein the first plate of the storage capacitor is electrically connected to the gate of the driving transistor, and the second plate of the storage capacitor is electrically connected to one of the anode and cathode of the light-emitting element.

9. A driving method for a display panel, characterized in that, Applied to a display panel as described in any one of claims 1 to 8, the pixel circuit further includes a compensation transistor, a second switching transistor, a second reset transistor, and a third reset transistor. The compensation transistor is electrically connected between the gate of the driving transistor and one of the source and drain of the driving transistor. The second switching transistor is electrically connected between one of the source and drain of the driving transistor and a first power supply line. The second reset transistor is electrically connected to one of the anode and cathode of the light-emitting element. The third reset transistor is electrically connected to the other of the source and drain of the driving transistor; The driving method for the display panel includes: The first reset transistor is turned on so that it transmits the first reset signal to the first node. The data writing transistor is controlled to turn on, so that the data writing transistor transmits the data signal to the gate of the driving transistor, thereby turning on the driving transistor; The driving transistor is controlled to generate a driving current according to the data signal to drive the light-emitting element to emit light; The step of controlling the first reset transistor to turn on includes: The first reset transistor, the compensation transistor, and the second switching transistor are all turned on, the first reset signal is transmitted to the first node, and the first power signal output from the first power line is transmitted to the drain and gate of the driving transistor. The step of controlling the first reset transistor to turn on further includes: The second reset transistor is turned on, and the second reset signal is transmitted to one of the anode and cathode of the light-emitting element; Between the step of controlling the first reset transistor to turn on and the step of controlling the data write transistor to turn on, the following steps are included: The third reset transistor is turned on, and a third reset signal is transmitted to the other of the source and drain of the driving transistor to turn on the driving transistor. The potential of the gate of the driving transistor is raised by the third reset signal until the driving transistor is turned off.

10. The driving method for a display panel according to claim 9, characterized in that, The gate of the driving transistor is connected to the first node through a first capacitor; The step of controlling the data writing transistor to turn on includes: The data writing transistor is turned on, the data signal is transmitted to the first node, and the potential of the gate of the driving transistor changes accordingly through the coupling effect of the first capacitor.

11. The driving method for a display panel according to any one of claims 9 to 10, characterized in that, The pixel circuit further includes a first switching transistor, which is electrically connected between the source and drain of the driving transistor and the anode and cathode of the light-emitting element. The step of controlling the driving transistor to generate a driving current according to the data signal to drive the light-emitting element to emit light includes: Both the first and second switching transistors are turned on, forming a path for the drive current to flow between the first power line and the other of the anode and cathode of the light-emitting element.

12. The driving method for a display panel according to any one of claims 9 to 10, characterized in that, The pixel circuit further includes a transmission transistor, which is electrically connected between the data write transistor, the first reset transistor, and the first node; Both the data writing transistor and the first reset transistor are low-temperature polysilicon transistors, and the transmission transistor is an oxide transistor. The step of controlling the first reset transistor to turn on includes: The first reset transistor and the transmission transistor are both turned on, and the first reset signal is transmitted to the first node.

13. The driving method for a display panel according to any one of claims 9 to 10, characterized in that, The pixel circuit further includes a transmission transistor, which is electrically connected between the data write transistor, the first reset transistor, and the first node; Both the data writing transistor and the first reset transistor are low-temperature polysilicon transistors, and the transmission transistor is an oxide transistor. The step of controlling the data writing transistor to turn on includes: Both the data writing transistor and the transmission transistor are turned on, and the data writing transistor transmits data to the gate of the driving transistor.

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