Storage device and method for driving storage device

Abstract

A novel semiconductor device, a memory device, and a driving method of the memory device are provided. One of a source and a drain of the first transistor is connected to one terminal of the first capacitor, the other of the source and the drain of the first transistor is connected to the bit line, a gate of the first transistor is connected to the word line, and the other terminal of the first capacitor is connected to the first driving circuit. The first drive circuit has a function of outputting a first potential, a function of outputting a second potential in conjunction with a timing of a change in potential of a selection signal supplied to a word line, and a function of outputting a third potential in conjunction with a timing of a change in potential of data supplied to a bit line. A change direction from the first potential to the second potential is opposite to a potential change direction of the selection signal, and a change direction from the first potential to the third potential is opposite to a potential change direction of the data.

Description

Technical Field

[0001] One embodiment of the present invention relates to a storage device and a method for driving the storage device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, a method, a driving method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition. Specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., there can be cited semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, computing processing devices, electronic computers, electronic devices, their driving methods or their manufacturing methods. Background Art

[0003] It is known that transistors containing an oxide semiconductor in their channel formation regions have extremely low off-state current. For example, Patent Document 1 discloses a low-power processing device (e.g., a CPU) that utilizes the low off-state current characteristic of this transistor. Furthermore, Patent Document 2 discloses a storage device (e.g., a main memory, a cache memory, etc.) that utilizes the low off-state current characteristic of this transistor to store data for a long period of time.

[0004] Furthermore, for example, Patent Document 3 discloses a technique for achieving high density of integrated circuits by stacking such transistors.

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 Summary of the Invention

[0006] One object of one embodiment of the present invention is to provide a semiconductor device capable of extending retention time, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing operating speed, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of reducing power consumption, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of increasing storage density, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of achieving miniaturization, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a semiconductor device capable of achieving high reliability, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device.

[0007] Furthermore, the inclusion of the aforementioned objectives does not preclude the existence of other objectives. Other objectives other than those mentioned above can be readily apparent and extracted from the description of this specification, the accompanying drawings, or the claims. Note that one embodiment of the present invention does not necessarily achieve all of the objectives (the aforementioned objectives and other objectives). (1) One embodiment of the present invention is a memory device comprising a memory array and a peripheral circuit, the memory array comprising a first memory cell, the peripheral circuit comprising a first driver circuit, the first memory cell comprising a first transistor and a first capacitor, one of a source and a drain of the first transistor being electrically connected to a terminal of the first capacitor, the other of a source and a drain of the first transistor being electrically connected to a bit line, the gate of the first transistor being electrically connected to a word line, and the other terminal of the first capacitor being electrically connected to the first driver circuit, the first driver circuit having a function of outputting a first potential, a function of outputting a second potential in conjunction with a timing of a potential change of a selection signal supplied to the word line, and a function of outputting a third potential in conjunction with a timing of a potential change of data supplied to the bit line, the direction of change from the first potential to the second potential being opposite to the direction of change of the potential of the selection signal, and the direction of change from the first potential to the third potential being opposite to the direction of change of the potential of the data. (2) One embodiment of the present invention is a memory device including a memory array and a peripheral circuit, the memory array including a first memory cell and a second memory cell, the peripheral circuit including a first driver circuit and a second driver circuit, the first memory cell including a first transistor and a first capacitor, the second memory cell including a second transistor and a second capacitor, one of a source and a drain of the first transistor being electrically connected to one terminal of the first capacitor, the other of the source and drain of the first transistor being electrically connected to a bit line, the gate of the first transistor being electrically connected to a first word line, the other terminal of the first capacitor being electrically connected to the first driver circuit, one of a source and a drain of the second transistor being electrically connected to one terminal of the second capacitor, the other of the source and drain of the second transistor being electrically connected to the bit line, the gate of the second transistor being electrically connected to a second word line, and the other terminal of the second capacitor being electrically connected to the second driver circuit, the first driver circuit having a function of outputting a signal whose potential changes in a direction opposite to that of a select signal supplied to the first word line, and the second driver circuit having a function of outputting a signal whose potential changes in a direction opposite to that of a select signal supplied to the second word line. (3) One embodiment of the present invention is a memory device including a memory array and a peripheral circuit, the memory array including a first memory cell and a second memory cell, the peripheral circuit including a first driver circuit and a second driver circuit, the first memory cell including a first transistor and a first capacitor, the second memory cell including a second transistor and a second capacitor, one of a source and a drain of the first transistor being electrically connected to one terminal of the first capacitor, the other of the source and the drain of the first transistor being electrically connected to a first bit line, the gate of the first transistor being electrically connected to a word line, the other terminal of the first capacitor being electrically connected to the first driver circuit, one of a source and a drain of the second transistor being electrically connected to one terminal of the second capacitor, the other of the source and the drain of the second transistor being electrically connected to a second bit line, the gate of the second transistor being electrically connected to the word line, and the other terminal of the second capacitor being electrically connected to the second driver circuit, the first driver circuit having a function of outputting a signal whose potential changes in a direction opposite to that of data supplied to the first bit line, and the second driver circuit having a function of outputting a signal whose potential changes in a direction opposite to that of data supplied to the second bit line. (4) One embodiment of the present invention is a memory device, which includes a memory array and a peripheral circuit, the memory array including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell, the peripheral circuit including a first drive circuit, a second drive circuit, a third drive circuit, and a fourth drive circuit, the first memory cell including a first transistor and a first capacitor, the second memory cell including a second transistor and a second capacitor, the third memory cell including a third transistor and a third capacitor, the fourth memory cell including a fourth transistor and a fourth capacitor, one of a source and a drain of the first transistor being electrically connected to a terminal of the first capacitor, the other of a source and a drain of the first transistor being electrically connected to a first bit line, the gate of the first transistor being electrically connected to a first word line, the other terminal of the first capacitor being electrically connected to the first drive circuit, and the second transistor including a gate. One of the source and drain of the transistor is electrically connected to one terminal of the second capacitor, the other of the source and drain of the second transistor is electrically connected to the first bit line, the gate of the second transistor is electrically connected to the second word line, and the other terminal of the second capacitor is electrically connected to the second driving circuit. One of the source and drain of the third transistor is electrically connected to one terminal of the third capacitor, the other of the source and drain of the third transistor is electrically connected to the second bit line, the gate of the third transistor is electrically connected to the first word line, and the other terminal of the third capacitor is electrically connected to the third driving circuit. One of the source and drain of the fourth transistor is electrically connected to one terminal of the fourth capacitor, the other of the source and drain of the fourth transistor is electrically connected to the second bit line, the gate of the fourth transistor is electrically connected to the second word line, and the other terminal of the fourth capacitor is electrically connected to the fourth driving circuit. (5) In any one of (1) to (4) above, the first transistor may include an oxide semiconductor in a channel formation region. (6) Furthermore, in any one of the above (1) to (4), the first transistor may also be provided on the first capacitor. (7) In addition, in the above (6), it can also include a first conductor, a second conductor on the first conductor, and a third conductor on the second conductor. The first conductor may include a region serving as the other terminal of the first capacitor, the second conductor may include a region serving as one terminal of the first capacitor and a region serving as one of the source and the drain of the first transistor, and the third conductor may include a region serving as the other of the source and the drain of the first transistor. (8) Furthermore, in any of the above (1) to (4), the memory array may be provided on the peripheral circuit. (9) One embodiment of the present invention is a method for driving a storage device, wherein the storage device includes a storage unit in which one of the source and drain of an n-channel transistor is electrically connected to one terminal of a capacitor, and the driving method includes the following steps: after lowering the potential of a selection signal supplied to the gate of the transistor, increasing the potential supplied to the other terminal of the capacitor. (10) One embodiment of the present invention is a method for driving a storage device, the storage device including a storage cell in which one of the source and drain of an n-channel transistor is electrically connected to one terminal of a capacitor, the driving method including the steps of: synchronously lowering the potential supplied to the other terminal of the capacitor at the timing of increasing the potential of data supplied to the other of the source and drain of the transistor.

[0018] According to one embodiment of the present invention, a semiconductor device capable of extending retention time, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of increasing operating speed, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of reducing power consumption, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of increasing storage density, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of achieving miniaturization, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of achieving high reliability, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device capable of achieving novel power consumption, a memory device including the same, a method for driving the semiconductor device, or a method for driving the memory device can be provided.

[0019] Furthermore, the description of the above-mentioned effects does not preclude the existence of other effects. Other effects other than those described above can be readily understood and extracted from the description of this specification, the drawings, or the claims. Note that one embodiment of the present invention does not necessarily have all the effects (the effects described above and others). BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit diagram illustrating an example of the structure of a storage device; Figure 2Aand Figure 2B is a timing diagram illustrating an example of operation of the storage device; Figures 3A to 3F is a circuit diagram illustrating an example of operation of a storage device; Figure 4A and Figure 4B is a timing diagram illustrating an example of operation of the storage device; 5A to 5D is a circuit diagram illustrating an example of operation of a storage device; Figure 6A and Figure 6B is a timing diagram illustrating an example of operation of the storage device; Figure 7A and Figure 7B is a circuit diagram illustrating an example of the structure of a storage device; Figure 8 is a circuit diagram illustrating an example of the structure of a storage device; Figure 9 is a timing diagram illustrating an example of operation of the storage device; Figure 10 is a circuit diagram illustrating an example of the structure of a storage device; Figure 11 is a timing diagram illustrating an example of operation of the storage device; Figure 12 is a circuit diagram illustrating an example of the structure of a storage device; Figure 13 is a timing diagram illustrating an example of operation of the storage device; Figure 14A and Figure 14B is a circuit diagram illustrating an example of the structure of a storage device; Figure 15 is a block diagram showing a structural example of a storage device; Figure 16 is a block diagram showing a structural example of a storage device; Figure 17A is a top view showing a structural example of a semiconductor device, Figure 17B and Figure 17C is a cross-sectional view showing a structural example of a semiconductor device; Figure 18A and Figure 18B is a cross-sectional view showing a structural example of a semiconductor device; Figure 19 is a cross-sectional view showing a structural example of a semiconductor device; 20A to 20C is a cross-sectional view showing a structural example of a semiconductor device; 21A to 21D is a circuit diagram showing a structural example of a semiconductor device; Figure 22A and Figure 22B is a top view showing a structural example of a semiconductor device; Figure 23A and Figure 23B is a cross-sectional view showing a structural example of a semiconductor device; Figure 24A and Figure 24B is a cross-sectional view showing a structural example of a semiconductor device; Figure 25 is a cross-sectional view showing a structural example of a semiconductor device; Figure 26 is a cross-sectional view showing a structural example of a semiconductor device; Figure 27A is a top view showing a structural example of a semiconductor device, Figure 27B and Figure 27C is a cross-sectional view showing a structural example of a semiconductor device; Figure 28A is a top view showing a structural example of a semiconductor device, Figure 28B is a perspective schematic diagram showing a structural example of a semiconductor device, Figures 28C to 28E is a cross-sectional view showing a structural example of a semiconductor device; Figure 29A and Figure 29B is a cross-sectional view showing a structural example of a semiconductor device; Figure 30A is a top view showing a structural example of a semiconductor device, Figure 30B is a perspective schematic diagram showing a structural example of a semiconductor device, Figures 30C to 30E is a cross-sectional view showing a structural example of a semiconductor device; Figure 31 is a cross-sectional view showing a structural example of a semiconductor device; Figure 32A is a top view showing a structural example of a semiconductor device, Figure 32B is a perspective schematic diagram showing a structural example of a semiconductor device, Figures 32C to 32E is a cross-sectional view showing a structural example of a semiconductor device; Figure 33A and Figure 33B is a cross-sectional view showing a structural example of a semiconductor device; Figure 34A is a top view showing a structural example of a semiconductor device, Figures 34B to 34D is a cross-sectional view showing a structural example of a semiconductor device; Figure 35 is a diagram showing various storage devices in a hierarchical manner; Figures 36A to 36H is a circuit diagram illustrating an example of the structure of a memory cell; Figure 37A and Figure 37B is a circuit diagram illustrating an example of the structure of a semiconductor device; Figure 38A and Figure 38B is a diagram showing an example of an electronic component; Figure 39A and Figure 39B is a diagram showing an example of an electronic device, Figures 39C to 39E is a diagram showing an example of a large computer; Figure 40A is a diagram showing an example of a space device, Figure 40B FIG. 1 is a diagram showing an example of a storage system that can be used in a data center; Figures 41A1 to 41A7 and Figures 41B1 to 41B6 It is a diagram illustrating "electrical connection"; Figure 42A is a top view showing a structural example of a semiconductor device, Figure 42B and Figure 42C is a cross-sectional view showing a structural example of a semiconductor device; Figure 43A and Figure 43B is a perspective schematic diagram showing a structural example of a semiconductor device; Figure 44A and Figure 44B is a cross-sectional view showing a structural example of a semiconductor device; Figure 45A and Figure 45B is a diagram showing evaluation results of oxide semiconductors; Figures 46A to 46D is a diagram showing evaluation results of oxide semiconductors; Figures 47A to 47H is a diagram showing evaluation results of oxide semiconductors; Figures 48A to 48D is a diagram illustrating a method for evaluating an oxide semiconductor; Figures 49A to 49H is a diagram showing evaluation results of oxide semiconductors; Figure 50 is a diagram showing evaluation results of oxide semiconductors; Figure 51A and Figure 51B is a diagram showing evaluation results of oxide semiconductors; Figures 52A to 52D is a diagram showing evaluation results of a transistor; Figure 53A and Figure 53B is a diagram showing evaluation results of a transistor; Figure 54A and Figure 54B is a diagram showing evaluation results of a transistor; Figure 55 is a diagram showing evaluation results of a transistor; Figure 56A and Figure 56B is a diagram showing evaluation results of a transistor; Figure 57A and Figure 57B is a diagram showing evaluation results of a transistor; Figure 58A and Figure 58B is a diagram showing evaluation results of a transistor; Figure 59 is a diagram showing evaluation results of a transistor; Figure 60 is a diagram showing evaluation results of a transistor; Figure 61 is a diagram showing evaluation results of a storage device; Figure 62A and Figure 62B is a diagram showing evaluation results of a storage device; Figure 63 is a diagram showing evaluation results of a storage device; Figure 64A and Figure 64B is a diagram showing evaluation results of a storage device; Figure 65 is a diagram showing evaluation results of a storage device; Figure 66 It is a diagram showing the evaluation results of the storage device. DETAILED DESCRIPTION

[0021] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, for example, a circuit including a semiconductor element (for example, a transistor, a diode, or a diode, etc.) or a device including the circuit, etc. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits including semiconductor elements, chips including integrated circuits, electronic components containing chips in packages, or electronic devices equipped with electronic components, etc. In addition, for example, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, electronic computers or electronic devices, etc. are themselves semiconductor devices, and sometimes include semiconductor devices.

[0022] The following describes the embodiments with reference to the accompanying drawings. Note that the embodiments may be implemented in a variety of different forms. Therefore, those skilled in the art will readily appreciate that the methods and details may be modified in a variety of ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the embodiments described herein.

[0023] In addition, in this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structures are shown in one embodiment, these structures can be appropriately combined and regarded as one mode of the present invention.

[0024] Note that with respect to the drawings illustrating the embodiments, in the structure of the invention, the same symbols are sometimes used in common in different drawings to represent the same parts or parts with the same function, thereby omitting repeated descriptions. In addition, in the drawings, when representing parts with the same function, the same hatching is sometimes used, for example, without adding special symbols. For example, in a stereogram or a top view (also called a "plan view"), for the sake of clarity, the illustration of some constituent elements is sometimes omitted. For example, the description of some hidden lines in the drawings is sometimes omitted. In addition, for example, the description of hatching, etc. in the drawings is sometimes omitted.

[0025] In the drawings, dimensions, layer thicknesses, or regions are sometimes exaggerated for clarity of explanation. Therefore, the drawings, for example, are not limited to the dimensions or aspect ratios shown in the drawings. In addition, the drawings schematically illustrate ideal examples, and therefore, the present invention, for example, is not limited to the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in actual circuit operation, for example, voltage or current may be uneven due to noise or timing deviation, but this is sometimes not reflected in the drawings for ease of understanding.

[0026] In this specification and the accompanying drawings, components are categorized by function and presented as independent components. However, categorization of components by function is difficult, as a single circuit may be involved in multiple functions, or multiple circuits may be involved in a single function. Therefore, the components shown in this specification and the accompanying drawings are not limited to the components described herein, and appropriate wording may be used.

[0027] In this specification and the accompanying drawings, when the same reference numeral is used for multiple components and it is necessary to distinguish them, an identification symbol such as "A," "b," "_1," "[n]," or "[m,n]" may be added to the reference numeral. Furthermore, when describing content common to multiple components assigned an identification symbol or when it is not necessary to distinguish them, the identification symbol may be omitted.

[0028] Note that in this specification, etc., the term "on-state" or "conducting state" of a transistor refers to, for example, a state in which the source and drain of the transistor are electrically short-circuited, or a state in which current can flow between the source and drain (also referred to as a state in which current can flow). For example, the following states are sometimes referred to as "on-state" or "on-state": a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Furthermore, the term "non-conducting state," "off-state," or "off-state" of a transistor refers to a state in which the source and drain of the transistor are electrically disconnected. For example, the following states are sometimes referred to as "non-conducting state," "off-state," or "off-state": a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage.

[0029] In addition, in this specification, etc., the voltage between the gate and the source (gate-source) is sometimes referred to as the "gate voltage", the voltage between the drain and the source (drain-source) is sometimes referred to as the "drain voltage", and the voltage between the back gate and the source (back gate-source) is sometimes referred to as the "back gate voltage". In addition, the current flowing between the drain and the source is sometimes referred to as the "drain current". Note that it is possible to appropriately convert descriptions such as "high gate voltage, high drain voltage, and high back gate voltage" of an n-channel transistor into descriptions such as "low gate voltage, low drain voltage, and low back gate voltage" of a p-channel transistor, respectively. In addition, it is possible to appropriately convert descriptions such as "low gate voltage, low drain voltage, and low back gate voltage" of an n-channel transistor into descriptions such as "high gate voltage, high drain voltage, and high back gate voltage" of a p-channel transistor, respectively.

[0030] In addition, in this specification and other documents, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification and other documents, the off-state current and the current flowing between the gate and the source and drain (also called gate leakage current) are sometimes referred to as leakage current.

[0031] Implementation Method 1 A semiconductor device according to one embodiment of the present invention will be described with reference to the accompanying drawings. For example, at least a portion of a semiconductor device according to one embodiment of the present invention can be used in a memory device. The memory device includes a memory cell and a circuit for driving the memory cell. Furthermore, one embodiment of the present invention is a method for driving the memory cell.

[0032] <Storage Device Configuration Example 1> Figure 1 This is a circuit diagram illustrating a memory device according to one embodiment of the present invention.

[0033] like Figure 1 As shown, the memory device 100 includes a memory cell array 110 and a peripheral circuit 120. The memory array includes a plurality of memory cells 111 arranged in a matrix. Figure 1 , one storage unit 111 is typically shown.

[0034] The memory cell 111 includes a transistor M11 and a capacitor C11. One of the source and drain of the transistor M11 is connected to one terminal of the capacitor C11. The other of the source and drain of the transistor M11 is connected to the wiring BL serving as a bit line. The gate of the transistor M11 is connected to the wiring WL serving as a word line. The other terminal of the capacitor C11 (sometimes referred to as the Plate terminal) is connected to the wiring PL serving as a signal line. Note that the wiring connecting one of the source and drain of the transistor M11 and one terminal of the capacitor C11 is sometimes described as wiring SN. In addition, as described later, after data is written to the memory cell 111, the potential corresponding to the data is retained in the wiring SN. Therefore, this wiring is sometimes referred to as a holding node.

[0035] Peripheral circuit 120 includes a driver circuit 121 that supplies a data potential to wiring BL, a driver circuit 122 that supplies a select signal potential to wiring WL, and a driver circuit 123 that supplies a control signal potential to wiring PL. In other words, driver circuit 121 outputs a data potential, driver circuit 122 outputs a select signal potential, and driver circuit 123 outputs a control signal potential.

[0036] Here, the control signal may have a first potential (equivalent to potential Vp0, described later), a second potential (equivalent to potential Vp1, described later), and a third potential (equivalent to potential Vp2, described later). Furthermore, the timing of the control signal's potential changing from the first potential to the second potential may be linked to the timing of the selection signal's potential change. Furthermore, the direction of the change from the first potential to the second potential may be opposite to the direction of the selection signal's potential change. Furthermore, the timing of the control signal's potential changing from the first potential to the third potential may be linked to the timing of the data's potential change. Furthermore, the direction of the change from the first potential to the third potential may be opposite to the direction of the data's potential change.

[0037] In memory cell 111, transistor M11 is either an n-channel transistor or a p-channel transistor. Here, transistor M11 is described as an n-channel transistor. N-channel transistors have a higher on-state current than p-channel transistors. Therefore, data read and write speeds can be increased in memory cell 111.

[0038] Furthermore, as the transistor M11, for example, a transistor including a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used. Furthermore, as the semiconductor, in addition to a single semiconductor whose main component is composed of a single element (for example, silicon or germanium), for example, a compound semiconductor (for example, silicon germanium or gallium arsenide) or an oxide semiconductor can also be used.

[0039] Furthermore, various types of transistors can be used as the transistor M11, such as a MOS field effect transistor, a junction field effect transistor, or a bipolar transistor.

[0040] In addition, various types of transistors can be used as transistor M11. For example, transistors of various structures such as top gate type (for example, planar type and staggered type), bottom gate type (for example, inverted planar type and inverted staggered type), dual gate type (a structure in which gates are arranged on both sides (for example, up and down) of a channel formation region), FIN type (fin type), TRI-GATE type (triple gate type) and GAA type (all-around gate) can be used. In addition, for example, a vertical transistor (a transistor having a longitudinal component (also called a height direction or a direction perpendicular to the formed surface) in the channel length direction) can be used.

[0041] In one embodiment of the present invention, an OS transistor (a transistor including an oxide semiconductor in a channel formation region) can be used as the transistor M11.

[0042] Since the band gap of the oxide semiconductor forming the channel is greater than 2eV, the OS transistor has a very small off-state current. At room temperature, the off-state current value of the OS transistor with a channel width of 1μm can be 1aA (1×10 -18 A) or less, 1zA(1×10 -21 A) or less or 1yA(1×10 -24 Note that in a Si transistor (a transistor whose channel formation region includes silicon), the off-state current value per channel width of 1 μm at room temperature is 1 fA (1×10 -15 A) and above 1pA(1×10 -12 A) or less. Therefore, it can be said that the off-state current of an OS transistor is approximately 10 bits smaller than that of a Si transistor. Therefore, for example, when a wiring connected to one of the source and drain of an OS transistor is in a floating state, the charge stored in that wiring can be retained for a long time. Therefore, for example, by forming a memory cell using an OS transistor, data written to that memory cell can be stored for a long time.

[0043] Furthermore, even in high-temperature environments, the off-state current of the OS transistor hardly increases. Specifically, even in environments above room temperature and below 200°C, the off-state current hardly increases. Furthermore, even in high-temperature environments, the on-state current of the OS transistor does not easily decrease. On the other hand, in high-temperature environments, the on-state current of the Si transistor decreases. In other words, in high-temperature environments, the on-state current of the OS transistor is greater than that of the Si transistor. Furthermore, even in environments above 125°C and below 150°C, the ratio of the on-state current to the off-state current of the OS transistor is large, enabling good switching operation. Therefore, semiconductor devices using OS transistors operate stably and have high reliability even in high-temperature environments.

[0044] Furthermore, an OS transistor has a high breakdown voltage between its source and drain (also referred to as a drain breakdown voltage). Therefore, a semiconductor device using an OS transistor operates stably and has high reliability even when driven at a high voltage.

[0045] Here, the structure using an OS transistor as an access transistor (transistor M11) in the memory cell 111 is sometimes referred to as DOSRAM (registered trademark). DOSRAM is the abbreviation of Dynamic Oxide Semiconductor RAM (Random Access Memory). DOSRAM uses an OS transistor with extremely small off-state current, so it can store data for a long time. In other words, because the written data can be stored for a long time, the refresh frequency of the data can be reduced. In addition, since the electrostatic capacitance of the cell capacitor (C11) can be reduced, the cell size can be reduced. Therefore, by using DOSRAM, the power consumption of the storage device including the DOSRAM can be reduced and the storage density can be increased.

[0046] In memory cells using OS transistors, data can be written and read by charging and discharging electrical charge, making data writing and reading virtually unlimited. Memory cells using OS transistors do not experience atomic-level structural changes like those in magnetic or resistive memory, resulting in excellent rewrite resistance. Furthermore, even with repeated writing, memory cells using OS transistors do not experience instability caused by the increase in electron trapping centers seen in flash memory, resulting in excellent stability.

[0047] Furthermore, memory cells using OS transistors can be freely configured, for example, on a silicon substrate already equipped with Si transistors, making integration easy. Furthermore, in memory cells using OS transistors, the OS transistors can be manufactured using the same manufacturing equipment as Si transistors, enabling low-cost manufacturing.

[0048] Furthermore, in a memory cell using an OS transistor, a plurality of such memory cells can be stacked in a monolithic manner, thereby improving the storage density, bandwidth, access delay, etc. of a memory device using the memory cell.

[0049] Furthermore, in the memory cell 111 according to one embodiment of the present invention, a vertical transistor can be used as the transistor M11. This reduces the layout area of ​​the memory cell 111. In other words, the storage density of a memory device including the memory cell 111 can be increased.

[0050] Furthermore, the transistor M11 can be stacked on the capacitor C11 and arranged so that the transistor M11 overlaps with the capacitor C11. This can further reduce the layout area of ​​the memory cell 111. In other words, the storage density of the memory device including the memory cell 111 can be further increased.

[0051] In the memory cell 111 , an example of a structure in which a transistor M11 is stacked on the capacitor C11 and a vertical transistor is used as the transistor M11 will be described later in Embodiment 2.

[0052] Furthermore, various transistors can be used as transistors constituting the peripheral circuit 120. For example, one or both of an n-channel transistor and a p-channel transistor can be used. Furthermore, for example, one or both of an OS transistor and a Si transistor can be used. Furthermore, for example, one or both of a planar transistor and a vertical transistor can be used. Note that a structural example of the driver circuit 123 included in the peripheral circuit 120 according to one embodiment of the present invention will be described later.

[0053] [Working Example 1] Figure 2A 、 Figure 2B and Figures 3A to 3F 1 is a timing chart and a circuit diagram illustrating an example of a driving method of the memory cell 111 . Figure 2A The timing chart shown is an example of an operation in which data “0” is written to the memory cell 111 holding data “1” and the memory cell 111 holds the data “0”.

[0054] In the following description, as the potential corresponding to the binary data supplied to the wiring BL, the potential corresponding to "1" in the binary data is set to a high power supply potential, that is, the potential VDD (sometimes simply referred to as VDD), and the potential corresponding to "0" in the binary data is set to a low power supply potential, that is, the potential VSS (sometimes simply referred to as VSS).

[0055] The potential of the signal supplied to the wiring WL is either a potential H (sometimes simply referred to as H) that can turn on the transistor M11 or a potential L (sometimes simply referred to as L) that can turn off the transistor M11.

[0056] Note that this working example describes the case where an n-channel transistor is used as transistor M11. If a p-channel transistor is used as transistor M11, the descriptions of the magnitude relationships between voltages and potentials can be appropriately modified. For example, "high voltage" can be appropriately modified to "low voltage," and vice versa. Furthermore, for example, "increase potential" can be appropriately modified to "decrease potential," and vice versa.

[0057] Here, when the threshold voltage of transistor M11 is Vth, in order to turn on transistor M11 during the operation of memory cell 111, the potential H can be determined such that the minimum gate voltage in the on state is greater than the threshold voltage (i.e., "H - VDD > Vth"). Further, in order to turn off transistor M11, the potential L can be determined such that the maximum gate voltage in the off state is less than the threshold voltage (i.e., "L - VSS < Vth").

[0058] In addition, the potential of the signal supplied to wiring PL is either potential Vp0 or potential Vp1 greater than potential Vp0.

[0059] Note that in the description of the operation, when the potential changes, for example, rise time and fall time occur due to loads (parasitic capacitance and parasitic resistance) such as wiring. Further, for example, even if the timings shown for two different operations are the same, it does not necessarily mean they are exactly the same. For example, even if there is a slight time lag caused by signal delay in the wiring, etc., it can sometimes be regarded as the same timing.

[0060] In addition, for ease of understanding the description, the lengths of each period are sometimes shown to be the same in the timing diagram, but the time length of each period can also be different.

[0061] Figure 2A The shown timing diagram shows the states of the potentials supplied to wiring WL, wiring BL, and wiring PL during each period of the operation. In addition, the potential change of wiring SN is shown. Further, the change in the gate voltage (sometimes denoted as Vgs) of transistor M is also shown.

[0062] In addition, Figures 3A to 3F the potentials of wiring WL, wiring BL, wiring PL, and wiring SN at each time of the operation are shown. In addition, the gate voltage Vgs of transistor M11 is shown by an arrow. At this time, symbols indicating potentials (also called potential symbols) such as "VDD" or "VSS" are sometimes recorded in a framed form near each wiring, etc.

[0063] During period T11, wiring WL is supplied with potential H, and wiring PL is supplied with potential Vp0. In addition, as an example, wiring BL is supplied with "VDD" corresponding to "l", and the potential of wiring SN of memory cell 111 is also "VDD". At this time, the gate voltage Vgs of transistor M11 is "H - VDD", and transistor M11 is in the on state. This state corresponds to the state after reading data "1" from memory cell 111 and writing the data back. Figure 3A The potentials of each wiring at this time are shown. Note that in the following description, unless otherwise stated, the previous state is maintained.

[0064] During period T12, "VSS" corresponding to "0" is supplied to wiring BL. Consequently, the potential of wiring SN gradually decreases through transistor M11 to "VSS." In other words, data "0" is written to memory cell 111. At this time, gate voltage Vgs of transistor M11 reaches "H - VSS." Figure 3B The potential of each wiring at this time is shown.

[0065] During period T13, the potential L is supplied to wiring WL. As a result, gate voltage Vgs of transistor M11 reaches "L-VSS," turning transistor M11 off. This completes writing data "0" to memory cell 111, and wiring SN maintains "VSS" corresponding to data "0." Figure 3C The potential of each wiring at this time is shown.

[0066] During period T14, the wiring BL is supplied with an intermediate potential Vpre between the potentials VDD and VSS. In other words, the wiring BL is precharged to the intermediate potential Vpre. Consequently, the potential of the wiring SN is lower than that of the wiring BL, so the wiring SN serves as the source of the transistor M11. Since the wiring SN remains at "VSS," the gate voltage Vgs of the transistor M11 remains at "L-VSS." Figure 3D The potential of each wiring at this time is shown. In addition, the wiring BL can also be precharged to "VDD".

[0067] During period T15, the potential Vp1 is supplied to wiring PL. That is, the potential of wiring PL rises from potential Vp0 to potential Vp1. Consequently, due to capacitive coupling through capacitor C11, the potential of wiring SN also rises. At this time, if the potential of wiring SN rises by "vp," the potential of wiring SN becomes "VSS + vp," and the gate voltage Vgs of transistor M11 becomes "L - (VSS + vp)." In other words, the gate voltage Vgs of transistor M11 drops by "vp." Figure 3E The potential of each wiring at this time is shown.

[0068] Then, the potential of the wiring SN is maintained at “VSS+vp”.

[0069] During period T16, the potential Vp0 is supplied to wiring PL. That is, the potential of wiring PL drops from potential Vp1 to potential Vp0. Consequently, due to capacitive coupling through capacitor C11, the potential of wiring SN also drops by "vp." At this point, the potential of wiring SN reaches "VSS," and the gate voltage Vgs of transistor M11 reaches "L-VSS." In other words, the potential of wiring SN returns to the state after data is written to memory cell 111 (equivalent to periods T13 and T14). Period T16, for example, corresponds to the state before data is read from memory cell 111. Figure 3F The potential of each wiring at this time is shown.

[0070] Here, the transistor M11 has a region (also called a subthreshold region) in which the off-state current (i.e., the drain current in the off state when the gate voltage is less than the threshold voltage) changes exponentially with respect to the gate voltage. That is, in the off-state transistor M11, the smaller the gate voltage Vgs, the smaller the off-state current.

[0071] Therefore, when the transistor M11 is turned off after data is written to the memory cell 111 , the lower the gate voltage Vgs of the transistor M11 is, the longer the potential of the wiring SN corresponding to the written data can be maintained.

[0072] In one embodiment of the present invention, by operating the memory cell 111 as in the aforementioned period T15 (i.e., after lowering the potential of the select signal supplied to the wiring WL, the potential supplied to the wiring PL is raised), the gate voltage Vgs of the transistor M11 in the off state can be reduced. This allows the potential of the wiring SN corresponding to the data written to the memory cell 111 to be maintained for a long period of time. Consequently, a memory device capable of long-term storage can be realized. For example, by reducing the data refresh frequency, power consumption can be reduced.

[0073] In other words, as one embodiment of the present invention, the driver circuit 123 can have a function of outputting a signal whose potential changes in a direction opposite to the direction of potential change of the selection signal supplied to the wiring WL. In this case, the timing of the potential change of the signal output from the driver circuit 123 can be linked to the timing of the potential change of the selection signal. That is, for example, the potential of the signal output from the driver circuit 123 can rise after the potential of the selection signal falls.

[0074] An OS transistor can also be used as the transistor M11 included in the memory cell 111. Compared to Si transistors, OS transistors have the characteristic of operating in the subthreshold region over a wide range of gate voltages Vgs. Therefore, by reducing the gate voltage Vgs, the off-state current of the OS transistor can be made smaller than the off-state current of the Si transistor. For example, by reducing the gate voltage Vgs to less than 0V, the off-state current can be made extremely small. In other words, in the memory cell 111 using an OS transistor as the transistor M11, the lower the gate voltage Vgs, the longer the potential of the wiring SN can be maintained.

[0075] Therefore, for example, the potential rise amount "vp" of wiring SN can be increased during the aforementioned period T15. This reduces gate voltage Vgs, thereby reducing the off-state current. For example, by increasing "vp," gate voltage Vgs can be reduced to less than 0V. This significantly reduces the off-state current of transistor M11, thereby maintaining the potential of wiring SN for a long period of time.

[0076] Here, “vp” in the period T15 is “(Vp1−Vp0)×the capacitance of the capacitor C11 / (the capacitance of the capacitor C11+the parasitic capacitance of the wiring SN)”.

[0077] Therefore, for example, the larger the capacitance of capacitor C11, the larger "vp" is, and the smaller the gate voltage Vgs of transistor M11 is. In other words, the larger the capacitance of capacitor C11 is, the longer the potential of wiring SN can be maintained.

[0078] To this end, for example, the capacitance of capacitor C11 can be made larger than the capacitance between the gate (equivalent to wiring WL) and one of the source and drain (equivalent to wiring SN) of transistor M11. Furthermore, for example, the thickness of the insulator serving as the dielectric of capacitor C11 can be made smaller than the thickness of the insulator serving as the gate insulating film of transistor M11. Furthermore, for example, the relative dielectric constant of the insulator serving as the dielectric of capacitor C11 can be made larger than the relative dielectric constant of the insulator serving as the gate insulating film of transistor M11.

[0079] Furthermore, for example, as the potential change of wiring PL (i.e., "Vp1 - Vp0") increases, "vp" increases, and the gate voltage Vgs of transistor M11 decreases. In other words, the greater the potential change of wiring PL, the longer the potential of wiring SN can be maintained.

[0080] To this end, for example, the amount of change in the potential of the wiring PL may be made larger than the amount of change in the potential of the selection signal supplied to the wiring WL (i.e., "HL"). Furthermore, from the perspective of suppressing an increase in power consumption due to a change in the potential of the wiring PL, the amount of change in the potential of the wiring PL may be made smaller than the amount of change in the potential of the selection signal.

[0081] Note that although the description here uses an operation example in which data "0" is written to a memory cell 111 holding data "1" and the data "0" is retained, the same operation also applies to the case where data "0" is written to a memory cell 111 holding data "0." Furthermore, the same operation also applies to the case where data "1" is written to a memory cell 111 holding either data "0" or "1" and the data "1" is retained.

[0082] Figure 2BThe timing diagram shows an example of an operation in which data "1" is written to memory cell 111, which previously held data "0," and the data "1" is retained. It illustrates the potentials applied to wiring WL, wiring BL, and wiring PL during each period of the operation. Note that changes in the potential of wiring SN and changes in gate voltage Vgs of transistor M11 are omitted. During period T12, when data "1" is written, the potential of wiring SN gradually rises from "VSS" to "VDD," and gate voltage Vgs of transistor M11 gradually decreases from "H-VSS" to "H-VDD." Furthermore, after data "1" is written, the potential of wiring SN reaches "VDD" during periods T13 and T14, and gate voltage Vgs of transistor M11 reaches "L-VDD." Furthermore, during period T15, the potential of wiring SN reaches "VDD+vp," and gate voltage Vgs of transistor M11 reaches "L-(VDD+vp)." Furthermore, during the period T16 , the potential of the wiring SN becomes “VDD”, and the gate voltage Vgs of the transistor M11 becomes “L-VDD”.

[0083] In other words, the gate voltage Vgs of transistor M11 in the off state when holding data "1" is lower than when holding data "0." Therefore, it can be said that if data "0" can be held for a long time according to the above working example, data "1" can also be held for a long time.

[0084] In one embodiment of the present invention, by operating the memory cell 111 as in the aforementioned period T15, for example, it is sometimes possible to achieve reduced power consumption. Specifically, from the perspective of reducing power consumption, it is preferable to reduce the amplitude of the signal in the peripheral circuit 120 during the operation of the memory cell 111. For example, it is preferable to reduce the amplitude of the signal supplied to the wiring WL (i.e., "HL"). To achieve this, for example, the potential L can be increased. However, increasing the potential L may not sufficiently reduce the gate voltage Vgs of the transistor M11 in the off state during periods T13 and T14, making it difficult to maintain the potential of the wiring SN for a long time using the off-state current. Therefore, by operating the memory cell 111 as in the aforementioned period T15, it is sometimes possible to reduce the gate voltage Vgs of the transistor M11 in the off state, thereby maintaining the potential of the wiring SN for a long time. Here, the dynamic power consumption of the peripheral circuit 120 is proportional to the square of the signal amplitude. Therefore, the reduction in power consumption resulting from the reduction in signal amplitude is greater than the increase in power consumption resulting from the addition of the driver circuit 123. Therefore, it is sometimes possible to realize a storage device capable of long-term storage while achieving low power consumption. For example, low power consumption can be achieved by reducing the frequency of data refresh.

[0085] Furthermore, in one embodiment of the present invention, by operating the memory cell 111 as in the aforementioned period T15, for example, miniaturization of the transistors used in the peripheral circuit 120 can sometimes be achieved. For example, miniaturization of the transistors used in the driver circuit 122, which generates a signal supplied to the wiring WL, can be achieved. As transistors are miniaturized, the voltage range of the circuit using the transistors decreases, so, for example, the amplitude (i.e., "HL") of the signal supplied to the wiring WL may be reduced. In other words, for example, the potential L may be increased. However, increasing the potential L may not sufficiently reduce the gate voltage Vgs of the transistor M11 in the off state during periods T13 and T14, making it difficult to maintain the potential of the wiring SN for a long period of time using the off-state current. Therefore, by operating the memory cell 111 as in the aforementioned period T15, the gate voltage Vgs of the transistor M11 in the off state may be reduced, thereby maintaining the potential of the wiring SN for a long period of time. Therefore, while miniaturization and downsizing of the transistors used in the peripheral circuit 120 can sometimes be achieved, a memory device capable of long-term storage can be realized. For example, by reducing the frequency of data refresh, power consumption can be reduced.

[0086] [Working Example 2] Figure 4A 、 Figure 4B and 5A to 5D 1 is a timing chart and a circuit diagram illustrating an example of a driving method of the memory cell 111 . Figure 4A The timing chart shown is an example of an operation in which data “1” is written to the memory cell 111 holding data “0” and the memory cell 111 holds the data “1”.

[0087] In the following description, the description of the above-mentioned Working Example 1 can be referred to as appropriate.

[0088] Furthermore, the potential of the signal supplied to the wiring PL is either the potential Vp0 or the potential Vp2 which is lower than the potential Vp0 .

[0089] During period T21, the potential H is applied to wiring WL, and the potential Vp0 is applied to wiring PL. Furthermore, as an example, "VSS," corresponding to "0," is applied to wiring BL, and the potential of wiring SN of memory cell 111 is also "VSS." At this time, the gate voltage Vgs of transistor M11 is "H-VSS," and transistor M11 is turned on. This state corresponds to the state after data "0" is read from memory cell 111 and written back. Figure 5A Note that in the following description, unless otherwise specified, the previous state is maintained.

[0090] During period T22, VDD, corresponding to "1," is supplied to wiring BL. At this time, a pulse of potential Vp2 is supplied to wiring PL. Specifically, the potential of wiring PL is simultaneously decreased from Vp0 to Vp2, and then increased from Vp2 to Vp0, in accordance with the timing of the supply of VDD to wiring BL. Consequently, through the operation described below, the potential of wiring SN gradually increases to VDD. In other words, data "1" is written to memory cell 111.

[0091] When the potential of wiring PL drops from Vp0 to Vp2, the potential of wiring SN drops due to capacitive coupling through capacitor C11. At this point, if the potential of wiring SN drops by "vp," the potential of wiring SN becomes "VSS-vp," and the gate voltage Vgs of transistor M11 becomes "H-(VSS-vp)." In other words, the gate voltage Vgs of transistor M11 increases by "vp." Figure 5B The potential of each wiring at this time is shown.

[0092] By instantaneously increasing the gate voltage Vgs at the timing of supplying VDD to the wiring BL, the on-state current of the transistor M11 can be instantaneously increased. Therefore, the speed at which the potential of the wiring SN gradually rises can be increased.

[0093] Then, when the potential of the wiring PL rises from the potential Vp2 to the potential Vp0, the potential of the wiring SN rises due to the capacitive coupling of the capacitor C11. Therefore, the time required for the potential of the wiring SN to reach "VDD" can be shortened.

[0094] Finally, the potential of the wiring SN reaches “VDD”, and the gate voltage Vgs of the transistor M11 reaches “H-VDD”. Figure 5C The potential of each wiring at this time is shown.

[0095] During period T23, the potential L is supplied to wiring WL. As a result, gate voltage Vgs of transistor M11 reaches "L-VDD," turning transistor M11 off. This completes the writing of data "1" into memory cell 111, and wiring SN maintains VDD corresponding to data "1." Figure 5D The potential of each wiring at this time is shown.

[0096] In one embodiment of the present invention, by operating the memory cell 111 as described during period T22 (i.e., decreasing the potential supplied to the wiring PL in sync with the rise in the potential of the data supplied to the wiring BL), the speed at which the potential of the wiring SN gradually rises when writing data "1" to the memory cell 111 can be increased, thereby shortening the time required to reach "VDD." In other words, the speed at which data is written to the memory cell 111 can be increased. Furthermore, since "VDD" is reached even at an increased data writing speed, the data reading speed can also be increased. Consequently, a memory device capable of increased operating speed can be realized.

[0097] In other words, as one aspect of the present invention, driver circuit 123 can function to output a signal whose potential changes in a direction opposite to the direction of potential change of the data supplied to wiring BL. In this case, the timing of potential changes of the signal output from the driver circuit can be linked to the timing of potential changes of the data. That is, for example, the potential of the signal output from driver circuit 123 can fall in sync with the timing of potential changes of the data.

[0098] Here, “vp” in the period T22 is “(Vp0−Vp2)×the capacitance of the capacitor C11 / (the capacitance of the capacitor C11+the parasitic capacitance of the wiring SN)”.

[0099] Therefore, it can be said that, for example, the larger the amount of change in the potential of the wiring PL (ie, “ Vp0 − Vp2 ”), the larger “vp” becomes, and the speed of writing data to the memory cell 111 can be increased.

[0100] To this end, for example, the amount of change in the potential of the wiring PL may be greater than the amount of change in the potential of the data supplied to the wiring BL (i.e., "VDD - VSS"). Furthermore, from the perspective of suppressing an increase in power consumption due to changes in the potential of the wiring PL, the amount of change in the potential of the wiring PL may be smaller than the amount of change in the potential of the data.

[0101] Note that the operation example described here is a case where data "1" is written to the memory cell 111 holding data "0" and the data "1" is held. However, in other cases, the operation in the above-described period T22 is preferably not employed.

[0102] For example, when data "0" is written to memory cell 111 holding data "0," the potential held by wiring SN continues to be "VSS." Furthermore, when data "1" is written to memory cell 111 holding data "1," the potential held by wiring SN continues to be "VDD." In this case, to prevent the potential of wiring SN from changing due to changes in the potential of wiring PL, it is preferable that the potential of wiring PL remain unchanged.

[0103] Furthermore, for example, when data "0" is written to memory cell 111 holding data "1," the potential of wiring SN gradually decreases during period T22 until it reaches "VSS." In this case, the potential of wiring SN increases as the potential of wiring PL rises from potential Vp2 to potential Vp0, thereby increasing the potential of wiring SN. Therefore, the time required for the potential of wiring SN to reach "VSS" cannot be shortened. Therefore, it is preferable not to change the potential of wiring PL.

[0104] Figure 4B The timing diagram shown is an example of an operation in which data "0" is written to the memory cell 111 that holds data "1" and the data "0" is held. The diagram shows the states of the potentials applied to the wiring WL, wiring BL, and wiring PL during each period of the operation. Note that changes in the potential of the wiring SN and changes in the gate voltage Vgs of the transistor M11 are omitted. In this case, during period T22 when the data "0" is written, the potential of the wiring SN gradually decreases from "VDD" to "VSS", and the gate voltage Vgs of the transistor M11 gradually increases from "H-VDD" to "H-VSS". At this time, since the potential of the wiring PL does not change, the potential change of the wiring SN due to capacitive coupling of the capacitor C11 does not occur. In addition, after the data "0" is written, the potential of the wiring SN becomes "VSS" during period T23, and the gate voltage Vgs of the transistor M11 becomes "L-VSS".

[0105] In one embodiment of the present invention, by operating the memory cell 111 as in the aforementioned period T22, for example, it is sometimes possible to achieve reduced power consumption. Specifically, from the perspective of reducing power consumption, it is preferable to reduce the amplitude of the signal in the peripheral circuit 120 during the operation of the memory cell 111. For example, it is preferable to reduce the amplitude of the signal supplied to the wiring WL (i.e., "HL"). To achieve this, for example, the potential H can be reduced. However, when the potential H is reduced, the gate voltage Vgs of the transistor M11 in the on state may not be sufficiently high, resulting in a decrease in the on-state current and a decrease in the speed of writing data to the memory cell 111. Therefore, by operating the memory cell 111 as in the period T22, it is possible to achieve, for example, an increase in the write speed and an increase in the read speed. Here, the dynamic power consumption of the peripheral circuit 120 is proportional to the square of the signal amplitude. Therefore, the reduction in power consumption due to the reduction in signal amplitude is greater than the increase in power consumption due to the addition of the driver circuit 123. Therefore, it is sometimes possible to realize a memory device that can simultaneously achieve reduced power consumption and increased operating speed. Alternatively, it is sometimes possible to realize a storage device that can suppress a decrease in operating speed while achieving low power consumption.

[0106] Furthermore, in one embodiment of the present invention, by operating the memory cell 111 as in the aforementioned period T22, it is sometimes possible to achieve, for example, miniaturization of the transistors used in the peripheral circuit 120. For example, miniaturization of the transistors used in the driver circuit 122, which generates the signal supplied to the wiring WL, can be achieved. As transistors are miniaturized, the voltage range of the circuit using the transistors decreases, so, for example, the amplitude (i.e., "HL") of the signal supplied to the wiring WL may be reduced. In other words, for example, the potential H may be reduced. However, when the potential H is reduced, the gate voltage Vgs of the transistor M11 in the on state may not be sufficiently high, resulting in a decrease in the on-state current and a decrease in the speed of writing data to the memory cell 111. Therefore, by operating the memory cell 111 as in the period T22, it is possible to achieve improvements in write speed and read speed. Therefore, it is sometimes possible to achieve miniaturization and downsizing of the transistors used in the peripheral circuit 120 while simultaneously realizing a memory device capable of increasing operating speed. Alternatively, it is sometimes possible to achieve downsizing while simultaneously suppressing a decrease in operating speed.

[0107] [Working Example 3] Figure 6A and Figure 6B 1 is a timing chart illustrating an example of a method for driving the memory cell 111 according to one embodiment of the present invention. Figure 6A and Figure 6B The timing diagram is a working example combining the above working examples 1 and 2. Therefore, the above description can be referred to, and detailed description is omitted here.

[0108] Figure 6A The timing diagram shown is an example of writing data "1" to the memory cell 111 holding data "0" and keeping the data "1". Figure 2B The timing diagram shown is the same as Figure 4A Combination of timing diagrams shown. Figure 6B The timing diagram shown is an example of writing data "0" to the memory cell 111 holding data "1" and keeping the data "0". Figure 2A The timing diagram shown is the same as Figure 4B Combination of timing diagrams shown.

[0109] In one embodiment of the present invention, by making the storage unit 111 Figure 6A and Figure 6B By operating as shown in the timing diagram, a memory device capable of achieving low power consumption and miniaturization while also achieving high operating speed and long-term storage can be realized. For example, low power consumption can be achieved by reducing the data refresh frequency.

[0110] [Drive circuit 123] Figure 7A and Figure 7B is a circuit diagram showing a structural example that can be used for the driver circuit 123.

[0111] Figure 7A The illustrated driver circuit 123 includes a transistor M2a and a transistor M2b. Transistor M2a has one of its source and drain connected to wiring PL, the other of its source and drain connected to wiring PLa, and its gate connected to wiring SEa. Transistor M2b has one of its source and drain connected to wiring PL, the other of its source and drain connected to wiring PLb, and its gate connected to wiring SEb.

[0112] Figure 7A The driving circuit 123 shown has a function of supplying the potential of either the wiring PLa or the wiring PLb to the wiring PL. Figure 7A In the driving circuit 123 shown, one of the transistor M2a and the transistor M2b is turned on and the other is turned off, whereby the potential of one of the wiring PLa and the wiring PLb is supplied to the wiring PL.

[0113] For example, in the storage device 100, by using Figure 7A The driving circuit 123 shown in FIG. 1 supplies a potential Vp1 to the wiring PLa and a potential Vp0 to the wiring PLb, and the memory cell 111 can be operated as in the above-described working example 1. In addition, for example, in the memory device 100, by using Figure 7A The driving circuit 123 shown supplies the potential Vp2 to the wiring PLa and supplies the potential Vp0 to the wiring PLb, and can operate the memory cell 111 as in the above-described Operation Example 2.

[0114] Figure 7B The driving circuit 123 shown in FIG. Figure 7A The illustrated drive circuit 123 further includes a transistor M2c. One of a source and a drain of the transistor M2c is connected to the wiring PL, the other of the source and the drain is connected to the wiring PLc, and the gate is connected to the wiring SEc.

[0115] Figure 7B The driving circuit 123 shown has a function of supplying the potential of any one of the wirings PLa to PLc to the wiring PL. Figure 7B In the driving circuit 123 shown, by turning on any one of the transistors M2 a to M2 c and turning off the other transistors, the potential of any one of the wirings PLa to PLc is supplied to the wiring PL.

[0116] For example, in the storage device 100, by using Figure 7BThe driving circuit 123 shown supplies a potential Vp1 to the wiring PLa, a potential Vp0 to the wiring PLb, and a potential Vp2 to the wiring PLc, and can operate the memory cell 111 as in the above-described Operation Example 3.

[0117] Notice, Figure 7A and Figure 7B The driver circuit 123 shown is merely an example, and the structure is not limited to this. Although an example of a structure using n-channel transistors is shown here, p-channel transistors or a CMOS circuit may also be used.

[0118] <Storage Device Configuration Example 2> Next, the connection relationship between the plurality of memory cells 111 arranged in a matrix and the plurality of drive circuits 123 will be described. Note that for simplicity of description, a case where four memory cells 111 are arranged in a matrix of 2 rows x 2 columns will be described as an example.

[0119] [Connection Example 1] Figure 8 1 is a circuit diagram illustrating an example of a connection relationship between four memory cells 111 arranged in a matrix of 2 rows×2 columns and two drive circuits 123 .

[0120] Figure 8 The memory cell 111[1,1] arranged in the first row and first column, the memory cell 111[1,2] arranged in the first row and second column, the memory cell 111[2,1] arranged in the second row and first column, and the memory cell 111[2,2] arranged in the second row and second column in the memory array 110 are shown. In addition, the driver circuit 123[1] arranged in the first row and the driver circuit 123[2] arranged in the second row in the peripheral circuit 120 are shown. Note that Figure 8 , the driving circuit 121[1] configured on the first column, the driving circuit 121[2] configured on the second column, the driving circuit 122[1] configured on the first row, and the driving circuit 122[2] configured on the second row are omitted.

[0121] The wiring PL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the drive circuit 123[1]. The wiring PL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2], and the drive circuit 123[2]. In addition, the wiring BL[1] arranged in the first column is connected to the memory cells 111[1,1] and 111[2,1], and the drive circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cells 111[1,2] and 111[2,2], and the drive circuit 121[2]. In addition, the wiring WL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the drive circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cell 111[2,1], the memory cell 111[2,2], and the driver circuit 122[2].

[0122] Figure 9 It is an explanation Figure 8 The timing diagram of an example of a driving method for the four memory cells 111 shown in FIG. Here, an operation example is shown in which data is maintained by selecting the first row, writing data "1" to the memory cell 111 [1, 1] holding data "0", and writing data "0" to the memory cell 111 [1, 2] holding data "1". As the driving method for each memory cell 111, the above-mentioned operation example 1 is adopted. Figure 8 In the structure shown, the wiring PL connects each memory cell 111 arranged in each row to the driver circuit 123. Therefore, it can be said that the structure of the above-mentioned working example 1 is suitable for driving the memory cell 111. In addition, the description of the above-mentioned working example 1 can be appropriately referred to.

[0123] Period T1a is a period during which the four memory cells 111 retain data. At this time, wiring WL[1] and wiring WL[2] are at potential L, wiring BL[1] and wiring BL[2] are at an intermediate potential between potential VDD and potential VSS, and wiring PL[1] and wiring PL[2] are at potential Vp1.

[0124] The period T1b is a period immediately before the start of reading and writing data from the first row memory cell 111 and corresponds to the period T16. Here, the potential of the wiring PL[1] is lowered from the potential Vp1 to the potential Vp0.

[0125] Period T1c is the period immediately following the start of data reading and writing back to the memory cell 111 in the first row. During this period, a potential H is applied to wiring WL[1]. At this point, the potential of wiring BL[1] drops from its intermediate potential, while the potential of wiring BL[2] rises from its intermediate potential. This change is amplified by the sense amplifier, and data is read. Note that the potential held in memory cell 111 changes due to data reading (i.e., the read state is destroyed), so data is subsequently written back.

[0126] The period T1d is a period immediately after the data reading and writing are completed for the memory cells 111 in the first row, and corresponds to the period T11.

[0127] The period T1e is a period during which data is written to the memory cell 111 [1, 1], and corresponds to the period T12.

[0128] The period T1f is a period during which data is written to the memory cell 111 [1, 2], and corresponds to the period T12.

[0129] The period T1g is a period immediately after the completion of data writing to the first row memory cell 111 and corresponds to the period T13. Here, the potential L is supplied to the wiring WL[1].

[0130] The period T1h is a period during which the wiring BL[1] and the wiring BL[2] are precharged to the intermediate potential Vpre, and corresponds to the period T14.

[0131] Period T1i is a period during which the potential of wiring PL[1] is increased to hold the data written to the memory cell 111 in the first row for a long period of time, and corresponds to period T15. Here, the potential of wiring PL[1] is increased from potential Vp0 to potential Vp1.

[0132] In this manner, a plurality of memory cells 111 and a plurality of drive circuits 123 arranged in a matrix are connected. Figure 8 When connected as shown, by using Figure 9 The driving method shown can retain the data written to the memory cell 111 for a long time. Therefore, a memory device capable of long-term storage can be realized. For example, by reducing the data refresh frequency, low power consumption can be achieved.

[0133] [Connection Example 2] Figure 10 1 is a circuit diagram illustrating another example of the connection relationship between four memory cells 111 arranged in a matrix of 2 rows×2 columns and two drive circuits 123 .

[0134] Figure 10The memory cell 111[1,1] arranged in the first row and first column, the memory cell 111[1,2] arranged in the first row and second column, the memory cell 111[2,1] arranged in the second row and first column, and the memory cell 111[2,2] arranged in the second row and second column in the memory array 110 are shown. In addition, the driver circuit 123[1] arranged in the first column and the driver circuit 123[2] arranged in the second column in the peripheral circuit 120 are shown. Note that in Figure 10 , the driving circuit 121[1] configured on the first column, the driving circuit 121[2] configured on the second column, the driving circuit 122[1] configured on the first row, and the driving circuit 122[2] configured on the second row are omitted.

[0135] The wiring PL[1] arranged in the first column is connected to the memory cell 111[1,1] and the memory cell 111[2,1], and the drive circuit 123[1]. The wiring PL[2] arranged in the second column is connected to the memory cell 111[1,2] and the memory cell 111[2,2], and the drive circuit 123[2]. In addition, the wiring BL[1] arranged in the first column is connected to the memory cell 111[1,1] and the memory cell 111[2,1], and the drive circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cell 111[1,2] and the memory cell 111[2,2], and the drive circuit 121[2]. In addition, the wiring WL[1] arranged in the first row is connected to the memory cell 111[1,1] and the memory cell 111[1,2], and the drive circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cell 111[2,1], the memory cell 111[2,2], and the driver circuit 122[2].

[0136] Figure 11 It is an explanation Figure 10 The timing diagram of an example of a driving method for the four memory cells 111 shown in FIG. Here, an operation example is shown in which data is maintained by selecting the first row, writing data "1" to the memory cell 111 [1, 1] holding data "0", and writing data "0" to the memory cell 111 [1, 2] holding data "1". As the driving method for each memory cell 111, the above-mentioned operation example 2 is adopted. Figure 10 In the illustrated structure, the wiring PL connects each memory cell 111 arranged in each column to the driver circuit 123. Therefore, it can be said that the structure of the above-mentioned working example 2 is suitable for driving the memory cell 111. In addition, the description of the above-mentioned working example 2 can be appropriately referred to.

[0137] Period T2b is a period during which the four memory cells 111 retain data. At this time, wiring WL[1] and wiring WL[2] are at potential L, wiring BL[1] and wiring BL[2] are at an intermediate potential between potential VDD and potential VSS, and wiring PL[1] and wiring PL[2] are at potential Vp0.

[0138] The period T2c, the period T2d, the period T2g, and the period T2h are respectively the same as the above-mentioned period T1c, the period T1d, the period T1g, and the period T1h.

[0139] Period T2e is a period for writing data to the memory cell 111[1,1] and corresponds to period T22. Here, data "1" is written to the memory cell 111[1,1] holding data "0", so a pulse of potential Vp2 is supplied to the wiring PL[1].

[0140] Period T2f is a period for writing data to the memory cell 111[1,2] and corresponds to period T22. Here, data "0" is written to the memory cell 111[1,2] holding data "1", so the potential of the wiring PL[2] does not change.

[0141] In this manner, a plurality of memory cells 111 and a plurality of drive circuits 123 arranged in a matrix are connected. Figure 10 When connected as shown, by using Figure 11 The driving method shown can increase the speed of writing data to the memory cell 111. Furthermore, even if the data writing speed is increased, "VDD" is reached, so the data reading speed can also be increased. Therefore, a memory device capable of increasing the operating speed can be realized.

[0142] [Connection Example 3] Figure 12 This is a circuit diagram illustrating another example of the connection relationship between four memory cells 111 arranged in a matrix of 2 rows×2 columns and four drive circuits 123 arranged in a matrix of 2 rows×2 columns.

[0143] Figure 12 The memory cell 111[1,1] arranged in the first row and first column, the memory cell 111[1,2] arranged in the first row and second column, the memory cell 111[2,1] arranged in the second row and first column, and the memory cell 111[2,2] arranged in the second row and second column in the memory array 110 are shown. In addition, the driver circuit 123[1,1] arranged in the first row and first column, the driver circuit 123[1,2] arranged in the first row and second column, the driver circuit 123[2,1] arranged in the second row and first column, and the driver circuit 123[2,2] arranged in the second row and second column in the peripheral circuit 120 are shown. Note that in Figure 12, the driving circuit 121[1] configured on the first column, the driving circuit 121[2] configured on the second column, the driving circuit 122[1] configured on the first row, and the driving circuit 122[2] configured on the second row are omitted.

[0144] The wiring PL[1,1] arranged in the first row and first column is connected to the memory cell 111[1,1] and the drive circuit 123[1,1]. The wiring PL[1,2] arranged in the first row and second column is connected to the memory cell 111[1,2] and the drive circuit 123[1,2]. The wiring PL[2,1] arranged in the second row and first column is connected to the memory cell 111[2,1] and the drive circuit 123[2,1]. The wiring PL[2,2] arranged in the second row and second column is connected to the memory cell 111[2,2] and the drive circuit 123[2,2]. In addition, the wiring BL[1] arranged in the first column is connected to the memory cell 111[1,1] and the memory cell 111[2,1], and the drive circuit 121[1]. The wiring BL[2] arranged in the second column is connected to the memory cell 111[1,2] and the memory cell 111[2,2], and the drive circuit 121[2]. Furthermore, the wiring WL[1] arranged in the first row is connected to the memory cells 111[1,1] and 111[1,2], and the driver circuit 122[1]. The wiring WL[2] arranged in the second row is connected to the memory cells 111[2,1] and 111[2,2], and the driver circuit 122[2].

[0145] Figure 13 It is an explanation Figure 12 The timing diagram of an example of a driving method for the four memory cells 111 shown in FIG. Here, an operation example is shown in which data is maintained by selecting the first row, writing data "1" to the memory cell 111 [1, 1] holding data "0", and writing data "0" to the memory cell 111 [1, 2] holding data "1". As the driving method for each memory cell 111, the above-mentioned operation example 3 is adopted. Figure 12 In the structure shown, the wiring PL is connected to the driving circuit 123 for each memory cell 111, so it can be said that the structure of the above-mentioned working example 3 is suitable as a driving method for the memory cell 111. Figure 13 The timing diagram shown above can also be said to be Figure 9 An example of the driving method shown is Figure 11 Therefore, the above description can be referred to, and detailed description is omitted here.

[0146] Figure 14A It shows Figure 12The circuit diagram is a configuration example of four drive circuits 123 arranged in a matrix of 2 rows and 2 columns in the connection example shown.

[0147] Figure 14A The peripheral circuit 120 shows a driving circuit 123[1,1] configured on the first row and first column, a driving circuit 123[1,2] configured on the first row and second column, a driving circuit 123[2,1] configured on the second row and first column, and a driving circuit 123[2,2] configured on the second row and second column.

[0148] Wiring PBL[1] arranged in the first column is connected to driving circuit 123[1,1] and driving circuit 123[2,1]. Wiring PBL[2] arranged in the second column is connected to driving circuit 123[1,2] and driving circuit 123[2,2]. Furthermore, wiring PWL[1] arranged in the first row is connected to driving circuit 123[1,1] and driving circuit 123[1,2]. Wiring PWL[2] arranged in the second row is connected to driving circuit 123[2,1] and driving circuit 123[2,2].

[0149] Each driver circuit 123 includes a transistor M21. One of a source and a drain of the transistor M21 is connected to the wiring PL, the other of the source and the drain is connected to the wiring PBL, and the gate is connected to the wiring PWL.

[0150] exist Figure 14A In the example, by supplying the potentials to the wiring PWL[1] and the wiring PWL[2], and the potentials to the wiring PBL[1] and the wiring PBL[2], a desired potential can be supplied to the wiring PL arranged in any row or column. That is, in the memory array 110, the potential of the wiring PL can be changed according to each memory cell 111. Therefore, Figure 13 The driving method shown.

[0151] Figure 14B 123 is a circuit diagram showing another configuration example of the driving circuit 123 . Figure 14B The driving circuit 123 shown is Figure 14A The driver circuit 123 shown differs in that it includes a NAND circuit X21 in place of the transistor M21. One of a pair of input terminals of the NAND circuit X21 is connected to the wiring PBL, the other of the pair of input terminals is connected to the wiring PWL, and the output terminal is connected to the wiring PL. A NAND gate available in a standard circuit library can be used as the NAND circuit X21.

[0152] Notice, Figure 14A and Figure 14B The driving circuit 123 shown is just an example, and the structure is not limited to this.

[0153] Here, in Figure 12 In the example of connection shown in FIG. 1 , a structure in which each memory cell 111 is stacked on each drive circuit 123 may also be adopted. Figure 14A In the structure shown, the transistor M11 and capacitor C11 included in each memory cell 111 may be stacked on the transistor M21 included in each driver circuit 123. By adopting a structure in which the transistor M11 and capacitor C11 are stacked on the transistor M21, the increase in occupied area due to the provision of the driver circuit 123 can be suppressed.

[0154] <Storage Device Configuration Example 3> A storage device 700 according to one embodiment of the present invention will be described.

[0155] Figure 15 and Figure 16 700 is a block diagram illustrating a configuration example of the storage device 700. Figure 15 and Figure 16 The illustrated memory device 700 includes a memory array portion 721 and a peripheral circuit portion 722 .

[0156] The memory array unit 721 includes a plurality of memory cells 111. The plurality of memory cells 111 are arranged in a matrix of M rows x N columns. Here, M is an integer greater than or equal to 1. N is an integer greater than or equal to 1.

[0157] In addition, Figure 15 and Figure 16 , typically shown are a storage cell 111[1,1] configured on the first row and first column, a storage cell 111[1,N] configured on the first row and Nth column, a storage cell 111[M,1] configured on the Mth row and first column, and a storage cell 111[M,N] configured on the Mth row and Nth column.

[0158] also, Figure 15 Shown are the wiring WL[1] and the wiring PL[1] connected to the N memory cells 111 arranged on the first row, the wiring WL[M] and the wiring PL[M] connected to the N memory cells 111 arranged on the M row, the wiring BL[1] connected to the M memory cells 111 arranged on the first column, and the wiring BL[N] connected to the M memory cells 111 arranged on the N column.

[0159] also, Figure 16Shown are the wiring WL[1] connected to the N memory cells 111 arranged on the first row, the wiring WL[M] connected to the N memory cells 111 arranged on the M row, the wiring BL[1] and the wiring PL[1] connected to the M memory cells 111 arranged on the first column, and the wiring BL[N] and the wiring PL[N] connected to the M memory cells 111 arranged on the N column.

[0160] Here, the memory array unit 721 corresponds to the memory array 110. Figure 15 The structure example of the storage array unit 721 shown is equivalent to the above Figure 8 The connection example shown. In addition, Figure 16 The structure example of the storage array unit 721 shown is equivalent to the above Figure 10 Connection example shown.

[0161] The peripheral circuit section 722 includes a power switch 761 , a power switch 762 , and a peripheral circuit 771 . The peripheral circuit 771 includes a peripheral circuit 781 , a control circuit 772 , and a voltage generating circuit 773 .

[0162] In one embodiment of the present invention, for example, Si transistors can be used as transistors constituting the peripheral circuit portion 722. Therefore, in the peripheral circuit portion 722, for example, a CMOS circuit (for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) in which the gate of an n-channel Si transistor and the gate of a p-channel Si transistor are connected can be used.

[0163] Furthermore, for example, by using OS transistors as transistors constituting the memory cell 111, the memory array unit 721 can be stacked on the peripheral circuit unit 722 using Si transistors. Consequently, the memory device 700 can be miniaturized. Furthermore, the wiring distance between the peripheral circuit unit 722 and the memory array unit 721 can be shortened. Consequently, the read and write speeds of the memory device 700 can be improved.

[0164] Although not shown, the following configuration may be employed: in the memory device 700, the memory array section 721 includes a plurality of sense amplifiers arranged in a matrix, with a plurality of memory cells 111 stacked on the sense amplifiers. This configuration allows simultaneous access to the plurality of sense amplifiers, enabling large-scale parallel reading of data stored in the memory array section 721.

[0165] Terminals BW, CE, GW, MCK, WAKE, ADDR, WDA, PON1, and PON2 all supply signals from outside the memory device 700. For example, terminal RDA outputs a signal to the outside of the memory device 700.

[0166] For example, a clock signal is supplied to terminal MCK. Furthermore, control signals are supplied to terminals BW, CE, and GW. A chip enable signal is supplied to terminal CE. A global write enable signal is supplied to terminal GW. A byte write enable signal is supplied to terminal BW. An address signal is supplied to terminal ADDR. Write data is supplied to terminal WDA. Read data is supplied to terminal RDA. Power gating control signals are supplied to terminals PON1 and PON2. Furthermore, the signals supplied to terminals PON1 and PON2 may also be generated, for example, in control circuit 772.

[0167] The control circuit 772 has a function of controlling the operation of the memory device 700. For example, the control circuit 772 has a function of performing a logical operation on the signals supplied to each of the terminals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device 700. Furthermore, the control circuit 772 has a function of generating a signal to control the peripheral circuit 781 so as to execute the operation mode.

[0168] The voltage generating circuit 773 has a function of generating an arbitrary potential for operating the peripheral circuit unit 722. For example, the voltage generating circuit 773 has a function of generating an arbitrary potential based on a signal supplied to a terminal WAKE and a clock signal supplied to a terminal MCK. For example, a signal is supplied to the terminal WAKE that controls whether the clock signal supplied to the terminal MCK is input to the voltage generating circuit 773.

[0169] The peripheral circuit 781 has the function of writing and reading data from the memory cell 111. For example, the peripheral circuit 781 has the function of generating various signals for controlling the operation of the memory cell 111. The peripheral circuit 781 includes a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0170] The row decoder 782 and column decoder 784 decode address signals supplied to the ADDR terminal. The row decoder 782 specifies the row to be accessed. The column decoder 784 specifies the column to be accessed. The row driver 783 selects the row specified by the row decoder 782 and supplies a desired signal to the corresponding memory cell 111, for example. The column driver 785 selects the column specified by the column decoder 784 and supplies a desired signal to the corresponding memory cell 111, for example.

[0171] The data driver 786 has the function of writing and reading data to and from the memory cell 111 selected by the row driver and column driver. The input circuit 787 has the function of holding data supplied to the terminal WDA from outside the memory device 700. The data (data Din) held in the input circuit 787 is written to the memory cell 111 via the data driver 786. The data stored in the memory cell 111 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has the function of holding the read data (data Dout). In addition, it has the function of outputting the held data to the outside of the memory device 700 via the terminal RDA.

[0172] Note that the peripheral circuit 781 can have a function equivalent to the above-described peripheral circuit 120. That is, it can have a function equivalent to the driver circuit 121, a function equivalent to the driver circuit 122, and a function equivalent to the driver circuit 123.

[0173] exist Figure 15 In the illustrated memory device 700, for example, the row driver 783 may have functions equivalent to the driver circuit 122 and the driver circuit 123, and the column driver 785 and the data driver 786 may have functions equivalent to the driver circuit 121. Specifically, the row driver 783 may supply desired signals to the wirings WL[1] to WL[M] and supply desired potentials to the wirings PL[1] to PL[M], and the column driver 785 and the data driver 786 may transmit and receive data to and from the wirings BL[1] to BL[N].

[0174] In addition, Figure 16In the illustrated memory device 700, for example, the row driver 783 may have a function equivalent to the driver circuit 122, and the column driver 785 and the data driver 786 may have a function equivalent to the driver circuit 121 and the driver circuit 123. Specifically, the row driver 783 may supply a desired signal to the wirings WL[1] to WL[M], and the column driver 785 and the data driver 786 may transmit and receive data to and from the wirings BL[1] to BL[N], thereby supplying a desired potential to the wirings PL[1] to PL[M].

[0175] The power switch 761 controls whether the potential supplied to terminal VMD is supplied to the peripheral circuit 771. The power switch 762 controls whether the potential supplied to terminal VMH is supplied to the row driver 783. For example, a high power supply potential (e.g., potential VDD) for operating the peripheral circuit unit 722 is supplied to terminal VMD, and a low power supply potential (e.g., potential VSS) is supplied to terminal VMS. Furthermore, for example, a high power supply potential (e.g., a potential higher than potential VDD) for operating the memory cell 111 and the like is supplied to terminal VMH. The conductive and non-conductive states of the power switch 761 are controlled by a signal supplied to terminal PON1. The conductive and non-conductive states of the power switch 762 are controlled by a signal supplied to terminal PON2.

[0176] In the peripheral circuit portion 722, each circuit and each terminal can be selected or removed as appropriate. In addition, other circuits and other terminals can be added as appropriate.

[0177] Note that one embodiment of the present invention is not limited to the working examples described in this embodiment mode. At least a portion of the structural examples, working examples, and drawings corresponding to these examples described in this embodiment mode may be appropriately combined with other structural examples, working examples, drawings, and other embodiments described elsewhere in this specification.

[0178] Implementation Method 2 This embodiment will describe a structural example of a memory cell that can be used in the memory device described in Embodiment 1. Also, a structural example of a transistor that can be used in the memory device described in Embodiment 1 will be described.

[0179] <Structure Example of Memory Cell> 17A to 17C 1 and 2 are top views and cross-sectional views illustrating a structural example of a semiconductor device 200 including a transistor 600 and a capacitor 690. At least a portion of the semiconductor device 200 can be used in a memory cell according to one embodiment of the present invention. For example, the semiconductor device 200 can be used in the memory cell 111 described in Embodiment 1.

[0180] Figure 17A is a top view of the semiconductor device 200 . Figure 17B It is along Figure 17A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 in FIG. Figure 17C It is along Figure 17A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 in FIG. Figure 17A In the top view, some components are omitted for clarity. Figure 43A FIG2 is a perspective view of a semiconductor device 200 with some components omitted. Figure 43A An example is shown in which the outer edge shapes of the conductor 630 , the conductor 634 , and the oxide 650 are circular when viewed from above.

[0181] 17A to 17C The figure shows an insulator 612, a conductor 610 on the insulator 612, a transistor 600 and a capacitor 690 on the conductor 610, an insulator 620 on the conductor 610, an insulator 640 on the insulator 620, and an insulator 678 on the transistor 600 and the capacitor 690. The insulator 612, the insulator 620, the insulator 640, and the insulator 678 serve as interlayer films. The conductor 610 serves as wiring.

[0182] like 17A to 17C As shown, transistor 600 overlaps with capacitor 690. Furthermore, opening 648, which is a portion of the structure in which transistor 600 is provided, has a region that overlaps with opening 628, which is a portion of the structure in which capacitor 690 is provided. In particular, conductor 630 serves as one of the source and drain electrodes of transistor 600 and one of a pair of electrodes of capacitor 690, so transistor 600 and capacitor 690 share a portion of the structure. This structure allows transistor 600 and capacitor 690 to be provided without significantly increasing the area occupied when viewed from above.

[0183] [Capacitor 690] Capacitor 690 includes a conductor 634 on conductor 610, an insulator 632 on conductor 634, and a conductor 630 on insulator 632. Conductor 630 serves as one of a pair of electrodes (sometimes referred to as the upper electrode), conductor 634 serves as the other of the pair of electrodes (sometimes referred to as the lower electrode), and insulator 632 serves as a dielectric. In other words, capacitor 690 forms a MIM (Metal-Insulator-Metal) capacitor.

[0184] like Figure 17B and Figure 17CAs shown, an opening 628 is provided in the insulator 620 that reaches the conductor 610. At least a portion of the conductor 634 is disposed in the opening 628. Note that the conductor 634 has a region in contact with the top surface of the conductor 610 in the opening 628, a region in contact with the side surface of the insulator 620 in the opening 628, and a region in contact with at least a portion of the top surface of the insulator 620. The insulator 632 is disposed so that at least a portion thereof is located in the opening 628. The conductor 630 is disposed so that at least a portion thereof is located in the opening 628. In addition, as shown in FIG. Figure 17B and Figure 17C As shown, the conductor 630 is preferably disposed in a manner of being embedded in the opening 628 .

[0185] Capacitor 690 has a structure where the upper electrode and the lower electrode face each other through a dielectric not only at the bottom but also on the side of opening 628, thereby increasing the electrostatic capacitance per unit area. Therefore, the deeper the opening 628, the greater the electrostatic capacitance of capacitor 690.

[0186] The side surfaces of the opening 628 (sometimes also referred to as the side surfaces of the opening 628 of the insulator 620) are preferably perpendicular to the top surface of the conductor 610. In other words, the insulator 620 can also be said to include the opening 628 extending in a direction perpendicular to the top surface of the conductor 610. In this case, the opening 628 has a cylindrical shape.

[0187] Note that while this embodiment shows an example in which the shape of the opening 628 when viewed from above is circular, one embodiment of the present invention is not limited to this. For example, the shape of the opening 628 when viewed from above may also be a substantially circular shape such as an ellipse, a polygon such as a square, or a shape with rounded corners on a polygon such as a square. In this case, the maximum width of the opening 628 can be appropriately calculated based on the shape of the uppermost portion of the opening 628 when viewed from above.

[0188] For example, when the opening 628 is a quadrangle in a plan view, the maximum width of the opening 628 may be the length of the diagonal of the quadrangle. Alternatively, when the opening 628 is a substantially circular shape such as an ellipse, a polygon, or a polygon with curved corners in a plan view, the maximum width of the opening 628 may be the maximum width of the shape of the opening 628 when viewed from above.

[0189] The portions of the conductor 634, the insulator 632, and the conductor 630 disposed in the opening 628 reflect the shape of the opening 628. Therefore, the conductor 634 is disposed along the opening 628, the insulator 632 is disposed so as to cover the conductor 634, and the conductor 630 is disposed so as to fit into a recess of the insulator 632 that reflects the shape of the opening 628.

[0190] In other words, a portion of the dielectric of capacitor 690 (equivalent to insulator 632) is disposed along the side surface of opening 628. In other words, it is disposed perpendicular to the top surface of conductor 610. In other words, both the surface where the upper electrode of capacitor 690 contacts the dielectric and the surface where the lower electrode contacts the dielectric have components perpendicular to the top surface of conductor 610.

[0191] Note that in Figure 17B and Figure 17C In the embodiment, the opening 628 is provided so that the side surface of the opening 628 is perpendicular to the top surface of the conductor 610 , but one embodiment of the present invention is not limited thereto. For example, the side surface of the opening 628 may also have a tapered shape.

[0192] In this specification, etc., a tapered shape refers to a shape in which at least a portion of a side surface of a component is inclined relative to the substrate surface. Furthermore, the angle formed by the inclined side surface and the substrate surface is referred to as the taper angle. In particular, in this specification, etc., a tapered shape having a taper angle greater than 0° and less than 90° is sometimes referred to as a positive taper, and a tapered shape having a taper angle greater than 90° and less than 180° is sometimes referred to as a negative taper.

[0193] Conductors 634 and insulators 632 are stacked along the side surfaces of opening 628 and the top surface of conductor 610. Furthermore, conductor 630 is provided on insulator 632 so as to be embedded in opening 628. In this specification, capacitor 690 having such a structure is sometimes referred to as a trench capacitor, trench capacitor, or deep-hole stacked capacitor.

[0194] The insulator 640 is disposed on the capacitor 690. That is, the insulator 640 is disposed above the conductor 634, the insulator 632, and the conductor 630. In other words, the conductor 630 is disposed below the insulator 640.

[0195] The conductor 610 is provided below the conductor 634 . The conductor 634 has a region in contact with the conductor 610 .

[0196] The conductor 610 is provided on the insulator 612. The conductor 610 can be provided in a planar shape, for example.

[0197] As the insulator 612 , for example, a material that can be used for the insulator 514 described later can be used.

[0198] Conductor 610 is preferably made of a highly conductive material. Conductor 610 may have a single-layer structure or a structure in which different materials are stacked. For example, materials that can be used for conductor 503 or conductor 560, described later, may be used as conductor 610. For example, tungsten or the like may be used.

[0199] Furthermore, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion, etc., as a single layer or a stacked layer as the conductor 634. Thus, when an oxide insulator is used as the insulator 632, oxidation of the conductor 634 by the insulator 632 can be suppressed. Furthermore, when an oxide insulator is used as the insulator 620, oxidation of the conductor 634 by the insulator 620 can be suppressed.

[0200] As the conductor 634, for example, a material that can be used for the conductor 503 or the conductor 560 described later can also be used. For example, titanium nitride or silicon-doped indium tin oxide can also be used. In addition, for example, a structure in which titanium nitride is stacked on tungsten can also be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride layer, and a second titanium nitride layer is stacked on the tungsten layer can also be used.

[0201] The insulator 632 is provided on the conductor 634. The insulator 632 is provided so as to contact the top and side surfaces of the conductor 634. In other words, the insulator 632 preferably covers the side ends of the conductor 634. This prevents the conductor 634 from short-circuiting with the conductor 630.

[0202] In addition, if Figure 17B and Figure 17C As shown, the insulator 632 may also extend in contact with the top surface of the insulator 620 .

[0203] Alternatively, a structure may be employed in which the side ends of the insulator 632 coincide with the side ends of the conductor 634. With this structure, the insulator 632 and the conductor 634 can be formed using the same mask, thereby simplifying the manufacturing process.

[0204] A material with a high relative dielectric constant, so-called high-k material, is preferably used as the insulator 632. By using a high-k material as the insulator 632, the thickness of the insulator 632 can be increased to a level that can suppress gate leakage current and ensure sufficient electrostatic capacitance of the capacitor 690.

[0205] For example, as an insulator composed of a high dielectric constant material, an oxide, oxynitride, oxynitride, or nitride containing one or more metal elements selected from aluminum, hafnium, zirconium, and gallium can be used. Furthermore, these materials may contain silicon. Furthermore, insulators composed of the above materials may be stacked.

[0206] In addition, as an insulator made of a high dielectric constant material, for example, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, or an oxynitride containing hafnium and zirconium, etc. can be used.

[0207] Alternatively, a laminate of an insulator made of the above materials may be used. In this case, a laminate of a high dielectric constant material and a material having a dielectric strength greater than that of the high dielectric constant material is preferably used.

[0208] As the above-mentioned insulator, for example, an insulator composed of zirconium oxide, aluminum oxide, and zirconium oxide stacked in sequence can be used. Another example is an insulator composed of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide stacked in sequence can be used. Another example is an insulator composed of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide stacked in sequence can be used. By stacking an insulator with relatively high dielectric strength, such as aluminum oxide, as this insulator, the dielectric strength can be increased, thereby suppressing electrostatic breakdown in capacitors using this insulator.

[0209] The conductor 630 is provided so as to be in contact with a portion of the top surface of the insulator 632. Furthermore, the side end portions of the conductor 630 are preferably located inside the side end portions of the conductor 634 in both the X and Y directions. Note that, when the insulator 632 covers the side end portions of the conductor 634, the side end portions of the conductor 630 may also be located outside the side end portions of the conductor 634.

[0210] A single layer or a stack of the above-mentioned conductive materials can be used for the conductor 630. As the conductor 630, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion.

[0211] As the conductor 630, for example, a material that can be used for the conductor 503, the conductor 560, or the conductor 542 described later can be used. For example, titanium nitride or tantalum nitride can be used.

[0212] Since insulator 620 is used as an interlayer film, its relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced. Insulator 620 can be a single layer or a stack of insulators containing a material with a low relative dielectric constant.

[0213] For example, a material that can be used for the insulator 516 described later can be used as the insulator 620. For example, silicon oxide or silicon oxynitride is preferably used from the viewpoint of thermal stability.

[0214] [Transistor 600] Transistor 600 includes a conductor 630, a conductor 660 on an insulator 640, an oxide 650, an insulator 672 on the oxide 650, and a conductor 670 on the insulator 672. Oxide 650 serves as a semiconductor film including a channel formation region, conductor 670 serves as a gate electrode, insulator 672 serves as a gate insulating film, conductor 630 serves as one of a source electrode and a drain electrode, and conductor 660 serves as the other of the source electrode and the drain electrode.

[0215] In the transistor 600, a metal oxide serving as an oxide semiconductor is used as the oxide 650 including the channel formation region. As the oxide 650, for example, a metal oxide that can be used for the oxide 530 described later can also be used.

[0216] Note that semiconductors that can be used as the oxide 650 including the channel formation region are not limited to metal oxides that can be used as oxide semiconductors. The same applies to oxides 530 and 830 described later. Therefore, in this specification and other documents, "oxide" may be replaced with "semiconductor," "semiconductor layer," or "semiconductor film," as appropriate.

[0217] like Figure 17B and Figure 17C As shown, an opening 648 is provided in the insulator 640 and the conductor 660, which reaches the conductor 630. At least a portion of the oxide 650 is disposed in the opening 648. Note that the oxide 650 has a region in contact with the top surface of the conductor 630 in the opening 648, a region in contact with the side surface of the conductor 660 in the opening 648, and a region in contact with at least a portion of the top surface of the conductor 660. The insulator 672 is disposed so that at least a portion thereof is located in the opening 648. The conductor 670 is disposed so that at least a portion thereof is located in the opening 648. In addition, as shown in FIG. Figure 17B and Figure 17C As shown, the conductor 670 is preferably disposed in a manner of being embedded in the opening 648 .

[0218] For example, a structure in which tantalum nitride is stacked on titanium nitride may be employed as the conductor 630. In this case, the titanium nitride may be in contact with the insulator 632, and the tantalum nitride may be in contact with the oxide 650. This structure can suppress excessive oxidation of the conductor 630 due to the oxide 650. Furthermore, when an oxide insulator is used as the insulator 632, excessive oxidation of the conductor 630 due to the insulator 632 can be suppressed. Furthermore, for example, a structure in which tungsten is stacked on titanium nitride may be employed as the conductor 630.

[0219] Furthermore, since the conductor 630 has a region in contact with the oxide 650, it is preferable to use a conductive material containing oxygen. This structure allows the conductor 630 to maintain conductivity even when oxygen is absorbed. Furthermore, when the insulator 632 is made of a material containing oxygen, the conductivity of the conductor 630 can also be maintained.

[0220] As the conductor 630 , for example, indium tin oxide (also referred to as ITO), silicon-added indium tin oxide (also referred to as ITSO), indium zinc oxide (also referred to as IZO (registered trademark)), or the like can be used in a single layer or a stacked layer.

[0221] Oxide 650 has a region in contact with the side surface of conductor 660 in opening 648 and a region in contact with a portion of the top surface of conductor 660. Thus, by oxide 650 contacting the top surface of conductor 660 in addition to the side surface, the contact area between oxide 650 and conductor 660 can be increased.

[0222] also, Figure 17C The structure shown is one in which the side ends of the oxide 650 are located inside the side ends of the conductor 660. Note that one embodiment of the present invention is not limited to this. For example, a structure may be employed in which the side ends of the oxide 650 and the side ends of the conductor 660 are aligned in the Y direction. Alternatively, a structure may be employed in which the side ends of the oxide 650 are located outside the side ends of the conductor 660.

[0223] like 17A to 17C As shown, it is preferred that the conductor 670 extends in the Y direction and the conductor 660 extends in the X direction. By adopting this structure, the conductor 670 and the conductor 660 intersect each other. Figure 17A The conductor 610 is provided in a planar shape, but one embodiment of the present invention is not limited thereto. For example, the conductor 610 may be parallel to the conductor 670 or the conductor 660 .

[0224] The side surfaces of the opening 648 (sometimes also referred to as the side surfaces of the opening 648 of the insulator 640) are preferably perpendicular to the top surface of the conductor 610. In other words, the insulator 640 can also be said to include the opening 648 extending in a direction perpendicular to the top surface of the conductor 610. In this case, the opening 648 has a cylindrical shape.

[0225] Note that while this embodiment shows an example in which the shape of the opening 648 when viewed from above is circular, one embodiment of the present invention is not limited to this. For example, the shape of the opening 648 when viewed from above may also be a substantially circular shape such as an ellipse, a polygon such as a square, or a shape with rounded corners on a polygon such as a square. In this case, the maximum width of the opening 648 can be appropriately calculated based on the shape of the top portion of the opening 648 when viewed from above.

[0226] For example, if the opening 648 is a quadrangle when viewed from above, the maximum width of the opening 648 may be the length of the diagonal of the quadrangle. Alternatively, if the opening 648 is a substantially circular shape such as an ellipse, a polygon, or a polygon with curved corners when viewed from above, the maximum width of the opening 648 may be the maximum width of the shape when viewed from above.

[0227] The arrangement of oxide 650, insulator 672, and conductor 670 in the portion of opening 648 reflects the shape of opening 648. Therefore, oxide 650 is provided along opening 648, insulator 672 is provided to cover oxide 650, and conductor 670 is provided to fit into a recess of insulator 672 that reflects the shape of opening 648.

[0228] That is, a portion of the semiconductor film (equivalent to the oxide 650) including the channel formation region of the transistor 600 is provided along the side surface of the opening 648. In other words, it is provided in a direction perpendicular to the top surface of the conductor 610. In other words, the channel length direction of the transistor 600 has a directional component perpendicular to the top surface of the conductor 610. In other words, the channel length direction has a longitudinal component (in the direction of the channel 648). 17A to 17C In other words, the source electrode and the drain electrode are located at different heights and the drain current flows in the vertical direction. Therefore, a transistor according to one embodiment of the present invention is a transistor having a vertical component in the channel length direction (i.e., a transistor in which the drain current flows in the vertical direction), and may be referred to as a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or the like.

[0229] Here, as conductor 660, for example, a material that can be used for conductor 630 can be used. Furthermore, as conductor 670, for example, a material that can be used for conductor 630 can be used. Furthermore, as insulator 672, for example, a material that can be used for insulator 522, insulator 524, or insulator 545, which will be described later, can be used. Furthermore, as insulator 640, for example, a material that can be used for insulator 620 can be used. Furthermore, as insulator 678, for example, a material that can be used for insulator 514, which will be described later, or the aforementioned insulator 612 can be used.

[0230] Note that in Figure 17B and Figure 17C In the embodiment, the opening 648 is provided so that the side surface of the opening 648 is perpendicular to the top surface of the conductor 610, but the present invention is not limited thereto. For example, the side surface of the opening 648 may also have a tapered shape.

[0231] In addition, Figure 17B and Figure 17C Although the oxide 650 is shown as a single-layer structure, one embodiment of the present invention is not limited thereto and the oxide 650 may have a stacked-layer structure of a plurality of oxide layers having different chemical compositions.

[0232] Here, Figure 18A Show Figure 17B The oxide 650 and its vicinity are enlarged. Figure 18B A cross-sectional view along the XY plane including the conductor 660 is shown.

[0233] like Figure 18A As shown, the oxide 650 includes a region 650i, and regions 650na and 650nb provided so as to sandwich the region 650i.

[0234] Region 650na is a region of oxide 650 in contact with conductor 630. At least a portion of region 650na is used as one of the source region and the drain region of transistor 600. Region 650nb is a region of oxide 650 in contact with conductor 660. At least a portion of region 650nb is used as the other of the source region and the drain region of transistor 600. Figure 18B As shown, conductor 660 is in contact with the entire periphery of oxide 650. Therefore, the other of the source region and the drain region of transistor 600 may be formed on the entire periphery of the portion of oxide 650 formed in the same layer as conductor 660.

[0235] Region 650i is a region between region 650na and region 650nb of oxide 650. At least a portion of region 650i serves as a channel formation region of transistor 600. In other words, the channel formation region of transistor 600 is located in the region between conductor 630 and conductor 660 of oxide 650. Alternatively, the channel formation region of transistor 600 can be said to be located in a region of oxide 650 that contacts insulator 640 or in a region near the region.

[0236] The channel length of the transistor 600 is the distance between the source region and the drain region. In other words, the channel length of the transistor 600 is determined by the thickness of the insulator 640 on the conductor 630. Figure 18A , the dotted double-headed arrow indicates the channel length L of the transistor 600. In cross-sectional view, the channel length L is the distance between the end of the region where the oxide 650 and the conductor 630 are in contact, and the end of the region where the oxide 650 and the conductor 660 are in contact. In other words, the channel length L corresponds to the length of the side surface of the insulator 640 on the side of the opening 648 in cross-sectional view.

[0237] Here, in planar transistors, the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult. However, in the present invention, the channel length can be set according to the thickness of the insulator 640. Therefore, the channel length of the transistor 600 can be set to a very fine structure below the exposure limit of photolithography (for example, less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm, or less than 10nm and more than 1nm or more than 5nm). As a result, the on-state current of the transistor 600 is increased, thereby improving the frequency characteristics.

[0238] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 648. Therefore, the area occupied by the transistor 600 can be reduced compared to a planar transistor in which the channel formation region, source region, and drain region are provided separately on the XY plane.

[0239] In addition, with Figure 18B Similarly, on the XY plane of the channel formation region including the oxide 650, the oxide 650, the insulator 672, and the conductor 670 are also arranged in a concentric circle. Therefore, the side surface of the conductor 670 arranged in the center is opposite to the side surface of the oxide 650 across the insulator 672. In other words, the entire periphery of the oxide 650 becomes the channel formation region when viewed from above. At this time, for example, the channel width of the transistor 600 is determined by the length of the periphery of the oxide 650. In other words, the channel width of the transistor 600 is determined by the maximum width of the opening 648 (the maximum diameter when the shape of the opening 648 when viewed from above is circular). Figure 18A and Figure 18B In FIG, the double-dot-dashed double arrow indicates the maximum width D of the opening 648. Figure 18B In FIG, a double-dot chain arrow indicates the channel width W of the transistor 600. By increasing the maximum width D of the opening 648, the channel width per unit area can be increased, thereby increasing the on-state current.

[0240] When the opening 648 is formed using photolithography, the maximum width D of the opening 648 is limited by the exposure limit of the photolithography, making further miniaturization difficult. In addition, the maximum width D of the opening 648 is set according to the thickness of the oxide 650, the insulator 672, and the conductor 670 provided in the opening 648. The maximum width D of the opening 648 is preferably, for example, greater than 5 nm, greater than 10 nm, or greater than 20 nm and less than 100 nm, less than 60 nm, less than 50 nm, less than 40 nm, or less than 30 nm. Note that when the shape of the opening 648 when viewed from above is circular, the maximum width D of the opening 648 is equivalent to the diameter of the opening 648, and the channel width W can be calculated as "D×π".

[0241] Furthermore, the channel length L of the transistor 600 according to one embodiment of the present invention is preferably at least smaller than the channel width W of the transistor 600. The channel length L of the transistor 600 according to one embodiment of the present invention is not less than 0.1 times and not more than 0.99 times, and preferably not less than 0.5 times and not more than 0.8 times, the channel width W of the transistor 600. By adopting this structure, a transistor having excellent electrical characteristics and high reliability can be realized.

[0242] Furthermore, by forming the opening 648 to have a circular shape in plan view, the oxide 650, the insulator 672, and the conductor 670 are arranged concentrically. This makes the distance between the conductor 670 and the oxide 650 uniform, so that a uniform gate electric field can be applied to the oxide 650.

[0243] In one embodiment of the present invention, at least a portion of the semiconductor device 200 can be used for the memory cell 111 shown in the above-mentioned embodiment 1. That is, the transistor 600 is equivalent to the transistor M11, and the capacitor 690 is equivalent to the capacitor C11. In other words, the conductor 670 includes a region serving as the gate of the transistor M11, the conductor 660 includes a region serving as the other of the source and drain of the transistor M11, the conductor 630 includes a region serving as one of the source and drain of the transistor M11 and a region serving as one terminal of the capacitor C11, and the conductor 610 includes a region serving as the other terminal of the capacitor C11. In addition, the conductor 670 is equivalent to the wiring WL, the conductor 660 is equivalent to the wiring BL, the conductor 610 is equivalent to the wiring PL, and the conductor 630 is equivalent to the wiring SN. Note that in 17A to 17C In FIG. 1 , portions corresponding to the transistor M11 , the capacitor C11 , the wiring WL, the wiring BL, the wiring PL, and the wiring SN are denoted by parenthesized symbols.

[0244] Notice, 17A to 17C The transistor 600 and the capacitor 690 shown are merely examples, and the structure is not limited to this.

[0245] [Transistor 600B] One embodiment of the present invention may use a transistor having a back gate in the semiconductor device 200 .

[0246] As one embodiment of the present invention, Figure 19 is a cross-sectional view illustrating a structural example of a transistor having a back gate. Figure 19 The transistor 600B shown is a modified example of the transistor 600. The transistor 600B includes two gate electrodes (a gate electrode and a back gate electrode) corresponding to each other with a channel formation region interposed therebetween.

[0247] Transistor 600B differs from transistor 600 in that transistor 600B includes a conductor 680 and an insulator 682. In transistor 600B, insulator 682 is provided between insulator 640 and oxide 650 on the side of opening 648, and conductor 680 is provided in a portion of insulator 640 so as to surround the outer periphery of oxide 650 via insulator 682.

[0248] Here, the conductor 670 may be used as a first gate (also simply referred to as a gate) electrode, and the conductor 680 may be used as a second gate (also referred to as a back gate) electrode. In this case, the insulator 672 is used as a first gate insulating film, and the insulator 682 is used as a second gate insulating film.

[0249] Transistor 600B differs from transistor 600 in that, in transistor 600B, conductor 630 has a recessed portion at a position overlapping opening 648. In transistor 600B, a portion of oxide 650 and a portion of insulator 682 are disposed in the recessed portion of conductor 630. In this case, the bottom surface of oxide 650 is located below the bottom surface of insulator 682.

[0250] By adopting such a structure, the contact area between the oxide 650 and the conductor 630 can be increased. Therefore, the contact resistance between the oxide 650 and the conductor 630 can be reduced.

[0251] Here, for example, the material that can be used for the conductor 670 can be used as the conductor 680. Also, for example, the material that can be used for the insulator 672 can be used as the insulator 682.

[0252] Here, in a transistor having a back gate, the threshold voltage shifts according to the back gate voltage. In addition, the back gate of the transistor may be connected to the gate, or may be connected to one of the source and drain, or the other of the source and drain.

[0253] Figure 20A 1 is a cross-sectional view illustrating a structural example in which a back gate (equivalent to the conductor 680 ) of the transistor 600B is connected to a gate (equivalent to the conductor 670 ) of the transistor 600B via a conductor 684 embedded in the insulator 672 and the insulator 640 . Figure 20B 6 is a cross-sectional view illustrating a structural example in which a back gate (equivalent to the conductor 680 ) of the transistor 600B is connected to the other of the source and drain of the transistor 600B (equivalent to the conductor 660 ) ​​through a conductor 684 embedded in the insulator 640 . Figure 20C6 is a cross-sectional view showing a structural example in which a back gate (corresponding to the conductor 680 ) of the transistor 600B is connected to one of the source and drain of the transistor 600B (corresponding to the conductor 630 ) via a conductor 684 embedded in the insulator 640 .

[0254] The conductor 684 is used as a plug or wiring. The details of the conductor used as the plug or wiring will be described later.

[0255] Figure 21A and Figure 21B This is an example of a circuit diagram in which the transistor constituting the memory cell 111 described in the first embodiment is replaced with a transistor having a back gate. Figure 21A As an example, the back gate of transistor M11 is connected to the gate. Figure 21B In FIG. 4 , as an example, the back gate of the transistor M11 is connected to the wiring BGL1 .

[0256] Figure 21C and Figure 21D This is an example of a circuit diagram in which the transistors constituting the driver circuit 123 shown in the above-mentioned embodiment 1 are replaced with transistors having a back gate. Figure 21C In FIG, as an example, the back gates of transistors M2a and M2b are connected to the gates. Figure 21D In FIG. 4 , as an example, the back gates of the transistors M2 a and M2 b are connected to the wiring BGL2 .

[0257] Here, by electrically connecting the back gate of the transistor to the gate, the on-state current of the transistor can be increased. In addition, by supplying an arbitrary potential to the back gate of the transistor, the threshold voltage of the transistor can be changed.

[0258] As one embodiment of the present invention, in the storage device described in the first embodiment, it is possible to use Figure 21B The structure shown is used as memory cell 111. At this time, a potential that increases the threshold voltage of transistor M11 can also be supplied to wiring BGL1. This reduces the off-state current of transistor M11, thereby maintaining the data written to memory cell 111 (i.e., the potential of wiring SN) for a long time. Furthermore, during data writing and reading, the potential supplied to wiring BGL1 can be changed in a manner that reduces the threshold voltage of transistor M11. This increases the on-state current of the transistor, thereby improving the writing and reading speeds.

[0259] In addition, you can use Figure 21C The structure shown in FIG. 1 is used as the driving circuit 123. Thus, the on-state current of the transistor M2a and the transistor M2b can be increased, thereby improving the operating speed when driving the memory cell 111. In addition, Figure 21D The structure shown is used as the driver circuit 123. In this case, a potential that reduces the threshold voltages of transistors M2a and M2b can be supplied to wiring BGL2. This increases the on-state current of transistors M2a and M2b, thereby increasing the operating speed when driving the memory cell 111.

[0260] [Modifications of the Semiconductor Device 200] The semiconductor device including the transistor and the capacitor that can be used in one embodiment of the present invention is not limited to 17A to 17C and Figure 43A The structure of the semiconductor device 200 shown in FIG. Figures 42A to 42C and Figure 43B The structure of the semiconductor device 200A is shown.

[0261] Figure 42A It is a top view of the semiconductor device 200A. Figure 42B It is along Figure 42A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 in FIG. Figure 42C It is along Figure 42A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 in FIG. Figure 42A In the top view, some components are omitted for clarity. Figure 43B FIG2 is a perspective view of a semiconductor device 200A with some components omitted. Figure 43B An example is shown in which the outer edge shapes of the conductor 630 , the conductor 634 , and the oxide 650 in a plan view are circular.

[0262] Semiconductor device 200A differs from semiconductor device 200 in that semiconductor device 200A includes an insulator 676. Insulator 676 is provided on insulator 672, and an opening is provided so as to overlap opening 648. The wiring region of conductor 670 is provided so as to contact the side surfaces and top surface of the opening of insulator 676. For example, the material used for insulator 620 or insulator 640 described above can also be used as insulator 676.

[0263] In semiconductor device 200A, insulators 672 and 676 are provided between conductors 670 and 660 in the region where conductors 670 and 660 overlap. Therefore, the distance between conductors 670 and 660 can be increased compared to semiconductor device 200. This reduces parasitic capacitance between conductors 660 and 670. Furthermore, since the thickness of conductor 670 can be easily increased, resistance can be reduced. Therefore, for example, when semiconductor device 200A is used in a memory cell, write and read speeds can be improved.

[0264] [Modification Examples of Transistor 600 and Capacitor 690] Transistors and capacitors that can be used in one embodiment of the present invention are not limited to 17A to 17C The transistor 600 and the capacitor 690 are shown. For example, a Figure 44A The transistor 600 having the structure shown in FIG. Figure 44B Capacitor 690 of the structure shown.

[0265] exist Figure 44A and Figure 44B , a stacked structure of a conductor 630_1 and a conductor 630_2 on the conductor 630_1 is shown as the conductor 630. The conductor 630_1 is used as a capacitor. One of the pair of electrodes 690 , the conductor 630_2 , is used as one of the source electrode and the drain electrode of the transistor 600 .

[0266] A stacked-layer structure of a conductor 660_1 and a conductor 660_2 on the conductor 660_1 is shown as the conductor 660. For example, the conductor 660_1 can be used as a wiring, and the conductor 660_2 can be used as the other of the source electrode and the drain electrode of the transistor 600.

[0267] exist Figure 44A In the illustrated transistor 600, the conductor 630_2 has a recessed portion at a location overlapping the opening 648. A portion of the oxide 650, a portion of the insulator 672, and a portion of the conductor 670 are disposed within the recessed portion of the conductor 630_2. In this case, the bottom surface of the conductor 670 within the recessed portion can be located below the top surface of the conductor 630_2 outside the recessed portion.

[0268] By providing the oxide 650 in the recessed portion of the conductor 630_2 , the contact area between the oxide 650 and the conductor 630_2 can be increased, thereby reducing the contact resistance between the oxide 650 and the conductor 630_2 .

[0269] Furthermore, by lowering the bottom surface height of conductor 670, the gate electric field is more easily applied to the channel formation region of oxide 650. This improves the electrical characteristics of transistor 600. Furthermore, the region of oxide 650 in contact with conductor 630_2 is also more easily subjected to the gate electric field. This improves the on-state current of transistor 600. Regardless of whether conductor 630 or conductor 660 is used as the drain electrode, transistor 600 can have excellent electrical characteristics.

[0270] Here, if Figure 44AAs shown, the oxide 650 may include a region 650p with a curved corner within the recess of the conductor 630_2. This can suppress electric field concentration near the region 650p on the insulator 672, for example, compared to a case where the region 650p is a right angle or an acute angle (having a corner). By suppressing electric field concentration on the insulator 672, dielectric breakdown of the insulator 672 can be suppressed, thereby providing a highly reliable semiconductor device.

[0271] exist Figure 44B In the illustrated capacitor 690, the conductor 610 has a recessed portion at a position overlapping the opening 628. A portion of the conductor 634, a portion of the insulator 632, and a portion of the conductor 630_1 are disposed within the recessed portion of the conductor 610. In this case, the bottom surface of the conductor 630_1 within the recessed portion can be located below the top surface of the conductor 610 outside the recessed portion.

[0272] By providing the conductor 634 in the recessed portion of the conductor 610, the contact area between the conductor 634 and the conductor 610 can be increased. Therefore, the contact resistance between the conductor 634 and the conductor 610 can be reduced.

[0273] Here, if Figure 44B As shown, the conductor 634 may also include a region 634p with a curved corner within the recess of the conductor 610. This can suppress electric field concentration on the insulator 632 near the region 634p, for example, compared to a case where the region 634p is a right angle or an acute angle (has a corner). Furthermore, the end 634q of the conductor 634 may be located below the top surface of the insulator 620. This can suppress electric field concentration on the insulator 632 near the end 634q, compared to a case where the end 634q is located on the insulator 620. By suppressing electric field concentration on the insulator 632 in this manner, dielectric breakdown of the insulator 632 can be suppressed, thereby providing a highly reliable semiconductor device.

[0274] <Storage Array Layout Example> Here, an example of a layout in which the semiconductor devices 200 are arranged in a matrix will be described.

[0275] Figure 22A and Figure 22B Each of these is a top view showing an example of a layout when semiconductor devices 200 are arranged in a matrix. In other words, for example, this can also be considered an example of a layout of a memory array 110 that can be applied when semiconductor devices 200 are used as memory cells 111 described in Embodiment 1 above.

[0276] exist Figure 22A and Figure 22B, nine semiconductor devices 200 are arranged in a matrix of three rows by three columns. Here, the semiconductor device 200 arranged in the first row and first column is referred to as semiconductor device 200[1,1], the semiconductor device 200 arranged in the first row and third column is referred to as semiconductor device 200[1,3], the semiconductor device 200 arranged in the third row and first column is referred to as semiconductor device 200[3,1], and the semiconductor device 200 arranged in the third row and third column is referred to as semiconductor device 200[3,3].

[0277] Furthermore, oxide 650 [3, 3], conductor 634 [3, 3], opening 648 [3, 3], and opening 628 [3, 3] are typically used to represent oxide 650, conductor 634, opening 648, and opening 628 included in semiconductor device 200 [3, 3], respectively.

[0278] The three semiconductor devices 200 arranged in the first row are connected to a conductor 670[1] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the second row are connected to a conductor 670[2] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the third row are connected to a conductor 670[3] extending in the row direction (Y direction).

[0279] The three semiconductor devices 200 arranged in the first column are connected to a conductor 660[1] extending in the column direction (X direction). The three semiconductor devices 200 arranged in the second column are connected to a conductor 660[2] extending in the column direction (X direction). The three semiconductor devices 200 arranged in the third column are connected to a conductor 660[3] extending in the column direction (X direction).

[0280] Here, Figure 22A For example, it can be applied to the above-mentioned embodiment 1 Figure 8 The example of the connection shown is the layout example. Figure 22A In the embodiment, the three semiconductor devices 200 arranged in the first row are connected to a conductor 610[1] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the second row are connected to a conductor 610[2] extending in the row direction (Y direction). The three semiconductor devices 200 arranged in the third row are connected to a conductor 610[3] extending in the row direction (Y direction).

[0281] Figure 23A yes Figure 22A 1 is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[1,2] and the semiconductor device 200[1,3] in the row direction (X direction) in the layout shown. Figure 23AAs shown, the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] share the conductor 660[1] extending in the column direction (X direction). Figure 23B 2 is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] in the row direction (Y direction). Figure 23B As shown, the semiconductor device 200 [ 1 , 1 ], the semiconductor device 200 [ 1 , 2 ], and the semiconductor device 200 [ 1 , 3 ] share the conductor 610 [ 1 ] and the conductor 670 [ 1 ] extending in the row direction (Y direction).

[0282] In other words, the direction in which conductors 610[1] to 610[3] extend is parallel to the direction in which conductors 670[1] to 670[3] extend, and is perpendicular to the direction in which conductors 660[1] to 660[3] extend.

[0283] Furthermore, when viewed from above, conductor 610[1] and conductor 670[1] have overlapping regions, conductor 610[2] and conductor 670[2] have overlapping regions, and conductor 610[3] and conductor 670[3] have overlapping regions. When viewed from above, the ends of conductor 610[1] and conductor 670[1] may not coincide with each other, the ends of conductor 610[2] and conductor 670[2] may not coincide with each other, and the ends of conductor 610[3] and conductor 670[3] may not coincide with each other.

[0284] also, Figure 22B For example, it can be applied to the above-mentioned embodiment 1 Figure 10 The example of the connection shown is the layout example. Figure 22B In the embodiment, the three semiconductor devices 200 arranged in the first column are connected to a conductor 610[1] extending in the column direction (X direction). The three semiconductor devices 200 arranged in the second column are connected to a conductor 610[2] extending in the column direction (X direction). The three semiconductor devices 200 arranged in the third column are connected to a conductor 610[3] extending in the column direction (X direction).

[0285] Figure 24A yes Figure 22B 1 is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[1,2] and the semiconductor device 200[1,3] in the row direction (X direction) in the layout shown. Figure 24AAs shown, the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] share the conductor 610[1] and the conductor 660[1] extending in the column direction (X direction). Figure 24B 2 is a cross-sectional view of the semiconductor device 200[1,1], the semiconductor device 200[2,1], and the semiconductor device 200[3,1] in the row direction (Y direction). Figure 24B As shown, the semiconductor device 200 [ 1 , 1 ], the semiconductor device 200 [ 1 , 2 ], and the semiconductor device 200 [ 1 , 3 ] share a conductor 670 [ 1 ] extending in the row direction (Y direction).

[0286] In other words, the direction in which the conductors 610[1] to 610[3] extend is parallel to the direction in which the conductors 660[1] to 660[3] extend, and is perpendicular to the direction in which the conductors 660[1] to 660[3] extend.

[0287] Furthermore, when viewed from above, conductor 610[1] and conductor 660[1] have overlapping regions, conductor 610[2] and conductor 660[2] have overlapping regions, and conductor 610[3] and conductor 660[3] have overlapping regions. When viewed from above, the ends of conductor 610[1] and conductor 660[1] may not coincide with each other, the ends of conductor 610[2] and conductor 660[2] may not coincide with each other, and the ends of conductor 610[3] and conductor 660[3] may not coincide with each other.

[0288] Thus, in one embodiment of the present invention, the semiconductor devices 200 arranged in a matrix are applied to the memory array 110 described in the first embodiment. Figure 22A As shown in FIG. 1 , the conductor 670 corresponding to the wiring WL and the conductor 610 corresponding to the wiring PL may be stacked. Figure 22B As shown in FIG. 1 , the conductor 660 corresponding to the wiring BL and the conductor 610 corresponding to the wiring PL can be stacked. Therefore, the area occupied by the memory cell 111 can be reduced, and the storage density can be improved.

[0289] Note that although the example shown here shows nine semiconductor devices 200 arranged in a matrix of three rows and three columns, the arrangement is not limited thereto. The semiconductor devices 200 may be arranged in two rows or four or more rows, or in two columns or four or more columns.

[0290] <Transistor Stacking Example> The memory device according to one embodiment of the present invention can utilize transistors having various structures. In addition, a stacked structure of transistors having various structures can be used.

[0291] Figure 25 is a cross-sectional view of a semiconductor device including transistor 550, transistor 500, transistor 600, and capacitor 690 (ie, semiconductor device 200). Figure 25 A cross-sectional view of the transistor 550 along the channel length direction is shown.

[0292] like Figure 25 As shown, the transistor 500 is disposed above the transistor 550. The semiconductor devices 200 (four are shown here as a typical example) are disposed above the transistor 500.

[0293] Furthermore, the conductor 328 on the transistor 550 may be connected to the conductor 548 on the transistor 500 via the conductor 330, the conductor 356, the conductor 518, the conductor 546, and the like. Furthermore, the conductor 548 may be connected to the conductor 670 via the conductor 616, the conductor 610, the conductor 626, the conductor 630, the conductor 646, and the like. Furthermore, these conductors may be formed using conductors used as plugs or wiring.

[0294] In this specification, etc., the same symbol may be used to represent multiple conductors that function as plugs or wiring. Furthermore, in this specification, etc., wiring and plugs may be considered a single component. In other words, a portion of a conductor may function as wiring, while another portion may function as a plug.

[0295] As the material of each plug and wiring, for example, a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used.

[0296] In particular, it is preferable to use a high-melting-point material that combines heat resistance and electrical conductivity for each plug or wiring. Examples of such materials include tungsten and molybdenum. Furthermore, it is preferable to use a low-resistance conductive material that can reduce wiring resistance for each plug or wiring. Examples of such materials include aluminum and copper.

[0297] [Transistor 550] The transistor 550 will be described.

[0298] like Figure 25 As shown, the transistor 550 is arranged on a substrate 311 and includes a conductor 316 serving as a gate electrode, an insulator 315 serving as a gate insulating film, a semiconductor region 313 serving as a channel formation region, a low resistance region 314a serving as one of a source region and a drain region, and a low resistance region 314b serving as the other of a source region and a drain region.

[0299] The transistor 550 may be either a p-channel transistor or an n-channel transistor. Furthermore, by electrically connecting the gate of the n-channel transistor 550 to the gate of the p-channel transistor 550, a CMOS circuit (e.g., a circuit in which transistors operate complementarily, a CMOS logic gate, or a CMOS logic circuit) can be formed.

[0300] Therefore, for example, when the transistor 550 is used in a memory device, it can also be used as a transistor constituting a peripheral circuit for operating the memory device. That is, for example, in the memory device 100 described in Embodiment 1, it can also be used as at least a portion of the transistors constituting the peripheral circuit 120. Furthermore, for example, in the memory device 700 described in Embodiment 1, it can also be used as at least a portion of the transistors constituting the peripheral circuit portion 722.

[0301] Furthermore, the transistor 550 may have, for example, Figure 26 The semiconductor region 313, which is formed by a portion of the substrate 311, has a so-called fin-type structure in which the top surface and side surfaces in the channel width direction are covered by a conductor 316 via an insulator 315. This increases the effective channel width, thereby improving the on-state characteristics of the transistor 550. Furthermore, since the electric field effect of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0302] For example, the transistor 550 preferably includes a semiconductor such as a silicon-based semiconductor, preferably single crystal silicon, in the channel formation region of the semiconductor region 313, the region near the channel formation region, the low resistance region 314a serving as one of the source and drain regions, and the low resistance region 314b serving as the other of the source and drain regions. Alternatively, the transistor 550 may be formed using a material such as germanium, silicon germanium, gallium arsenide, or gallium aluminum arsenide. Alternatively, the transistor 550 may be formed using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the interplanar spacing. Alternatively, the transistor 550 may be a high electron mobility transistor (HEMT) using gallium arsenide or gallium aluminum arsenide.

[0303] The low-resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic and phosphorus, or an element imparting p-type conductivity such as boron.

[0304] Semiconductor materials such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron can be used as the conductor 316. Alternatively, conductive materials such as metals, alloys, and metal oxides can be used.

[0305] Furthermore, since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor.

[0306] For example, titanium nitride or tantalum nitride is preferably used as the conductor 316. Furthermore, to achieve both conductivity and embeddability, a laminate of a metal material such as tungsten or aluminum is preferably used. In particular, a laminate of tungsten is preferably used from the perspective of heat resistance.

[0307] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0308] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used as the insulators 320, 322, 324, and 326. In particular, silicon oxide or silicon oxynitride is preferably used from the viewpoint of thermal stability.

[0309] Note that in this specification and other documents, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon nitride oxide" refers to a material containing more nitrogen than oxygen. Note that in this specification and other documents, "aluminum oxynitride" refers to a material containing more oxygen than nitrogen, while "aluminum nitride oxide" refers to a material containing more nitrogen than oxygen.

[0310] The insulator 322 can also be used as a planarization film for planarizing steps caused by the transistor 550 disposed thereunder. For example, to improve the flatness of the top surface of the insulator 322, the top surface can be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0311] As the insulator 324 , an insulator having a barrier property that can prevent impurities such as hydrogen from diffusing from the substrate 311 or the transistor 550 located below the insulator 324 to a region located above the insulator 324 is preferably used.

[0312] As an insulator having a barrier property against hydrogen, silicon nitride formed by chemical vapor deposition (CVD) can be used. Alternatively, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide can be used.

[0313] Here, hydrogen may diffuse into a semiconductor element including an oxide semiconductor, such as transistor 600, causing degradation in the characteristics of the semiconductor element. Therefore, it is preferable to provide an insulator that suppresses hydrogen diffusion between the region where transistor 600 is provided and the region where transistor 550 is provided. Specifically, the insulator that suppresses hydrogen diffusion refers to a film that minimizes hydrogen desorption.

[0314] The dielectric constant of insulator 326 is preferably lower than that of insulator 324. For example, the relative dielectric constant of insulator 326 is preferably less than 4, more preferably less than 3. For example, the relative dielectric constant of insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0315] Furthermore, the conductor 328 and the like are embedded in the insulator 320 and the insulator 322. Furthermore, the conductor 330 is embedded in the insulator 324 and the insulator 326.

[0316] Furthermore, the conductors 328 and 330 are used as plugs or wiring.

[0317] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Figure 25 In the embodiment, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354.

[0318] Conductor 356 functions as a plug or wiring. Conductor 356 can be formed using, for example, the same material as conductors 328 and 330. In particular, it is preferable to use a conductor that has a barrier property against hydrogen.

[0319] Insulators 350, 352, and 354 can use the same materials as those used for insulators 324, 322, and 326. In particular, it is preferable to use an insulator having a barrier property against hydrogen.

[0320] Here, a conductor having hydrogen barrier properties is formed in the opening of the hydrogen barrier insulator 350. This structure allows the region where the transistor 550 is provided to be isolated from the outside of the region using the conductor having hydrogen barrier properties. Consequently, diffusion of hydrogen outside the region where the transistor 550 is provided can be suppressed.

[0321] Tantalum nitride or the like can be used as a conductor that has hydrogen barrier properties. Alternatively, a laminate of tantalum nitride and highly conductive tungsten can be used. Using a laminate of tantalum nitride and tungsten as the conductor not only maintains conductivity as wiring but also suppresses hydrogen diffusion.

[0322] That is, by stacking tantalum nitride and tungsten as the conductor 356, electrical conductivity as a wiring can be maintained while also suppressing hydrogen diffusion from the transistor 550. In this case, the tantalum nitride layer in the conductor 356 having a barrier property to hydrogen is preferably in contact with the insulator 350 having a barrier property to hydrogen.

[0323] Note that although the wiring layer including the conductor 356 is described here, the present invention is not limited to this. The wiring layer including the conductor 356 may not be provided, or two or more wiring layers similar to the wiring layer including the conductor 356 may be provided.

[0324] Notice, Figure 25 The transistor 550 shown is just an example and is not limited to this structure.

[0325] [Transistor 500] The transistor 500 will be described.

[0326] Figure 27A is a top view of transistor 500. Here, Figure 27B It is along Figure 27A The cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 5 is also a cross-sectional view taken along the channel length direction (indicated as the X direction) of the transistor 500 . Figure 27C It is along Figure 27A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 in FIG is also a cross-sectional view taken along the channel width direction (indicated as the Y direction) of the transistor 500. Note that for clarity, Figure 27A Some components are omitted in the top view.

[0327] Transistor 500 is a so-called planar transistor, and its channel length can be easily increased compared to vertical transistors such as transistor 600. This makes it easier to reduce short-channel effects, such as drain-induced barrier lowering (DIBL). In other words, it is easier to achieve a transistor with high saturation (small changes in drain current with respect to drain voltage in the transistor's saturation region).

[0328] Therefore, for example, when the transistor 500 is used in a memory device, it can also be used as a transistor constituting a sense amplifier for reading data from a memory cell included in the memory device. That is, for example, in the memory device 100 described in Embodiment 1 above, it can also be used as at least a portion of the transistors constituting the peripheral circuit 120. Furthermore, for example, in the memory device 700 described in Embodiment 1 above, it can also be used as at least a portion of the transistors constituting the peripheral circuit portion 722.

[0329] like Figure 27B and Figure 27C As shown, an insulator 514 and an insulator 516 are sequentially stacked on the insulator 512 .

[0330] As any of the insulator 512 , the insulator 514 , and the insulator 516 , an insulator having a barrier property against oxygen, hydrogen, and the like is preferably used.

[0331] The insulator 514 is preferably an insulator having a barrier property that can prevent impurities such as hydrogen from diffusing from outside the region where the transistor 500 is provided into the region where the transistor 500 is provided. For example, the insulator 514 can be made of the same material as that of the insulator 324 described above.

[0332] For example, as an insulator having a barrier property against hydrogen, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are preferably used.

[0333] In particular, aluminum oxide has high barrier properties against both oxygen and impurities such as hydrogen and water. Therefore, during and after the transistor manufacturing process, aluminum oxide can prevent impurities such as hydrogen and water from entering the transistor 500 and suppress the release of oxygen from the oxide constituting the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0334] Furthermore, for example, parasitic capacitance generated between wirings can be reduced by using a material having a low dielectric constant for the insulator 512 and the insulator 516. For example, the insulator 512 and the insulator 516 can be made of the same material as the insulator 326 described above.

[0335] like Figure 27B and Figure 27CAs shown, the transistor 500 includes a conductor 503 configured in a manner of embedding an insulator 514 and an insulator 516, an insulator 522 configured on the insulator 516 and the conductor 503, an insulator 524 configured on the insulator 522, an oxide 530a configured on the insulator 524, an oxide 530b configured on the oxide 530a, a conductor 542a and a conductor 542b configured separately from each other on the oxide 530b, an insulator 580 configured on the conductors 542a and 542b and forming an opening in a manner overlapping between the conductors 542a and 542b, an insulator 545 configured along the opening, and a conductor 560 configured on the formation surface of the insulator 545.

[0336] Note that the oxide 530 a and the oxide 530 b are sometimes collectively referred to as an oxide 530 .

[0337] The oxide 530 is used as a semiconductor film including a channel formation region of the transistor 500 .

[0338] The conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560 .

[0339] Here, conductor 503 preferably includes conductor 503a disposed in contact with insulator 514 and insulator 516, and conductor 503b disposed embedded inside conductor 503a. Furthermore, insulator 544 is preferably disposed between oxide 530a, oxide 530b, conductors 542a and 542b, and insulator 580. Furthermore, conductor 560 preferably includes conductor 560a disposed inside insulator 545, and conductor 560b disposed embedded inside conductor 560a. Furthermore, insulator 582 is preferably disposed on insulator 580, conductor 560, and insulator 545.

[0340] Note that in Figure 27B and Figure 27C In the transistor 500 shown in the figure, two layers of a conductor 503a and a conductor 503b are stacked as the conductor 503, but the present invention is not limited to this and may have a single-layer structure or a stacked-layer structure of three or more layers.

[0341] In addition, although the structure in which the ends of the conductors 542a and 542b are aligned with the ends of the oxide 530 is shown, the present invention is not limited thereto. For example, the conductors 542a and 542b may extend beyond the ends of the oxide 530.

[0342] The oxide 530 is shown to have a two-layer stacked structure of an oxide 530a and an oxide 530b, but the present invention is not limited thereto and may have, for example, a single-layer structure or a stacked structure of three or more layers.

[0343] Although the conductor 560 has a two-layer structure in which the conductors 560a and 560b are stacked, the conductor 560 is not limited thereto and may have a single-layer structure or a stacked structure of three or more layers.

[0344] Here, in the transistor 500 , the conductor 560 serves as a gate electrode, the insulator 545 serves as a gate insulating film, and the conductor 542 a and the conductor 542 b serve as one of a source electrode and the other of a drain electrode.

[0345] As described above, the conductor 560 is provided in a manner embedded in the opening of the insulator 580 formed in the region sandwiched between the conductor 542a and the conductor 542b (sometimes referred to as the opening of the insulator 580). The arrangement of the conductor 560, the conductor 542a, and the conductor 542b relative to the opening of the insulator 580 is selected so as to be self-aligned. That is, in the transistor 500, the gate electrode can be arranged between the source electrode and the drain electrode in a self-aligned manner. By adopting this structure, the conductor 560 can be formed in a manner that does not require room for alignment. Therefore, the area occupied by the transistor 500 can be reduced. As a result, miniaturization or high integration of semiconductor devices can be achieved.

[0346] Furthermore, conductor 560 is formed in a self-aligned manner in the region between conductor 542a and conductor 542b, so conductor 560 does not overlap with conductor 542a or conductor 542b. This reduces parasitic capacitance between conductor 560 and conductors 542a and 542b. Consequently, the switching speed of transistor 500 can be increased, thereby improving the frequency characteristics of the semiconductor device.

[0347] Furthermore, as semiconductor devices are miniaturized, the gate length of transistor 500 needs to be shortened. However, this requires preventing a decrease in the conductivity of conductor 560. Therefore, increasing the thickness of conductor 560 may result in conductor 560 having a shape with a high aspect ratio. Therefore, by providing conductor 560 so that it is embedded in the opening of insulator 580, conductor 560 with a high aspect ratio can be formed without collapsing during the process.

[0348] Here, the conductor 560 may be used as a first gate (also simply referred to as a gate) electrode, and the conductor 503 may be used as a second gate (also referred to as a back gate) electrode. In this case, the insulator 545 is used as a first gate insulating film, and the insulators 522 and 524 are used as second gate insulating films.

[0349] As described above, the conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Therefore, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated by the conductor 560 and the electric field generated by the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered.

[0350] In this case, in the transistor 500, the threshold voltage of the transistor 500 can be controlled by changing the potential supplied to the conductor 503 independently of the potential supplied to the conductor 560. In particular, by supplying a negative potential to the conductor 503, the threshold voltage of the transistor 500 can be increased and the off-state current can be reduced. Therefore, for example, by supplying a negative potential to the conductor 503, the drain current (sometimes referred to as the off-state current) when the potential supplied to the conductor 560 is 0 V can be reduced.

[0351] Note that in this specification, etc., the structure of a transistor in which the channel forming region is surrounded by the electric field of the gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, it can also be said that the S-channel structure disclosed in this specification, etc. is different from the Fin-type structure and the planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can also be regarded as one of the Fin-type structure and the planar structure. In addition, in this specification, etc., the Fin-type structure refers to a structure in which the gate electrode is configured in a manner that surrounds at least two or more sides of the channel (specifically, two sides, three sides or four sides, etc.). By adopting the Fin-type structure and the S-channel structure, a transistor with improved resistance to short channel effects can be realized. In other words, a transistor that is not prone to short channel effects can be realized.

[0352] By adopting a transistor having the above-mentioned S-channel structure, the channel formation region can be electrically surrounded by the electric field of the gate electrode. Since the S-channel structure is a structure in which the channel formation region is electrically surrounded by the electric field of the gate electrode, it can also be said that the structure is essentially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate AllAround: lateral full surround gate) structure. By making the transistor have an S-channel structure, a GAA structure or a LGAA structure, the channel formation region formed at or near the interface between the semiconductor film and the gate insulating film can be set in the entire bulk of the semiconductor film. Therefore, the current density flowing through the transistor can be increased, so the on-state current of the transistor or the field effect mobility of the transistor can be improved.

[0353] As described above, in the conductor 503 , the conductor 503 a is formed so as to be in contact with the insulator 514 and the insulator 516 , and the conductor 503 b is formed inside the conductor 503 a .

[0354] For example, the conductor 503a is preferably a conductive material that has a barrier property against impurities such as hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules), water, and copper (having a function of suppressing the diffusion of these impurities, i.e., these impurities do not easily permeate). Furthermore, for example, the conductor 503a is preferably a conductive material that has a barrier property against oxygen (e.g., at least one of oxygen atoms and oxygen molecules, etc., having a function of suppressing the diffusion of oxygen, i.e., oxygen does not easily permeate). In other words, the conductor 503a preferably has a barrier property against one or all of the above impurities and oxygen.

[0355] For example, by making the conductor 503a have a barrier property against oxygen, a decrease in conductivity due to oxidation of the conductor 503b can be suppressed.

[0356] In this case, it is preferable to use a highly conductive material as the conductor 503b. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used.

[0357] Alternatively, the transistor 500 may not include the conductor 503 (ie, may not include a back gate).

[0358] Here, the insulator in contact with the oxide 530 preferably contains oxygen in excess of the stoichiometric composition. This oxygen is easily released from the insulator by heating. In this specification, etc., the oxygen released by heating is sometimes referred to as "excess oxygen."

[0359] The insulator 524 is in contact with the oxide 530. Therefore, it is preferable that a region containing excess oxygen (also referred to as an "excess oxygen region") is formed in the insulator 524.

[0360] By providing the above-mentioned insulator containing excess oxygen in contact with the oxide 530, the oxygen vacancies (V O : oxygen vacancy), thereby improving the reliability of the transistor 500.

[0361] Here, an oxide semiconductor that can be used for the oxide 530 is described. This oxide semiconductor includes a metal oxide.

[0362] The metal oxide preferably contains at least one of indium and zinc. For example, it preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin.

[0363] In particular, as the metal oxide, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also referred to as IAGZO) can be used. Alternatively, an oxide containing indium (In), tin (Sn) and zinc (Zn) (also referred to as "ITZO (registered trademark)") can be used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also referred to as "IGZTO") can be used.

[0364] By increasing the proportion of the number of indium atoms in the metal oxide to the total number of atoms of all metal elements, excellent characteristics such as high on-state current, high field-effect mobility and high frequency characteristics can be obtained in a transistor in which the metal oxide is used for a semiconductor film including a channel formation region.

[0365] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of the atomic ratio of metal elements in such an In-M-Zn oxide include a composition of In:M:Zn=1:1:1 or thereabouts, a composition of In:M:Zn=1:1:1.2 or thereabouts, a composition of In:M:Zn=2:1:3 or thereabouts, a composition of In:M:Zn=3:1:2 or thereabouts, a composition of In:M:Zn=4:2:3 or thereabouts, a composition of In:M:Zn=4:2:4.1 or thereabouts, a composition of In:M:Zn=5:1:3 or thereabouts, a composition of In:M:Zn=5:1:6 or thereabouts, a composition of In:M:Zn=5:1:7 or thereabouts, a composition of In:M:Zn=5:1:8 or thereabouts, a composition of In:M:Zn=6:1:6 or thereabouts, or a composition of In:M:Zn=5:2:5 or thereabouts. Furthermore, the atomic ratio of In in such an In-M-Zn oxide may sometimes be smaller than the atomic ratio of M. Examples of the atomic ratio of the metal elements in this In-M-Zn oxide include compositions of In:M:Zn = 1:3:2 or in the vicinity thereof, and compositions of In:M:Zn = 1:3:4 or in the vicinity thereof. Note that the near composition ranges within ±30% of the desired atomic ratio.

[0366] For example, when the atomic number ratio of metal elements is described as In:Ga:Zn = 4:2:3 or a composition thereof, the content ratios of the elements include the following: when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Furthermore, when the atomic number ratio of metal elements is described as In:Ga:Zn = 5:1:6 or a composition thereof, the content ratios of the elements include the following: when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Furthermore, when the atomic number ratio of metal elements is described as In:Ga:Zn = 1:1:1 or a composition thereof, the content ratios of the elements include the following: when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0367] Furthermore, when stacking metal oxides, for example, a three-layer structure can be employed: a first layer of a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1, a second layer of a metal oxide having an atomic ratio of In:Zn = 4:1, and a third layer of a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1. It is preferred that the band gaps of the metal oxides in the first and third layers be larger than the band gap of the metal oxide in the second layer. This structure allows the metal oxide in the second layer to serve as the primary current path, thus achieving a so-called embedded channel structure.

[0368] As an analysis of the composition of the metal oxide, for example, secondary ion mass spectrometry (SIMS), energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS) or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. In addition, a combination of multiple methods can be used for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0369] Metal oxides can be formed using sputtering or atomic layer deposition (ALD). Note that when forming metal oxides using sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content of the formed metal oxide may drop to approximately 50% of the zinc content in the sputtering target.

[0370] The oxide semiconductor preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS are preferably used as the oxide semiconductor, with CAAC-OS being particularly preferred.

[0371] CAAC-OS preferably has multiple layered crystal regions with their c-axes oriented normal to the surface on which they are formed. For example, an oxide semiconductor preferably has layered crystals parallel to the surface on which it is formed. This structure allows the layered crystals of the oxide semiconductor to be parallel to the channel length of the transistor, thereby increasing the transistor's on-state current.

[0372] In addition, in one embodiment of the present invention, in a deposition method for an oxide semiconductor, a highly crystalline oxide semiconductor CAAC-OS can be used as a core or seed to improve the crystallinity of the oxide semiconductors formed above and below the CAAC-OS. This can improve the crystallinity of the entire oxide semiconductor. In other words, by solid-phase growing the upper and lower oxide semiconductors using CAAC-OS as a core or seed, a highly crystalline oxide semiconductor can be formed. The oxide semiconductor formed using this deposition method can be referred to as axial growth CAAC (AG CAAC).

[0373] By improving the crystallinity of an oxide semiconductor, a transistor with excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field-effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) and a transistor with high reliability, etc.) can be realized in a transistor in which the oxide semiconductor is used as a semiconductor film including a channel formation region.

[0374] When or after depositing the oxide semiconductor, it is preferred to perform a treatment for improving the crystallinity of the oxide semiconductor. As the above-mentioned treatment for improving the crystallinity of the oxide semiconductor, for example, heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment and light (for example, ultraviolet light) irradiation treatment can be cited. Note that multiple of the above-mentioned treatments can be performed simultaneously or in sequence. For example, heat treatment and microwave plasma treatment can be performed simultaneously. Alternatively, microwave plasma treatment can be performed after heat treatment.

[0375] In this specification, microwaves refer to electromagnetic waves with a frequency of 300 MHz or higher and 300 GHz or lower. Microwave plasma treatment, for example, refers to treatment using an apparatus including a power source that generates high-density plasma using microwaves. Microwave plasma treatment may also be referred to as microwave-excited high-density plasma treatment.

[0376] In addition, it is more preferable to perform a treatment for improving the crystallinity of the oxide semiconductor multiple times when depositing the oxide semiconductor. For example, in the case of forming an oxide semiconductor film by the ALD method, it is preferable to perform microwave plasma treatment each time an atomic layer is formed. Alternatively, by performing a treatment for improving crystallinity each time an oxide semiconductor layer having a thickness within a predetermined range is formed, productivity can be improved, so it is preferable. Specifically, it is preferable to form a first oxide semiconductor film of 1 nm or more and 10 nm or less and perform a first microwave plasma treatment, and then form a second oxide semiconductor layer of 1 nm or more and 10 nm or less and perform a second microwave plasma treatment. Note that there is no particular limitation on the deposition method of the first oxide semiconductor film and the second oxide semiconductor film, and they can be deposited by the ALD method or the sputtering method respectively. In particular, by depositing the first oxide semiconductor film by the ALD method, it is possible to prevent the elements of the layer constituting the formed surface from being mixed into the first oxide semiconductor film and the second oxide semiconductor film (also called mixing), so it is preferable. In particular, it is suitable for cases where the element in the layer constituting the formed surface blocks the crystallization of the oxide semiconductor (for example, when silicon, carbon, etc. are included). Furthermore, the first oxide semiconductor film and the second oxide semiconductor film may have different compositions. Furthermore, although a stacked-layer structure of the first oxide semiconductor film and the second oxide semiconductor film is shown here, the present invention is not limited thereto. The same treatment can be applied even when the oxide semiconductor film has a single-layer structure or a stacked-layer structure of three or more layers.

[0377] In addition, a treatment for improving the crystallinity of the oxide semiconductor may also be performed after the oxide semiconductor is deposited. Specifically, the treatment may be performed directly on the deposited oxide semiconductor, or may be performed with another film, such as an insulating film, deposited on the oxide semiconductor interposed therebetween. For example, microwave plasma treatment may be performed after the oxide semiconductor is deposited, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be deposited after the oxide semiconductor is deposited, and then the oxide semiconductor may be subjected to heat treatment or microwave plasma treatment with the insulating film interposed therebetween.

[0378] Note that the above-mentioned treatment for improving the crystallinity of the oxide semiconductor may also serve as a treatment for removing impurities in the oxide semiconductor. For example, carbon, hydrogen, nitrogen, etc. in the oxide semiconductor may be appropriately removed. Alternatively, by performing the treatment for improving the crystallinity of the oxide semiconductor in an oxygen atmosphere, oxygen vacancies (also referred to as Vo: oxygen vacancy) in the oxide semiconductor may be reduced.

[0379] When performing treatment to improve the crystallinity of the oxide semiconductor, the substrate temperature is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher and 600° C. or higher, or 300° C. or higher and 450° C. or lower. Furthermore, the temperature of the heat treatment is preferably 100° C. or higher and 700° C. or higher and 300° C. or lower, or lower, than 450° C.

[0380] By improving the crystallinity of an oxide semiconductor, a transistor with high reliability can be realized.

[0381] The crystallinity of the oxide semiconductor can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, a combination of these methods may be used for analysis.

[0382] In addition, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. O ) bonds to form hydrogen into oxygen vacancies (V O ) caused by defects (also known as V O H), so the transistor characteristics (for example, the initial Id-Vg characteristics of the transistor or the Id-Vg characteristics in a long-term reliability test, etc.) are likely to deteriorate. As a material surrounding the oxide semiconductor, for example, as a material for an insulator in contact with the oxide semiconductor, it is preferred to use a material that releases a small amount of hydrogen. As the material that releases a small amount of hydrogen, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. can be cited. Thereby, the mixing of hydrogen into the oxide semiconductor can be suppressed. In particular, when silicon nitride is used for at least one of the insulators in contact with the oxide semiconductor, the reliability of the transistor can be improved. Note that a material that releases a small amount of hydrogen sometimes has the function of capturing or fixing hydrogen (also called doping) inside the insulator.

[0383] In addition, in the oxide 530, VoH is sometimes used as a donor to generate electrons as carriers. In addition, sometimes electrons as carriers are generated because a portion of hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing a large amount of hydrogen tend to have normally-on characteristics. In addition, since hydrogen in oxide semiconductors is easily transferred due to heat, electric field, etc., when the oxide semiconductor contains a large amount of hydrogen, the reliability of the transistor may be reduced. In one embodiment of the present invention, it is preferred to reduce the V O H becomes high-purity intrinsic or substantially high-purity intrinsic.

[0384] So, in order to get V O For an oxide semiconductor with sufficiently reduced H, it is important to: remove impurities such as hydrogen and water in the oxide semiconductor (sometimes also called "dehydration" or "dehydrogenation treatment"); and supply oxygen to the oxide semiconductor to fill oxygen vacancies (sometimes also called "oxidation treatment"). O An oxide semiconductor in which impurities such as H are sufficiently reduced is used for a channel formation region of a transistor, thereby providing stable electrical characteristics.

[0385] When the insulator 524 includes an excess oxygen region, the insulator 522 preferably has a barrier property against oxygen. When the insulator 522 has a barrier property against oxygen, for example, diffusion of oxygen contained in the oxide 530 toward the insulator 516 can be suppressed. Furthermore, reaction between the conductor 503 and oxygen contained in the insulator 524, the oxide 530, or the like can be suppressed.

[0386] Here, in the channel formation region of the transistor using an oxide semiconductor for a semiconductor film, it is preferred that there are fewer oxygen vacancies or the impurity concentration (for example, the concentration of hydrogen, nitrogen, and metal elements) is lower than that in the source region and the drain region. In addition, sometimes hydrogen near the oxygen vacancies forms VoH to generate electrons that become carriers, so VoH is also preferably less. In this way, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Thus, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0387] Furthermore, the source and drain regions preferably have more oxygen vacancies, more VoH, or a higher impurity concentration than the channel formation region of the transistor. Thus, the source and drain regions are n-type regions with a higher carrier concentration and lower resistance than the channel formation region of the transistor.

[0388] The band gap of the metal oxide used as the oxide semiconductor is preferably 2 eV or greater, more preferably 2.5 eV or greater. By using a metal oxide with a large band gap as the oxide semiconductor, the off-state current of the transistor can be reduced.

[0389] As the insulator 522, an insulator made of a high-dielectric constant (high-k) material (a material having a high relative dielectric constant) is preferably used.

[0390] As transistors become increasingly miniaturized and highly integrated, problems such as gate leakage current may occur due to thinner gate insulating films. Using high-k materials as insulators for gate insulating films can reduce the gate potential during transistor operation while maintaining the physical thickness.

[0391] As an insulator used as a gate insulating film, it is preferred to use a single layer or a stack of insulators such as aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or barium strontium titanate (BST).

[0392] In particular, as an insulator having barrier properties against oxygen and impurities, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. Examples of such insulators include aluminum oxide, hafnium oxide, and metal oxides containing aluminum and hafnium (hafnium aluminate).

[0393] Furthermore, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, the insulator may be nitrided. Furthermore, silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0394] When the insulator 522 is formed using such a material, the insulator 522 can function as an insulator that suppresses release of oxygen from the oxide 530 and entry of impurities such as hydrogen into the oxide 530 from the peripheral portion of the transistor 500 .

[0395] Note that in Figure 27B and Figure 27C In the transistor 500 shown, two layers of insulator 522 and insulator 524 are stacked as the second gate insulating film, but the present invention is not limited to this. For example, a single-layer structure or a stacked structure of three or more layers may be used. In this case, a structure of stacked layers of the same material or different materials may be used.

[0396] In the transistor 500, a single layer or a stack of layers of a metal oxide serving as an oxide semiconductor is used as the oxide 530 including the channel formation region. For example, the semiconductors that can be used for the oxide 650 described above can also be used as the oxide 530. Note that semiconductors that can be used for the oxide 530 are not limited to metal oxides.

[0397] In the oxide 530 , when the oxide 530 a is provided below the oxide 530 b , diffusion of impurities from a structure formed below the oxide 530 a into the oxide 530 b can be suppressed.

[0398] Furthermore, the oxide 530 preferably has a structure of multiple oxide layers having different atomic ratios of metal atoms. Specifically, the atomic ratio of the element M in the constituent elements of the metal oxide used in the oxide 530a is preferably greater than the atomic ratio of the element M in the constituent elements of the metal oxide used in the oxide 530b. Furthermore, the atomic ratio of the element M to In in the metal oxide used in the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used in the oxide 530b. Furthermore, the atomic ratio of In to the element M in the metal oxide used in the oxide 530b is preferably greater than the atomic ratio of In to the element M in the metal oxide used in the oxide 530a.

[0399] It is preferable that the energy of the conduction band bottom of oxide 530a be higher than that of oxide 530b. In other words, the electron affinity of oxide 530a is preferably lower than that of oxide 530b.

[0400] Here, the energy level of the conduction band bottom changes smoothly at the junction of oxide 530a and oxide 530b. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of oxide 530a and oxide 530b changing continuously or being continuously joined. As a result, the defect state density of the mixed layer formed at the interface between oxide 530a and oxide 530b can also be reduced.

[0401] Specifically, by making oxide 530a and oxide 530b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when oxide 530b is an In-Ga-Zn oxide, oxide 530a can be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.

[0402] At this time, the main path of carriers is oxide 530b. By making oxide 530a have the above structure, the defect state density at the interface between oxide 530a and oxide 530b can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the on-state current of transistor 500 can be increased.

[0403] Conductors 542 a and 542 b serving as a source electrode and a drain electrode are provided over the oxide 530 b .

[0404] As the conductor 542a and the conductor 542b, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing the above metal elements, or an alloy combining the above metal elements can be used. In particular, as a conductive material that is not easily oxidized or a material that maintains its conductivity even when absorbing oxygen, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. are preferably used. Furthermore, from the perspective of having barrier properties against oxygen and hydrogen, for example, a metal nitride film such as tantalum nitride is preferably used.

[0405] Note that in Figure 27B and Figure 27C In the transistor 500 shown in the figure, the conductor 542a and the conductor 542b have a single-layer structure, but the present invention is not limited to this. The conductor 542a and the conductor 542b may have a stacked-layer structure of two or more layers, for example.

[0406] As conductors 542a and 542b, for example, a stacked structure of tantalum nitride film and tungsten film, a stacked structure of titanium film and aluminum film, a structure in which an aluminum film is stacked on a tungsten film, a structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a structure in which a copper film is stacked on a titanium film, or a structure in which a copper film is stacked on a tungsten film can be used.

[0407] In addition, for example, a three-layer structure can be adopted: an aluminum film or a copper film is stacked on a titanium film or a titanium nitride film, and a titanium film or a titanium nitride film is stacked thereon; or an aluminum film or a copper film is stacked on a molybdenum film or a molybdenum nitride film, and a molybdenum film or a molybdenum nitride film is stacked thereon, etc.

[0408] Alternatively, the conductors 542 a and 542 b may be made of a transparent conductive material including indium oxide, tin oxide, or zinc oxide.

[0409] In addition, if Figure 27B As shown, region 543a is sometimes formed as a low-resistance region at or near the interface between oxide 530 and conductor 542a. Similarly, region 543b is sometimes formed as a low-resistance region at or near the interface between oxide 530 and conductor 542b. In this case, region 543a serves as one of the source and drain regions, while region 543b serves as the other. Furthermore, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0410] In this manner, by providing the conductors 542a and 542b in contact with the oxide 530, the oxygen concentration in the regions 543a and 543b may be reduced. Furthermore, a metal compound layer containing the metal in the conductors 542a and 542b and the components of the oxide 530 may be formed in the regions 543a and 543b. In this case, the carrier concentration in the regions 543a and 543b increases, and the regions 543a and 543b become low-resistance regions.

[0411] Insulator 544 is provided to cover conductors 542a and 542b to suppress oxidation of conductors 542a and 542b. In this case, insulator 544 may be provided to cover the side surfaces of oxide 530 and insulator 524 and to be in contact with insulator 522.

[0412] The insulator 544 can be made of a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, or magnesium. Alternatively, for example, silicon nitride oxide or silicon nitride can be used.

[0413] Alternatively, an insulator containing an oxide of one or both aluminum and hafnium may be used. For example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) may be used. Hafnium aluminate is particularly preferred because it has high heat resistance and is less susceptible to crystallization during subsequent heat treatment.

[0414] In addition, when the conductors 542a and 542b are made of a material having oxidation resistance or a material whose conductivity does not significantly decrease even when absorbing oxygen, the insulator 544 is not necessarily required.

[0415] Furthermore, the inclusion of the insulator 544 can prevent impurities such as hydrogen and water contained in the insulator 580 from diffusing into the oxide 530b. Furthermore, oxidation of the conductors 542a and 542b by excess oxygen contained in the insulator 580 can be prevented.

[0416] As the insulator 545, an insulator containing excess oxygen and releasing oxygen by heating is preferably used, similar to the insulator 524. Therefore, oxygen can be efficiently supplied from the insulator 545 to the channel formation region of the oxide 530b.

[0417] Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide having pores can be used as the insulator 545. In particular, silicon oxide or silicon oxynitride is preferably used from the viewpoint of thermal stability.

[0418] As with the insulator 524, an insulator having a reduced concentration of impurities such as hydrogen and water is preferably used as the insulator 545. The thickness of the insulator 545 is preferably not less than 1 nm and not more than 20 nm.

[0419] Here, in order to efficiently supply excess oxygen contained in the insulator 545 to the oxide 530, a metal oxide may be provided between the insulator 545 and the conductor 560. The metal oxide preferably has a barrier property to oxygen. This suppresses the diffusion of excess oxygen from the insulator 545 to the conductor 560. Therefore, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, the material that can be used for the insulator 544 can also be used.

[0420] exist Figure 27B and Figure 27C In the transistor 500 shown, the insulator 545 has a single-layer structure, but is not limited thereto. For example, similar to the insulators 522 and 524 used as the second gate insulating film, the insulator 545 used as the first gate insulating film may also have a stacked structure of two or more layers. For example, the insulator 545 may have a stacked structure of a high-k material and a thermally stable material. This allows the gate voltage of the transistor 500 to be reduced during operation while maintaining the physical thickness of the insulator 545.

[0421] As the conductor 560a included in the conductor 560, a conductive material having a barrier property against impurities such as hydrogen, water, nitrogen, nitrogen oxides (e.g., NO, NO, etc.), and copper is preferably used. Furthermore, a conductive material having a barrier property against oxygen is preferably used. When the conductor 560a has a barrier property against oxygen, it is possible to prevent oxygen contained in the insulator 545 from oxidizing the conductor 560b and causing a decrease in conductivity.

[0422] As the conductive material having a barrier property against oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

[0423] Alternatively, an oxide semiconductor that can be used for the oxide 530 can be used as the conductor 560a. In this case, by depositing the conductor 560b by sputtering, the resistance of the conductor 560a can be reduced, making it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0424] The conductor 560 may also function as a wiring. Therefore, as with the conductor 503b, a highly conductive material is preferably used as the conductor 560b. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used.

[0425] Alternatively, the conductor 560b may have a structure in which different materials are stacked, for example, a stacked structure of titanium or titanium nitride and the above-mentioned conductive materials.

[0426] The insulator 580 is preferably provided on the conductor 542 a and the conductor 542 b via the insulator 544 .

[0427] The insulator 580 preferably has an excess oxygen region.

[0428] As the insulator 580, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, silicon oxide with pores, or resin can be used. In particular, silicon oxide or silicon oxynitride is preferably used from the perspective of thermal stability. Furthermore, from the perspective of easily forming an excess oxygen region in a subsequent step, silicon oxide or silicon oxide with pores is preferably used.

[0429] Providing the insulator 580 with an excess oxygen region allows oxygen to be released by heating, so that the oxygen in the insulator 580 can be efficiently supplied to the oxide 530. Furthermore, it is preferable to reduce the concentration of impurities such as hydrogen and water in the insulator 580.

[0430] The insulator 582 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 545. By depositing the insulator 582 by sputtering, an excess oxygen region can be formed in the insulator 545 and the insulator 580. Oxygen can thereby be supplied from the excess oxygen region to the oxide 530.

[0431] As the insulator 582, for example, a metal oxide containing one or two or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used.

[0432] In particular, aluminum oxide has high barrier properties against impurities such as hydrogen, and even thin films with a thickness of 0.5 nm to 3.0 nm can suppress the diffusion of impurities such as hydrogen. Therefore, aluminum oxide deposited by sputtering can be used as an oxygen supply source while also serving as an insulator with barrier properties against impurities such as hydrogen.

[0433] An insulator 584 serving as an interlayer film is preferably provided over the insulator 582. As with the insulator 524 and the like, the concentration of impurities such as hydrogen and water in the insulator 584 is preferably reduced.

[0434] Furthermore, conductors 540a and 540b are disposed in openings formed in insulators 584, 582, 580, and 544. Conductors 540a and 540b are disposed so as to face each other with conductor 560 interposed therebetween. Conductors 540a and 540b have the same structure as conductor 546, which will be described later.

[0435] An insulator 586 is provided on the insulator 584 .

[0436] An insulating material having a barrier property against oxygen, hydrogen, etc. is preferably used as the insulator 586. For example, the same material as that of the insulator 514 can be used as the insulator 586.

[0437] An insulator 588 is provided on the insulator 586 .

[0438] Parasitic capacitance generated between wirings can be reduced by using, for example, a material having a low dielectric constant as the insulator 588. For example, the same material as the insulator 512 or the insulator 516 can be used as the insulator 588.

[0439] For example, the conductor 546 and the like are embedded in the insulator 580, the insulator 582, the insulator 584, and the insulator 586. Furthermore, for example, the conductor 548 and the like are embedded in the insulator 588.

[0440] Conductor 546 and conductor 548 are both used as plugs or wiring.

[0441] In addition, after forming the transistor 500, an opening may be formed around the transistor 500, and an insulator having high barrier properties to hydrogen or water may be formed to cover the opening. By wrapping the transistor 500 with the above-mentioned insulator having high barrier properties, hydrogen and water can be prevented from entering from the outside. Alternatively, multiple transistors 500 may be wrapped with an insulator having high barrier properties to hydrogen or water. In addition, in the case of forming an opening around the transistor 500, for example, an opening may be formed that reaches the insulator 522 or the insulator 514 and the above-mentioned insulator having high barrier properties may be formed in contact with the insulator 522 or the insulator 514. Thus, it can also serve as part of the manufacturing process of the transistor 500. In addition, as an insulator having high barrier properties to hydrogen or water, for example, the same material as the insulator 522 or the insulator 514 can be used.

[0442] Notice, Figures 27A to 27C The transistor 500 shown is only an example and is not limited to the above structure.

[0443] [Transistor 500F] Reference Figures 28A to 32EA structural example of a transistor having a structure different from that of the transistor 500 will be described. Figure 28A is a top view of transistor 500F. Figure 28B is a three-dimensional schematic diagram of transistor 500F. In addition, Figures 28C to 28E is a cross-sectional view of transistor 500F. Here, Figure 28C It is along Figure 28A The cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 5 is also a cross-sectional view of the transistor 500F in the channel width direction (here, indicated as the Y direction). Figure 28D It is along Figure 28A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 is also a cross-sectional view of the transistor 500F in the channel width direction. Figure 28E It is along Figure 28A The cross-sectional view of the portion indicated by the dot-dash line A5-A6 is also a cross-sectional view of the transistor 500F in the channel length direction (here, indicated as the X direction). Here, the dot-dash line A5-A6 is orthogonal to the dot-dash line A1-A2 and the dot-dash line A3-A4, and the dot-dash line A1-A2 and the dot-dash line A3-A4 are parallel to each other. Note that Figure 28A Top view and Figure 28B In the three-dimensional schematic diagram, some components are omitted. Figure 29A Show Figure 28E An enlarged view of the vicinity of the conductor 560. In addition, Figure 29B Show Figure 28C An enlarged view of the vicinity of the oxide 530 .

[0444] Compared to the transistor 500, the transistor 500F has a structure that allows a larger channel width without significantly increasing the occupied area. In other words, the on-state current can be increased without significantly increasing the occupied area.

[0445] Therefore, for example, by using the transistor 500F in a memory device, the operating speed of the memory device, such as the speed of reading and writing data from and to memory cells included in the memory device, can be increased. Specifically, for example, in the memory device 100 described in Embodiment 1 above, the transistor 500F can also be used to form at least a portion of the transistors constituting the peripheral circuit 120. Furthermore, for example, in the memory device 700 described in Embodiment 1 above, the transistor 500F can also be used to form at least a portion of the transistors constituting the peripheral circuit portion 722.

[0446] The transistor 500F includes an insulator 514 on a substrate (not shown), an insulator 516 on the insulator 514, an insulator 521 on the insulator 516, an insulator 522 on the insulator 521, an oxide 530 on the insulator 522, conductors 542a and 542b on the oxide 530 and on the insulator 522, an insulator 545 on the oxide 530, and a conductor 560 (conductors 560a and 560b) on the insulator 545. In this specification and other documents, the conductors 542a and 542b may be collectively referred to as the conductor 542.

[0447] An insulator 544 is provided on the conductor 542, and an insulator 580 is provided on the insulator 544. An insulator 545 and a conductor 560 are provided within a first opening that passes through the insulator 580 and the insulator 544 and reaches the oxide 530. The first opening includes, when viewed from above, a region overlapping with the oxide 530 and a region extending in the channel width direction beyond the end of the oxide 530. Therefore, when viewed from above, the insulator 545 and the conductor 560 provided within the first opening also include a region overlapping with the oxide 530 and a region extending in the channel width direction beyond the end of the oxide 530. Conductor 560 also serves as wiring. Insulator 545 includes a region in contact with the oxide 530 in the first opening. Furthermore, an insulator 582 is provided on the insulator 580 and the conductor 560. Furthermore, an insulator 584 is provided on the insulator 582.

[0448] Furthermore, insulator 541a is provided so as to contact the side surface of the second opening that passes through insulators 584, 582, 580, and 544 to conductor 542a, and conductor 540a is provided so as to contact insulator 541a. Conductor 540a has a region at the bottom of the first opening that contacts conductor 542a.

[0449] Furthermore, insulator 541b is provided so as to contact the side surface of the third opening that passes through insulators 584, 582, 580, and 544 to conductor 542b, and conductor 540b is provided so as to contact insulator 541b. Conductor 540b has a region at the bottom of the second opening that contacts conductor 542b.

[0450] In this specification and the like, the conductor 540a and the conductor 540b may be collectively referred to as the conductor 540. In addition, the insulator 541a and the insulator 541b may be collectively referred to as the insulator 541.

[0451] Oxide 530 includes a channel formation region for transistor 500F. Conductor 560 includes a region serving as a gate electrode for transistor 500F. Insulator 545 includes a region serving as a gate insulating film for transistor 500F. In transistor 500F, a region of oxide 530 that overlaps with conductor 560 serves as a channel formation region. Furthermore, a region of conductor 560 that overlaps with oxide 530 serves as a gate electrode. Furthermore, a region of insulator 545 that overlaps with oxide 530 and with conductor 560 serves as a gate insulating film.

[0452] Conductor 542a has a region serving as one of the source and drain electrodes of transistor 500F. Conductor 540a serves as a plug connected to conductor 542a. Conductor 542b has a region serving as the other of the source and drain electrodes of transistor 500F. Conductor 540b serves as a plug connected to conductor 542b.

[0453] Oxide 530 is formed on insulator 522. Figure 29B As shown, the oxide 530 has a high aspect ratio when viewed in a cross section in the channel width direction. Therefore, it can be said that the oxide 530 has a fin-like shape.

[0454] In this specification, etc., the maximum length of the oxide 530 in the channel formation region in the channel width direction is referred to as length Lx, and the maximum length of the oxide 530 in the channel formation region in the direction perpendicular to the formed surface (for example, the top surface of the insulator 522) (here, the Z direction) is referred to as length H. In this case, the ratio of length H to length Lx is referred to as the aspect ratio of the oxide 530. In addition, a fin shape refers to a shape in which the oxide 530 has a high aspect ratio (a shape in which length H is large relative to length Lx) when viewed in a cross-section in the channel width direction. Here, a transistor in which the semiconductor layer including the channel formation region is fin-shaped is sometimes referred to as a fin-type transistor, a Fin-type transistor, a Fin transistor, or the like.

[0455] Note that the length Lx can also be referred to as the maximum width of the oxide 530 in the channel formation region. Therefore, "length Lx" can be replaced by "width Lx." Furthermore, the length H can also be referred to as the maximum height of the oxide 530 in the channel formation region. Therefore, "length H" can be replaced by "height H."

[0456] The aspect ratio of the oxide 530 is preferably as high as possible within a range that prevents the oxide 530 from collapsing during the manufacturing process of the transistor 500F. The aspect ratio of the oxide 530 may also be greater than 1 and less than 400, preferably greater than 2 and less than 100, more preferably greater than 5 and less than 40, and even more preferably greater than 10 and less than 20. That is, in the channel formation region of the oxide 530, the height H of the oxide 530 is preferably at least longer than the length Lx of the oxide 530. The height H of the oxide 530 may also be greater than 1 times and less than 400 times the length Lx of the oxide 530, preferably greater than 2 times and less than 100 times, more preferably greater than 5 times and less than 40 times, and even more preferably greater than 10 times and less than 20 times. In addition, for example, the height H may also be greater than 2 times and less than 10 times the length Lx. For example, the length Lx may also be greater than 5 nm and less than 100 nm, preferably greater than 5 nm and less than 50 nm, and even more preferably greater than 10 nm and less than 30 nm. Furthermore, for example, the height H may be greater than or equal to 50 nm and less than or equal to 2000 nm, preferably greater than or equal to 100 nm and less than or equal to 1000 nm. Furthermore, for example, the height H may be greater than or equal to 50 nm and less than or equal to 100 nm.

[0457] In addition, if Figure 29B As shown, in a cross-section viewed in the channel width direction, an angle θ formed between the surface where the oxide 530 is formed on the insulator 522 and the side surface of the oxide 530 is preferably perpendicular.

[0458] The insulator 545, the conductor 560, and the conductor 542 are provided so as to cover the oxide 530 having a high aspect ratio. Figure 29B As shown, the insulator 545 and a portion of the conductor 560 are arranged so as to be folded in half with the oxide 530 interposed therebetween. Thus, in a cross-sectional view along the channel width, the oxide 530 and the conductor 560 are arranged facing each other with the insulator 545 interposed therebetween on the upper portion of the oxide 530, the side surface on the A1 side, and the side surface on the A2 side. In other words, the upper portion of the oxide 530, the side surface on the A1 side, and the side surface on the A2 side are all used as channel formation regions. As a result, compared to a case where the oxide 530 is formed in a planar shape, the channel width of the transistor 500F is increased by the size of the side surface on the A1 side and the side surface on the A2 side of the oxide 530.

[0459] As described above, increasing the channel width can improve the on-state current, mutual conductance, and frequency characteristics of transistor 500F. This allows for a high-speed semiconductor device. Furthermore, in the structure of transistor 500F, the channel width can be increased without increasing the area occupied by oxide 530. This allows for miniaturization and high integration of semiconductor devices.

[0460] In addition, if Figure 29B As shown in FIG. 1 and FIG. 2 , the upper portion of the oxide 530 may also have a curved shape. By having such a curved shape, defects such as voids can be prevented from being formed in the insulator 545 and the conductor 542 near the upper portion of the oxide 530. Figure 29B In the embodiment, a bilaterally symmetrical structure is used in which both the A1 side and the A2 side of the upper portion of the oxide 530 have curved shapes. However, one embodiment of the present invention is not limited thereto. For example, an asymmetrical structure is sometimes used in which only one of the A1 side and the A2 side of the upper portion of the oxide 530 has a curved shape.

[0461] Here, a structural example is shown in which the oxide 530 includes an oxide 530 a , an oxide 530 b in contact with the oxide 530 a , and an oxide 530 c in contact with the oxide 530 b .

[0462] At this time, for example, the films that will become the oxide 530a and the oxide 530c can be formed by atomic layer deposition (ALD) and the film that will become the oxide 530b can be formed by sputtering. Specifically, the film that will become the oxide 530a can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto. Alternatively, indium oxide can be used for the film that will become the oxide 530a. In addition, the film that will become the oxide 530b can be deposited using an oxide target having a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition close thereto. In addition, the film that will become the oxide 530c can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or a composition close thereto. Alternatively, indium oxide can be used for the film that will become the oxide 530c.

[0463] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range where the oxide 530 does not undergo polycrystallization.

[0464] For example, the heat treatment may be performed at a temperature of 450° C. for one hour with a flow ratio of nitrogen gas to oxygen gas of 4:1.

[0465] By depositing oxide 530 using the above method and then performing a heat treatment, oxide 530 can be made into AGCAAC. This improves the on-state current, S value, field-effect mobility, and frequency characteristics of transistor 500F, thereby providing a semiconductor device with excellent electrical characteristics. Furthermore, a highly reliable semiconductor device can be provided.

[0466] In addition, when an oxide semiconductor is used as the oxide 530, as shown in FIG. Figure 29A and Figure 29BAs shown, the insulator 545 preferably has a stacked structure of an insulator 545a in contact with the oxide 530, an insulator 545b on the insulator 545a, an insulator 545c on the insulator 545b, and an insulator 545d on the insulator 545c. In this case, the insulator 545a and the insulator 545c preferably have the function of capturing or fixing hydrogen.

[0467] Examples of insulators capable of capturing or fixing hydrogen include metal oxides with an amorphous structure. For example, magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used as insulator 545a and insulator 545c. These amorphous metal oxides sometimes have the property of having dangling bonds in their oxygen atoms, which can capture or fix hydrogen. In other words, metal oxides with an amorphous structure have a high ability to capture or fix hydrogen.

[0468] Insulators 545a and 545c are preferably made of a high-k material. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. Using a high-k material for insulators 545a and 545c reduces the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulating film. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulating film can be reduced.

[0469] As the insulator 545a and the insulator 545c, an oxide containing one or both of aluminum and hafnium is preferably used, and an oxide having an amorphous structure and containing one or both of aluminum and hafnium is more preferably used.

[0470] As the insulator 545a, for example, an aluminum oxide film can be used. Furthermore, the aluminum oxide preferably has an amorphous structure. Here, by providing the insulator 545a in contact with the oxide 530, hydrogen contained in the oxide 530 and the like can be more effectively captured and fixed.

[0471] The insulator 545c can be made of, for example, hafnium oxide. Here, by providing the insulator 545c between the insulator 545b and the insulator 545d, hydrogen contained in the insulator 545b and the like can be more efficiently captured and fixed.

[0472] Next, a thermally stable insulator such as silicon oxide or silicon oxynitride is preferably used as the insulator 545b. The silicon oxide film used as the insulator 545b is preferably formed by a PEALD method.

[0473] Furthermore, in order to suppress oxidation of the conductors 542a, 542b, and 560, an oxygen-blocking insulator is preferably provided near each of the conductors 542a, 542b, and 560. For example, an oxygen-blocking insulator may be provided in the insulators 545a, 545d, 545c, and 544.

[0474] Note that in this specification, etc., a blocking insulator refers to an insulator with barrier properties. In this specification, etc., having barrier properties means having the property of hindering the permeation of the corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has the property of preventing the corresponding substance from diffusing into the insulator. For example, an insulator with barrier properties has the function of capturing or fixing (also referred to as gettering) the corresponding substance within the insulator.

[0475] Examples of oxygen-blocking insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, insulators 545a, 545c, 545d, and 544 preferably have a single-layer structure or a stacked-layer structure of the above-described oxygen-blocking insulators.

[0476] The insulator 545a preferably has a barrier property to oxygen. The insulator 545a is preferably less susceptible to oxygen permeation than the insulator 580. The insulator 545a has a region in contact with the side surfaces of the conductor 542a and the side surfaces of the conductor 542b. When the insulator 545a has a barrier property to oxygen, oxidation of the side surfaces of the conductors 542a and 542b and the formation of oxide films on these side surfaces can be suppressed. Consequently, a decrease in the on-state current of the transistor 500F or a decrease in the field-effect mobility can be suppressed.

[0477] Furthermore, the insulator 545a is provided in contact with the top and side surfaces of the oxide 530 and the top surface of the insulator 522. When the insulator 545a has a barrier property against oxygen, it is possible to suppress the release of oxygen from the channel formation region of the oxide 530 during heat treatment, etc. Therefore, the formation of oxygen vacancies in the oxide 530 can be reduced.

[0478] Furthermore, by providing the insulator 545a, excessive oxygen supply from the insulator 580 to the oxide 530 is suppressed, so that an appropriate amount of oxygen can be supplied to the oxide 530. Therefore, a decrease in the on-state current or field-effect mobility of the transistor 500F due to excessive oxidation of the source and drain regions can be suppressed.

[0479] Since an oxide containing one or both of aluminum and hafnium has a barrier property against oxygen, it can be suitably used as the insulator 545 a .

[0480] The insulator 545d also preferably has a barrier property against oxygen. The insulator 545d is provided between the channel formation region of the oxide 530 and the conductor 560, and between the insulator 580 and the conductor 560. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide 530 into the conductor 560, thereby preventing oxygen vacancies from forming in the channel formation region of the oxide 530. In addition, it is possible to suppress the diffusion of oxygen in the oxide 530 and oxygen in the insulator 580 into the conductor 560, thereby preventing the oxidation of the conductor 560. The insulator 545d is preferably less susceptible to oxygen permeation than the insulator 580. For example, a silicon nitride film is preferably used as the insulator 545d. In this case, the insulator 545d is an insulator containing at least nitrogen and silicon.

[0481] The insulator 545 d preferably has a barrier property against hydrogen, thereby preventing impurities such as hydrogen contained in the conductor 560 from diffusing into the oxide 530 .

[0482] The insulator 544 also preferably has a barrier property against oxygen. The insulator 544 is provided between the insulator 580 and the conductor 542a and between the insulator 580 and the conductor 542b. The insulator 544 is provided in a manner in contact with the side surfaces of the conductor 542, the side surfaces of the oxide 530, and the top surface of the insulator 522. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in the insulator 580 into the conductor 542. Therefore, it is possible to suppress the oxidation of the conductor 542 caused by the oxygen contained in the insulator 580, which causes an increase in resistivity. The insulator 544 is preferably less susceptible to oxygen permeation than the insulator 580. For example, silicon nitride is preferably used as the insulator 544. In this case, the insulator 544 is an insulator containing at least nitrogen and silicon.

[0483] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region of the oxide 530 , a hydrogen blocking insulator is preferably provided near the source region and the drain region. For example, a hydrogen blocking insulator is used as the insulator 544 .

[0484] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 544 preferably has a single-layer structure or a stacked-layer structure of the above-mentioned hydrogen barrier insulators.

[0485] The provision of the insulator 544 can reduce the diffusion of hydrogen from the source and drain regions to the outside, thereby suppressing a decrease in the hydrogen concentration in the source and drain regions.

[0486] By adopting the above structure, the channel formation region can be i-type or substantially i-type, and the source and drain regions can be n-type, thereby providing a semiconductor device with excellent electrical characteristics. By adopting the above structure, even when the semiconductor device is miniaturized or highly integrated, it can still have excellent electrical characteristics. Furthermore, by miniaturizing the transistor 500F, high-frequency characteristics can be improved. Specifically, the cutoff frequency can be increased.

[0487] Insulators 545a to 545d serve as part of the gate insulating film. Insulators 545a to 545d are disposed together with conductor 560 in an opening formed in insulator 580. To achieve miniaturization of transistor 500F, the thickness of insulators 545a to 545d is preferably small. The thickness of insulators 545a to 545d is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, further preferably 0.5 nm to 5.0 nm, still further preferably 1.0 nm to less than 5.0 nm, and even further preferably 1.0 nm to 3.0 nm. Furthermore, at least a portion of each of insulators 545a to 545d may include a region having the aforementioned thickness.

[0488] Note that the thickness of the silicon oxide film used as the insulator 545 is preferably greater than or equal to 0.7 nm and less than or equal to 3 nm.

[0489] In order to reduce the thickness of insulators 545a to 545d as described above, it is preferable to deposit them using the ALD method. Furthermore, in order to provide insulators 545a to 545d in openings such as insulator 580, it is preferable to deposit them using the ALD method. By depositing insulator 545 using the ALD method, it is possible to deposit insulator 545 with high coverage on the side surfaces of the first opening formed in insulator 580, the side ends of conductor 542a, and the side ends of conductor 542b.

[0490] Note that while the insulator 545 has a four-layer structure consisting of insulators 545a to 545d, one embodiment of the present invention is not limited thereto. The insulator 545 may have a structure including at least one of the insulators 545a to 545d. By forming the insulator 545 with one, two, or three layers of the insulators 545a to 545d, the manufacturing process of the transistor 500F can be simplified, thereby improving the productivity of the semiconductor device including the transistor 500F.

[0491] like Figure 28AAs shown, the shape of the oxide 530 when viewed from above is preferably circumferential (it can also be said to be frame-shaped, ring-shaped, loop-shaped or closed curve-shaped). In other words, the oxide 530 preferably has multiple portions extending in the channel width direction and multiple portions extending in the channel length direction. Therefore, when the oxide 530 has a structure with a high aspect ratio, it is possible to prevent the oxide 530 from falling down during the manufacturing process of the transistor. In addition, it can also be said that Figure 28A The oxide 530 shown has an opening in the center. Figure 28A In FIG. 5 , the shape of the oxide 530 in a plan view is line-symmetrical about A1-A2, but one embodiment of the present invention is not limited thereto. For example, the shape of the oxide 530 in a plan view may be asymmetrical.

[0492] Figure 28A The structure shown is a structure in which two circular oxides 530 are formed in the channel width direction. Figure 28A As shown, the oxide 530 preferably overlaps the conductor 560 at two or more locations in a plan view. Therefore, the conductor 560 preferably has two or more regions overlapping with the oxide 530. In other words, the oxide 530 and the conductor 560 preferably have two or more regions overlapping each other.

[0493] By adopting this structure, Figure 28B As shown, in a cross-sectional view along the channel width, multiple fin oxides 530 are formed. Each of the multiple fin oxides 530 includes a channel formation region. In other words, transistor 500F is used as a multi-channel transistor. Therefore, in transistor 500F, the channel width can be further increased, thereby increasing the on-state current. Consequently, the operating speed of a semiconductor device including transistor 500F can be increased.

[0494] Here, a structure in which two circumferential oxides 530 are provided is described, but one embodiment of the present invention is not limited thereto. For example, a structure in which one, three, or more circumferential oxides 530 are provided may be employed. Furthermore, circumferential oxides 530 may be connected to form an oxide 530 having a shape including multiple openings. Furthermore, an oxide 530 having a grid-like shape when viewed from above may also be used.

[0495] Insulators 584, 582, 522, and 521 preferably all include an insulator that has the function of inhibiting the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon oxynitride can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for insulators 584 and 521. Furthermore, for example, aluminum oxide, which has a high ability to capture or fix hydrogen, is preferably used for insulator 582. Furthermore, for example, hafnium oxide, which has a high ability to capture or fix hydrogen and is a high-k material, is preferably used for insulator 522.

[0496] Note that, in addition to the above materials, a stacked-layer structure of silicon oxide or silicon oxynitride may be used as at least one of the insulators 521 and 522. For example, a stacked-layer structure of silicon nitride and silicon oxide may be used as the insulator 521. Furthermore, for example, a stacked-layer structure of hafnium oxide and silicon oxide may be used as the insulator 522.

[0497] By adopting this structure, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film, etc., disposed above the insulator 584, into the transistor 500F, etc. Furthermore, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film, etc. disposed below the insulator 521, into the transistor 500F, etc. Furthermore, hydrogen in the insulators 580 and 545, etc., can be captured or fixed to the insulators 582 and 522. Furthermore, by providing the insulators 582 and 584, it is possible to suppress the diffusion of oxygen in the insulators 580, etc., into the upper portion of the transistor 500F, etc. Furthermore, by providing the insulators 522 and 521, it is possible to suppress the diffusion of oxygen in the oxide 530, etc., into the lower portion of the transistor 500F, etc. Thus, by adopting a structure in which the upper and lower portions of the transistor 500F are surrounded by an insulator having the function of suppressing the diffusion of impurities such as water and hydrogen, as well as oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen into the oxide semiconductor. This can thereby improve the electrical characteristics and reliability of the semiconductor device.

[0498] The dielectric constant of each of the insulator 516 and the insulator 580 is preferably lower than that of the insulator 522. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0499] For example, the insulator 516 and the insulator 580 preferably both include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes.

[0500] Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with vacancies are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0501] In addition, the top surfaces of insulator 516 and insulator 580 may also be planarized.

[0502] The concentration of impurities such as water and hydrogen in the insulator 580 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 580 .

[0503] In addition, if Figures 30A to 30E As shown, in the transistor 500F, an insulator 524 may be provided under the oxide 530. The planar shape of the insulator 524 (here, the shape when viewed from the Z direction) is the same as that of the oxide 530, and the insulator 524 overlaps with the oxide 530 when viewed from above. The bottom surface of the insulator 524 is in contact with the insulator 522, the side surface of the insulator 524 is in contact with the insulator 545 and the conductor 542a, and the top surface of the insulator 524 is in contact with the bottom surface of the oxide 530. In addition, the insulating material that can be used for the insulator 545b can also be used as the insulator 524. For example, silicon oxide can be used as the insulator 524. Here, Figures 30A to 30E Corresponding to Figures 28A to 28E .also, Figure 31 Corresponding to Figure 29B In About Figures 30A to 30E and Figure 31 For matters not described below, please refer to the above Figures 28A to 28E and Figure 29B Description, etc.

[0504] Here, if Figure 31 As shown, the thickness t2 of the insulator 545 at the bottom of the first opening is preferably thinner than the thickness t1 (the length in the direction perpendicular to the surface on which the insulator 524 is formed) of the insulator 524. With this structure, the bottom surface of the conductor 560 (conductor 560a) located in the first opening can be lower than the bottom surface of the oxide 530 by the difference between the thickness t1 and the thickness t2 (t1-t2).

[0505] By placing the bottom surface of the conductor 560 below the bottom surface of the oxide 530, a sufficient gate electric field can be applied from the upper end to the lower end of the oxide 530. In other words, within the opening of the insulator 580 or the like, the entire oxide 530 can be electrically surrounded by the electric field of the conductor 560 and used as a channel formation region. By adopting this structure, the lower end of the oxide 530 can be prevented from being used as a parasitic channel, thereby reducing the off-state current between the source and drain electrodes. In addition, the normally-on state of the transistor caused by this parasitic channel can be suppressed. In other words, the electrical characteristics of the transistor 500F can be improved.

[0506] As described above, by using the upper and lower ends of the oxide 530 as a channel formation region, the channel width can be increased, thereby improving the on-state current, mutual conductance, frequency characteristics, etc. of the transistor 500F.

[0507] Note that in this specification and other publications, the structure of a transistor in which the channel formation region is surrounded by the electric field of the gate electrode is referred to as a surrounded channel (S-channel) structure. In an S-channel structure, the gate electrode is arranged so as to surround at least two or more sides of the channel (specifically, two, three, or four sides). By adopting an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is less susceptible to short channel effects can be realized.

[0508] The S-channel structure is a structure that electrically surrounds the channel formation region, so it can be said that the structure is essentially the same as the GAA (Gate All Around: full-surround gate) structure or the LGAA (Lateral Gate All Around: lateral full-surround gate) structure. By making the transistor 500F have an S-channel structure, a GAA structure or a LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the insulator 545 used as a gate insulating film can be set in the entire bulk of the oxide 530. As a result, the current density flowing through the transistor can be increased, so the on-state current of the transistor or the field effect mobility of the transistor can be increased. In addition, in one embodiment of the present invention, the oxide 530 has a CAAC structure and a fin shape. By adopting this structure, it is possible that the current path flowing between the source and drain of the transistor is parallel to the ab plane of the crystal axis. In other words, the oxide semiconductor having a CAAC structure and a fin shape has a conduction path equivalent to that of a two-dimensional semiconductor material. In addition, by using such an oxide semiconductor, a device with two-dimensional conduction performance can be manufactured.

[0509] In addition, if Figures 32A to 32EAs shown, in the transistor 500F, the conductor 503 may be provided under the insulator 521. Note that Figures 32A to 32E Corresponding to Figures 28A to 28E In About Figures 32A to 32E For matters not described below, please refer to the above Figures 28A to 28E Description, etc.

[0510] Like the conductor 560, the conductor 503 has a region serving as a gate electrode. The conductor 560 is sometimes referred to as the first gate electrode (upper gate electrode) of the transistor 500F, and the conductor 503 is sometimes referred to as the second gate electrode (lower gate electrode) of the transistor 500F. Furthermore, the conductor 560 is sometimes referred to as the gate electrode of the transistor 500F, and the conductor 503 is sometimes referred to as the back gate electrode of the transistor 500F.

[0511] When the transistor 500F includes the conductive body 503 below the insulator 521, the insulators 522 and 521 both include regions that function as gate insulating films, similarly to the insulator 545. Specifically, the regions overlapping the conductive body 503 in each of the insulators 522 and 521 function as gate insulating films. Furthermore, the insulator 545 is sometimes referred to as the first gate insulating film (the upper gate insulating film), and the insulators 522 and 521 are sometimes referred to as the second gate insulating films (the lower gate insulating films).

[0512] In the transistor 500F, the conductor 503 is arranged so as to overlap with the oxide 530 and the conductor 560. Figure 32C and Figure 32E In the embodiment, the conductor 503 is provided inside the fourth opening that passes through the insulator 516 and reaches the insulator 514. Furthermore, the fourth opening includes, when viewed from above, a region overlapping with the oxide 530 and a region extending in the channel width direction beyond the end of the oxide 530. Therefore, the conductor 503 provided inside the fourth opening also includes, when viewed from above, a region overlapping with the oxide 530 and a region extending in the channel width direction beyond the end of the oxide 530. The conductor 503 is also used as wiring.

[0513] like Figure 32C and Figure 32E As shown, the conductor 503 preferably includes a conductor 503a and a conductor 503b. The conductor 503a is provided so as to contact the bottom and side surfaces of the fourth opening. The conductor 503b is provided so as to be embedded in the recess of the conductor 503a formed along the bottom and side surfaces of the fourth opening. Here, the height of the top surface of the conductor 503 is the same as the height of the top surface of the insulator 516.

[0514] Here, the conductor 503a preferably includes a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferably included a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0515] By using a conductive material that has the function of inhibiting hydrogen diffusion as the conductor 503a, impurities such as hydrogen contained in the conductor 503b can be prevented from diffusing into the oxide 530 through the insulator 516 and the like. In addition, by using a conductive material that has the function of inhibiting oxygen diffusion as the conductor 503a, oxidation of the conductor 503b and a decrease in conductivity can be suppressed. Examples of conductive materials that have the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 503a can have a single layer structure or a stacked layer structure of the above conductive materials. For example, the conductor 503a preferably includes titanium nitride.

[0516] Furthermore, the conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 503b preferably contains tungsten.

[0517] As described above, the conductor 503 can be used as a second gate electrode. In this case, the threshold voltage of the transistor 500F can be controlled by independently changing the potential supplied to the conductor 503 without interlocking it with the potential supplied to the conductor 560. In particular, by applying a negative potential to the conductor 503, the threshold voltage of the transistor 500F can be increased and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 503, the drain current when the potential of the conductor 560 is 0V can be reduced compared to when no negative potential is applied to the conductor 503.

[0518] The resistivity of the conductor 503 is designed based on the potential applied to the conductor 503, and the thickness of the conductor 503 is set based on this resistivity. Furthermore, the thickness of the insulator 516 is substantially the same as that of the conductor 503. It is preferable to reduce the thickness of the conductor 503 and the insulator 516 within the design allowable range of the conductor 503. Reducing the thickness of the insulator 516 can reduce the absolute amount of impurities such as hydrogen contained in the insulator 516, thereby suppressing the diffusion of these impurities into the oxide 530.

[0519] Note that while a stacked structure of conductors 503a and 503b is shown here, the present invention is not limited to this. Conductor 503 may have a single-layer structure or a stacked structure of three or more layers. For example, to achieve a three-layer stacked structure of conductors 503a and 503b, a conductor made of the same material as conductor 503a may be provided on conductor 503b. In this case, conductor 503b may be formed so that its top surface is lower than the uppermost portion of conductor 503a and is embedded in a recess formed by conductors 503a and 503b.

[0520] [Transistor 800] Figure 33A and Figure 33B 1 is a cross-sectional view illustrating another transistor that can be used in the memory device according to one embodiment of the present invention.

[0521] Figure 33A and Figure 33B 1 and 2 show a transistor 800 on an insulator 810, an insulator 880, an insulator 881 on the insulator 880, and the semiconductor device 200 (the transistor 600 and the capacitor 690) on the transistor 800. The insulator 810, the insulator 880, and the insulator 881 serve as interlayer films.

[0522] Also shown are conductor 820, oxide 830, insulator 850, and conductor 860 included in transistor 800. In transistor 800, oxide 830 serves as a semiconductor film including a channel formation region, conductor 860 serves as a gate electrode, insulator 850 serves as a gate insulator, conductor 820 serves as one of a source electrode and a drain electrode, and conductor 610 serves as the other of the source and drain electrodes. Conductor 610 also serves as the other of a pair of electrodes for capacitor 690. Furthermore, conductors 820 and 860 also serve as wiring.

[0523] Figure 33A and Figure 33B The structural example shown can be applied to the above-mentioned embodiment 1, for example. Figure 12 In the connection example shown, the drive circuit 123 is used Figure 14AThe structure shown. At this time, transistor 600 is equivalent to transistor M11, capacitor 690 is equivalent to capacitor C11, and transistor 800 is equivalent to transistor M21. In other words, conductor 670 includes a region serving as the gate of transistor M11, conductor 660 includes a region serving as the other of the source and drain of transistor M11, conductor 630 includes a region serving as one of the source and drain of transistor M11 and a region serving as one terminal of capacitor C11, conductor 610 includes a region serving as the other terminal of capacitor C11 and a region serving as one of the source and drain of transistor M21, conductor 860 includes a region serving as the gate of transistor M21, and conductor 820 includes a region serving as the other of the source and drain of transistor M21. In addition, conductor 670 is equivalent to wiring WL, conductor 660 is equivalent to wiring BL, conductor 610 is equivalent to wiring PL, conductor 630 is equivalent to wiring SN, conductor 860 is equivalent to wiring PWL, and conductor 820 is equivalent to wiring PBL. Note that in Figures 33A to 33B In FIG. 1 , portions corresponding to the transistor M11 , the capacitor C11 , the transistor M21 , the wiring WL, the wiring BL, the wiring PL, the wiring SN, the wiring PWL, and the wiring PBL are denoted by parenthesized symbols.

[0524] That is to say, in Figure 33A and Figure 33B In the example of the structure shown, the capacitor C11 is stacked on the transistor M21, and the transistor M11 is stacked on the capacitor C11. In other words, the transistor M21, the capacitor C11, and the transistor M11 all have overlapping regions when viewed from above. Therefore, for example, in the first embodiment described above, Figure 12 In the connection example shown, when used as a drive circuit 123 Figure 14A When the structure shown is applied Figure 33A and Figure 33B The structure shown can suppress the increase in occupied area due to the provision of the driving circuit 123.

[0525] The transistor 800 will be described. Note that the transistor 600 and the capacitor 690 can be described with reference to the above description, and therefore their description will be omitted here.

[0526] Figure 34A is a top view of transistor 800 . Figure 34B corresponds to Figure 34A FIG. 8 is a cross-sectional view of the transistor 800 at the portion indicated by the dashed line A1-A2. Figure 34C It is along Figure 34A1 is a cross-sectional view of transistor 800, shown in the portion indicated by the dashed line A3-A4. Note that the dashed line A1-A2 is a straight line parallel to the X direction in the drawing, and the dashed line A3-A4 is a straight line parallel to the Y direction in the drawing. In addition, some components are omitted in the top view for easier understanding. Some components may also be omitted in the following top views.

[0527] Figures 34B to 34C 1 and 2. The transistor 800 is shown on an insulator 810, an insulator 880, and an insulator 881 on the insulator 880. The insulator 810, the insulator 880, and the insulator 881 serve as interlayer films.

[0528] Transistor 800 includes a conductor 820 on an insulator 810 , an oxide 830 on conductor 820 , an insulator 850 on insulator 880 , a conductor 860 on insulator 850 , and a conductor 610 on oxide 830 , insulator 850 , and insulator 881 .

[0529] The insulator 880 is provided on the conductor 820 and the insulator 810 . The insulator 881 is provided on the insulator 850 and the conductor 860 .

[0530] The side surface of the oxide 830 is preferably perpendicular to the top surface of the insulator 810. By adopting this structure, miniaturization or high integration of the transistor 800 can be achieved. At this time, the films arranged on the outside of the oxide 830 are preferably formed using the ALD method. The ALD method can deposit atoms layer by layer, thereby having the effects of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Therefore, the film can be deposited with high coverage on the side surface of the oxide 830. For example, the insulator 850 and the conductor 860 are preferably both formed using the ALD method.

[0531] In the case where the side surface of the oxide 830 is perpendicular to the top surface of the insulator 810, as shown in FIG. Figure 34B and Figure 34C As shown, oxide 830 has a cylindrical shape. Oxide 830 is provided in a manner extending in the Z direction. That is, the normal line of the bottom surface and the normal line of the top surface of oxide 830 are parallel to the Z direction. In addition, the bottom surface of oxide 830 contacts a portion of the top surface of conductor 820, the top surface of oxide 830 contacts a portion of the bottom surface of conductor 610, and at least a portion of the side surface of oxide 830 contacts insulator 850. In addition, Figure 34B and Figure 34C In the structure shown, another portion of the side of the oxide 830 is in contact with the insulator 880 .

[0532] The height of the top surface of the oxide 830 coincides with each of the height of the top surface of the insulator 850 and the height of the top surface of the insulator 881 .

[0533] The insulator 850 covers at least a portion of the side surface of the oxide 830. The insulator 850 has a region in contact with the conductor 610. The insulator 850 has a first region between the oxide 830 and the conductor 860 and a second region between the conductor 820 and the conductor 860. The second region can be said to be located between the insulator 880 and the conductor 860. Figure 34B In FIG. 8 , the width of the first region of insulator 850 in the direction from oxide 830 to conductor 860 (X or Y direction) is W850. Furthermore, the width of the second region of insulator 850 in the direction from conductor 820 to conductor 860 (Z direction) is H850. For example, when insulator 850 is formed using ALD, width W850 is equal to width H850.

[0534] The top surface of the portion of conductor 860 that extends along the side surface of oxide 830 is located below the top surface of oxide 830 (on the side of insulator 810). Conductor 860 includes a first region that faces the side surface of oxide 830 via insulator 850, and a second region that overlaps conductor 820 via insulator 850. For example, when conductor 860 is formed using ALD, the width of the first region of conductor 860 in the X or Y direction is equal to the width of the second region of conductor 860 in the Z direction.

[0535] exist Figure 34B and Figure 34C In the transistor 800 shown, the conductor 860 is provided so as to extend in the Y direction, and the conductor 820 is provided so as to extend in the X direction.

[0536] In transistor 800, oxide 830 is used as a semiconductor film including a channel formation region, conductor 860 is used as a gate electrode, insulator 850 is used as a gate insulating film, conductor 820 is used as one of a source electrode and a drain electrode, and conductor 610 is used as the other of the source electrode and the drain electrode.

[0537] In addition, in transistor 800, one of the source and drain electrodes (here, conductor 820) is located below and the other (here, conductor 610) is located above. Therefore, transistor 800 has a structure in which current flows in the vertical direction. In other words, a channel is formed along the side of oxide 830. In addition, transistor 800 has a structure in which the gate electrode surrounds the channel formation region. Therefore, transistor 800 can be said to be a GAA structure transistor.

[0538] In the transistor 800, the oxide 830 including the channel formation region preferably includes a metal oxide (also referred to as an oxide semiconductor) serving as a semiconductor. For example, the metal oxides that can be used for the above-described oxide 650 can also be used as the oxide 830. Note that semiconductors that can be used for the oxide 830 are not limited to the above-described metal oxides.

[0539] Here, as insulator 850, for example, a material that can be used for insulator 672 described above can also be used. Furthermore, as conductor 860, for example, a material that can be used for conductor 610 described above can also be used. Furthermore, as conductor 820, for example, a material that can be used for conductor 610 described above can also be used. Furthermore, as insulator 810, for example, a material that can be used for insulator 612 described above can also be used. Furthermore, as insulator 880 and insulator 881, for example, a material that can be used for insulator 620 or insulator 640 described above can also be used.

[0540] In transistor 800, the region of oxide 830 covered by conductor 860 via insulator 850 serves as a channel formation region. The region of oxide 830 in contact with conductor 820 serves as one of the source and drain regions, while the region in contact with conductor 610 serves as the other. In other words, the channel formation region is sandwiched between the source and drain regions.

[0541] When oxide 830 contacts conductor 820, metal compounds or oxygen vacancies are formed, lowering the resistance of the region of oxide 830 in contact with conductor 820. This reduces the contact resistance between oxide 830 and conductor 820. Similarly, contact between oxide 830 and conductor 610 reduces the resistance of the region of oxide 830 in contact with conductor 610. This reduces the contact resistance between oxide 830 and conductor 610.

[0542] When the conductor 860 is used as a gate electrode, the channel length of the transistor 800 is equivalent to the length of the region of the oxide 830 that overlaps with the conductor 860 via the insulator 850 in a cross-sectional view. In other words, the channel length of the transistor 800 is determined by the height of the conductor 860. Figure 34B The dotted double arrow in FIG. 8 represents the channel length L of the transistor 800 .

[0543] In the transistor 800, the channel length can be set according to the height of the conductor 860. As a result, the channel length L of the transistor 800 can be set to a very fine structure below the exposure limit of photolithography (for example, 0.1 nm to 100 nm, 1 nm to 100 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 5 nm to 30 nm, 5 nm to 20 nm, or 5 nm to 10 nm). As a result, the on-state current of the transistor 800 is increased, thereby improving the frequency characteristics.

[0544] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the oxide 830. Therefore, compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane, the occupied area of ​​the transistor 800 can be reduced. Consequently, high integration of the transistor 800 can be achieved. Furthermore, when the transistor 800 according to one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.

[0545] The height of the oxide 830 needs to be greater than the channel length L of the transistor 800. On the other hand, the height of the oxide 830 needs to be within a range that does not cause the oxide 830, which has been processed into a cylindrical shape, to collapse. Therefore, the height of the oxide 830 is preferably, for example, 20 nm to 200 nm, more preferably 50 nm to 200 nm, even more preferably 80 nm to 200 nm, even more preferably 80 nm to 150 nm, and even more preferably 80 nm to 120 nm.

[0546] Here, Figure 34D 8 shows an enlarged cross-sectional view of the XY plane including the oxide 830, the insulator 850, the conductor 860, and the insulator 881. Figure 34D It can also be said that it is a cross-sectional view on the XY plane of the channel formation region including the oxide 830. Figure 34D As shown, the insulator 850 and the conductor 860 are arranged in a concentric circle shape. Therefore, the side surface of the oxide 830 arranged in the center is opposite to the side surface of the conductor 860 across the insulator 850. In other words, the entire periphery of the oxide 830 becomes a channel forming region when viewed from above. At this time, for example, the channel width of the transistor 800 is determined by the length of the periphery of the oxide 830. In other words, the channel width of the transistor 800 is determined by the width of the oxide 830 (the diameter when the shape of the oxide 830 is circular when viewed from above). Figure 34B and Figure 34D In FIG, the width D of the oxide 830 is indicated by a double-dashed double arrow. Figure 34DIn FIG, a double-dash arrow indicates a channel width W of the transistor 800. By increasing the width D of the oxide 830, the channel width can be increased, thereby increasing the on-state current.

[0547] When oxide 830 is formed using photolithography, the width D of oxide 830 is set according to the exposure limit of the photolithography. The width D of oxide 830 can be 5 nm to 100 nm, 5 nm to 60 nm, 5 nm to 50 nm, or 5 nm to 40 nm. Note that when oxide 830 is circular in plan view, the width D of oxide 830 corresponds to the diameter of oxide 830, and the channel width W can be calculated as "D×π".

[0548] Therefore, the ratio of the height of the oxide 830 to the width D of the oxide 830 can be 0.2 or more and 40 or less, or 1 or more and 40 or less.

[0549] The height of oxide 830 is preferably greater than the width D of oxide 830. In other words, the width D of oxide 830 is preferably smaller than the height of oxide 830. By adopting this structure, miniaturization or high integration of transistor 800 can be achieved. In addition, when the height of oxide 830 is increased to increase the channel length L of transistor 800, the variation in the threshold voltage of transistor 800 can be reduced. When the height of oxide 830 is increased to increase the physical distance between conductor 860 and conductor 610, the parasitic capacitance generated between conductor 860 and conductor 610 can be reduced. In addition, the height of oxide 830 can be set to be equal to or smaller than the width D of oxide 830.

[0550] Furthermore, the channel length L of the transistor 800 may be smaller than the channel width W of the transistor 800. The channel length L of the transistor 800 is preferably not less than 0.1 times and not more than 0.99 times, and more preferably not less than 0.5 times and not more than 0.8 times, the channel width W of the transistor 800. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0551] In addition, this embodiment shows an example in which the shape of the oxide 830 is circular when viewed from above, but the present invention is not limited to this. For example, the shape of the oxide 830 when viewed from above may be a substantially circular shape such as an ellipse, a polygonal shape such as a square, or a shape with rounded corners such as a square.

[0552] Insulator 880 contacts another portion of the side surface of oxide 830. Insulator 880 contacts the top surface and side surface of conductor 820. Insulator 880 includes a region between conductor 820 and insulator 850. The thickness of insulator 880 on conductor 820 is preferably 1 nm to 50 nm, more preferably 3 nm to 30 nm, even more preferably 5 nm to 30 nm, and even more preferably 10 nm to 20 nm. By adopting this structure, the physical distance between conductor 820 and conductor 860 can be increased, and the parasitic capacitance generated between conductor 820 and conductor 860 can be reduced.

[0553] The insulator 881 has a region located between the top surface of the portion of the conductor 860 along the side of the oxide 830 and the bottom surface of the conductor 610. By adopting this structure, the conductor 860 and the conductor 610 can be prevented from short-circuiting. In addition, by increasing the height of the above-mentioned region (the shortest distance from the top surface of the portion of the conductor 860 along the side of the oxide 830 to the bottom surface of the conductor 610), the parasitic capacitance generated between the conductor 860 and the conductor 610 can be reduced. The height of the above-mentioned region can be, for example, 5 nm to 50 nm, 5 nm to 30 nm, or 5 nm to 20 nm. In addition, the height (thickness) of the insulator 881 in the region that does not overlap with the conductor 860 is the sum of the height of the above-mentioned region and the height of the conductor 860 (channel length L).

[0554] Notice, Figures 34A to 34D The transistor 800 shown is only an example and is not limited to this structure.

[0555] <Constituent Materials of Storage Device> The constituent materials that can be used for semiconductor devices including transistors and capacitors are not limited to the above-mentioned structural examples. In one embodiment of the present invention, in addition to the above-mentioned constituent materials, the constituent materials shown below can also be used as appropriate.

[0556] [Substrate] As substrates for semiconductor devices and memory devices including the semiconductor devices that can be provided as one embodiment of the present invention, for example, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, metal substrates (for example, stainless steel substrates, substrates including stainless steel foil, tungsten substrates, substrates including tungsten foil, etc.), semiconductor substrates (for example, single crystal semiconductor substrates, polycrystalline semiconductor substrates, or compound semiconductor substrates), or SOI (Silicon on Insulator) substrates can be used. Furthermore, heat-resistant plastic substrates can also be used as substrates. Examples of glass substrates include barium borosilicate glass, aluminosilicate glass, aluminoborosilicate glass, and soda-lime glass. Furthermore, examples of glass substrates include crystallized glass.

[0557] In addition, as a substrate, for example, a flexible substrate, a laminating film, paper or base film containing a fibrous material can be used. For example, as a flexible substrate, a laminating film or base film, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, synthetic resins such as acrylic resins can be cited. Alternatively, for example, polypropylene, polyester, polyvinyl fluoride or polyvinyl chloride can be cited. Alternatively, for example, polyamide, polyimide, aromatic polyamide resin, epoxy resin, inorganic vapor-deposited film, paper, etc. can be cited. In particular, by manufacturing transistors, for example, using semiconductor substrates, single crystal substrates or SOI substrates, it is possible to manufacture transistors with small deviations in characteristics, size or shape, high current capacity and small size. When a circuit is formed using the above-mentioned transistors, low power consumption of the circuit or high integration of the circuit can be achieved.

[0558] In addition, a flexible substrate can be used as a substrate, and one or more transistors, resistors, capacitors, etc. can be directly formed on the flexible substrate. Alternatively, a peeling layer can be provided between the substrate and one or more transistors, resistors, capacitors, etc. The peeling layer can be used in the following cases, that is, a part or all of the semiconductor device is manufactured on the peeling layer, and then it is separated from the substrate and transferred to another substrate. In this case, one or more transistors, resistors, capacitors, etc. can also be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned peeling layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, a structure with an organic resin film such as polyimide formed on a substrate, or a silicon film containing hydrogen can be used.

[0559] That is to say, after forming a semiconductor device on one substrate, the semiconductor device can be transferred to another substrate. As the substrate to which the semiconductor device is transferred, not only the above-mentioned substrates on which transistors can be formed can be used, but also paper substrates, glassine substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium fiber, rayon, regenerated polyester), etc.), leather substrates, rubber substrates, etc. can be used. By using these substrates, it is possible to manufacture flexible semiconductor devices or manufacture semiconductor devices that are not easily damaged. In addition, heat resistance can be imparted to the semiconductor device. In addition, it is possible to achieve lightweighting and thinning of the semiconductor device.

[0560] By providing a semiconductor device on a flexible substrate, a semiconductor device can be provided that is less prone to damage while suppressing weight increase.

[0561] [Ferroelectrics] As an insulator (insulator 632, etc.) used as a dielectric in a semiconductor device that can be used in one embodiment of the present invention, a material having ferroelectricity can also be used. Examples of materials having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, there can be mentioned a material in which an element J1 is added to hafnium oxide (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). In addition, the atomic number ratio of hafnium to element J1 can be appropriately set. For example, the atomic number ratio of hafnium to element J1 can be 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, there can be mentioned a material in which an element J2 is added to zirconium oxide (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.). In addition, the atomic number ratio of zirconium to element J2 can be appropriately set. For example, the atomic number ratio of zirconium to element J2 can be 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0562] In addition, as materials that can have ferroelectricity, metal nitrides containing element M1, element M2, and nitrogen can be cited. Here, element M1 is, for example, one or more selected from aluminum, gallium, indium, etc. In addition, element M2 is, for example, one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the atomic number ratio of element M1 to element M2 can be appropriately set. In addition, metal nitrides containing element M1 and nitrogen sometimes have ferroelectricity even if they do not contain element M2. In addition, as materials that can have ferroelectricity, materials obtained by adding element M3 to the above-mentioned metal nitrides can be cited. Here, element M3 is, for example, one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In this case, the atomic number ratio of element M1, element M2, and element M3 can be appropriately set.

[0563] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0564] Note that although metal oxides and metal nitrides are shown as examples in the above description, the present invention is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal oxynitrides obtained by adding oxygen to the above metal nitrides may also be used.

[0565] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the above materials can be used. In addition, as an insulator using a material that can have ferroelectricity, a stacked structure composed of a plurality of materials selected from the above materials can be used. The crystal structure (properties) of the materials and the like listed above may change not only depending on the deposition conditions but also depending on various processes and the like. Therefore, in this specification and the like, sometimes not only a material that exhibits ferroelectricity is referred to as a ferroelectric, but also a material that can have ferroelectricity is also referred to as a ferroelectric.

[0566] The metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if it is processed into a thin film of several nm, so it is preferred. Here, the thickness of the insulator using the material having ferroelectricity can be less than 100nm, preferably less than 50nm, more preferably less than 20nm, and further preferably less than 10nm (typically, more than 2nm and less than 9nm). For example, the thickness of the insulator is preferably more than 8nm and less than 12nm. By using a ferroelectric layer that can be thin-filmed as an insulator for a dielectric used as a capacitor, the capacitor can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. In this specification, etc., the material that can have ferroelectricity that is formed into a layer is sometimes referred to as a ferroelectric layer, a metal oxide film or a metal nitride film. In addition, in this specification, etc., sometimes a device including a ferroelectric layer, a metal oxide film or a metal nitride film is referred to as a ferroelectric device.

[0567] Furthermore, metal oxides containing one or both of hafnium and zirconium are preferred because they can exhibit ferroelectricity even when their area is small. For example, even if the area (occupied area) of the ferroelectric layer is 100 μm in top view, 2 Below 10μm 2 Below 1μm 2 Below or 0.1μm 2 The following may also have ferroelectric properties. In addition, sometimes the ferroelectric layer has an area (occupied area) of 10000nm when viewed from above. 2 Below or 1000nm 2 The following also has ferroelectric properties. By forming a small ferroelectric layer, the area occupied by the capacitor can be reduced.

[0568] Ferroelectrics are insulators that become internally polarized when exposed to an external electric field and maintain this polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric. Nonvolatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, with one of the transistor's source and drain connected to one terminal of the ferroelectric capacitor.

[0569] In addition, ferroelectricity is believed to be exhibited because oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the structure of the crystals contained in the ferroelectric layer. Therefore, in order to exhibit ferroelectricity using an insulator of a material that can have ferroelectricity, the insulator needs to contain crystals. In particular, the insulator preferably contains crystals having an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystal contained in the insulator is one or more selected from the group consisting of an isometric system, a tetragonal system, an orthorhombic system, a monoclinic system, and a hexagonal system. In addition, the insulator may also have an amorphous structure. In this case, the insulator may also have a composite structure of an amorphous structure and a crystal structure.

[0570] Note that one embodiment of the present invention is not limited to the working examples described in this embodiment mode. At least a portion of the structural examples, working examples, and drawings corresponding to these examples described in this embodiment mode may be appropriately combined with other structural examples, working examples, drawings, and other embodiments described elsewhere in this specification.

[0571] Implementation 3 In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. The OS transistor is briefly described in comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0572] [OS transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of an oxide semiconductor is to be reduced, the impurity concentration in the oxide semiconductor can be reduced to reduce the defect state density in the oxide semiconductor. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0573] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes also have a low trap state density. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear, sometimes acting like fixed charges. Consequently, transistors with channel formation regions formed in oxide semiconductors with a high trap state density sometimes experience unstable electrical characteristics.

[0574] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to elements other than the main components of the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0575] In an OS transistor, when impurities or oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed, which may reduce the reliability. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, in the OS transistor, when V O When the voltage is V, the donor concentration in the channel formation region may increase. Therefore, in the OS transistor, as the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor will have a normally-on characteristic (a characteristic in which the drain current flows when the gate voltage is 0V). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0576] Furthermore, the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or greater, more preferably 2.5 eV or greater, and even more preferably 3.0 eV or greater. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also known as Ioff) of the transistor can be reduced.

[0577] For example, in Si transistors, as transistors become increasingly miniaturized, a short channel effect (SCE) occurs. Therefore, miniaturization of Si transistors is difficult. One reason for the short channel effect is the small band gap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with large band gaps, to suppress the short channel effect. In other words, OS transistors have no short channel effect or very little short channel effect.

[0578] The short-channel effect refers to the degradation of electrical properties that occurs with transistor miniaturization (reduction in channel length). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), and an increase in leakage current. The S value refers to the change in gate voltage in the subthreshold region that causes a single-digit change in drain current at a fixed drain voltage.

[0579] Characteristic length is widely used as an indicator of resistance to short channel effects. Characteristic length refers to the curvature of the potential in the channel formation region. The smaller the characteristic length, the more steeply the potential rises, and therefore it can be said that the resistance to short channel effects is high.

[0580] OS transistors are accumulation-mode transistors, while Si transistors are inversion-mode transistors. Therefore, compared to Si transistors, the characteristic lengths between the source region and the channel formation region, and the characteristic lengths between the drain region and the channel formation region, in OS transistors are smaller. Consequently, OS transistors are more resistant to short-channel effects than Si transistors. In other words, when manufacturing transistors with short channel lengths, OS transistors are more suitable than Si transistors.

[0581] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor. Therefore, the energy difference in the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to 0.1 eV or more and 0.2 eV or less. Therefore, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel forming region is n - Type region, source region and drain region are both n + Type area.

[0582] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even with miniaturization or high integration. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the short channel effect. Therefore, compared with Si transistors, OS transistors are suitable for use as transistors with a small channel length. Gate length refers to the length of the gate electrode in the direction in which carriers migrate within the channel formation region when the transistor is working, that is, the width of the bottom surface of the gate electrode of the transistor when viewed from above.

[0583] Furthermore, miniaturizing the OS transistor can improve the transistor's high-frequency characteristics. Specifically, the transistor's cutoff frequency can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the transistor's cutoff frequency can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0584] As described above, OS transistors have advantages superior to Si transistors, such as small off-state current and the ability to manufacture transistors with small channel lengths.

[0585] The configuration, structure, method, and the like described in this embodiment can be used in combination with the configuration, structure, method, and the like described in other embodiments, etc., as appropriate.

[0586] Implementation 4 In this embodiment, an application example of a storage device according to one embodiment of the present invention is described.

[0587] <Storage Device Hierarchical Structure Example> Generally speaking, various memory devices are used in semiconductor devices such as computers according to their applications. Figure 35 Various storage devices are shown in layers. The higher the layer, the faster the operating speed is required, while the lower the layer, the larger the storage capacity and the higher the storage density is required. Figure 35In the figure, registers, cache memory, main memory, and storage are shown in order from the top layer. In addition, the cache memory may also include a first-level cache (L1), a second-level cache (L2), and a third-level cache (L3) from the top layer. Note that although the example shown here includes at most a third-level cache, cache memories at lower levels may also be included. The cache memory at the bottom layer is sometimes called LLC (Last Level Cache) or FLC (Final Level Cache). In addition, for example, a storage-level memory may also be included between the main memory and the storage.

[0588] Registers are integrated into arithmetic processing units (also known as processors) such as CPUs (Central Processing Units), GPUs (Graphics Processing Units), NPUs (Neural Processing Units), and TPUs (Tensor Processing Units) to temporarily store the results of core calculations. Registers also hold configuration information for the arithmetic processing units. Consequently, they are frequently accessed by the arithmetic processing units. Consequently, registers are required to operate at high speeds.

[0589] For example, SRAM (Static Random Access Memory) is used as a cache memory. Cache memory copies and stores a portion of the data stored in main memory. By copying frequently used data, access speed can be increased. Cache memory is required to operate faster than main memory.

[0590] As the main memory, for example, DRAM (Dynamic Random Access Memory) is used. The main memory has the function of storing programs and data read from the memory. Compared with the cache memory, the main memory is required to have a larger storage capacity and higher storage density.

[0591] Storage has the function of storing data that needs to be preserved for a long time and various programs used by processing devices. Therefore, storage requires large storage capacity and high storage density. For example, HDDs (Hard Disk Drives) and SSDs (Solid State Drives) located above HDDs can be used as storage. For example, NAND flash memory (e.g., 3D NAND) and other large-capacity, non-volatile storage devices can be used as SSDs.

[0592] A memory device according to one embodiment of the present invention (for example, a memory device using an oxide semiconductor) has the following advantages: high operating speed, ability to retain data for a long time, high rewrite resistance, and ability to be driven at a low voltage.

[0593] From the perspective of long-term data retention, a storage device according to one embodiment of the present invention is preferably used as a storage device located in a first target area that includes the cache memory layer, the main memory layer, and the storage layer. In other words, a storage device according to one embodiment of the present invention is preferably used in the first target area that includes the main memory layer, the boundary area between the main memory and the storage layer, and the boundary area between the main storage and the cache memory.

[0594] Therefore, for example, it is preferable to use a memory device according to one embodiment of the present invention instead of DRAM used for main memory. DRAM is a memory device that requires refresh operations and destructive reads, and therefore consumes higher power than other memory devices. Therefore, by not using DRAM, power consumption can be reduced. For example, it is also preferable to use a memory device according to one embodiment of the present invention instead of a portion of SRAM used for cache memory or a portion of 3D NAND used for storage.

[0595] Furthermore, from the perspective of achieving high-speed and excellent write and read operations, the memory device according to one embodiment of the present invention is suitable for use as a memory device located in a second target area that includes a hierarchy where a cache memory is located and a hierarchy where registers are located. In other words, the memory device according to one embodiment of the present invention is preferably used in a second target area that includes a portion of an area where a cache memory is located and an area where registers are located.

[0596] Therefore, for example, a storage device according to one embodiment of the present invention is preferably used as at least a portion of registers included in a CPU, GPU, NPU, etc. Furthermore, for example, a storage device according to one embodiment of the present invention is preferably used as at least a portion of a cache memory (L1, L2, L3, LLC, FLC, etc.).

[0597] One embodiment of the present invention eliminates the need for DRAM, which is typically used for main memory. In this case, a storage device according to one embodiment of the present invention can be used in place of DRAM. By adopting this structure, power consumption can be significantly reduced (e.g., by 1 / 100 or 1 / 1000 or less). Therefore, global warming can be mitigated by globally distributing information processing devices, including supercomputers (also known as HPCs), computers, and servers, that have this structure.

[0598] <Structure Example of Memory Cell> A memory device according to one embodiment of the present invention is a memory device using an oxide semiconductor. The memory device includes a memory cell using an OS transistor. Examples of such a memory cell include the memory cell 111 described in Embodiment 1 and the like, and the following structures.

[0599] Figure 36A The illustrated memory cell 950a includes a transistor M911 and a capacitor C911. One of the source and drain of transistor M911 is connected to one terminal of capacitor C911. The other of the source and drain of transistor M911 is connected to wiring BL serving as a bit line. The gate of transistor M911 is connected to wiring WL serving as a word line. The other terminal of capacitor C911 is connected to wiring CL. Note that the wiring connecting one of the source and drain of transistor M911 and one terminal of capacitor C911 is sometimes referred to as wiring MN in the following descriptions.

[0600] In the memory cell 950a, by setting the potential corresponding to the amount of charge stored in the capacitor C911, that is, the amount of charge held in the wiring MN, to "1" or "0," respectively, it is possible to store two values ​​of data. Note that, for example, three or more values ​​of data can also be stored. In addition, when writing data to the memory cell 950a, by controlling the conduction state of the transistor M911, a potential corresponding to the data is supplied from the wiring BL to the wiring MN, thereby holding the charge corresponding to the potential. In addition, when reading data from the memory cell 950a, by controlling the conduction state of the transistor M911, the charge held in the wiring MN can be extracted to the wiring BL.

[0601] When data is read from memory cell 950a, the charge held in wiring MN is extracted to wiring BL, causing the potential of wiring MN to change. In other words, reading data from memory cell 950a destroys the stored data. In other words, when data is read from memory cell 950a, destructive reading is performed. Therefore, after reading data from memory cell 950a, the data must be written back (refreshed).

[0602] In one embodiment of the present invention, for example, an n-channel OS transistor can be used as the transistor M911.

[0603] Figure 36A The memory cell 950a shown is a memory cell of a DRAM (Dynamic Random Access Memory). In particular, a structure that uses an OS transistor as transistor M911 is sometimes referred to as DOSRAM (registered trademark). DOSRAM uses an OS transistor with extremely small off-state current, so it can store data for a long time. In addition, multi-value data or analog data can be stored. In addition, since written data can be stored for a long time, the refresh frequency of the data can be reduced. In addition, since the electrostatic capacitance of the cell capacitor (capacitor C911) can be reduced, the cel...

Claims

1. A storage device, comprising: A memory array including a first memory cell; as well as A peripheral circuit including a first driving circuit, The first storage unit includes a first transistor and a first capacitor. One of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor, The other of the source and the drain of the first transistor is electrically connected to a first bit line, The gate of the first transistor is electrically connected to the first word line, The other terminal of the first capacitor is electrically connected to the first drive circuit, The first drive circuit is configured to output a first potential, output a second potential in conjunction with a timing of a potential change of a selection signal supplied to the first word line, and output a third potential in conjunction with a timing of a potential change of data supplied to the first bit line. The direction of change from the first potential to the second potential is opposite to the direction of change of the potential of the selection signal. Furthermore, a change direction from the first potential to the third potential is opposite to a change direction of the potential of the data.

2. A storage device, comprising: A storage array comprising a first storage unit and a second storage unit; as well as A peripheral circuit including a first driving circuit and a second driving circuit, The first storage unit includes a first transistor and a first capacitor. The second storage unit includes a second transistor and a second capacitor, One of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor, The other of the source and the drain of the first transistor is electrically connected to a first bit line, The gate of the first transistor is electrically connected to the first word line, The other terminal of the first capacitor is electrically connected to the first drive circuit, One of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor, The other of the source and the drain of the second transistor is electrically connected to the first bit line, The gate of the second transistor is electrically connected to the second word line, The other terminal of the second capacitor is electrically connected to the second drive circuit, the first drive circuit is configured to output a signal whose potential changes in a direction opposite to a potential change direction of a selection signal supplied to the first word line, Furthermore, the second drive circuit is configured to output a signal whose potential changes in a direction opposite to a direction in which a potential changes in a selection signal supplied to the second word line.

3. A storage device, comprising: A storage array comprising a first storage unit and a second storage unit; as well as A peripheral circuit including a first driving circuit and a second driving circuit, The first storage unit includes a first transistor and a first capacitor. The second storage unit includes a second transistor and a second capacitor. One of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor, The other of the source and the drain of the first transistor is electrically connected to a first bit line, The gate of the first transistor is electrically connected to the first word line, The other terminal of the first capacitor is electrically connected to the first drive circuit, One of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor, The other of the source and the drain of the second transistor is electrically connected to a second bit line, The gate of the second transistor is electrically connected to the first word line, The other terminal of the second capacitor is electrically connected to the second drive circuit, the first drive circuit is configured to output a signal whose potential changes in a direction opposite to a direction of potential change of data supplied to the first bit line, Furthermore, the second driving circuit is configured to output a signal whose potential changes in a direction opposite to a direction of potential change of data supplied to the second bit line.

4. A storage device, comprising: A storage array comprising a first storage unit, a second storage unit, a third storage unit and a fourth storage unit; as well as The peripheral circuit includes a first driving circuit, a second driving circuit, a third driving circuit and a fourth driving circuit, The first storage unit includes a first transistor and a first capacitor. The second storage unit includes a second transistor and a second capacitor. The third storage unit includes a third transistor and a third capacitor. The fourth storage unit includes a fourth transistor and a fourth capacitor, One of a source and a drain of the first transistor is electrically connected to one terminal of the first capacitor, The other of the source and the drain of the first transistor is electrically connected to a first bit line, The gate of the first transistor is electrically connected to the first word line, The other terminal of the first capacitor is electrically connected to the first drive circuit, One of a source and a drain of the second transistor is electrically connected to one terminal of the second capacitor, The other of the source and the drain of the second transistor is electrically connected to the first bit line, The gate of the second transistor is electrically connected to the second word line, The other terminal of the second capacitor is electrically connected to the second drive circuit, One of the source and the drain of the third transistor is electrically connected to one terminal of the third capacitor, The other of the source and the drain of the third transistor is electrically connected to a second bit line, The gate of the third transistor is electrically connected to the first word line, The other terminal of the third capacitor is electrically connected to the third driving circuit, One of the source and the drain of the fourth transistor is electrically connected to one terminal of the fourth capacitor, The other of the source and the drain of the fourth transistor is electrically connected to the second bit line, The gate of the fourth transistor is electrically connected to the second word line, Furthermore, the other terminal of the fourth capacitor is electrically connected to the fourth driving circuit.

5. The storage device according to claim 1, The first transistor includes an oxide semiconductor in a channel formation region.

6. The storage device according to claim 1, Wherein the first transistor is on the first capacitor.

7. The storage device according to claim 6, further comprising: a first electrical conductor; a second electrical conductor on the first electrical conductor; as well as a third conductor on the second conductor, wherein the first electrical conductor comprises another terminal of the first capacitor, The second conductor includes one terminal of the first capacitor and one of the source and the drain of the first transistor, And the third electrical conductor includes the other of the source and the drain of the first transistor.

8. The storage device according to claim 1, The storage array is located on the peripheral circuit.

9. The storage device according to claim 2, The first transistor includes an oxide semiconductor in a channel formation region.

10. The storage device according to claim 2, Wherein the first transistor is on the first capacitor.

11. The storage device according to claim 10, further comprising: a first electrical conductor; a second electrical conductor on the first electrical conductor; as well as a third conductor on the second conductor, wherein the first electrical conductor comprises another terminal of the first capacitor, The second conductor includes one terminal of the first capacitor and one of the source and the drain of the first transistor, And the third electrical conductor includes the other of the source and the drain of the first transistor.

12. The storage device according to claim 2, The storage array is located on the peripheral circuit.

13. The storage device according to claim 3, The first transistor includes an oxide semiconductor in a channel formation region.

14. The storage device according to claim 3, Wherein the first transistor is on the first capacitor.

15. The storage device according to claim 14, further comprising: a first electrical conductor; a second electrical conductor on the first electrical conductor; as well as a third conductor on the second conductor, wherein the first electrical conductor comprises another terminal of the first capacitor, The second conductor includes one terminal of the first capacitor and one of the source and the drain of the first transistor, And the third electrical conductor includes the other of the source and the drain of the first transistor.

16. The storage device according to claim 3, The storage array is located on the peripheral circuit.

17. The storage device according to claim 4, The first transistor includes an oxide semiconductor in a channel formation region.

18. The storage device according to claim 4, Wherein the first transistor is on the first capacitor.

19. The storage device according to claim 18, further comprising: a first electrical conductor; a second electrical conductor on the first electrical conductor; as well as a third conductor on the second conductor, wherein the first electrical conductor comprises another terminal of the first capacitor, The second conductor includes one terminal of the first capacitor and one of the source and the drain of the first transistor, And the third electrical conductor includes the other of the source and the drain of the first transistor.

20. The storage device according to claim 4, The storage array is located on the peripheral circuit.

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