Memory circuit and operating method thereof

Abstract

A memory circuit includes a memory array including a plurality of first memory cells. The memory circuit includes a trace column including one or more second memory cells, where each of the one or more second memory cells is coupled to a first trace bit line, a second trace bit line, and a first trace word line. The memory circuit includes a controller operably coupled to the memory array and the trace column and configured to: identify a transition edge of a first signal present on the first trace bit line and assert a second signal present on the first trace word line, raise a third signal present on the second trace bit line; a trigger signal is generated based on the third signal, where a transition edge of the trigger signal causes a write operation performed on at least one of the first memory cells to stop. The embodiment of the invention also discloses a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components, such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of first memory cells; a tracking column comprising one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line, and a first tracking word line; and a controller, operably coupled to the memory array and the tracking column, and configured to: identify a transition edge of a first signal present on the first tracking bit line, and assert a second signal present on the first tracking word line, causing a third signal present on the second tracking bit line to rise; and generate a trigger signal based on the third signal, wherein the transition edge of the trigger signal causes a write operation performed on at least one of the first memory cells to stop.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a memory array comprising a plurality of first memory cells; a tracking column comprising one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line and a first tracking word line, and is configured to emulate a write operation performed on the first memory cell, wherein before the write operation, a first signal present on the first tracking bit line and a second signal present on the second tracking bit line are provided in a first logic state and a second logic state, respectively; and a controller operably coupled to the memory array and the tracking column, and configured to adjust the timing of a falling edge of an internal clock signal based on a rising edge of the second signal.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: asserting an internal clock signal after initiating a write operation performed on a nominal memory cell; negating a first signal present on a first tracking bit line coupled to a tracking unit; activating the tracking unit in response to identifying a rising edge of the internal clock signal or a falling edge of the first signal; and negating the internal clock signal in response to identifying a rising edge of a second signal present on a second tracking bit line coupled to the tracking unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 A block diagram of a memory device including a memory controller according to some embodiments is shown.

[0008] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The following are respectively shown according to some embodiments Figure 1 Implementation of a memory controller.

[0009] Fig.10 A method for operating according to some embodiments is shown. Figure 2-Figure 9 Waveforms of various signals of at least one of the memory controllers.

[0010] Fig.11 An example circuit diagram of a tracking unit according to some embodiments is shown.

[0011] Fig.12 A method for operating according to some embodiments is shown. Figure 2-Figure 9 Waveforms of various signals of at least one of the memory controllers.

[0012] Fig.13 Another example circuit diagram of a tracking unit according to some embodiments is shown.

[0013] Fig.14 shows a device configured to form a Fig.13 Example layout of a tracking unit.

[0014] Fig.15 Yet another example circuit diagram of a tracking unit according to some embodiments is shown.

[0015] Fig.16 shows a device configured to form a Fig.15 Example layout of a tracking unit.

[0016] Fig.17 Yet another example circuit diagram of a tracking unit according to some embodiments is shown.

[0017] Fig.18 shows a device configured to form a Fig.17 Example layout of a tracking unit.

[0018] Fig.19 An example circuit diagram of a trim circuit coupled to a tracking bit line is shown in accordance with some embodiments.

[0019] Fig. 20 Shown is a graph comparing the performance of various memory devices in accordance with some embodiments.

[0020] Fig.21 An example flow chart of a method for operating a memory device including a memory controller configured to adjust the timing of a falling edge of an internal clock signal is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] Static random access memory (SRAM) is a volatile semiconductor memory that uses a bistable circuit that does not require refreshing to store data bits. An SRAM cell may be referred to as a bit cell because it stores one bit of information represented by the logic state of two cross-coupled inverters. A memory array includes a plurality of bit cells arranged in rows and columns. Each bit cell in a memory array typically includes connections to a power supply voltage and a reference voltage. Logic signals on the bit lines control reading from and writing to the bit cells, and word lines control the connection of the bit lines to the inverters. Word lines may be coupled to the bit cells in a row of a memory array, providing different word lines for different rows.

[0024] Each consecutive bit cell along a bit line or word line has a characteristic input capacitance, and each conductor leg between bit cells (e.g., a portion of a bit line or word line) has a resistance, resulting in a signal propagation delay. Delays are longer for bit cells that are farther along the signal path (starting at the memory addressing and control signal sources, such as the outputs of address decoding gates and line drivers coupled at the edge of the memory array) than other bit cells. Delays affect the time required to access a bit cell and limit the highest frequency at which the memory can operate. For example, for a read / write operation, the time required to access an SRAM bit cell can vary depending on several factors, including the relative position of the accessed bit cell within the SRAM array. Reliable estimates of SRAM timing characteristics are important to ensure consistency of system components and high system performance.

[0025] In this regard, various techniques have been proposed to provide timing tracking functions to accurately and efficiently monitor SRAM devices. Timing tracking can determine when a nominal memory cell completes a read or write operation. For example, a tracking cell that is substantially similar to a nominal memory cell storing data is requisitioned or reused to provide a signal for controlling the timing of memory operations. Typically, the tracking cell is connected to a tracking word line and a tracking bit line. The timing of the tracking cell pulling down the voltage on the tracking bit line triggers a timing signal (sometimes referred to as a "TRIG signal"). The TRIG signal will provide the correct timing to pull down the internal clock signal (e.g., and then pull down the word line signal), thereby defining the time window for the operation (e.g., a write operation) performed on the nominal memory cell.

[0026] However, due to manufacturing variations, not all nominal memory cells are equivalent to tracking cells. To account for these variations, a delay can be added to the TRIG signal. The delay provided by the delay circuit can be predetermined. For example, the delay is typically estimated based on how much longer a slow memory cell (e.g., a memory cell formed at a slow process voltage temperature (PVT) corner of the array) may take to pull down the bit line voltage than an average memory cell. In terms of process variability, a sufficiently large delay for the slowest PVT corner typically adds unnecessary delays to the operation of the memory cell under other PVT conditions. These unnecessary delays significantly slow down memory operations. Therefore, existing timing tracking techniques or corresponding circuits for SRAM devices are not entirely satisfactory in some respects.

[0027] The present disclosure provides various embodiments of a memory device including a controller, at least one memory array, and a tracking column. In various embodiments, the memory array includes a plurality of nominal memory cells configured to store data, and the tracking column includes a plurality of tracking cells configured to provide signals for determining tracking timing. For example, at least one tracking cell can be coupled to a pair of tracking bit lines and tracking word lines. One of the tracking bit lines (sometimes referred to as "TRKBL") can be precharged to a voltage level corresponding to a logic 1 (e.g., VDD), and the other (sometimes also referred to as "TRKBLB") can be pre-discharged to a voltage level corresponding to a logic 0 (e.g., VSS). At least one tracking cell can be controlled (e.g., activated or deactivated) by a tracking word line (sometimes referred to as "TRKWL"). Such tracking bit lines (TRKBL and TRKBLB) and tracking word lines (TRKWL) have substantially the same RC effect as the nominal bit lines and word lines formed within the memory array. Therefore, the operation timing of the nominal memory cells (whether formed at a fast corner or a slow corner) coupled to the corresponding nominal bit lines and word lines can still be accurately tracked or otherwise captured. In other words, a delay circuit with a pre-estimated delay is not required to provide the timing tracking technique.

[0028] In various aspects of the present disclosure, a controller can provide a tracking technique by first pulling up a voltage (TRKWL signal) present on a tracking word line that closely follows the voltage present on a nominal word line. In some embodiments, the TRKWL signal can be asserted (e.g., pulled up) based on a rising edge of an internal clock (ICLK) signal. In some other embodiments, the TRKWL signal can be asserted (e.g., pulled up) based on a falling edge of a voltage (TRKBL signal) present on a precharged tracking bit line. The pulled-up TRKWL signal can activate the tracking unit. Next, the controller can identify a rising edge of a voltage (TRKBLB signal) present on a pre-discharged tracking bit line. In various embodiments, the controller can generate a trigger (TRIG) signal that closely follows the TRKBLB signal. When the TRIG signal transitions to a logic 1 (asserted or pulled up), the controller can determine to negate (e.g., pull down) the ICLK signal, which results in stopping the operation (e.g., write operation) performed on the nominal bit cell. Thus, as disclosed herein, the controller does not rely on a delay circuit with a pre-estimated delay to determine when to negate (eg, pull down) the internal clock signal. Thus, power waste can be significantly reduced, especially for those nominally slower memory cells.

[0029] In some other embodiments of the present disclosure, the direction of transition of the various signals described above may be reversed by adding an odd number of reverse logic gates (e.g., inverters) or utilizing transistors of opposite conductivity types. That is, when a signal is asserted, the signal may transition to a logic 0. Similarly, when a signal is negated, the signal may transition to a logic 1. Purely for the sake of clarity, the following discussion will be directed to asserting a signal by pulling up its logic state, and negating a signal by pulling down its logic state.

[0030] Figure 1 1 is a block diagram of a memory device 100 according to various embodiments. For illustration purposes, Figure 1 The memory device 100 shown in FIG. 1 is simplified, and thus, it should be understood that the memory device 100 may include any of a variety of other components while still being within the scope of the present disclosure.

[0031] As shown, the memory device 100 includes a memory controller 105 and a memory array 120. The memory array 120 may include a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). The memory controller 105 may write data to or read data from the memory array 120 based on electrical signals through the word lines WL and the bit lines BL. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the WL signal conducted through the corresponding asserted word line WL based on the timing of the voltage level discharged through the tracking cell, which will be discussed in further detail below. In other embodiments, the memory device 100 includes a plurality of storage circuits or memory cells 125 arranged in a two-dimensional or three-dimensional array. Each memory cell 125 may be coupled to one or more corresponding word lines (WL) and one or more corresponding bit lines (BL). The memory controller 105 may write data to or read data from the memory array 120 based on electrical signals through the word lines WL and the bit lines BL. In addition, according to various embodiments of the present disclosure, the memory controller 105 may adjust the pulse width of the WL signal conducted through the corresponding asserted word line WL based on the timing of the voltage level discharged through the tracking cell, which will be discussed in further detail below. Figure 1 More, fewer or different components may be shown.

[0032] The memory array 120 is a hardware component that stores data. In one aspect, the memory array 120 includes a plurality of storage circuits or memory cells 125. The memory array 120 includes word lines WL0 . . . WL J and bit lines BL0…BL K , each word line extends in a first direction (e.g., X direction), and each bit line extends in a second direction (e.g., Y direction). In some embodiments, the memory array 120 may be referred to as having a plurality of columns and a plurality of rows, wherein each column corresponds to a corresponding one of the bit lines BL, and each row corresponds to a corresponding one of the word lines WL. That is, the memory array 120 may include K columns and J rows of memory cells 125. The word lines WL and the bit lines BL may be conductive metals or conductive rails. Each memory cell 125 is coupled to a corresponding word line WL and a corresponding bit line BL, and may be operated according to a voltage or current passing through the corresponding word line WL and the corresponding bit line BL.

[0033] In some embodiments, each bit line includes a bit line BL and a BLB, which is coupled to one or more memory cells 125 in a group of memory cells 125 arranged along a second direction (e.g., a Y direction). The bit lines BL and BLB may receive and / or provide a differential signal. Each memory cell 125 may include a volatile memory, a non-volatile memory, or a combination thereof. In some embodiments, each memory cell 125 is implemented as a static random access memory (SRAM) cell or other type of memory cell. In some embodiments, the memory array 120 includes additional lines (e.g., a select line, a reference line, a reference control line, a power rail, etc.).

[0034] For example, the memory cell 125 can be implemented as a six-transistor (6T) static random access memory (SRAM) cell consisting of six transistors. Typically, the nominal memory cell 125 includes a pair of access transistors or pass-gate transistors PG1 and PG2 biased by (e.g., gated by) a corresponding word line WL. The pass-gate transistors PG1 and PG2 provide access to the first and second cross-coupled inverters, respectively. When the WL signal fed into the gate terminals of the pass-gate transistors PG1 and PG2 becomes true, the pass-gate transistors PG1 and PG2 can pass the bit line signal to the internal nodes of the cross-coupled inverters. The first inverter includes a pull-up (e.g., PMOS) transistor PU1 and a pull-down (e.g., NMOS) transistor PD1, and the second inverter includes a pull-up (e.g., PMOS) transistor PU2 and a pull-down (e.g., NMOS) transistor PD2. The pass-gate transistors PG1 and PG2 are coupled to a first bit line BL ("bit line") and a second bit line BLB ("inverted bit line" or bit line complement), respectively. This configuration is called a 6T (six-transistor) configuration.

[0035] During standby mode, WL is not asserted, so pass-gate transistors PG1 and PG2 disconnect memory cell 125 from the bit lines, BL and BLB. The cross-coupled inverters are coupled between power supplies (VDD and VSS) and reinforce each other to maintain one of two possible logic states, where one stored data bit is located at an internal node between the inverters (sometimes referred to as node Q or node BL_IN) and the complement of that bit is stored at another node between the inverters (sometimes referred to as node QB or node BLB_IN). During a read operation, BL and BLB are precharged to a high logic state (e.g., logic 1) and WL is asserted. The data bit stored at node Q is transferred to BL and the data bit at node QB is also transferred to BLB. During a write operation, when WL is asserted, the value to be written is provided at BL and the complement of that value is provided at BLB. Although a 6T SRAM cell is described herein as an example implementation of the memory cell 125, it should be understood that the memory cell 125 can be implemented as other types of memory cells, including memory types other than SRAM and other types of SRAM configurations other than 6T (e.g., eight-transistor (8T) or ten-transistor (10T) configurations), while still within the scope of the present disclosure.

[0036] In addition to memory cells 125 configured to store data (sometimes referred to as nominal memory cells 125), memory device 100 may also include one or more tracking columns 130 disposed adjacent to or integrated into memory array 120. For example, in Figure 1 , the tracking column 130 may be arranged along the memory array 120 and the bit lines BL0 to BL K The tracking columns 130 are arranged at one of the edges extending parallel to each other. The tracking columns 130 may each include a plurality of tracking cells 135, and optionally a plurality of dummy cells 140. In addition, in some embodiments, the tracking columns 130 may include two types of tracking cells 135, one configured to track a read operation performed on a nominal memory cell (sometimes referred to as a read tracking cell), and the other configured to track a write operation performed on the nominal memory cell (sometimes referred to as a write tracking cell). The tracking cells 135 and the dummy cells 140 may be configured in any corresponding number while still being within the scope of the present disclosure. In some embodiments, the total number of tracking cells 135 and dummy cells 140 may be equal to the number of rows (J). For example, the number of tracking cells 135 may be selected to mimic a worst-case scenario in a write and / or read operation.

[0037] In some embodiments, the tracking column 130 may also include one or more tracking word lines 145 and one or more tracking bit lines 150. Depending on the different (write and read) types of the tracking cells 135, the tracking column 130 may also include two types of tracking word lines, such as a write tracking word line and a read tracking word line. The write tracking cell may be coupled to (or activated by) the write tracking word line, and the read tracking cell may be connected to (or activated by) the read tracking word line. Typically, each tracking cell 135 may be operably coupled to a corresponding tracking word line 145 and operably connected to one or more corresponding tracking bit lines 150. However, each dummy cell 140 may not be operably coupled to any tracking word line 145, but may be operably connected to at least one corresponding tracking bit line 150.

[0038] For example, the tracking column 130 may include one tracking word line (TRKWL) operably coupled to the write tracking cell 135, one tracking bit line (TRKBL) operably coupled to the write tracking cell 135, and one tracking inversion bit line (TRKBLB) operably coupled to the write tracking cell 135. In another example, the tracking column 130 may include one tracking word line (TRKWL) operably coupled to the write tracking cell 135 but not coupled to the dummy cell 140, one tracking bit line (TRKBL) operably coupled to the write tracking cell 135 and also coupled to the dummy cell 140, and one tracking inversion bit line (TRKBLB) operably coupled to the write tracking cell 135 but not coupled to the dummy cell 140. In another example, the tracking column 130 may include a write tracking word line (WTRKWL) operably coupled to the write tracking cell 135, a read tracking word line (RTRKWL) operably coupled to the read tracking cell 135, a tracking bit line (TRKBL) operably coupled to the write tracking cell and the read tracking cell, and a tracking inverted bit line (TRKBLB) operably coupled to the write tracking cell 135 but not to the read tracking cell 135. The tracking word line 145 and the tracking bit line 150 are configured to conduct corresponding tracking signals (e.g., TRKBL signal, TRKBLB signal, TRKWL / WTRKWL signal, RTRKWL signal, etc.), which will be discussed in further detail below. By conducting the tracking signals, the tracking word line 145 and the tracking bit line 150 can respectively emulate signal routing delays in a functional memory array (e.g., 120) for read or write operations at a far edge.

[0039] For example, tracking word line 145 may include a (eg, horizontal) portion extending along a row (not explicitly shown) of memory array 120, and Figure 1140. The length of the vertical portion of the tracking word line 145 can be approximately equal to the height of the memory array (e.g., according to Figure 1 The length of the horizontal portion of the tracking word line 145 can be approximately equal to the width of the memory array 120 (e.g., according to Figure 1 Thus, tracking the sum of the lengths of the first and second portions of word line 145 can cause metal routing delays for accessing a cell at the upper right corner of memory array 120 to be emulated, for example, delays propagating horizontally and vertically from a signal entry at the lower left corner across a path distance equal to the path length from one corner to the diagonally opposite corner.

[0040] Generally speaking, the tracking cells 135 function differently than the (nominal) memory cells 125 in terms of storing data and supporting read / write operations. Rather, the tracking cells 135 may initially be a subset of the nominal memory cells 125, but may be requisitioned or repurposed for timing tracking. For example, the tracking cells 135 are bit cells having fixed logic values ​​that are configured and coupled to each other so as to respond in a predictable manner when addressed by a test or tracking signal. Figure 11-Figure 18 Some non-limiting implementations of tracking cells 135 are discussed. The dummy cells 140 enable the capacitive and resistive environments to be closely matched so as to accurately model the environment of the nominal memory cell. The bit line being tracked typically has two factors that determine the propagation delay of the transmitted signal, namely, series resistance and shunt capacitance. The dummy cells 140 have a true capacitive load and mimic the capacitance of the bit line BL coupled to the nominal memory cell. If the dummy cells 140 are not provided, the length of the tracking bit lines will effectively appear shorter than the nominal bit lines BL that they are meant to mimic, which will reduce the resistance and capacitance and may cause the tracking circuit to determine that a read or write operation has ended prematurely.

[0041] The memory controller 105 is a hardware component configured to control various operations of the memory array 120, such as reading data bits from the memory cells 125, writing data bits to the memory cells 125, performing tracking schemes on various timings of read / write operations, adjusting the tracking timings of read / write operations, etc. In various embodiments, the memory controller 105 may include a plurality of circuits, each of which may be implemented as a logic circuit, an analog circuit, or a combination thereof, to perform these operations.

[0042] As a representative example, the memory controller 105 may include a clock generator, a precharger, a TRKWL generator, and a buffer. In some embodiments, the clock generator may receive a clock (CLK) signal and provide an internal clock (ICLK) signal having a rising edge based on the CLK signal. The rising edge is configured to be used for the write driver (upon receiving a write enable signal) to perform a write operation on a nominal memory cell, for the precharger to stop precharging the TRKBL coupled to the write tracking unit, and for the TRKWL generator to pull up the TRKWL signal. In response to the TRKWL signal transitioning to logic 1, at least one corresponding write tracking unit may be activated, causing the TRKBL signal (e.g., the voltage present on TRKBL) to be pulled down and the TRKBLB signal (e.g., the voltage present on TRKBLB) to be pulled up, respectively. The memory controller 105 may provide a trigger (TRIG) signal to the clock generator through a buffer, wherein the TRIG signal may follow the TRKBLB signal. When the TRIG signal is pulled up, the clock generator may pull down the ICLK signal, which may cause the write operation (performed by the write driver) to stop accordingly. For example, the falling edge of the ICLK signal can cause the WL signal applied to the WL operatively coupled to the nominal memory cell to be pulled down. In other words, the pulse width of the WL signal can be adjusted according to the TRIG signal (or TRKBLB signal). Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 Various implementations of memory controller 105 are discussed in more detail.

[0043] In some embodiments, the memory device 100 may also include various other circuit components, such as a write (or WL) driver / controller 160, an input / output (I / O) circuit 170, etc., each of which may be embodied as a logic circuit, an analog circuit, or a combination thereof. The write driver 160 may provide a voltage or current conducted through one or more word lines WL of the memory array 120. Such a voltage / current may sometimes be referred to as a WL signal. The memory controller 105 may use an adjusted ICLK signal to adjust the pulse width of the WL signal (as described above). The I / O circuit 170 may sense a voltage or current conducted through one or more bit lines BL of the memory array 120. For example, the I / O circuit 170 may include a plurality of sense amplifiers, each of which may be operably coupled to one or more bit lines BL within the memory array 120.

[0044] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig. 9 The memory controller 105 ( Figure 1 ) are block diagrams of various embodiments 200, 300, 400, 500, 600, 700, 800 and 900. Hereinafter, the embodiments 200, 300, 400, 500, 600, 700, 800 and 900 are respectively referred to as "controller 200", "controller 300", "controller 400", "controller 500", "controller 600", "controller 700", "controller 800" and "controller 900".

[0045] As a brief overview, during an operation (e.g., a write operation or a read operation) performed on a nominal memory cell, the disclosed memory controller (e.g., one of the controllers 200 to 900) can adjust the timing to pull down the internal clock (ICLK) signal (i.e., the timing of the falling edge of the ICLK signal) based on a trigger (TRIG) signal immediately following a signal present on TRKBLB (TRKBLB signal) or a signal present on TRKBL (TRKBL signal). By adjusting the timing of the falling edge of the ICLK signal, the write / read operation can be performed more efficiently.

[0046] First reference Figure 2 , the controller 200 includes a clock generator 210, a precharger 220, a TRKWL generator 230 and a buffer 240. In addition, a write driver 250 ( Figure 1 A portion of the write driver 160 in the embodiment of the present invention) and the write tracking unit 260 ( Figure 1 A portion of the tracking unit 135 of the embodiment of the present invention is operably coupled to the controller 200. It should be understood that for the purpose of illustration, Figure 2 The block diagram has been simplified, and the controller 200 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 200 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0047] The clock generator 210 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 250 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as logic 1 or logic 0, logic 1 is configured to perform a write operation on a nominal memory cell, and logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 250 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 220 includes an input terminal configured to receive an ICLK signal and is further coupled to TRKBL. The write tracking unit 260 is coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, before performing any operation on the nominal memory cell, the precharger 220 can precharge the TRKBL signal to logic 1 (and the TRKBLB signal can be pre-discharged to logic 0). In some embodiments, the precharger 220 may stop precharging after recognizing a rising edge of the ICLK signal.

[0048] TRKWL generator 230 may provide a signal (TRKWL signal) conducted through TRKWL based on the ICLK signal. For example, TRKWL generator 230 may pull up the TRKWL signal after identifying a rising edge of the ICLK signal. Once the TRKWL signal is pulled up to a logic 1 or substantially high voltage level, write tracking unit 260 may be activated. After being activated, write tracking unit 260 may simulate a write operation performed on a nominal memory cell. In some embodiments, similar to a nominal memory cell being programmed (or written), the activated write tracking unit 260 may cause a precharge TRKBL signal and a predischarge TRKBLB signal, which respectively simulate signals conducted through a bit line BL and an inverted bit line BLB of a nominal memory cell, to fall and rise, respectively.

[0049] In some embodiments, the buffer 240 may couple TRKBLB to one of the inputs of the clock generator 210 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 210), the clock generator 210 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by the write driver 250 and configured to assert the nominal memory cell may be pulled down following the pull-down of the TRKBLB signal. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0050] Next reference Figure 3 , the controller 300 includes a clock generator 310, a precharger 320, a TRKWL generator 330 and a buffer 340. In addition, a write driver 350 ( Figure 1 A portion of the write driver 160 in the embodiment of the present invention) and the write tracking unit 360 ( Figure 1 135) is operably coupled to a controller 300. The controller 300 is substantially similar to the controller 200, except that a TRKWL generator 330 is operably coupled to the TRKBL. It should be understood that for purposes of illustration, Figure 3 The block diagram has been simplified, and the controller 300 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 300 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0051] The clock generator 310 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 350 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as logic 1 or logic 0, logic 1 is configured to perform a write operation on a nominal memory cell, and logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 350 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 320 includes an input terminal configured to receive an ICLK signal and is further coupled to TRKBL. The write tracking unit 360 is coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, before performing any operation on the nominal memory cell, the precharger 320 can precharge the TRKBL signal to logic 1 (and the TRKBLB signal can be pre-discharged to logic 0). In some embodiments, the precharger 320 may stop precharging the TRKBL signal after recognizing the rising edge of the ICLK signal.

[0052] The TRKWL generator 330 may provide a signal (TRKWL signal) conducted through the TRKWL based on the TRKBL signal. For example, after identifying a falling edge of the TRKBL signal, the TRKWL generator 330 may pull up the TRKWL signal. Once the TRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 360 may be activated. After being activated, the activated write tracking unit 360 may simulate a write operation performed on a nominal memory cell. In some embodiments, similar to a nominal memory cell being programmed (or written), the activated write tracking unit 360 may cause a precharge TRKBL signal and a predischarge TRKBLB signal, which respectively simulate signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively.

[0053] In some embodiments, the buffer 340 may couple TRKBLB to one of the inputs of the clock generator 310 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 310), the clock generator 310 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by the write driver 350 and configured to assert the nominal memory cell may be pulled down following the pull-down of the TRKBLB signal. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0054] Next reference Figure 4 , the controller 400 includes a clock generator 410, a precharger 420, a TRKWL generator 430 and a buffer 440. In addition, a write driver 450 ( Figure 1 A portion of the write driver 160) and a plurality of write tracking units 460 ( Figure 1 The controller 400 is substantially similar to the controller 200, except that the controller 400 is operably coupled to a plurality of write tracking units. It should be understood that for purposes of illustration, Figure 4 The block diagram has been simplified, and the controller 400 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 400 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0055] The clock generator 410 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 450 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as logic 1 or logic 0, logic 1 is configured to perform a write operation on a nominal memory cell, and logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 450 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 420 includes an input terminal configured to receive an ICLK signal and is further coupled to TRKBL. The write tracking unit 460 is each coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, before performing any operation on the nominal memory cell, the precharger 420 can precharge the TRKBL signal to logic 1 (and the TRKBLB signal can be pre-discharged to logic 0). In some embodiments, the precharger 420 may stop precharging the TRKBL signal after recognizing the rising edge of the ICLK signal.

[0056] The TRKWL generator 430 may provide a signal (TRKWL signal) conducted through TRKWL based on the ICLK signal. For example, after identifying a rising edge of the ICLK signal, the TRKWL generator 430 may pull up the TRKWL signal. Once the TRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 460 may be activated. After being activated, the activated write tracking unit 460 may simulate a write operation performed on a nominal memory cell. In some embodiments, similar to a nominal memory cell being programmed (or written), the activated write tracking unit 460 may cause a precharge TRKBL signal and a pre-discharge TRKBLB signal, which respectively simulate signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to drop and rise, respectively. According to some embodiments, the number of write tracking units 460 is inversely proportional to the local variation of the tracking unit. For example, the local variation of the tracking unit may be reduced. times, where N represents the number of write tracking units 460.

[0057] In some embodiments, buffer 440 may couple TRKBLB to one of the inputs of clock generator 410 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by clock generator 410), clock generator 410 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by write driver 450 and configured to assert the nominal memory cell may be pulled down immediately following the TRKBLB signal being pulled down. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0058] Next reference Figure 5 , the controller 500 includes a clock generator 510, a precharger 520, a TRKWL generator 530 and a buffer 540. In addition, a write driver 550 ( Figure 1 A portion of the write driver 160), a plurality of write tracking units 560 ( Figure 1 of the tracking unit 135) and one or more pseudo units 570 ( Figure 1 The controller 500 is substantially similar to the controller 400, except that the controller 500 is also operably coupled to a plurality of dummy units. It should be understood that for purposes of illustration, Figure 5 The block diagram has been simplified, and the controller 500 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 500 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0059] The clock generator 510 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 550 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as logic 1 or logic 0, logic 1 is configured to perform a write operation on a nominal memory cell, and logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 550 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 520 includes an input terminal configured to receive an ICLK signal and is further coupled to TRKBL. The write tracking unit 560 is each coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, before performing any operation on the nominal memory cell, the precharger 520 can precharge the TRKBL signal to logic 1 (and the TRKBLB signal can be pre-discharged to logic 0). In some embodiments, the precharger 520 may stop precharging the TRKBL signal after recognizing a rising edge of the ICLK signal.

[0060] The TRKWL generator 530 can provide a signal (TRKWL signal) conducted through TRKWL based on the ICLK signal. For example, after identifying the rising edge of the ICLK signal, the TRKWL generator 530 can pull up the TRKWL signal. Once the TRKWL signal is pulled up to a logic 1 or a substantially high voltage level, the write tracking unit 560 can be activated. After being activated, the activated write tracking unit 560 can simulate a write operation performed on a nominal memory cell. In some embodiments, similar to the nominal memory cell being programmed (or written), the activated write tracking unit 560 can cause the pre-charge TRKBL signal and the pre-discharge TRKBLB signal, which respectively simulate the signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively. According to some embodiments, the number of write tracking units 560 is inversely proportional to the local variation of the tracking unit. For example, the local variation of the tracking unit can be reduced. times, where N represents the number of write tracking cells 560. Unlike the write tracking cells 560, the dummy cells 570 may not be coupled to TRKWL. For example, the corresponding gate terminals of the access (or transmission gate) transistors of the write tracking cells 560 are connected to TRKWL, while the corresponding gate terminals of the access (or transmission gate) transistors of the dummy cells 570 are connected to ground (e.g., VSS).

[0061] In some embodiments, the buffer 540 may couple TRKBLB to one of the inputs of the clock generator 510 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 510), the clock generator 510 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write or read operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by the write driver 550 and configured to assert the nominal memory cell may be pulled down immediately following the TRKBLB signal being pulled down. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0062] Next reference Figure 6 , the controller 600 includes a clock generator 610, a precharger 620, a write (WTRKWL) generator 630, a read (RTRKWL) generator 640, a multiplexer 650, and a buffer 660. In addition, a write driver 670 ( Figure 1 part of the write driver 160), one or more write tracking units 680 and one or more read tracking units 690 ( Figure 1 The controller 600 is substantially similar to the controller 200, except that the controller 600 also includes a RTRKWL generator and is also operably coupled to a plurality of read tracking units. It should be understood that for purposes of illustration, Figure 6 The block diagram has been simplified, and the controller 600 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 600 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0063] The clock generator 610 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 670 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as a logic 1 or a logic 0, where a logic 1 is configured to perform a write operation on a nominal memory cell, and a logic 0 is configured to perform a read operation on a nominal memory cell. In contrast to the WE signal logic, the controller 600 can also receive a WEB signal input to the RTRKWL generator 640. The write driver 670 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 620 includes an input terminal configured to receive an ICLK signal, and is further coupled to TRKBL. The write tracking unit 680 is each coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, the precharger 620 may precharge the TRKBL signal to logic 1 (and the TRKBLB signal may be pre-discharged to logic 0) before any operation is performed on the nominal memory cells. In some embodiments, the precharger 620 may stop precharging the TRKBL signal after recognizing the rising edge of the ICLK signal.

[0064] During a write operation performed on a nominal memory cell (e.g., the WE signal and the WEB signal are provided at logic 1 and logic 0, respectively), the WTRKWL generator 630 can provide a signal (WTRKWL signal) conducted through the write tracking word line WTRKWL based on the ICLK signal and the WE signal. For example, when the rising edge of the ICLK signal is identified and the WE signal is asserted as logic 1, the WTRKWL generator 630 can pull up the WTRKWL signal. Once the WTRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 680 can be activated. After being activated, the write tracking unit 680 can simulate a write operation performed on the nominal memory cell. In some embodiments, similar to the nominal memory cell being programmed (or written), the activated write tracking unit 680 can cause the precharge TRKBL signal and the pre-discharge TRKBLB signal, which respectively simulate the signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively.

[0065] During a read operation performed on a nominal memory cell (e.g., the WE signal and the WEB signal are provided at logic 0 and logic 1, respectively), the RTRKWL generator 640 may provide a signal (RTRKWL signal) conducted through a read tracking word line RTRKWL based on the ICLK signal and the WEB signal. For example, when a rising edge of the ICLK signal is identified and the WEB signal is asserted as logic 1, the RTRKWL generator 640 may pull up the RTRKWL signal. In other words, the WTRKWL generator 630 and the RTRKWL generator 640 may be activated alternately. Once the RTRKWL signal is pulled up to a logic 1 or substantially high voltage level, the read tracking unit 690 may be activated. After being activated, the read tracking unit 690 may simulate a read operation performed on the nominal memory cell. In some embodiments, similar to the nominal memory cell being read, the activated read tracking unit 690 may cause the precharge TRKBL signal that simulates a signal conducted through the bit line BL of the nominal memory cell to drop.

[0066] In some embodiments, the multiplexer 650 controlled by the WE signal includes two input terminals coupled to TRKBLB and TRKBL, respectively, and one output terminal coupled to the buffer 660. For example, when the WE signal is provided at a logic 1, the multiplexer 650 may select the TRKBLB signal as its output to the buffer 660; and when the WE signal is provided at a logic 0, the multiplexer 650 may select the TRKBL signal as its output to the buffer 660. In addition, TRKBL may be coupled to the input terminal of the multiplexer 650 through an inverter. The buffer 660 may couple the selected TRKBLB or TRKBL (inverted) to one of the inputs of the clock generator 610 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal or the inverted TRKBL signal.

[0067] Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 610), the clock generator 610 can pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write or read operation) performed on the nominal memory cell can be stopped. For example, the WL signal provided by the write driver 670 and configured to assert the nominal memory cell can be pulled down immediately following the transition of the TRKBLB or TRKBL signal to a different logic state. In other words, no additional delay circuit is required to adjust the timing of pulling down the WL signal. Therefore, the pulse width of the WL signal can be shortened.

[0068] Next reference Figure 7, the controller 700 includes a clock generator 710, a precharger 720, a WTRKWL generator 730, a RTRKWL generator 740, a multiplexer 750, and a buffer 760. In addition, a write driver 770 ( Figure 1 part of the write driver 160), one or more write tracking units 780 and one or more read tracking units 790 ( Figure 1 135) is operably coupled to the controller 700. The WTRKWL generator 730 is coupled to each write tracking unit 780 via the WTRKWL, and the simulated WL load 795 is coupled to the WTRKWL; the RTRKWL generator 740 is coupled to each read tracking unit 790 via the RTRKWL, and the simulated WL load 795 is coupled to the RTRKWL. The controller 700 is substantially similar to the controller 600, except that the controller 700 is further operably coupled to the simulated WL load. It should be understood that for the purpose of illustration, Figure 7 The block diagram has been simplified, and the controller 700 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure. For example, the controller 700 may include a pre-discharger configured to pre-discharge the TRKBLB before performing an operation on the corresponding nominal memory cell.

[0069] The simulated WL load 795 is configured to provide a resistance and capacitance similar to the nominal word line WL of the memory array to the write and / or RTRKWL. In some embodiments, the simulated WL load 795 includes multiple gates coupled to the read and WTRKWL. In some embodiments, the gates are arranged in parallel with a row of the memory array. In some embodiments, the gate terminals have the same pitch as the gate terminals of the access (transmission gate) transistors to which the nominal word line WL is connected. This gate arrangement is convenient in chip design, layout, and accurate simulation of WL capacitance.

[0070] The clock generator 710 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 770 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as logic 1 or logic 0, logic 1 is configured to perform a write operation on a nominal memory cell, and logic 0 is configured to perform a read operation on a nominal memory cell. In contrast to the WE signal logic, the controller 700 can also receive a WEB signal input to the RTRKWL generator 740. The write driver 770 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 720 includes an input terminal configured to receive an ICLK signal, and is further coupled to TRKBL. The write tracking unit 780 is each coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. In some embodiments, the precharger 720 may precharge the TRKBL signal to logic 1 (and the TRKBLB signal may be pre-discharged to logic 0) before any operation is performed on the nominal memory cells. In some embodiments, the precharger 720 may stop precharging the TRKBL signal after recognizing the rising edge of the ICLK signal.

[0071] During a write operation performed on a nominal memory cell (e.g., the WE signal and the WEB signal are provided at logic 1 and logic 0, respectively), the WTRKWL generator 730 can provide a signal (WTRKWL signal) conducted through the WTRKWL based on the ICLK signal and the WE signal. For example, when the rising edge of the ICLK signal is identified and the WE signal edge is asserted as logic 1, the WTRKWL generator 730 can pull up the WTRKWL signal. Once the WTRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 780 can be activated. After being activated, the write tracking unit 780 can simulate a write operation performed on the nominal memory cell. In some embodiments, similar to the nominal memory cell being programmed (or written), the activated write tracking unit 780 can cause the precharge TRKBL signal and the pre-discharge TRKBLB signal, which respectively simulate the signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively.

[0072] During a read operation performed on a nominal memory cell (e.g., the WE signal and the WEB signal are provided at logic 0 and logic 1, respectively), the RTRKWL generator 740 may provide a signal (RTRKWL signal) conducted through the RTRKWL based on the ICLK signal and the WEB information. For example, when a rising edge of the ICLK signal is identified and the WEB signal is asserted as logic 1, the RTRKWL generator 740 may pull up the RTRKWL signal. In other words, the WTRKWL generator 730 and the RTRKWL generator 740 may be activated alternately. Once the RTRKWL signal is pulled up to a logic 1 or substantially high voltage level, the read tracking unit 790 may be activated. After being activated, the read tracking unit 790 may simulate a read operation performed on the nominal memory cell. In some embodiments, similar to the nominal memory cell being read, the activated read tracking unit 790 may cause the precharge TRKBL signal that simulates a signal conducted through the bit line BL of the nominal memory cell to drop.

[0073] In some embodiments, the multiplexer 750 controlled by the WE signal includes two input terminals coupled to TRKBLB and TRKBL, respectively, and one output terminal coupled to the buffer 760. For example, when the WE signal is provided at a logic 1, the multiplexer 750 can select the TRKBLB signal as its output to the buffer 760; and when the WE signal is provided at a logic 0, the multiplexer 750 can select the TRKBL signal as its output to the buffer 760. In addition, TRKBL can be coupled to the input terminal of the multiplexer 750 through an inverter. The buffer 760 can couple the selected TRKBLB or TRKBL (inverted) to one of the inputs of the clock generator 710 that receives the TRIG signal. In other words, the TRIG signal can follow the TRKBLB signal or the inverted TRKBL signal.

[0074] Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 710), the clock generator 710 can pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write or read operation) performed on the nominal memory cell can be stopped. For example, the WL signal provided by the write driver 770 and configured to assert the nominal memory cell can be pulled down immediately following the transition of the TRKBLB or TRKBL signal to a different logic state. In other words, no additional delay circuit is required to adjust the timing of pulling down the WL signal. Therefore, the pulse width of the WL signal can be shortened.

[0075] Next reference Figure 8, the controller 800 includes a clock generator 810, a precharger 820, a predischarger 830, a TRKWL generator 840 and a buffer 850. In addition, a write driver 860 ( Figure 1 A portion of the write driver 160), a plurality of write tracking units 870 ( Figure 1 of the tracking unit 135) and one or more pseudo units 880 ( Figure 1 A portion of the dummy unit 140 of FIG. 1 is operably coupled to the controller 800. The TRKWL generator 840 is coupled to each write tracking unit 870 via the TRKWL, and the simulated WL load 895 is coupled to the TRKWL. It should be understood that for the purpose of illustration, Figure 8 The block diagram has been simplified, and the controller 800 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure.

[0076] The clock generator 810 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 860 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as a logic 1 or a logic 0, where a logic 1 is configured to perform a write operation on a nominal memory cell, and a logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 860 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal. The precharger 820 includes an input terminal configured to receive an ICLK signal, and is further coupled to TRKBL. The write tracking unit 870 is each coupled between TRKBL and TRKBLB, and the voltage present on TRKBLB is sometimes referred to as a TRKBLB signal. The pre-discharger 830 includes an input terminal configured to receive an ICLK signal, and is also coupled to TRKBLB. In some embodiments, the precharger 820 may precharge the TRKBL signal to logic 1, respectively, and the predischarger 830 may predischarge the TRKBLB signal to logic 0, respectively, before performing any operation on the nominal memory cell. In some embodiments, after recognizing the rising edge of the ICLK signal, the precharger 820 may stop precharging the TRKBL signal, respectively, and the predischarger 830 may stop predischarging the TRKBLB signal.

[0077] The TRKWL generator 840 may provide a signal (TRKWL signal) conducted through TRKWL based on the ICLK signal. For example, after identifying a rising edge of the ICLK signal, the TRKWL generator 840 may pull up the TRKWL signal. Once the TRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 870 may be activated. After being activated, the activated write tracking unit 870 may simulate a write operation performed on a nominal memory cell. In some embodiments, similar to a nominal memory cell being programmed (or written), the activated write tracking unit 870 may cause a precharge TRKBL signal and a predischarge TRKBLB signal, which respectively simulate signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively.

[0078] According to some embodiments, the number of writes to the tracking unit 870 is inversely proportional to the local variation of the tracking unit. For example, the local variation of the tracking unit can be reduced times, where N represents the number of write tracking cells 870. Unlike the write tracking cells 870, the dummy cells 880 may not be coupled to TRKWL. For example, each gate terminal of the access (or transfer gate) transistor of the write tracking cells 870 is connected to TRKWL, while each gate terminal of the access (or transfer gate) transistor of the dummy cells 880 is connected to ground (e.g., VSS).

[0079] In some embodiments, the buffer 850 may couple TRKBLB to one of the inputs of the clock generator 810 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 810), the clock generator 810 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write or read operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by the write driver 860 and configured to assert the nominal memory cell may be pulled down immediately following the TRKBLB signal being pulled down. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0080] Next reference Fig. 9 , the controller 900 includes a clock generator 910, a precharger 920, a pre-discharger 930, a TRKPCE driver 935, a TRKWL generator 940 and a buffer 950. In addition, a write driver 960 ( Figure 1 A portion of the write driver 160), a plurality of write tracking units 970 ( Figure 1 of the tracking unit 135) and one or more pseudo units 980 ( Figure 1 A portion of the dummy unit 140 of FIG. 1 is operably coupled to the controller 900. The TRKWL generator 940 is coupled to each write tracking unit 970 via the TRKWL, and the simulated WL load 995 is coupled to the TRKWL. It should be understood that for the purpose of illustration, Fig. 9 The block diagram has been simplified, and the controller 900 (or memory device 100) may include any of a variety of other components while still within the scope of the present disclosure.

[0081] The clock generator 910 includes two input terminals configured to receive a clock (CLK) signal and a trigger (TRIG) signal, respectively, and an output terminal providing an internal clock (ICLK) signal. The write driver 960 includes two input terminals configured to receive an ICLK signal and a write enable (WE) signal, respectively. The WE signal can be asserted as a logic 1 or a logic 0, where a logic 1 is configured to perform a write operation on a nominal memory cell and a logic 0 is configured to perform a read operation on a nominal memory cell. The write driver 960 can also be coupled to (e.g., controlled by) a voltage present on TRKBL, which is sometimes referred to as a TRKBL signal.

[0082] The write tracking units 970 are each coupled between TRKBL and TRKBLB, and are also coupled to TRKPCE, where the voltages present on TRKBLB and TRKPCE are sometimes referred to as TRKBLB signals and TRKPEC signals, respectively. The precharger 920 includes an input terminal configured to receive an ICLK signal and is further coupled to TRKBL. The pre-discharger 930 includes an input terminal configured to receive an ICLK signal and is further connected to TRKBLB. The TRKPCE driver 935 includes an input terminal for receiving an ICLK signal and is further connected to TRKPCE. Before any operation is performed on the nominal memory cell, the precharger 920 can precharge the TRKBL signal to logic 1, respectively, and the pre-discharger 930 can pre-discharge the TRKBLB signal to logic 0. In some embodiments, after identifying the rising edge of the ICLK signal, the precharger 920 can stop precharging the TRKBL signal, respectively, and the pre-discharger 930 can stop pre-discharging the TRKBLB signal. The TRKPCE driver 935 may pull up the TRKPCE signal after recognizing a rising edge of the ICLK signal.

[0083] As will be Figure 17-Figure 18As discussed in , TRKPCE can be connected to the respective gate terminals of the pull-up transistor and the pull-down transistor of at least one write tracking cell 970, which allows the TRKPCE driver 935 or the TRKPCE signal to mimic contention between the pull-up transistor and the pull-down transistor of a nominal memory cell. Such contention can even be distinguishable when the nominal memory cell is a weak or weakened memory cell (e.g., a memory cell having lower or degraded threshold voltage (Vth) pull-down and pull-up transistors and / or a pass gate transistor having a higher Vth compared to other normal nominal memory cells).

[0084] The TRKWL generator 940 may provide a signal (TRKWL signal) conducted through the TRKWL based on the ICLK signal. For example, after identifying a rising edge of the ICLK signal, the TRKWL generator 940 may pull up the TRKWL signal. Once the TRKWL signal is pulled up to a logic 1 or substantially high voltage level, the write tracking unit 970 may be activated. After being activated, the write tracking unit 970 may simulate a write operation performed on a nominal memory cell. In some embodiments, similar to a nominal memory cell being programmed (or written), the activated write tracking unit 970 may cause a precharge TRKBL signal and a predischarge TRKBLB signal, which respectively simulate signals conducted through the bit line BL and the inverted bit line BLB of the nominal memory cell, to fall and rise, respectively.

[0085] According to some embodiments, the number of writes to tracking cells 970 is inversely proportional to the local variation of the tracking cells. For example, the local variation of the tracking cells can be reduced times, where N represents the number of write tracking cells 970. Unlike the write tracking cells 970, the dummy cells 980 may not be coupled to TRKWL. For example, respective gate terminals of the access (or transfer gate) transistors of the write tracking cells 970 are connected to TRKWL, while respective gate terminals of the access (or transfer gate) transistors of the dummy cells 980 are connected to ground (e.g., VSS).

[0086] In some embodiments, the buffer 950 may couple TRKBLB to one of the inputs of the clock generator 910 that receives the TRIG signal. In other words, the TRIG signal may follow the TRKBLB signal. Once the falling edge of the TRIG signal is detected (e.g., detected by the clock generator 910), the clock generator 910 may pull down the ICLK signal. As the ICLK signal is pulled down (e.g., to logic 0), the ongoing operation (e.g., write or read operation) performed on the nominal memory cell may be stopped. For example, a WL signal provided by the write driver 960 and configured to assert the nominal memory cell may be pulled down immediately following the TRKBLB signal being pulled down. In other words, no additional delay circuit is required to adjust the timing of the pull-down WL signal. Therefore, the pulse width of the WL signal may be shortened.

[0087] Fig.10 1 shows example waveforms of various signals, WE signal, CLK signal, ICLK signal, TRKBL signal, TRKWL signal, TRKBLB signal, TRIG signal, and voltages respectively present on the nominal WL and nominal BL of the asserted nominal memory cell 125, that vary during certain time periods when the disclosed memory controller 105 operates according to some embodiments. For example, Fig.10 The waveform shown can correspond to Figure 3 It should be understood that providing Fig.10 The waveforms are intended to illustrate the relative transitions between the signals, and therefore, the respective scales of the signals may vary within the scope of the present disclosure.

[0088] As shown, the signals may vary over six time periods that may collectively correspond to write operations performed on the asserted nominal memory cell 125. During (or at the beginning of) a first time period, the WE signal is provided to transition from a logic 0 to a logic 1, which allows the asserted nominal memory cell 125 to be programmed. At approximately the same time that the WE signal is pulled up, the CLK signal is pulled up from a logic 0 to a logic 1. During (or at the beginning of) a second time period, the clock generator 310 recognizes the rising edge of the CLK signal, thereby pulling up the ICLK signal, as indicated by arrow 1010. In some embodiments, during the first and second time periods (e.g., before actually programming the asserted nominal memory cell 125), the TRKBL signal and the TRBLB signal remain at a logic 1 and a logic 0, respectively, as shown. Fig.10 shown.

[0089] During (or at the beginning of) the third time period, the precharger 320 recognizes the rising edge of the ICLK signal and thereby stops maintaining the voltage level present on TRKBL, causing the TRKBL signal to fall, as indicated by arrow 1020. At approximately the same time that the TRKBL signal begins to fall, the voltage level on nominal BL falls. In other words, the TRKBL signal tracks the timing of the voltage level present on nominal BL. During (or at the beginning of) the fourth time period, the TRKWL generator 330 recognizes the falling edge of the TRKBL signal and thereby pulls up the TRKWL signal, as indicated by arrow 1030. At approximately the same time that the TRKWL signal begins to rise, the voltage level on nominal WL rises. In other words, the TRKWL signal tracks the timing of the voltage level present on nominal WL. In some embodiments, when the voltage level on nominal WL is pulled up, the pass gate transistor of the asserted nominal memory cell 125 is activated or turned on, which allows the asserted nominal memory cell 125 to be programmed. At the same time, the write tracking unit 360 is also activated or turned on (via the TRKWL signal being pulled up). As a result, the TRKBLB signal may begin to rise.

[0090] For example, during (or at the beginning of) the fifth time period, the TRKBLB signal is pulled up to logic 1, as indicated by arrow 1040. In some embodiments, the TRIG signal follows the TRKBLB signal. Upon recognizing that the TRKBLB / TRIG signal transitions to logic 1, the clock generator 310 may pull down the ICLK signal, as indicated by arrow 1050. During (or at the beginning of) the sixth time period, upon recognizing that the ICLK signal transitions back to logic 0, the write driver 350 may pull down the voltage level present on the nominal WL (also pulling down the TRKWL signal), as indicated by arrow 1060. Thus, programming access to the nominal memory cell 125 may be terminated, and the write tracking unit 360 may also be disabled or turned off. In some embodiments, TRKBL may be recharged to logic 1 (i.e., without waiting for the TRKWL signal to transition back to logic 0), as indicated by arrow 1060. Fig.10 shown.

[0091] Fig.11 An example circuit diagram of some components of the memory device 100 is shown according to some embodiments. Fig.11 The circuit diagram includes a write tracking unit 135 ( Figure 1 ), write driver 160 ( Figure 1 ) and a portion of the controller 105. For example, Fig.11 The circuit diagram can correspond to Figure 3 The controller 300, and the write tracking unit 360 and the write driver 350 operatively coupled thereto. It should be understood that Fig.11The circuit diagrams are provided for illustration purposes and are not necessarily intended to limit the scope of the present disclosure.

[0092] like Fig.11 As shown, the precharger 320 of the controller 300 is implemented as a PMOS transistor 1104, and the controller 300 also includes an NMOS transistor 1106 used as its pre-discharger. Based on the ICLK signal, the transistor 1104 is configured to pre-charge TRKBL, and the transistor 1106 is configured to pre-discharge TRKBLB. For example, the corresponding gate terminals of the transistor 1104 and the transistor 1106 are configured to receive the ICLK signal (from the ICLK signal) through two inverters and one inverter, respectively. Fig.11 10). The write driver 350 coupled to the controller 300 may be implemented as another NMOS transistor 1102, whose gate terminal is configured to receive the ICLK signal through two inverters. Therefore, when the ICLK signal transitions from logic 0 to logic 1, the transistor (write driver) 1102, the transistor (precharger) 1104, and the transistor (predischarger) 1106 may be turned on, off, and off, respectively, which causes the precharged TRKBL signal to fall and the predischarged TRKBLB signal to rise.

[0093] Still reference Fig.11 , an example implementation of the write tracking unit 360 is shown. The write tracking unit 360 includes NMOS transistors 1108 and 1114 and PMOS transistors 1110 and 1112. In some embodiments, transistor 1108 can emulate one of the pass gate transistors of a nominal memory cell connected to bit line BL, transistor 1110 can emulate one of the pull-up transistors in the nominal memory cell, transistor 1112 can emulate another pull-up transistor in the nominal memory cell, and transistor 1114 can emulate one of the pull-down transistors in the nominal memory cell. Transistors 1112 and 1114 can act as inverters with their inputs (BL_IN nodes) coupled to TRKBL through transistor 1108 and their outputs connected to TRKBLB. Transistor 1108 is gated by the TRKWL signal, and transistor 1110 is gated by (or coupled to) the TRKBLB signal.

[0094] Fig.12 According to some embodiments, the controller 300 (according to Fig.11 Example waveforms of various signals that change within a specific timing period when the MCU is working, the ICLK signal, the TRKBL signal, the TRKWL signal, the TRKBLB signal, the voltage level on the BL_IN node (BL_IN signal) and the TRIG signal. Fig.12 The waveform and Fig.10The waveforms shown are substantially similar, so the following discussion will focus primarily on the differences.

[0095] As shown, the rising edge of the ICLK signal causes the TRKBL signal to fall (arrow 1210), and the falling edge of TRKBL causes the TRKWL signal to rise (arrow 1220). When the TRKBL signal changes to logic 0 (or remains at logic 0) and the TRKWL signal changes to logic 1 (or remains at logic 1), the BL_IN signal may be pulled down. However, the logic low TRKBLB signal may pull up the BL_IN signal, which may cause contention between the TRKBL signal and TRKBLB. When the TRKBLB signal changes to logic 1, the ICLK signal may be pulled back to logic 0. Therefore, transistor (write driver) 1102, transistor (precharger) 1104, and transistor (pre-discharger) 1106 may be turned off, turned on, and turned on, respectively. Therefore, the current write operation may be stopped, and before the next operation, TRKBL and TRKBLB may be precharged and pre-discharged to logic 1 and logic 0, respectively, again.

[0096] Fig.13 The write tracking unit 135 ( Figure 1 ) is another example circuit diagram of one of the above. In the following, Fig.13 The circuit diagram of the write tracking unit 1300 is referred to as the write tracking unit 260 ( Figure 2 )、360( Figure 3 )、460( Figure 4 )、560( Figure 5 )、680( Figure 6 )、780( Figure 7 ) and 870( Figure 8 ) can be realized as Fig.13 The write tracking unit 1300 shown in FIG. Fig.14 shows that it can be used to manufacture Fig.13 An example layout 1400 of two write tracking units 1300 (eg, 1300-1 and 1300-2) is shown in FIG. It should be understood that Fig.13 The circuit diagram and Fig.14 The corresponding layouts shown in are provided for illustrative purposes and are not necessarily intended to limit the scope of the present disclosure.

[0097] In some embodiments, the write tracking cell 1300 is substantially similar to one of the nominal memory cells implemented in a 6T SRAM configuration. Fig.13, the write tracking unit 1300 also includes NMOS pass gate (PG) transistors 1310 and 1320, PMOS pull-up (PU) transistors 1330 and 1340, and NMOS pull-down (PD) transistors 1350 and 1360. In some embodiments, one of the PG transistors 1310 may have a gate terminal connected to TRKWL, and the other of the PG transistors 1320 may have its gate terminal connected to the nominal word line WL. In addition, the drain terminal of the PG transistor 1310 is connected to TRKBL, and the source terminal of the PG transistor 1310 is connected to the output (BL_IN node) of the first inverter formed by the pull-up transistor 1330 and the pull-down transistor 1350; the drain terminal of the PG transistor 1320 is electrically floating, and its source terminal is connected to the output (BLB_IN node) of the second inverter formed by the pull-up transistor 1340 and the pull-down transistor 1360, and is further connected to TRKBLB. An input terminal of the first inverter is connected to the BLB_IN node; an input terminal of the second inverter is connected to the BL_IN node.

[0098] Next reference Fig.14 , the layout 1400 includes patterns 1402, 1404, 1406, 1408, and 1410, respectively, configured to form active regions (sometimes referred to as oxide diffusion / definition regions), and patterns 1412, 1414, 1416, 1418, 1420, 1422, 1424, and 1426, respectively, configured to form gate terminals. Hereinafter, the patterns 1402 to 1410 are respectively referred to as active regions 1402 to 1410, and the patterns 1412 to 1426 are respectively referred to as gate terminals 1412 to 1426. In some embodiments, the active regions 1402 to 1410 may each extend along the X direction, and the gate terminals 1412 to 1426 may each extend along the Y direction. In some embodiments, the active regions 1402 to 1410 and the gate terminals 1412 to 1426 may form a plurality of (e.g., 12) transistors operably configured for two 6T SRAM cells.

[0099] For example, Fig.14 As shown, the active area 1410 and the gate terminal 1420 can form a PD transistor 1350; the active area 1410 and the gate terminal 1424 can form a PG transistor 1310; the active area 1408 and the gate terminal 1420 can form a PU transistor 1330; the active area 1402 and the gate terminal 1426 can form a PD transistor 1360; the active area 1402 and the gate terminal 1422 can form a PG transistor 1320; and the active area 1406 and the gate terminal 1426 can form a PU transistor 1340.

[0100] The layout 1400 also includes patterns 1428, 1430, 1432, 1434, 1436, 1438, 1440, 1442, 1444, 1446, 1448, 1450, and 1452, respectively, configured to form conductive source / drain connection structures (sometimes referred to as MDs). Hereinafter, the patterns 1428 to 1452 are respectively referred to as MDs 1428 to 1455. In some embodiments, each of the MDs 1428 to 1452 may extend along the Y direction, and further, each of the MDs 1428 to 1452 may overlap (e.g., be electrically coupled to) a portion of a corresponding active region, which may be operatively used as a source or drain terminal of a corresponding transistor.

[0101] For example, Fig.14 As shown, MD 1432 can be in contact with one of the source / drain terminals of PD transistor 1350, and PD transistor 1350 can be electrically coupled to a metal track carrying VSS; MD 1434 can be in contact with the other of the source / drain terminals of PD transistor 1350 and one of the source / drain terminals of PG transistor 1310; MD 1436 can be in contact with the other of the source / drain terminals of PG transistor 1310, which can be electrically coupled to a metal track used as TRKBL; MD 1442 can be in contact with one of the source / drain terminals of PU transistor 1330, which can be electrically coupled to a metal track carrying VDD; MD 1446 can be in contact with one of the source / drain terminals of PU transistor 1340, which can be electrically coupled to a metal track carrying VDD; MD 1444 can contact one of the source / drain terminals of the PD transistor 1360 and one of the source / drain terminals of the PG transistor 1320, which terminal can be configured to be electrically coupled to the BLB_IN node of the metal track used as TRKBLB; MD 1450 can contact the other of the electrically floating source / drain terminals of the PG transistor 1320; MD 1452 can contact the other of the source / drain terminals of the PD transistor 1360, which terminal can be electrically coupled to the metal track carrying VSS.

[0102] The layout 1400 also includes patterns 1460, 1462, 1464, 1466, 1468, and 1470, respectively, configured to form metal tracks disposed in the metallization layer M0. The metallization layer M0 is generally referred to as the bottommost one of a plurality of metallization layers disposed on the front side surface of the substrate where the active region and the gate terminal are formed. Hereinafter, the patterns 1460 to 1470 are respectively referred to as M0 tracks 1462 to 1470. In some embodiments, each of the M0 tracks 1462 to 1470 may extend along the X direction, and further, each of the M0 tracks 1462 to 1470 may overlap (e.g., be coupled to) one or more MDs or one or more gate terminals.

[0103] For example, Fig.14 As shown, M0 rail 1460 can be coupled to gate terminal 1424 (e.g., the gate terminal of PG transistor 1310), which can be configured as TRKWL; M0 rail 1462 can be coupled to MD 1436 (e.g., the drain terminal of PG transistor 1310), which can be configured as TRKBL; M0 rail 1464 can be coupled to MD 1442 and 1446 (e.g., the respective source terminals of PU transistors 1330 and 1340), which can be configured as part of the power rail carrying VDD; M0 rail 1466 can be coupled to MD 1444 (e.g., the source terminal of PG transistor 1320), which can be configured as TRKBLB; M0 rail 1468 can be coupled to MD 1452 (e.g., the source terminal of PD transistor 1360), which can be configured as part of a power rail carrying VSS; M0 rail 1470 can be coupled to gate terminal 1422 (e.g., the gate terminal of PG transistor 1320), which can be configured as a nominal word line WL (e.g., WL[0]).

[0104] Fig.15 The write tracking unit 135 ( Figure 1 ) is another example circuit diagram of one of the above. In the following, Fig.15 The circuit diagram of the write tracking unit 1500 is referred to as the write tracking unit 1500. For example, the write tracking unit 260 ( Figure 2 )、360( Figure 3 )、460( Figure 4 )、560( Figure 5 )、680( Figure 6 )、780( Figure 7 ) and 870( Figure 8 ) Each can be implemented as Fig.15 The write tracking unit 1500 shown in FIG. Fig.16 shows that it can be used to manufacture Fig.15An example layout of two write tracking units 1500 (eg, 1500-1 and 1500-2) is shown in FIG. It should be understood that Fig.15 The circuit diagram and Fig.16 The corresponding layouts shown in are provided for illustrative purposes and are not necessarily intended to limit the scope of the present disclosure.

[0105] In some embodiments, the write tracking cell 1500 is substantially similar to one of the nominal memory cells implemented in a 6T SRAM configuration. Fig.15 , the write tracking unit 1500 also includes NMOS pass gate (PG) transistors 1510 and 1520, PMOS pull-up (PU) transistors 1530 and 1540, and NMOS pull-down (PD) transistors 1550 and 1560. In some embodiments, one of the PG transistors 1510 may have a gate terminal connected to TRKWL, and the other of the PG transistors 1520 may have its gate terminal connected to the nominal word line WL. In addition, the drain terminal of the PG transistor 1510 is connected to TRKBL, and the source terminal of the PG transistor 1510 is connected to the output (BL_IN node) of the first inverter formed by the pull-up transistor 1530 and the pull-down transistor 1550; the drain terminal of the PG transistor 1520 is electrically floating, and its source terminal is connected to the output (BLB_IN node) of the second inverter formed by the pull-up transistor 1540 and the pull-down transistor 1560, and is further connected to TRKBLB. An input terminal of the first inverter is connected to the BLB_IN node; an input terminal of the second inverter is connected to the BL_IN node.

[0106] Next reference Fig.16 , the layout 1600 includes patterns 1602, 1604, 1606, 1608, and 1610, respectively configured to form active regions (sometimes referred to as oxide diffusion / definition regions), and patterns 1612, 1614, 1616, 1618, 1620, 1622, 1624, and 1626, respectively configured to form gate terminals. Hereinafter, the patterns 1602 to 1610 are respectively referred to as active regions 1602 to 1610, and the patterns 1612 to 1626 are respectively referred to as gate terminals 1612 to 1626. In some embodiments, the active regions 1602 to 1610 may each extend along the X direction, and the gate terminals 1612 to 1626 may each extend along the Y direction. In some embodiments, the active regions 1602 to 1610 and the gate terminals 1612 to 1626 may form a plurality of (e.g., 12) transistors operably configured for two 6T SRAM cells.

[0107] For example, Fig.16As shown, the active area 1610 and the gate terminal 1620 can form a PD transistor 1550; the active area 1610 and the gate terminal 1624 can form a PG transistor 1510; the active area 1608 and the gate terminal 1620 can form a PU transistor 1550; the active area 1602 and the gate terminal 1626 can form a PD transistor 1560; the active area 1602 and the gate terminal 1622 can form a PG transistor 1520; the active area 1606 and the gate terminal 1626 can form a PU transistor 1540.

[0108] The layout 1600 also includes patterns 1628, 1630, 1632, 1634, 1636, 1638, 1640, 1642, 1644, 1646, 1648, 1650, and 1652, respectively, configured to form conductive source / drain connection structures (sometimes referred to as MDs). Hereinafter, the patterns 1628 to 1652 are respectively referred to as MDs 1628 to 1622. In some embodiments, each of the MDs 1628 to 1652 may extend along the Y direction, and further, each of the MDs 1628 to 1652 may overlap (e.g., be electrically coupled to) a portion of a corresponding active region, which may be operatively used as a source or drain terminal of a corresponding transistor.

[0109] For example, Fig.16 As shown, MD 1632 can be in contact with one of the source / drain terminals of PD transistor 1550, which terminal can be electrically floating; MD 1634 can be in contact with the other of the source / drain terminals of PD transistor 1550 and one of the source / drain terminals of PG transistor 1510, which terminal can be configured as a BL_IN node; MD 1636 can be in contact with the other of the source / drain terminals of PG transistor 1510, which terminal can be electrically coupled to a metal track used as TRKBL; MD 1642 can be in contact with one of the source / drain terminals of PU transistor 1530, which terminal can be electrically coupled to a metal track carrying VDD; MD 1646 can be in contact with one of the source / drain terminals of PU transistor 1540, which terminal can be electrically coupled to a metal track carrying VDD; MD 1644 can contact one of the source / drain terminals of the PD transistor 1560 and one of the source / drain terminals of the PG transistor 1520, which terminal can be configured to be electrically coupled to the BLB_IN node of the metal track used as TRKBLB; MD 1650 can contact the other of the source / drain terminals of the PG transistor 1520, which terminal is electrically floating; MD 1652 can contact the other of the source / drain terminals of the PD transistor 1560, which terminal can be electrically coupled to the metal track carrying VSS.

[0110] The layout 1600 also includes patterns 1660, 1662, 1664, 1666, 1668, and 1670, respectively, configured to form metal tracks disposed in the metallization layer M0. The metallization layer M0 is generally referred to as the bottommost one of a plurality of metallization layers disposed on the front side surface of the substrate where the active region and the gate terminal are formed. Hereinafter, the patterns 1660 to 1670 are respectively referred to as M0 tracks 1662 to 1670. In some embodiments, each of the M0 tracks 1662 to 1670 may extend along the X direction, and further, each of the M0 tracks 1662 to 1670 may overlap (e.g., be coupled to) one or more MDs or one or more gate terminals.

[0111] For example, Fig.16 As shown, M0 rail 1660 can be coupled to gate terminal 1624 (e.g., the gate terminal of PG transistor 1510), which can be configured as TRKWL; M0 rail 1662 can be coupled to MD 1636 (e.g., the drain terminal of PG transistor 1510), which can be configured as TRKBL; M0 rail 1664 can be coupled to MD 1642 and 1646 (e.g., the respective source terminals of PU transistors 1530 and 1540), which can be configured as part of the power rail carrying VDD; M0 rail 1666 can be coupled to MD 1644 (e.g., the source terminal of PG transistor 1520), which can be configured as TRKBLB; M0 rail 1668 can be coupled to MD 1652 (e.g., the source terminal of PD transistor 1560), which terminal can be configured as part of a power rail carrying VSS; M0 rail 1670 can be coupled to gate terminal 1622 (e.g., the gate terminal of PG transistor 1520), which terminal can be configured as a nominal word line WL (e.g., WL[0]).

[0112] Generally speaking, for transistors, a higher threshold voltage (V th ) results in a lower drain-to-source current (I DS ). More specifically, I DS The change can be determined according to the following relationship, where V gs is the gate-to-source voltage difference, b and a are factors that are essentially independent of manufacturing variations: I DS =b*(V gs -V th )^a. According to this equation, reducing V gs With increasing V th has the same effect.

[0113] In some embodiments of the present disclosure, TRKWL (e.g., Fig.11 , Fig.13 and Fig.15 ) can be driven with an inhibiting voltage, and / or TRKBL (e.g., as Fig.11 , Fig.13 , Fig.15 ) can also be driven with increased voltages to mimic a weak nominal memory cell. A weak memory cell typically has at least one th of the pass-gate transistor and / or at least one with an abnormally low V th The suppressed TRKWL signal is a voltage maintained below the nominal word line WL drive voltage, while the boosted TRKBL signal is a voltage maintained above the nominal bit line BL drive voltage.

[0114] applied to a pass gate transistor of the tracking unit (e.g. Fig.15 The suppressed TRKWL signal (eg, voltage) at the gate terminal of the tracking cell 1530 is less than the nominal word line WL drive voltage, thereby reducing the V of the pass gate transistor in the tracking cell. gs Therefore, the tracking cell can exhibit a higher V th For example, the voltage applied to TRKWL reduces the V of the slowest memory cell in the memory array by at least th The V th In another example, the voltage applied to TRKWL is lower than the driving voltage of the nominal word line WL by V between the nominal memory cells in the array. th In another example, the voltage applied to TRKWL is about six times the standard deviation lower than the nominal word line WL drive voltage. Similarly, one of the pull-up transistors (e.g. Fig.15 The increased TRKBL signal (eg, voltage) at the gate terminal of the pull-up transistor 1540 is set to be higher than the drive voltage of the nominal bit line BL, so that the V gs within the tracking cell. Therefore, the tracking cell can present a lower V th The timing of other equivalent memory cells with pull-up transistors.

[0115] Fig.17 The write tracking unit 135 ( Figure 1 ) is another example circuit diagram of one of the above. In the following, Fig.17 The circuit diagram of the write tracking unit 1700 is referred to as the write tracking unit 970. For example, the write tracking unit 970 ( Fig. 9 ) can be realized as Fig.17 The write tracking unit 1700 shown in FIG. Fig.18 shows that it can be used to manufacture Fig.17An example layout of two write tracking units 1700 (e.g., 1700-1 and 1700-2) is shown in FIG. It should be understood that Fig.17 The circuit diagram and Fig.18 The corresponding layouts shown in are provided for illustrative purposes and are not necessarily intended to limit the scope of the present disclosure.

[0116] In some embodiments, the write tracking cell 1700 is substantially similar to one of the nominal memory cells implemented in a 6T SRAM configuration. Fig.17 In the embodiment, the write tracking unit 1700 also includes NMOS pass gate (PG) transistors 1710 and 1720, PMOS pull-up (PU) transistors 1730 and 1740, and NMOS pull-down (PD) transistors 1750 and 1760. In some embodiments, one of the PG transistors 1710 may have a gate terminal connected to TRKWL, and the other of the PG transistors 1720 may have its gate terminal connected to the nominal word line WL. In addition, the drain terminal of the PG transistor 1710 is connected to TRKBL, and the source terminal of the PG transistor 1710 is connected to the output (BL_IN node) of the first inverter formed by the pull-up transistor 1730 and the pull-down transistor 1750; the drain terminal of the PG transistor 1720 is electrically floating, and its source terminal is connected to the output (BLB_IN node) of the second inverter formed by the pull-up transistor 1740 and the pull-down transistor 1760, and is further connected to TRKBLB. An input terminal of the first inverter is connected to TRKPCE; an input terminal of the second inverter is connected to the BL_IN node.

[0117] Next reference Fig.18 , the layout 1800 includes patterns 1802, 1804, 1806, 1808, and 1810, respectively configured to form active regions (sometimes referred to as oxide diffusion / definition regions), and patterns 1812, 1814, 1816, 1818, 1820, 1822, 1824, and 1826, respectively configured to form gate terminals. Hereinafter, the patterns 1802 to 1810 are respectively referred to as active regions 1802 to 1810, and the patterns 1812 to 1826 are respectively referred to as gate terminals 1812 to 1826. In some embodiments, the active regions 1802 to 1810 may each extend along the X direction, and the gate terminals 1812 to 1826 may each extend along the Y direction. In some embodiments, the active regions 1802 to 1810 and the gate terminals 1812 to 1826 may form a plurality of (e.g., 12) transistors operably configured for two 6T SRAM cells.

[0118] For example, Fig.18As shown, the active area 1810 and the gate terminal 1820 can form a PD transistor 1750; the active area 1810 and the gate terminal 1824 can form a PG transistor 1710; the active area 1808 and the gate terminal 1820 can form a PU transistor 1750; the active area 1802 and the gate terminal 1826 can form a PD transistor 1760; the active area 1802 and the gate terminal 1822 can form a PG transistor 1720; and the active area 1806 and the gate terminal 1826 can form a PU transistor 1740.

[0119] The layout 1800 also includes patterns 1828, 1830, 1832, 1834, 1836, 1838, 1840, 1842, 1844, 1846, 1848, 1850, and 1852, respectively, configured to form conductive source / drain connection structures (sometimes referred to as MDs). Hereinafter, the patterns 1828 to 1852 are respectively referred to as MDs 1828 to 1822. In some embodiments, each of the MDs 1828 to 1852 may extend along the Y direction, and further, each of the MDs 1828 to 1852 may overlap (e.g., be electrically coupled to) a portion of a corresponding active region, which may be operatively used as a source or drain terminal of a corresponding transistor.

[0120] For example, Fig.18 As shown, MD 1832 can be in contact with one of the source / drain terminals of PD transistor 1750, which terminal can be electrically floating; MD 1834 can be in contact with the other of the source / drain terminals of PD transistor 1750 and one of the source / drain terminals of PG transistor 1710, which terminal can be configured as BL_IN node; MD 1836 can be in contact with the other of the source / drain terminals of PG transistor 1710, which terminal can be electrically coupled to a metal track used as TRKBL; MD 1842 can be in contact with one of the source / drain terminals of PU transistor 1730, which terminal can be electrically coupled to a metal track carrying VDD; MD 1846 can be in contact with one of the source / drain terminals of PU transistor 1740, which terminal can be electrically coupled to a metal track carrying VDD; MD 1844 can contact one of the source / drain terminals of the PD transistor 1760 and one of the source / drain terminals of the PG transistor 1720, which terminal can be configured to be electrically coupled to the BLB_IN node of the metal track used as TRKBLB; MD 1850 can contact the other of the source / drain terminals of the PG transistor 1720, which terminal is electrically floating; MD 1852 can contact the other of the source / drain terminals of the PD transistor 1760, which terminal can be electrically coupled to the metal track carrying VSS.

[0121] Layout 1800 also includes patterns 1860, 1862, 1864, 1866, 1868, and 1870, respectively, configured to form metal tracks disposed in metallization layer M0. Metallization layer M0 is generally referred to as the bottommost one of a plurality of metallization layers disposed on the front side surface of the substrate where the active region and the gate terminal are formed. Hereinafter, patterns 1860 to 1870 are referred to as M0 tracks 1862 to 1870, respectively. In some embodiments, each of M0 tracks 1862 to 1870 may extend along the X direction, and further, each of M0 tracks 1862 to 1870 may overlap (e.g., be coupled to) one or more MDs or one or more gate terminals.

[0122] For example, Fig.18 As shown, M0 rail 1860 can be coupled to gate terminal 1824 (e.g., the gate terminal of PG transistor 1710), which can be configured as TRKWL; M0 rail 1862 can be coupled to MD 1836 (e.g., the drain terminal of PG transistor 1710), which can be configured as TRKBL; M0 rail 1864 can be coupled to MD 1842 and 1846 (e.g., the respective source terminals of PU transistors 1730 and 1740), which can be configured as part of the power rail carrying VDD; M0 rail 1866 can be coupled to gate terminal 1820 (e.g., the respective gate terminals of transistors 1730 and 1750), which can be configured as TRKPCE; M0 rail 1868 can be coupled to MD 1844 (e.g., the source terminal of PG transistor 1720), which can be configured as TRKBLB; M0 rail 1870 can be coupled to MD 1852 (e.g., the source terminal of PD transistor 1760), which can be configured as part of a power rail carrying VSS; M0 rail 1872 can be coupled to gate terminal 1822 (e.g., the gate terminal of PG transistor 1720), which can be configured as a nominal word line WL (e.g., WL[0]).

[0123] In some embodiments, the TRKPCE signal is used to emulate or otherwise control the contention level between a first pull-up transistor and a first pull-down transistor of a nominal memory cell connected to a nominal bit line BL. The contention level is typically the voltage present on the BL_IN node (i.e., the output of a first inverter formed by the first pull-up and pull-down transistors). By adjusting the TRKPCE signal (i.e., the voltage applied to the input of the first inverter), the contention level can be varied accordingly. This contention level can further control the operation of a second inverter formed by a second pull-up and second pull-down transistor of a nominal memory cell connected to a nominal inverted bit line BLB. Again in combination Fig. 9 and Fig.17Referring to FIG. 1 , when the ICLK signal rises, the TRKPCE driver 935 may provide a TRKPCE signal having an inhibited level to emulate a weak memory cell. For example, when the TRKPCE signal is provided with an adjusted (e.g., inhibited) level, the voltage present on the BL_IN node of the tracking cell 1700 may be adjusted (e.g., inhibited) accordingly. Thus, a weak memory cell may be emulated whose pull-up and / or pull-down transistors tend to have a lower V th .

[0124] Fig.19 s shown coupled to TRKBL (e.g., Figure 2-Figure 9 An example circuit diagram of an adjustment circuit 1900 for TRKBL) is shown in FIG. A write driver (eg, Figure 2-Figure 9 The write driver shown) is also coupled to TRKBL. Similar to the previous discussion, the adjustment circuit 1900 can adjust (e.g., increase) the voltage level present on TRKBL to simulate a weak memory cell. As shown, the adjustment circuit 1900 can include a plurality of stacked (e.g., NMOS) transistors, wherein each stacked transistor includes at least two transistors 1910 and 1915, 1920 and 1925, and 1930 and 1935. Specifically, the stacked transistors are each coupled between VDD and TRKBL. In addition, the gate terminal of each of the transistors 1910 to 1935 is configured to receive a control signal TRKBL_SEL[n:0], wherein at Fig.19 In the example of , n is equal to 3. Different stacked transistors can be selectively turned on based on the control signal TRKBL_SEL[n:0].

[0125] Fig. 20 Graph 2000 comparing the respective advantages (e.g., delay) of various memory devices according to various embodiments is shown. Graph 2000 includes graphs 2010, 2020, 2030, and 2040, corresponding to an existing memory device, another existing memory device, a controller 500 ( Figure 5 ) of a memory device and a controller 900 ( Fig. 9 ) memory device. The X-axis of the graph 2000 represents different supply voltages and the Y-axis represents different tracking delays. As shown, by implementing the disclosed memory controller to perform a tracking scheme on a nominal memory cell, the tracking delay can be significantly suppressed. For example, when the supplied voltage is about 0.9 volts (V), the ratio of the tracking delay caused by the controller 500 to the write time of the nominal memory cell is reduced to about 15%. In another example, when the supplied voltage is about 0.9V, the ratio of the tracking delay caused by the controller 900 to the write time of the nominal memory cell is reduced to about 2%.

[0126] Fig.21 2100 is shown for operating a memory device including a memory controller configured to adjust the timing of a falling edge of an internal clock signal based on a voltage present on TRKBL or TRKBLB according to various embodiments. For example, at least some operations of method 2100 may be performed by reference to Figure 1-Figure 9 Therefore, in the following discussion of method 2100, at least Figure 1-Figure 9 Reference numbers used in the method 2100. It should be noted that the method 2100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 2100 may be used in Fig.21 Additional operations are provided before, during, and after method 2100, and some other operations may only be briefly described herein.

[0127] Method 2100 may begin with operation 2110, which pulls up an internal clock (ICLK) signal after initiating an operation performed on a nominal memory cell. In some embodiments, a clock generator (e.g., Figure 2 210 Figure 3 310 Figure 4 410 Figure 5 510 Figure 6 610 Figure 7 710 Figure 8 810 Fig. 9 910) can provide an ICLK signal having a rising edge after recognizing the rising edge of the received clock (CLK) signal. Such a rising edge of the CLK signal is usually provided after asserting an enable signal to perform a specific (e.g., write or read) operation on a nominal memory cell (e.g., 125).

[0128] The method 2100 may continue to operation 2120 by pulling down a first signal present on a first tracking bit line coupled to the tracking cell. The TRKBL and TRKBL signals may be example implementations of the first tracking line and the first signal, respectively. Prior to any operation, the TRKBL signal (or TRKBL) may be precharged by a precharger (e.g., Figure 2 220 Figure 3 320 Figure 4 420 Figure 5 520 Figure 6 620 Figure 7 720 Figure 8 820 Fig. 9 920) is precharged to VDD or logic 1. In some embodiments, when the ICLK signal is pulled up, the precharger can stop charging TRKBL, which causes the TRKBL signal to fall.

[0129] The method 2100 can proceed to the operation 2130 of activating the tracking unit in response to identifying the rising edge of the internal clock signal or the falling edge of the first signal. Figure 2 230 Figure 4 430 Figure 5 530 Figure 6 630 / 640, Figure 7 When the TRKWL generator (e.g., 730 / 740) identifies the rising edge of the ICLK signal, the TRKWL generator can pull up the TRKWL signal, which in turn can activate (e.g., turn on) one or more corresponding tracking units. Figure 3 330 Figure 8 840 Fig. 9 When 940) identifies the falling edge of the TRKBL (first) signal, the TRKWL generator can pull up the TRKWL signal, which in turn can activate (e.g., turn on) one or more corresponding tracking units.

[0130] In response to identifying a rising edge of a second signal present on a second tracking bit line coupled to the tracking cell, method 2100 may proceed to operation 2140 of pulling down the internal clock signal. TRKBLB and TRKBLB signals may be example implementations of a second tracking line and a second signal, respectively. In some embodiments, after the tracking cell is activated, the precharged TRKBL and pre-discharged TRKBLB may begin to fall and rise, respectively. A clock generator (e.g., Figure 2 210 Figure 3 310 Figure 4 410 Figure 5 510 Figure 6 610 Figure 7 710 Figure 8 810 Fig. 9 910) can receive a trigger (TRIG) signal following the TRKBLB signal, and identify the rising edge of the TRIG signal to pull down the ICLK signal.

[0131] In one aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array, which includes a plurality of first memory cells. The memory circuit includes a tracking column, which includes one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line, and a first tracking word line. The memory circuit includes a controller, which is operably coupled to the memory array and the tracking column, and is configured to: identify a transition edge of a first signal present on the first tracking bit line, and assert a second signal present on the first tracking word line, causing a third signal present on the second tracking bit line to rise; and generate a trigger signal based on the third signal, wherein the transition edge of the trigger signal causes a write operation performed on at least one of the first memory cells to stop.

[0132] In some embodiments, the controller is further configured to charge the first signal to a first logic state and discharge the third signal to a second logic state, respectively, prior to the write operation.

[0133] In some embodiments, the trigger signal substantially follows the third signal.

[0134] In some embodiments, the tracking column further includes one or more third memory cells, wherein each of the one or more third memory cells is coupled to the first tracking bit line but not to the second tracking bit line or the first tracking word line.

[0135] In some embodiments, the tracking column further includes one or more fourth memory cells, wherein each of the one or more fourth memory cells is coupled to the first tracking bit line and the second tracking word line but not to the second tracking bit line or the first tracking word line.

[0136] In some embodiments, the second signal present on the first tracking word line and the fourth signal present on the second tracking word line are logically opposite to each other.

[0137] In some embodiments, the controller includes a multiplexer controlled by an enable signal specifying a read operation or a write operation to be performed on at least one first memory cell, and the multiplexer has first and second inputs coupled to the first and second tracking bit lines, respectively.

[0138] In some embodiments, the multiplexer is configured to select the third signal based on an enable signal specifying a write operation, and to select the first signal based on an enable signal specifying a read operation.

[0139] In some embodiments, the controller includes a clock generator configured to provide an internal clock signal of the memory array.

[0140] In some embodiments, a transition edge of the trigger signal causes the internal clock signal to fall, thereby stopping a write operation or a read operation performed on the at least one first memory cell.

[0141] In another aspect of the present disclosure, a memory circuit is disclosed. The memory circuit includes a memory array, which includes a plurality of first memory cells. The memory circuit includes a tracking column, which includes one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line, and a first tracking word line, and is configured to emulate a write operation performed on the first memory cell, wherein before the write operation, a first signal present on the first tracking bit line and a second signal present on the second tracking bit line are provided in a first logic state (e.g., logic 1) and a second logic state (e.g., logic 0), respectively. The memory circuit includes a controller, which is operably coupled to the memory array and the tracking column, and is configured to adjust the timing of the falling edge of the internal clock signal based on the rising edge of the second signal.

[0142] In some embodiments, the controller is further configured to provide a trigger signal that substantially follows the second signal.

[0143] In some embodiments, the rising edge of the trigger signal determines the timing of the falling edge of the internal clock signal.

[0144] In some embodiments, the controller is further configured to pull up a third signal present on a first tracking word line coupled to each of the one or more second memory cells upon identifying a falling edge of the first signal.

[0145] In some embodiments, the tracking column further includes one or more third memory cells, wherein each of the one or more third memory cells is coupled to the first tracking bit line but not to the second tracking bit line or the first tracking word line.

[0146] In some embodiments, the tracking column further includes one or more fourth memory cells, wherein each of the one or more fourth memory cells is coupled to the first tracking bit line and the second tracking word line but not to the second tracking bit line or the first tracking word line.

[0147] In some embodiments, the controller is further configured to pull up a third signal present on the first tracking word line when a write operation is performed on the first memory cell, and to pull up a fourth signal present on the second tracking word line when a read operation is performed on the first memory cell.

[0148] In another aspect of the present disclosure, a method for operating a memory circuit is disclosed. The method includes asserting an internal clock signal after initiating a write operation performed on a nominal memory cell. The method includes negating a first signal present on a first tracking bit line coupled to a tracking unit. The method includes activating the tracking unit in response to identifying a rising edge of the internal clock signal or a falling edge of the first signal. The method includes negating the internal clock signal in response to identifying a rising edge of a second signal present on a second tracking bit line coupled to the tracking unit.

[0149] In some embodiments, the method further includes generating a trigger signal after the second signal, wherein a rising edge of the trigger signal causes negation of the internal clock signal.

[0150] In some embodiments, before the write operation, the first signal has been precharged to a first logic state, and the second signal has been pre-discharged to a second logic state.

[0151] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of a value (e.g., +10%, ±20%, or ±30% of a value).

[0152] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory circuit, comprising: A memory array including a plurality of first memory cells; a tracking column comprising one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line, and a first tracking word line; and a controller operably coupled to the memory array and the tracking column and configured to: identifying a transition edge of a first signal present on the first tracking bit line and asserting a second signal present on the first tracking word line, causing a third signal present on the second tracking bit line to rise; and A trigger signal is generated based on the third signal, wherein a transition edge of the trigger signal causes a write operation performed on at least one of the first memory cells to stop.

2. The memory circuit according to claim 1, wherein: The controller is also configured to charge the first signal to a first logic state and discharge the third signal to a second logic state, respectively, prior to the write operation.

3. The memory circuit according to claim 1, wherein: The trigger signal substantially follows the third signal.

4. The memory circuit according to claim 1, wherein: The tracking column also includes one or more fourth memory cells, wherein each of the one or more fourth memory cells is coupled to the first tracking bit line and the second tracking word line but not to the second tracking bit line or the first tracking word line.

5. The memory circuit according to claim 4, wherein: The second signal present on the first tracking word line and the fourth signal present on the second tracking word line are logically opposite to each other.

6. The memory circuit according to claim 5, wherein: The controller includes a multiplexer controlled by an enable signal designating a read operation or a write operation to be performed on the at least one first memory cell, and the multiplexer has first and second inputs coupled to the first and second tracking bit lines, respectively.

7. A memory circuit comprising: A memory array including a plurality of first memory cells; a tracking column comprising one or more second memory cells, wherein each of the one or more second memory cells is coupled to a first tracking bit line, a second tracking bit line, and a first tracking word line, and is configured to emulate a write operation performed on the first memory cell, wherein prior to the write operation, a first signal present on the first tracking bit line and a second signal present on the second tracking bit line are provided at a first logic state and a second logic state, respectively; and A controller is operably coupled to the memory array and the tracking column and is configured to adjust the timing of a falling edge of an internal clock signal based on a rising edge of the second signal.

8. The memory circuit according to claim 7, wherein: The controller is further configured to pull up a third signal present on the first tracking word line coupled to each of the one or more second memory cells upon identifying a falling edge of the first signal.

9. The memory circuit according to claim 7, wherein: The tracking column also includes one or more third memory cells, wherein each of the one or more third memory cells is coupled to the first tracking bit line but not to the second tracking bit line or the first tracking word line.

10. A method of operating a memory circuit, comprising: asserting the internal clock signal after initiating a write operation to the nominal memory cell; negating a first signal present on a first tracking bit line coupled to the tracking cell; activating the tracking unit in response to identifying a rising edge of the internal clock signal or a falling edge of the first signal; as well as The internal clock signal is negated in response to identifying a rising edge of a second signal present on a second tracking bit line coupled to the tracking cell.

Images