RRAM memory and operation method
By designing the current limiting unit and series resistor in RRAM memory, the current limiting protection of the memory cells is achieved, and the problems of high circuit complexity and large area in the prior art are solved, thereby reducing the area and circuit complexity of the memory.
Patent Information
- Application Number
- CN202510094087.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2025-05-13
AI Technical Summary
When the existing RRAM memory switches from a high-impedance state to a low-impedance state, peripheral circuits require current limiting, resulting in high circuit complexity and large area.
A RRAM memory is designed to achieve current limiting protection of the memory cell by adding a current limiting unit to the memory array and dynamically allocating the voltage using a series resistor.
This reduces the resistance difference between RRAM devices in RRAM memory, reduces the complexity of the overall circuit structure, and helps to reduce the memory area.
Smart Images
Figure CN119993235A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of memory technology, and in particular to a RRAM memory and an operation method thereof. Background Art
[0002] RRAM (resistance-regulating RAM) is a new type of non-volatile memory. Its working principle is: when no voltage is applied to both ends, the two ends of the storage unit are in a high impedance state (HRS) due to the default insulation of the oxide layer between the electrodes; when voltage is applied to both ends, if the voltage exceeds the formation voltage, "conductive fiber (CF)" is formed in the middle of the oxide layer, causing the storage unit to enter a low impedance state (LRS), where the resistance value corresponding to LRS is at least one order of magnitude lower than the resistance value corresponding to HRS.
[0003] Taking the bipolar memory structure as an example, if a reverse voltage is applied to both ends of a memory cell in LRS, the process is reset, the applied voltage is the reset voltage, and the memory cell changes from LRS to HRS. If a forward voltage is applied to both ends of a memory cell in HRS, the process is set, the applied voltage is the set voltage, and the memory cell changes from HRS to LRS.
[0004] In the process of the memory cell changing from HRS to LRS, it is usually necessary to limit the current of the memory cell to prevent the memory cell from showing a very low resistance when in LRS, which would cause the subsequent required reset current to be too large, causing the memory cell to fail. In traditional solutions, peripheral circuits (e.g., current source circuits) are usually used to limit the current of the memory cell, which not only increases the circuit complexity, but also is not conducive to reducing the memory area.
[0005] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention
[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a RRAM memory and an operation method thereof, so as to solve the problems of complex circuits and large area in the prior art solutions.
[0007] To achieve the above objectives and other related objectives, the present invention provides a RRAM memory, the RRAM memory comprising:
[0008] A plurality of memory cells are arranged into a memory array in M rows and N columns, wherein M and N are both natural numbers greater than 1; in the memory array, the memory cells in each row share a word line, and the memory cells in each column share a bit line;
[0009] N current limiting units are respectively connected in series on N bit lines and are used to perform current limiting protection on the storage unit when the storage unit switches from a high impedance state to a low impedance state.
[0010] Optionally, the current limiting unit includes a current limiting resistor, a first switch and a second switch. The first end of the current limiting resistor is connected to the corresponding storage unit, the second end of the current limiting resistor is connected to the first end of the first switch, the second end of the first switch is connected to the corresponding bit line, the first end of the second switch is connected to the first end of the current limiting resistor, and the second end of the second switch is connected to the second end of the first switch; wherein, the resistance value of the current limiting resistor satisfies the formula 0.5*LR < Rexi < HR, Rex is the resistance value of the i-th current limiting resistor, LR is the corresponding resistance value when the storage unit is in a low impedance state, and HR is the corresponding resistance value when the storage unit is in a high impedance state.
[0011] Optionally, among the current limiting resistors, at least two of the current limiting resistors have equal resistance values.
[0012] Optionally, the first switch and the second switch are implemented by MOS transistors.
[0013] Optionally, in the storage array, the storage units in each row share a source line; the storage unit includes an NMOS transistor and an RRAM device, the gate of the NMOS transistor is connected to the corresponding word line, the drain of the NMOS transistor is connected to the corresponding bit line through the RRAM device, and the source of the NMOS transistor is connected to the corresponding source line.
[0014] Optionally, in the storage units of each column, two adjacent storage units are mirror-symmetrically arranged; at this time, in the storage array, the storage units in every two adjacent rows share a source line.
[0015] Optionally, the storage unit is a bipolar storage structure.
[0016] The present invention also provides an operation method for the RRAM memory as described in any one of the above, and the operation method includes:
[0017] A write operation, by changing the impedance state of the storage unit to be operated, completing a reset operation or a set operation on the storage unit to be operated;
[0018] Wherein, during the process of performing a set operation on the storage unit to be operated, when the storage unit to be operated switches from a high impedance state to a low impedance state, current limiting protection is performed on the storage unit to be operated based on the current limiting unit.
[0019] Optionally, the current limiting unit is closed during the reset operation and opened during the set operation.
[0020] Optionally, when the current limiting unit includes a current limiting resistor, current limiting protection for the storage unit to be operated is implemented based on dynamic voltage division of series resistors.
[0021] As described above, the RRAM memory and operation method of the present invention realize current limiting by designing a current limiting unit and dynamically allocating voltage by a series resistor, that is, when the resistance value of the RRAM device in the memory cell is relatively low, the voltage allocated to the RRAM device is also relatively low, and when the resistance value of the RRAM device in the memory cell is relatively high, the voltage allocated to the RRAM device is also relatively high, thereby reducing the difference between the RRAM devices in different memory cells; the present invention can realize current limiting by adding a plurality of current limiting units in the memory array, without the need for peripheral circuits, reducing the complexity of the overall circuit structure, and facilitating reducing the area of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 Shown is a schematic diagram of the structure of an RRAM memory in an embodiment of the present invention.
[0023] Figure 2 Shown is a flow chart of an operation method of an RRAM memory in an embodiment of the present invention.
[0024] Component number description
[0025] 100 RRAM memory
[0026] 110 Storage Units
[0027] 120 Current limiting unit DETAILED DESCRIPTION
[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] See also Figure 1 and Figure 2 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0030] like Figure 1As shown, this embodiment provides a RRAM memory 100 including a plurality of storage units 110 and a plurality of current limiting units 120 .
[0031] A plurality of memory cells 110 are arranged in M rows and N columns to form a memory array, where M is a natural number greater than 1 and N is a natural number greater than 1. Specifically, in the memory array, the memory cells 110 in each row share a word line, and the memory cells 110 in each column share a bit line; Figure 1 Taking the 2-row and 4-column memory array shown as an example, the four memory cells 110 in the first row share a word line WL1, the four memory cells 110 in the second row share a word line WL2, the two memory cells 110 in the first column share a bit line BL1, the two memory cells 110 in the second column share a bit line BL2, the two memory cells 110 in the third column share a bit line BL3, and the two memory cells 110 in the fourth column share a bit line BL4.
[0032] Furthermore, in the memory array, the memory cells 110 of each row share a source line. As an optional solution, in the memory cells 110 of each column, two adjacent memory cells 110 are mirrored, so that the memory cells 110 of each two adjacent rows in the memory array share a source line, thereby simplifying the number of source lines; for example, the memory cells 110 in the first and second rows share a source line SL1, the memory cells 110 in the third and fourth rows share a source line SL2, the memory cells 110 in the fifth and sixth rows share a source line SL3, and so on.
[0033] The circuit structure of each storage unit 110 is the same; in one embodiment, the storage unit 110 includes an NMOS tube and a RRAM device, wherein the gate of the NMOS tube is connected to the corresponding word line, the drain of the NMOS tube is connected to the corresponding bit line via the RRAM device (that is, the drain of the NMOS tube is connected to the first end of the RRAM device, and the second end of the RRAM device is connected to the corresponding bit line), and the source of the NMOS tube is connected to the corresponding source line.
[0034] In applications, the memory cell 110 is usually a bipolar memory structure, that is, the memory cell 110 performs a reset operation based on a reverse voltage and performs a set operation based on a forward voltage; of course, it is also feasible for the memory cell 110 to be a unipolar memory structure, which has no substantial impact on the implementation of the solution of this embodiment. It should be noted that both the bipolar memory structure and the unipolar memory structure are composed of NMOS tubes and RRAM devices, and the two are only slightly different in the RRAM device, and the other parts are exactly the same. The difference in the RRAM device is ultimately reflected in the different polarity of the corresponding write voltage during the write operation.
[0035] N current limiting units 120 are respectively connected in series on N bit lines, that is, each current limiting unit 120 is respectively connected in series with the memory cells 110 in each column on each bit line, and is used to limit the current of the memory cell 110 when the memory cell 110 switches from a high impedance state to a low impedance state, so as to avoid the failure of the memory cell 110.
[0036] In one embodiment, the current limiting unit 120 includes a current limiting resistor, a first switch and a second switch. Wherein, the first end of the current limiting resistor is connected to the corresponding memory cell 110. For example, the first end of the current limiting resistor is connected to the second end of the RRAM device of the first memory cell 110 or the last memory cell 110 in the corresponding column. The second end of the current limiting resistor is connected to the first end of the first switch. The second end of the first switch is connected to the corresponding bit line. The first end of the second switch is connected to the first end of the current limiting resistor. The second end of the second switch is connected to the second end of the first switch. In applications, the first switch and the second switch are usually implemented by MOS transistors. For example, they are implemented by NMOS transistors. Of course, other device structures capable of performing switching functions are also feasible, which has no substantial impact on the implementation of the solution of this embodiment.
[0037] Wherein, the resistance value of the current limiting resistor satisfies the formula 0.5*LR < Rexi < HR, where Rexi is the resistance value of the i-th current limiting resistor, LR is the resistance value corresponding to the memory cell 110 in the low impedance state, and HR is the resistance value corresponding to the memory cell 110 in the high impedance state. In fact, among the current limiting resistors, at least two current limiting resistors have equal resistance values; as an optional solution, the resistance values of all current limiting resistors are equal, so as to simplify the circuit design; since the resistance value distribution of the RRAM device is very discrete, when designing the resistance value of the current limiting resistor, it should be reasonably selected to avoid the situation that does not meet the above formula limiting conditions. In applications, it is also feasible to separately design the resistance value of the corresponding current limiting resistor according to the resistance value of the RRAM device of the memory cell 110 in each column, so as to increase the design flexibility.
[0038] As Figure 2 shown, this embodiment also provides an operation method of an RRAM memory, including a write operation, and further including a read operation; wherein, the RRAM memory is implemented by the circuit structure described above.
[0039] The write operation completes the reset operation or the set operation of the memory cell to be operated by changing the impedance state of the memory cell to be operated.
[0040] For the reset operation, the word line of the memory cell to be operated is set to a high level, the source line of the memory cell to be operated is set to a low level, and the bit line of the memory cell to be operated is connected to a reset voltage (taking a bipolar storage structure as an example, the reset voltage is a reverse voltage). In this way, the memory cell to be operated is changed from a low impedance state to a high impedance state, and the reset operation is completed; wherein, during the reset operation of the memory cell to be operated, the current limiting unit 120 is closed, for example, the first switch is opened and the second switch is closed, thereby realizing the closing of the current limiting unit 120.
[0041] For the set operation, the word line of the memory cell to be operated is set to a high level, the source line of the memory cell to be operated is set to a low level, and the bit line of the memory cell to be operated is connected to a set voltage (taking a bipolar storage structure as an example, the set voltage is a forward voltage). In this way, the memory cell to be operated is changed from a high impedance state to a low impedance state, and the set operation is completed; wherein, during the set operation on the operating memory cell, the current limiting unit 120 is opened, for example, the first switch is closed and the second switch is opened, thereby realizing the opening of the current limiting unit 120.
[0042] In one embodiment, when the current limiting unit 120 includes a current limiting resistor, current limiting protection of the memory cell to be operated is realized based on the function of dynamic voltage division of the series resistor. Specifically, when the memory cell to be operated has not yet switched to the low impedance state, at this time, the memory cell to be operated is in a high impedance state, because the resistance value of the current limiting resistor is less than the corresponding resistance value when the memory cell to be operated is in the high impedance state, most of the set voltage falls on the RRAM device of the memory cell to be operated, and at this time, it can be considered that the current limiting resistor does not work; when the memory cell to be operated switches from the high impedance state to the low impedance state, at this time, the memory cell to be operated is in a low impedance state, because the resistance value of the current limiting resistor is greater than the corresponding resistance value when the memory cell to be operated is in the low impedance state, the voltage value of the set voltage falling on the RRAM device of the memory cell to be operated drops rapidly, thereby realizing current limiting protection of the memory cell to be operated.
[0043] The read operation reads the low impedance state or the high impedance state of the memory cell to be operated, thereby realizing the reading of the information stored in the memory cell to be operated.
[0044] For the read operation, the word line of the memory cell to be operated is set to a high level, the source line of the memory cell to be operated is connected to the read voltage, and the bit line of the memory cell to be operated is set to a low level, thereby realizing the reading of the information stored in the memory cell to be operated. In fact, in order to prevent the read voltage from changing the impedance state of the memory cell to be operated, the read voltage is usually designed to be smaller than the write voltage, wherein the write voltage includes a reset voltage and a set voltage. In applications, the read voltage is usually made smaller than the smaller one of the reset voltage and the set voltage.
[0045] In summary, the RRAM memory and operation method of the present invention realizes current limiting by designing a current limiting unit and dynamically allocating voltage by a series resistor, that is, when the resistance of the RRAM device in the memory cell is relatively low, the voltage allocated to the RRAM device is also relatively low, and when the resistance of the RRAM device in the memory cell is relatively high, the voltage allocated to the RRAM device is also relatively high, thereby reducing the difference between RRAM devices in different memory cells; the present invention can realize current limiting by adding a number of current limiting units in the memory array, without the need for peripheral circuits, reducing the complexity of the overall circuit structure, and helping to reduce the area of the memory. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0046] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A RRAM memory, characterized in that: The RRAM memory includes: A plurality of memory cells arranged in a memory array in M rows and N columns, where M and N are natural numbers greater than 1; in the memory array, the memory cells in each row share a word line, and the memory cells in each column share a bit line; N current-limiting units respectively connected in series on N bit lines for current-limiting protection of the memory cells when the memory cells switch from a high-impedance state to a low-impedance state.
2. The RRAM memory according to claim 1, characterized in that: The current-limiting unit includes a current-limiting resistor, a first switch, and a second switch. The first end of the current-limiting resistor is connected to the corresponding memory cell, the second end of the current-limiting resistor is connected to the first end of the first switch, the second end of the first switch is connected to the corresponding bit line, the first end of the second switch is connected to the first end of the current-limiting resistor, and the second end of the second switch is connected to the second end of the first switch; wherein, the resistance value of the current-limiting resistor satisfies the formula 0.5*LR < Rexi < HR, Rex is the resistance value of the i-th current-limiting resistor, LR is the resistance value corresponding to the memory cell in the low-impedance state, and HR is the resistance value corresponding to the memory cell in the high-impedance state.
3. The RRAM memory according to claim 2, characterized in that: Among the current-limiting resistors, the resistance values of at least two current-limiting resistors are equal.
4. The RRAM memory according to claim 2, characterized in that: The first switch and the second switch are implemented by MOS transistors.
5. The RRAM memory according to claim 1, characterized in that: In the memory array, the memory cells in each row share a source line; the memory cell includes an NMOS transistor and an RRAM device, the gate of the NMOS transistor is connected to the corresponding word line, the drain of the NMOS transistor is connected to the corresponding bit line through the RRAM device, and the source of the NMOS transistor is connected to the corresponding source line.
6. The RRAM memory according to claim 5, characterized in that: In each column of the memory cells, two adjacent memory cells are mirror-symmetrically arranged; at this time, in the memory array, every two adjacent rows of memory cells share a source line.
7. The RRAM memory according to claim 5, characterized in that: The memory cell is a bipolar memory structure.
8. An operating method of the RRAM memory according to any one of claims 1 to 7, characterized in that: The operation method includes: A write operation, which completes a reset operation or a set operation on the memory cell to be operated by changing the impedance state of the memory cell to be operated; Among them, during the process of setting the memory cell to be operated, when the memory cell to be operated switches from a high-impedance state to a low-impedance state, current-limiting protection is performed on the memory cell to be operated based on the current-limiting unit.
9. The operating method of the RRAM memory according to claim 8, characterized in that: The current-limiting unit is closed during the reset operation and opened during the set operation.
10. The operating method of the RRAM memory according to claim 8 or 9, characterized in that: When the current-limiting unit includes a current-limiting resistor, current-limiting protection for the memory cell to be operated is achieved based on dynamic voltage division of series resistors.