Method for realizing asynchronous sampling rate conversion of video signals

Abstract

The invention discloses a method for realizing asynchronous sampling rate conversion in a video signal digital-to-analog conversion process, which comprises the following steps of: designing an FIR (finite impulse response) type asynchronous sampling rate conversion filter (as shown in an attached drawing) with a frequency response function of (kT / 2) / sin (kT / 2) type; and the frequency component signal gain of the video signal subjected to digital-to-analog conversion and long-distance transmission is kept constant. Therefore, various technical indexes such as a frequency response curve, a chromaticity and brightness gain difference, group delay and a signal-to-noise ratio of video signals subjected to digital-to-analog conversion and long-distance transmission can meet requirements. The FIR type asynchronous sampling rate conversion filter is realized through an FPGA, prototype filter coefficients of 24 basic phases are stored in the FPGA, filter coefficients on finer phases and optimization of the filter coefficients are realized through 3-order Lagrange interpolation, and filtering processing of 16 paths of video signals is simultaneously realized through one FPGA module, so that the performance of the asynchronous sampling rate conversion filter is effectively improved, and the filtering efficiency is improved. And the storage space of the coefficient is saved.

Description

Technical Field

[0001] The invention relates to a method for realizing asynchronous sampling rate conversion in a video signal digital-to-analog conversion process, and belongs to the technical fields of video signal processing, video digital conversion and video transmission. Background Art

[0002] Analog video signals are converted into discrete digital video signals after high-speed sampling and digital quantization. After these digital signals are converted to digital-to-analog, their signal quality is greatly reduced, mainly because the output gain decreases with the increase of frequency, resulting in insufficient high-frequency components in the restored video signal, which will cause the degradation of several key parameters of the video signal, including spectrum distortion, color brightness gain difference, increased group delay, and decreased signal-to-noise ratio.

[0003] Usually, the method used to reduce the impact of digital-to-analog and analog-to-digital conversion on signal quality is to use a very high sampling clock to sample the video signal, and the sampling clock frequency is generally three to four times the video bandwidth. The disadvantage is that it requires a higher analog-to-digital and digital-to-analog processing bandwidth, and it also takes up a lot of storage space. Summary of the invention

[0004] In order to solve the many shortcomings of the existing video signal digital-to-analog conversion methods, a method for implementing asynchronous sampling rate conversion of video signals was invented. This method is based on the principle of FIR (finite impulse response) filters. By sampling a multiplier-accumulator (MAC) and multiple optimizations of the filter parameters, the gain of the frequency component signal after analog-to-digital and digital-to-analog conversion remains basically constant. A small-scale FPGA (field programmable array) is used in hardware to implement it.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] After the ideal sampling signal is converted by A / D (analog to digital), it goes through a series of remote transmission and exchange and other processing, and then output through the D / A (digital to analog) converter. Its frequency response function is a sin(kT / 2) / (kT / 2) type curve. For this function curve, we need to design a FIR type asynchronous sampling rate conversion filter. Its implementation mechanism is as follows Figure 1 Its frequency response function should be a (kT / 2) / sin(kT / 2) type curve, so that the final frequency component signal gain in the 0-k / 2 frequency band remains substantially constant.

[0007] Through Matlab's filter design and analysis tools, the parameters of the relevant asynchronous sampling rate conversion filter can be obtained.

[0008] Figure 2It is a graphical representation of the frequency response performance curve of the designed asynchronous sampling rate conversion filter.

[0009] In the implementation of the FPGA program, in order to save resources, prototype filter coefficients of 24 basic phases are stored, and the filter coefficient settings on more refined phases are implemented by interpolation using the third-order Lagrange mean value principle (Lagrange's theorem, also known as the finite increment theorem). Figure 3 The structure is implemented by FPGA. The shift registers realize the delay of input data, and the delay line length can be selected according to the requirements of the number of stages. The Rom read-only memory stores the coefficients of each order of the asynchronous sampling conversion filter. The multiplication accumulator and ROM perform multiplication and addition operations together with the input data according to the clock beat under the control logic. In the output stage, the upper and lower overflows and the range are limited, the timing is reorganized, and finally the data is output. Such an implementation method greatly saves the storage space of the coefficients and effectively improves the performance of the asynchronous sampling rate conversion filter, so that the final frequency component signal gain of the video signal in the 0-k / 2 frequency band remains basically constant, so that the video signal after digital-to-analog conversion and long-distance transmission meets the system requirements in various technical indicators such as frequency response curve, chrominance and brightness gain difference, group delay, and signal-to-noise ratio.

[0010] The beneficial effect of the present invention is that the method can ensure that the video signal indicators will not be reduced due to digital-to-analog conversion and long-distance transmission, including frequency response curve (spectral distortion), chrominance and brightness gain difference, group delay, signal-to-noise ratio, etc. At the same time, due to the use of parallel design, one FPGA module can simultaneously perform real-time conversion on 16 video signals, greatly saving the required FPGA logic and storage resources. Compared with the commonly used high-frequency sampling clock solution, the implementation method of asynchronous sampling rate conversion described in the present invention greatly improves the integration and cost performance of the product.

[0011] This method can be used in situations such as long-distance transmission of digital video and video broadcasting, effectively avoiding the disadvantage of traditional design that requires the sampling frequency and output frequency to be complete multiples, greatly simplifying the technical implementation of the entire system, and greatly improving the stability of the system, reducing the hardware cost of the system, and improving the cost performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Schematic diagram of the logical mechanism of FIR type asynchronous sampling rate conversion filter.

[0013] Figure 2 Graphical representation of the frequency response performance curve of the designed asynchronous sampling rate conversion filter.

[0014] Figure 3Diagram of the logic module structure of the asynchronous sampling rate conversion filter designed using FPGA.

Claims

1. A method for implementing asynchronous sampling rate conversion of a video signal, characterized in that: An FIR (finite impulse response) asynchronous sampling rate conversion filter with a frequency response function of (kT / 2) / sin(kT / 2) is designed through FPGA. After digital-to-analog conversion, the frequency component signal gain of the video signal remains constant within the 0-k / 2 frequency band.

2. The method for implementing asynchronous sampling rate conversion according to claim 1, characterized in that The design of FIR type asynchronous sampling rate conversion filter is realized by sampling a multiplier accumulator (MAC).

3. Use Matlab to analyze the data and obtain the basic phase parameters of the asynchronous sampling rate conversion filter.

4. The method for implementing asynchronous sampling rate conversion according to claim 1, characterized in that The fine phase asynchronous sampling rate conversion filter parameters are determined using a third-order Lagrangian median interpolation method.

5. The method for implementing asynchronous sampling rate conversion according to claim 1, characterized in that The FPGA module can process 16 video input signals in parallel and in real time.

6. The method for implementing asynchronous sampling rate conversion according to claim 1, characterized in that The asynchronous sampling rate conversion filter parameters of 24 basic phases are fixedly stored in the FPGA.

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