Safety communication real-time cut-off system for train signal system and implementation method

Abstract

The invention relates to a safety communication real-time cut-off system for a train signal system and an implementation method, the system comprises a dual-channel FPGA, a dynamic driving circuit, a safety cut-off circuit and an enabling safety communication module which are connected in sequence, and the dual-channel FPGA comprises a first FPGA and a second FPGA; the first FPGA and the second FPGA carry out driving and recovery detection on the dynamic driving circuit and output a cut-off signal to the enabling safety communication module through the safety cut-off circuit so as to carry out real-time cut-off of safety communication. Compared with the prior art, the method has the advantages of better real-time performance and the like.

Description

Technical Field

[0001] The invention relates to a rail transit signal system, and in particular to a safety communication real-time cutoff system for a train signal system and an implementation method thereof. Background Art

[0002] In the rail transit signal system, the system's safety computing board and input and output board communicate safely through the bus. During the normal operation of the system, normal real-time safety communication needs to be established, but when the system detects a system failure, the safety communication can be cut off by means of downtime, etc., to meet the safety-oriented strategy. The software downtime method requires a certain delay, which is related to the software architecture, and the evaluation of the delay is more difficult. In a system with real-time requirements, there is a need for a real-time cut-off safety communication implementation technology that can more accurately evaluate the system delay of fault-oriented safety and meet the real-time requirements.

[0003] After searching, Chinese patent publication number CN107145402A discloses a method and electronic device for detecting software downtime, which specifically discloses monitoring interrupt instructions for detecting software downtime; executing an interrupt for detecting software downtime based on the interrupt instruction, wherein the interrupt includes a first interrupt for running an executable program; monitoring the execution of the first interrupt, and determining that a software downtime has occurred when an abnormality is detected in the execution of the first interrupt. However, the existing patent still uses software to cut off communication. Therefore, in a 2-out-of-2 system, when the dual-channel CPU cuts off secure communication through software downtime, the real-time performance is evaluated, which has the following defects:

[0004] 1. If the software is operated in a periodic polling mode, it will introduce a periodic waiting error and increase the delay time of cutting off.

[0005] 2. When software crashes are triggered by interrupts, the software also needs to periodically collect external status, respond to interrupts, and then take crash actions. The real-time response of interrupts is also affected by higher-priority tasks, and the delay is difficult to evaluate.

[0006] 3. The software crash function cannot be detected. Once the operation is made, it cannot be restored. The system can only be restored through external intervention.

[0007] 4. The software cannot provide more maintenance and self-check information in the event of a crash. Summary of the invention

[0008] The purpose of the present invention is to overcome the defects of the above-mentioned prior art and provide a real-time disconnection system and implementation method for safety communication of train signal system with better real-time performance.

[0009] The purpose of the present invention can be achieved by the following technical solutions:

[0010] According to a first aspect of the present invention, there is provided a safety communication real-time cutoff system for a train signal system, the system comprising a dual-channel FPGA, a dynamic drive circuit, a safety cutoff circuit and a safety communication enabling module connected in sequence, the dual-channel FPGA comprising a first FPGA and a second FPGA;

[0011] The first FPGA and the second FPGA drive the dynamic drive circuit and perform recovery detection, and output a cutoff signal to enable the safety communication module through the safety cutoff circuit to cut off the safety communication in real time.

[0012] As a preferred technical solution, the dual-channel FPGA determines the driving cycle and the recovery cycle according to the real-time requirements.

[0013] As a preferred technical solution, the driving cycle is specifically:

[0014] The first FPGA outputs a square wave signal with a frequency of f1 in the time period t1 as the primary input of the safety cut-off circuit, and the second FPGA outputs a square wave signal with a frequency of f2 in the time period t2 as the primary input of the safety cut-off circuit. t1+t2 constitute a complete driving cycle of the "dynamic drive circuit".

[0015] As a preferred technical solution, the recovery cycle is specifically:

[0016] The first FPGA and the second FPGA detect a square wave signal with a frequency of f1 in the time period t1, and the first FPGA and the second FPGA detect a square wave signal with a frequency of f2 in the time period t2. t1+t2 constitute a complete recovery cycle of the "dynamic drive circuit".

[0017] As a preferred technical solution, the dynamic drive circuit includes a first drive circuit, a second drive circuit, a first recovery circuit and a second recovery circuit. The first drive circuit and the first recovery circuit are respectively connected to the first FPGA, and the second drive circuit and the second recovery circuit are respectively connected to the second FPGA.

[0018] As a preferred technical solution, both the first driving circuit and the second driving circuit include MOS tubes, and both the first recovery circuit and the second recovery circuit include resistors.

[0019] As a preferred technical solution, the safety cut-off circuit includes a transformer T1, a secondary full-wave rectifier circuit and a filter circuit which are connected in sequence.

[0020] As a preferred technical solution, the first FPGA and the second FPGA perform data synchronization, wherein the synchronization content includes a dual-channel driving strategy, a dual-channel differentiated frequency, and a verification design.

[0021] As a preferred technical solution, the first FPGA and the second FPGA perform an enable decision of "opening secure communication", wherein any single-channel FPGA can cut off secure communication.

[0022] According to a second aspect of the present invention, there is provided a method for implementing the safety communication real-time disconnection system for a train signal system, characterized in that the method is implemented based on a parallel processing method of an FPGA, and the implementation method comprises:

[0023] First, the first FPGA and the second FPGA drive and recover the dynamic drive circuit, and determine the drive cycle and the recovery cycle according to the real-time requirements;

[0024] Secondly, the first FPGA and the second FPGA perform dual-channel synchronization on the results of the mining;

[0025] Finally, the safety cut-off circuit outputs a cut-off signal to the enabling safety communication module to cut off the safety communication in real time.

[0026] According to a third aspect of the present invention, there is provided an electronic device, comprising a memory and a processor, wherein a computer program is stored in the memory, and the method described above is implemented when the processor executes the program.

[0027] According to a fourth aspect of the present invention, there is provided a computer-readable storage medium having a computer program stored thereon, wherein the program implements the method described when executed by a processor.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1) Based on the good parallel processing capability of FPGA, the present invention can perform differentiated and hierarchical real-time design for multiple security variables and different real-time requirements;

[0030] 2) CPU is a serial processing mechanism. In a multi-tasking system, due to the existence of time slices, there are difficulties and bottlenecks in evaluating the real-time performance of hardware control. The present invention adopts FPGA hardware implementation to achieve better real-time performance.

[0031] 3) The FPGA of the present invention has the advantage of parallel processing, and has more advantages in increasing and decreasing channels;

[0032] 4) The present invention reduces the difficulty of designing CPU software for complex systems;

[0033] 5) The frequency of the FPGA of the present invention is adjustable. Different frequencies can be used for occasions with different delay requirements, which facilitates the optimization and adjustment of the solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural schematic diagram of the real-time disconnection system for secure communication of the present invention;

[0035] Figure 2 is a specific circuit diagram of the dynamic driving circuit of the present invention;

[0036] Figure 3 It is a specific circuit diagram of the safety cut-off circuit of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0038] like Figure 1 As shown, the present invention is a real-time safety communication cut-off system for a train signal system, the system comprising a dual-channel FPGA, a dynamic drive circuit 3, a safety cut-off circuit 4 and a safety communication enabling module 5 connected in sequence, the dual-channel FPGA comprising a first FPGA 1 and a second FPGA 2;

[0039] The first FPGA 1 and the second FPGA 2 drive and detect the dynamic drive circuit 3, and output a cutoff signal to the enabling safety communication module 5 through the safety cutoff circuit 4 to cut off the safety communication in real time.

[0040] The present invention is based on the parallel processing mode of FPGA. Through the dual-channel FPGA, the cutting unit is driven and recovered at the same time. According to the real-time requirements, the variables such as the driving cycle and the recovery cycle are determined, the results of the recovery are synchronized in dual channels, and finally the decision on the enablement of the driving "safe communication" is made. Based on the good parallel processing capability of FPGA, differentiated and hierarchical real-time design can be carried out for multiple safety variables and different real-time requirements.

[0041] The implementation method of the present invention is implemented in a 2-out-of-2 system through the following scheme:

[0042] 1) If Figure 2 As shown, the dynamic drive circuit includes a first drive circuit, a second drive circuit, a first recovery circuit and a second recovery circuit. The first drive circuit and the first recovery circuit are respectively connected to the first FPGA, and the second drive circuit and the second recovery circuit are respectively connected to the second FPGA. The first drive circuit and the second drive circuit both include MOS tubes, and the first recovery circuit and the second recovery circuit both include resistors.

[0043] 2) If Figure 3 As shown, the key circuit of the "safety cut-off module" in the system is determined, and its structure consists of transformer T1, secondary full-wave rectifier circuit, and filter circuit.

[0044] 3) The first FPGA outputs a square wave signal with a frequency of f1 as the primary input of the transformer in the time period t1, and the second FPGA outputs a square wave signal with a frequency of f2 as the primary input of the transformer in the time period t2. t1+t2 constitute a complete driving cycle of the "dynamic driving circuit".

[0045] 4) The first FPGA and the second FPGA detect a square wave signal with a frequency of f1 in time period t1, and the first FPGA and the second FPGA detect a square wave signal with a frequency of f2 in time period t2. t1+t2 constitute a complete recovery cycle of the "dynamic drive circuit".

[0046] 5) Max(t1, t2) The maximum value is the longest time for both channels to be fully safe. Assuming that the "dynamic drive circuit" stops outputting, after t3 time, the "safety cut-off module" output is invalid "enable safety communication", then Max(t1, t2) + t3 is the longest fault response time for both channels; if t = t1 = t2, then the time is t + t3.

[0047] 6) Assume that CPU1 has security event A, which requires the disconnection of security communication. The time when the first FPGA receives the security event corresponding to CPU1 is t4, and the synchronization time between the first FPGA and the second FPGA is t5. If the second FPGA starts to send a square wave with a frequency of f1 and does not receive a disconnection command from CPU2, but does not receive a synchronization command from the first FPGA, then the maximum time for the dual-channel to disconnect security communication is t4+min(t,t5)+t3.

[0048] 7) The FPGA cycle can be flexibly adjusted according to needs and can be shortened to the us level. Compared with real-time operating systems, it can greatly reduce delays and improve real-time evaluation accuracy.

[0049] The above is an introduction to the embodiments of the system and the implementation method. The following further illustrates the scheme of the present invention through the embodiments of electronic equipment and storage cutoff.

[0050] The embodiment of the present invention also provides an electronic device including a central processing unit (CPU), which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) or computer program instructions loaded from a storage unit into a random access memory (RAM). In the RAM, various programs and data required for device operation can also be stored. The CPU, ROM, and RAM are connected to each other via a bus. An input / output (I / O) interface is also connected to the bus.

[0051] Multiple components in the device are connected to the I / O interface, including: input units, such as keyboards, mice, etc.; output units, such as various types of displays, speakers, etc.; storage units, such as disks, optical disks, etc.; and communication units, such as network cards, modems, wireless communication transceivers, etc. The communication unit allows the device to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunication networks.

[0052] The processing unit performs the various methods and processes described above, such as the method of the present invention. For example, in some embodiments, the method of the present invention can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit. In some embodiments, part or all of the computer program can be loaded and / or installed on the device via a ROM and / or a communication unit. When the computer program is loaded into RAM and executed by the CPU, one or more steps of the method of the present invention described above can be performed. Alternatively, in other embodiments, the CPU can be configured to perform the method of the present invention by any other appropriate means (e.g., by means of firmware).

[0053] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0054] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0055] In the context of the present invention, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0056] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A real-time safety communication disconnection system for a train signal system, characterized in that: The system includes a dual-channel FPGA, a dynamic drive circuit, a safety cut-off circuit, and a safety communication enabling module connected in sequence, wherein the dual-channel FPGA includes a first FPGA and a second FPGA; The first FPGA and the second FPGA drive the dynamic drive circuit and perform recovery detection, and output a cutoff signal to enable the safety communication module through the safety cutoff circuit to cut off the safety communication in real time.

2. The real-time safety communication disconnection system for a train signal system according to claim 1, characterized in that: The dual-channel FPGA determines the driving cycle and the recovery cycle according to the real-time requirement.

3. The real-time safety communication disconnection system for a train signal system according to claim 2, characterized in that: The driving cycle is specifically: The first FPGA outputs a square wave signal with a frequency of f1 in the time period t1 as the primary input of the safety cut-off circuit, and the second FPGA outputs a square wave signal with a frequency of f2 in the time period t2 as the primary input of the safety cut-off circuit. t1+t2 constitute a complete driving cycle of the "dynamic drive circuit".

4. The real-time safety communication disconnection system for a train signal system according to claim 2, characterized in that: The recovery cycle is specifically: The first FPGA and the second FPGA detect a square wave signal with a frequency of f1 in the time period t1, and the first FPGA and the second FPGA detect a square wave signal with a frequency of f2 in the time period t2. t1+t2 constitute a complete recovery cycle of the "dynamic drive circuit".

5. The real-time safety communication disconnection system for a train signal system according to claim 1, characterized in that: The dynamic drive circuit includes a first drive circuit, a second drive circuit, a first recovery circuit and a second recovery circuit. The first drive circuit and the first recovery circuit are connected to the first FPGA respectively, and the second drive circuit and the second recovery circuit are connected to the second FPGA respectively.

6. The real-time safety communication disconnection system for a train signal system according to claim 5, characterized in that: The first driving circuit and the second driving circuit both include MOS tubes, and the first recovery circuit and the second recovery circuit both include resistors.

7. The real-time safety communication disconnection system for a train signal system according to claim 1, characterized in that: The safety cut-off circuit comprises a transformer T1, a secondary full-wave rectifier circuit and a filter circuit which are connected in sequence.

8. The real-time safety communication disconnection system for a train signal system according to claim 1, characterized in that: The first FPGA and the second FPGA perform data synchronization, wherein the synchronization content includes a dual-channel driving strategy, a dual-channel differentiated frequency, and a verification design.

9. The real-time safety communication disconnection system for a train signal system according to claim 1, characterized in that: The first FPGA and the second FPGA perform an enable decision of “opening secure communication”, wherein any single-channel FPGA can cut off secure communication.

10. A method for implementing the real-time disconnection system for safety communication of a train signal system according to any one of claims 1 to 9, characterized in that: The method is implemented based on the parallel processing mode of FPGA, and the implementation method includes: First, the first FPGA and the second FPGA drive and recover the dynamic drive circuit, and determine the drive cycle and the recovery cycle according to the real-time requirements; Secondly, the first FPGA and the second FPGA perform dual-channel synchronization on the results of the mining; Finally, the safety cut-off circuit outputs a cut-off signal to the enabling safety communication module to cut off the safety communication in real time.

11. An electronic device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the program, the method according to claim 10 is implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to claim 10 is implemented.

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