Data access method and equipment
By introducing a forwarding mechanism of request messages and response messages in a distributed shared storage system, the bus connection complexity problem caused by the increase in the number of processors is solved, and the effect of simplifying data access and reducing resource usage is achieved.
Patent Information
- Application Number
- CN202510343076.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-05-13
AI Technical Summary
In distributed shared storage systems, as the number of processors increases, the complexity of bus connections increases, resulting in complex data access and high resource utilization.
By introducing a forwarding mechanism of request messages and response messages between the node and the interconnection device, the node can send request messages to the target node through the interconnection device and receive response messages, thereby simplifying the data access process.
It reduces the type of signal that needs to be sent between nodes, reduces the use of communication resources, and simplifies hardware resources and interconnection complexity.
Smart Images
Figure CN119996487A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data processing technology, and in particular to a data access method and device. Background Art
[0002] Distributed Shared Memory (DSM) is a system that connects dispersed storage systems through a network. Distributed shared memory provides a logically unified address space, and any processor or node can directly read and write to this address space. It has the advantages of scalability of distributed memory structure, as well as the advantages of good versatility, portability, and easy programming of shared memory structure.
[0003] To connect multiple processors into a multiprocessor system, a bus is probably the simplest interconnect network. In other words, a bus is a set of wires shared by all processors. When a processor communicates with other processors, it needs to put addresses, commands, and data on the bus, and other processors must listen to the bus.
[0004] However, when the number of processors increases, one processor needs to be connected to multiple other processors through a bus. Since the bus can be divided into a command bus, an address bus, and a data bus, the complexity of the interconnection increases as the number of processors increases. Summary of the invention
[0005] In view of this, an embodiment of the present application provides a data access method and device to simplify the access complexity between shared memories.
[0006] To solve the above problems, the technical solutions provided in the embodiments of the present application are as follows:
[0007] In a first aspect of the present application, a data access method is provided. The method is applied to a first node, the first node communicates with at least one second node through an interconnection device, and the first node and the at least one second node both include a memory, including:
[0008] Sending a request message to the interconnection device, the request message including a request type and information related to the request, the request message being used to request access to a memory in a target second node;
[0009] A response message sent by the interconnection device is received, wherein the response message is determined by the target second node based on the request message forwarded by the interconnection transposition and sent to the interconnection device, and the response message includes a response result to the access request.
[0010] In a second aspect of the present application, a data access method is provided, the method being applied to an interconnection device, the interconnection device being used to implement communication between a first node and at least one second node, the first node and the at least one second node both including a memory, including:
[0011] receiving a request message sent by the first node, the request message including a request type and information related to the request message, the request message being used to request access to a memory in a target second node;
[0012] forwarding the request message to the target second node;
[0013] receiving a response message sent by the target second node in response to the request message, wherein the response message includes a response result;
[0014] The response message is forwarded to the first node.
[0015] In a third aspect of the present application, a data access device is provided, which is applied to a first node and includes:
[0016] a sending unit, configured to send a request message to the interconnection device, wherein the request message includes a request type and information related to the request, and the request message is used to request access to a memory in a target second node;
[0017] A receiving unit is used to receive a response message sent by the interconnection device, wherein the response message is determined by the target second node based on the request message forwarded by the interconnection transposition and sent to the interconnection device, and the response message includes a response result for the access request.
[0018] In a fourth aspect of the present application, a data access device is provided, which is applied to an interconnection device, comprising:
[0019] A receiving unit, configured to receive a request message sent by a first node, wherein the request message includes a request type and information related to the request message, and the request message is used to request access to a memory in a target second node;
[0020] A sending unit, configured to forward the request message to the target second node;
[0021] A receiving unit, configured to receive a response message sent by the target second node in response to the request message, wherein the response message includes a response result;
[0022] A sending unit is used to forward the response message to the first node.
[0023] In a fifth aspect of the embodiments of the present application, an electronic device is provided, including: a processor, a memory;
[0024] The memory is used to store computer-readable instructions or computer programs;
[0025] The processor is used to read the computer-readable instructions or the computer program so that the electronic device implements the data access method described in the first aspect or the second aspect.
[0026] In a sixth aspect of the present application, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium. When the instructions are executed on a device, the device executes the data access method described in the first aspect or the second aspect.
[0027] In a seventh aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is enabled to execute the data access method described in the first aspect or the second aspect.
[0028] It can be seen that the embodiments of the present application have the following beneficial effects:
[0029] In the present application, a data access method is provided, which is applicable to a distributed shared storage system, the system comprising at least two nodes and an interconnection device, wherein each of the at least two nodes comprises a memory, and each node can access the memory in other nodes through the interconnection device. Specifically, if the first node needs to access the target second node, the first node sends a request message to the interconnection device, and the request message includes the request type and information related to the request message. After receiving the request message sent by the first node, the interconnection device forwards the request message to the target second node to be accessed. After receiving the request message, the target second node processes based on the request message and returns a response message to the interconnection device, and then the interconnection device sends a response message to the first node, thereby completing the access. Through the data access method provided by this scheme, when nodes access each other, the types of signals required to be sent are reduced, and only signals closely related to the access request, such as the request type and information related to the request, need to be sent, thereby reducing the occupation of communication resources. In this way, the types of communication interfaces between nodes and the interconnection device are reduced, thereby reducing hardware resources and reducing the complexity of interconnection. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of a distributed shared storage system provided in an embodiment of the present application;
[0031] Figure 2 A data access interaction diagram provided for an embodiment of the present application;
[0032] Figure 3a and Figure 3bA schematic diagram of a write request provided in an embodiment of the present application;
[0033] Figure 4a and Figure 4b A schematic diagram of a read request provided in an embodiment of the present application;
[0034] Figure 5 A schematic diagram of an exclusive request provided in an embodiment of the present application;
[0035] Figure 6 A schematic diagram of an invalid request provided in an embodiment of the present application;
[0036] Figure 7 A structural diagram of a data access device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0037] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0038] See also Figure 1 , which is a distributed shared storage system. Figure 1 As shown, the system 10 includes a node cluster 100 and an interconnection device 200. The node cluster 100 includes n nodes, namely, node 101, node 102, node 103, and so on.
[0039] In this embodiment, each node includes a memory and a processor, each node is connected to the interconnection device 200, and accesses the memory in other nodes through the interconnection device 200. To facilitate understanding of the functions of the above-mentioned nodes, the access of node 101 to other nodes will be described as an example. Among them, the message sent by node 101 to other nodes is a request message, and the message replied by other nodes based on the request message sent by node 101 is a response message.
[0040] The signal types corresponding to the ports connected to each node and the interconnection device are shown in the following table, where input indicates that the node receives the signal sent by the interconnection device, and output indicates the signal sent by the node to the interconnection device. Clk is used to synchronize the clocks of node 101 with other nodes; id is the node identifier, req indicates the type of request signal or response signal; data is used to carry information related to the request or the response result; user is used to indicate the check code used when checking the information in data.
[0041] Among them, req can be expressed as the following: READADDR (RA) indicates a read request signal, and its corresponding data is the target address; READDATA (RD) indicates a read data signal, which is the response replied by the accessed node, and its corresponding data is the target data read; WRITEADDR (WA) indicates a write request signal, and its corresponding data is the target address; WRITEDATA (WD) indicates a write data signal, and its corresponding data is the data to be written; EXCULSIVE (EXC) indicates an exclusive request, and its corresponding data is the target address; INVALID (INV) indicates an invalid request, and its corresponding data is the target address.
[0042] RESP indicates a response signal, and its corresponding data may be write done (write done, wdone), exclusive done (exclusive done, edone), invalid done (invalid done, idone) and error code (error code, err_c). The error code refers to the content carried by the response message when the access request of the node 101 is not completed. The error code may indicate an error correction code (Error Correction Code, ECC) error or a parity code error, an illegal address, the address to be accessed is being exclusively occupied, and there is no permission to access the address, etc.
[0043] Table 1 Signal types
[0044]
[0045] To facilitate understanding of the technical implementation of this application, Figure 1 And Table 1 for explanation.
[0046] See also Figure 2 , which is a flow chart of a data access method provided by an embodiment of the present application, such as Figure 2 As shown, the method includes:
[0047] S201 : the node 101 sends a request message to the interconnection device 200 .
[0048] The request message is used to request access to the memory in the node 102. Specifically, the request message includes a request type and information related to the request message.
[0049] Among them, in some application scenarios, such as when there is no secure transmission requirement or there are only two nodes in the node cluster, the request message may only include the request type and information related to the request message. The request type may include a read request, a write request, an exclusive request, an invalid request, etc. Different request types have different operations on the memory. For example, a read request is used to request to read the data stored at the target address in the memory corresponding to the node 102; a write request is used to request the node 102 to write the target data to the target address in the corresponding memory; an exclusive request is used to request to exclusively occupy the target address in the memory corresponding to the node 102; and an invalid request is used to request to invalidate the data stored at the target address in the memory corresponding to the node 102.
[0050] As can be seen from the above, different request types perform different operations, so the request-related information carried in the request message may also be different. For example, if the request message is a read request, an exclusive request, or an invalid request, the request-related information is the target address in the memory corresponding to the target second node.
[0051] If the request message is a write request, the information related to the request includes the target data and the target address in the memory corresponding to the target second node.
[0052] In some application scenarios, if the node cluster 100 includes three or more nodes, in order to enable the interconnection device 200 to clearly identify the target node to be accessed, the node 101 needs to inform the interconnection device 200 which nodes to access. Therefore, the request message also includes the node identifier corresponding to the node to be accessed.
[0053] Since the request message can carry a node identifier, and usually the node identifier occupies fewer resources, in order to improve access efficiency, a request message can carry multiple node identifiers. For example, if node 101 needs to access node 102 and node 103, the request message sent by node 101 to the interconnection device 200 can include both the identifier of node 102 and the identifier of node 103.
[0054] The specific form of the node identification can be set according to the actual application situation, for example, it can be identified by multiple binary bits, each bit corresponds to a node. If the bit corresponding to the node is 1, it indicates that the node corresponding to the bit is to be accessed; if the bit corresponding to the node is 0, it indicates that the node corresponding to the bit is not to be accessed. For example, if there are 3 nodes in the node cluster, the lowest bit of the 3 binary bits indicates node 101, the middle bit indicates node 102, and the highest bit indicates node 103. If the identifier in the request message is 10, it indicates that node 102 is to be accessed; if the identifier in the request message is 110, it indicates that nodes 102 and 103 are to be accessed.
[0055] S202 : The interconnection device 200 forwards the request message to the node 102 .
[0056] In this embodiment, if there are only nodes 101 and 102 in the distributed sharing system, the request message does not need to carry a node identifier, and after receiving the request message, the interconnection device directly forwards it to node 102. Since there are only two nodes in the system, after receiving the request message, node 102 can determine that it is node 101 that accesses it.
[0057] When there are multiple nodes in the system or multiple nodes are accessed simultaneously, the request message sent by node 101 includes a node identifier, which indicates the target node to be accessed, such as accessing node 102 and node 103 .
[0058] In order to enable the accessed node to know which node accesses its own memory, after receiving the request message sent by node 101, the interconnection device 200 updates the node identifier in the request message to the identifier of node 101, and sends the updated request message to node 102 or node 103.
[0059] S203: After receiving the request message, the node 102 determines a response result based on the request message.
[0060] S204 : the node 102 sends a response message to the interconnection device 200 .
[0061] After receiving the request message forwarded by the interconnection device 200 , the accessed node (eg, node 102 or node 103 ) will respond to the request message, obtain a response result, and send a response message including the response result to the interconnection device 200 .
[0062] If there are multiple nodes in the system, the response message sent by the node 102 to the interconnection device 200 includes the identifier of the node 101, so that the interconnection device 200 determines to which node the response message should be forwarded.
[0063] S205 : The interconnection device 200 forwards the response message to the node 101 .
[0064] In this embodiment, if the response message includes a node identifier, after receiving the response message sent by node 102, the interconnection device 200 updates the identifier of node 101 in the response message to the identifier of node 102, and forwards it to node 101, so that node 101 can determine which node sent the message through the node identifier in the response message. Similarly, after receiving the response message sent by node 103, the interconnection device 200 updates the identifier of node 101 in the response message to the identifier of node 103, and forwards the updated response message to node 101.
[0065] In some application scenarios, in order to ensure functional safety, the information sent can be protected. Specifically, the request message also includes first verification information, which is used to verify the information related to the request. The response message also includes second verification information, which is used to verify the response result. The first verification information and the second verification information can be ECC or Parity.
[0066] Specifically, after receiving the request message, node 102 uses the first verification information in the request message to verify the information related to the request. If the verification passes, it indicates that the information related to the request (such as the address) has not been tampered with, and subsequent processing can be performed based on the request message; if the verification fails, it indicates that the information related to the request may have been tampered with, and the request message may not be responded to, but a response message may still be replied, in which the data field carries an ECC error or a Parity error.
[0067] Similarly, after receiving the response message, node 101 uses the second verification information in the response message to verify the response result. If the verification passes, it indicates that the response result has not been tampered with, and the response message can be processed; if the verification fails, it indicates that the response result is likely to be tampered with, and the response result can be refused to be parsed.
[0068] When node 102 processes the request message, the corresponding response result may be a completed request or an uncompleted request. When the response result is an uncompleted request, the response result may also carry the reason for the uncompleted request. The reason may include one of a checksum error (e.g., an ECC error or a Parity error), an illegal target address to be accessed, an exclusive use of the target address to be accessed, and no permission to access the target address.
[0069] In addition, due to different request types, when the response result is a completion request, different response types may be carried for different request types, for example, the response result may be read completion, write completion, exclusive completion, and invalid completion.
[0070] As can be seen from the above, the response result can indicate multiple response types and multiple cause types. The number of response types and cause types that a specific response result can indicate is determined by the number of bus bits occupied by the response result. For example, if the number of bus bits occupied by the response result is n, then the response result can carry 2 n Type encoding.
[0071] In this embodiment, when the request type of the request message is a write request, the node 101 will send two messages related to the write request in two consecutive clock cycles. Specifically, the node 101 sends a first write request message to the interconnection device 200 in the first clock cycle, and the request-related information included in the first write request message is the target address in the memory corresponding to the node 102.
[0072] The node 101 sends a second write request message in the second clock cycle. The request-related information included in the second write request message is the target data to be written into the target address.
[0073] For example, Figure 3a In the schematic diagram of the write operation shown, node 101 sends a write request message to node 102 through the interconnection device 200, and the write request message includes id_out, req_out, data_out and user_out. Among them, id_out carries the identifier b10 of node 102; req_out carries WA in the write request message sent in the first clock cycle, and carries WD in the write request message sent in the second clock cycle; data_out carries wadd in the write request message sent in the first clock cycle, and carries wdata in the write request message sent in the second clock cycle; user_out carries the check information ECC in the write request messages sent in the two clock cycles.
[0074] After receiving the write request message sent by node 101, the interconnection device 200 modifies the ID in the write request message sent in different clock cycles from node 102 to node 101 (b1), and forwards the updated write request message to node 102, corresponding to Figure 3a The midnode 102 receives the write request message (id_in / req_in, data_in, and user_in).
[0075] Node 102 performs a write operation based on the write request message. If no exception (error) occurs during the write operation, a response message (id_out / req_out, data_out, and user_out) is generated. Among them, id_out carries the identifier (b1) of node 101, req_out carries RESP (indicating that it is a reply message), data_out carries wdone (indicating that the write is completed), and user_out carries verification information (used to encrypt the content carried in data_out).
[0076] After receiving the response message sent by node 102, interconnection device 200 modifies id_out in the response message from b1 to b10, and forwards the updated response message to node 101, corresponding to Figure 2 The response message (id_in / req_in, data_in and user_in) received by the middle node 101.
[0077] If node 102 encounters an abnormality during the write operation, the signal sent is as follows: Figure 3b As shown, data_out in the response message generated by node 102 carries an error code (err_c), and the contents carried in other fields remain unchanged. Correspondingly, data_in in the response message received by node 101 carries an error code.
[0078] See also Figure 4a and Figure 4b The read request process shown in Figure 4a During a normal read operation, req_out in the read request message sent by node 101 indicates that the message sent is the read address RA, and data_out carries the target address (the address in the memory corresponding to node 102); req_out in the response message sent by node 102 indicates that the message is the read data RD, and data_out carries the target data to be read.
[0079] Figure 4b This is a process of an abnormal read operation. In this scenario, in the response message sent by the node 102, req_out indicates that the message is a reply message RESP, and data_out carries an error code err_c.
[0080] Figure 5 The diagram is a diagram of an exclusive request. In the request message sent by node 101, req_out carries EXC, indicating that the message is an exclusive request message; data_out carries the exclusive target address. In the response message sent by node 102, req_out carries RESP, indicating that the message is a reply message; data_out carries exclusive done (exculsive done, edone), indicating that the exclusive use of the target address has been completed.
[0081] Figure 6The schematic diagram of an invalid request shows that req_out in the request message sent by node 101 carries INV, indicating that the message is an invalid request message; data_out carries an invalid target address. The response message sent by node 102 carries RESP in req_out, indicating that the message is a reply message; data_out carries invalid done (invaliddone, edone), indicating that the invalidation of the data in the target address has been completed.
[0082] It should be noted that the premise for node 101 to initiate an invalidation request to node 102 is that the storage space corresponding to node 102 has a backup of data 1 stored by node 101. In addition, if data 1 in node 101 is exclusively occupied by other nodes, such as node 103, node 101 will invalidate the backup of data 1 stored by node 102.
[0083] Based on the above method embodiment, the embodiment of the present application provides a data access device, which will be described below in conjunction with a specific embodiment.
[0084] See also Figure 7 , which is a structural diagram of a data access device provided in an embodiment of the present application, such as Figure 7 As shown, the device 700 includes a sending unit 701 and a receiving node 702 .
[0085] In some embodiments, the device 700 can implement the functions of the first node, specifically including:
[0086] A sending unit 701 is configured to send a request message to the interconnection device, where the request message includes a request type and information related to the request, and the request message is used to request access to a memory in a target second node;
[0087] The receiving unit 702 is used to receive a response message sent by the interconnection device, wherein the response message is determined by the target second node based on the request message forwarded by the interconnection transposition and sent to the interconnection device, and the response message includes a response result to the access request.
[0088] In some implementations, if there are at least two second nodes, the request message further includes a node identifier of at least one target second node to be accessed.
[0089] In some implementations, the node identifier in the request message forwarded by the interconnection device and received by the target second node is the identifier of the first node, and the identifier of the first node included in the request message is converted by the interconnection device after receiving the access request sent by the first node;
[0090] The node identifier in the response message is converted by the interconnection device from the node identifier of the first node to the node identifier of the target second node after receiving the response message sent by the target second node.
[0091] In some implementations, the request message further includes first verification information, where the first verification information is used to verify the information related to the request message;
[0092] The response message also includes second verification information, and the second verification information is used to verify the response result.
[0093] In some implementations, if the request message is a read request, an exclusive request, or an invalidation request, the request-related information is a target address in a memory corresponding to the target second node;
[0094] If the request message is the write request, the information related to the request includes the target address and target data in the memory corresponding to the target second node, and the request message is used to request the target second processor to write the target data to the target address.
[0095] In some implementations, the response result is completing the access request or not completing the access request;
[0096] If the response result is a completion of the access request, the response result also carries a response type, which includes read completion, write completion, exclusive completion, and invalid completion;
[0097] If the request result is the incomplete access request, the response result carries the reason for the incomplete access request, and the reason includes at least one of a checksum error, an illegal target address for access, an exclusive use of the target address for access, and lack of permission to access the target address.
[0098] In some implementations, the number of response types and cause types that can be indicated by the response result is determined by the number of bus bits occupied by the response result.
[0099] In some embodiments, if the request message is a write request, the sending unit 701 is specifically used to send a first write request message in a first clock cycle, and the information related to the first write request included in the first write request message is the target address; and send a second write request message in a second clock cycle, and the information related to the second write request included in the second write request message is the target data to be written to the target address.
[0100] In some embodiments, the device 700 can implement the functions of interconnecting devices, specifically including:
[0101] A receiving unit 702 is configured to receive a request message sent by a first node, where the request message includes a request type and information related to the request message, and the request message is used to request access to a memory in a target second node;
[0102] The sending unit 701 is configured to forward the request message to the target second node;
[0103] The receiving unit 702 is further configured to receive a response message sent by the target second node in response to the request message, where the response message includes a response result;
[0104] The sending unit 701 is further configured to forward the response message to the first node.
[0105] In some implementations, if there are at least two second nodes, the request message further includes a node identifier of at least one target second node to be accessed, and the apparatus 700 further includes: a processing unit 703;
[0106] The processing unit 703 is configured to update the node identifier in the request message from the target second node to the first node, and obtain an updated request message;
[0107] A sending unit 701, configured to forward the updated access request to the target second node;
[0108] The processing unit is further configured to update the node identifier in the response message from the first node to the target second node, and obtain an updated response message;
[0109] The sending unit 701 is further configured to forward the updated response message to the first node.
[0110] It should be noted that the information execution process of each unit in the above-mentioned device and other contents can be specifically referred to the description in the method embodiment shown in the above-mentioned application, and will not be repeated here.
[0111] In addition, an embodiment of the present application provides an electronic device, including: a processor, a memory;
[0112] The memory is used to store computer-readable instructions or computer programs;
[0113] The processor is used to read the computer-readable instructions or the computer program so that the device implements the data access method.
[0114] An embodiment of the present application provides a computer-readable storage medium, including instructions or computer programs, which, when executed on a computer, enable the computer to execute the above-mentioned data access method.
[0115] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system or device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.
[0116] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0117] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0118] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
[0119] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A data access method, characterized in that: The method is applied to a first node, the first node communicates with at least one second node through an interconnection device, and the first node and the at least one second node both include a memory, including: Sending a request message to the interconnection device, the request message including a request type and information related to the request, the request message being used to request access to a memory in a target second node; A response message sent by the interconnection device is received, wherein the response message is determined by the target second node based on the request message forwarded by the interconnection transposition and sent to the interconnection device, and the response message includes a response result to the access request.
2. The method according to claim 1, characterized in that If there are at least two second nodes, the request message further includes a node identifier of at least one target second node to be accessed.
3. The method according to claim 2, characterized in that The node identifier in the request message forwarded by the interconnection device and received by the target second node is the identifier of the first node, and the identifier of the first node included in the request message is converted by the interconnection device after receiving the access request sent by the first node; The node identifier in the response message is converted by the interconnection device from the node identifier of the first node to the node identifier of the target second node after receiving the response message sent by the target second node.
4. The method according to any one of claims 1 to 3, characterized in that: The request message also includes first verification information, where the first verification information is used to verify the information related to the request message; The response message also includes second verification information, and the second verification information is used to verify the response result.
5. The method according to claim 1, characterized in that: If the request message is a read request, an exclusive request or an invalid request, the information related to the request is a target address in the memory corresponding to the target second node; If the request message is the write request, the information related to the request includes the target address and target data in the memory corresponding to the target second node, and the request message is used to request the target second processor to write the target data to the target address.
6. The method according to claim 1, characterized in that The response result is that the access request is completed or the access request is not completed; If the response result is a completion of the access request, the response result also carries a response type, which includes read completion, write completion, exclusive completion, and invalid completion; If the request result is the incomplete access request, the response result carries the reason for the incomplete access request, and the reason includes at least one of a checksum error, an illegal target address for access, an exclusive use of the target address for access, and lack of permission to access the target address.
7. The method according to claim 6, characterized in that The number of response types and cause types that can be indicated by the response result is determined by the number of bus bits occupied by the response result.
8. The method according to claim 1, characterized in that If the request message is a write request, sending the request message to the interconnection device includes: Sending a first write request message in a first clock cycle, wherein the information related to the first write request included in the first write request message is a target address; A second write request message is sent in a second clock cycle, wherein the information related to the second write request included in the second write request message is the target data to be written into the target address.
9. A data access method, characterized in that: The method is applied to an interconnection device, the interconnection device is used to implement communication between a first node and at least one second node, the first node and the at least one second node both include a memory, and includes: receiving a request message sent by the first node, the request message including a request type and information related to the request message, the request message being used to request access to a memory in a target second node; forwarding the request message to the target second node; receiving a response message sent by the target second node in response to the request message, wherein the response message includes a response result; The response message is forwarded to the first node.
10. The method according to claim 9, characterized in that If there are at least two second nodes, the request message further includes a node identifier of at least one target second node to be accessed, and the forwarding of the request message to the target second node includes: Update the node identifier in the request message from the target second node to the first node, and obtain an updated request message; forwarding the updated access request to the target second node; The forwarding the response message to the first node includes: Update the node identifier in the response message from the first node to the target second node, and obtain an updated response message; Forward the updated response message to the first node.
11. An electronic device, characterized in that: Including: processor, memory; The memory is used to store computer-readable instructions or computer programs; The processor is used to read the computer-readable instructions or the computer program so that the electronic device can execute the data access method described in any one of claims 1 to 8, or execute the data access method described in claim 9 or 10.
12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on a device, the device is enabled to implement the data access method described in any one of claims 1 to 8, or to execute the data access method described in claim 9 or 10.