Power supply synchronization control method, device, equipment and medium

Abstract

The invention discloses a power supply synchronization control method, device and equipment and a medium, a complete unidirectional transmission optical communication ring communication link is constructed through an FPGA optical fiber communication module, so that the communication efficiency can be effectively improved, and meanwhile, the power supply synchronization control method and device can be applied to the field of communication. The whole synchronous control process can adapt to a high-speed communication environment provided by an annular communication link by periodically updating set current and set voltage and periodically sending parallel data frames by using the PGA optical fiber communication module, and then synchronous output is completed by further using the delay output module, so that the synchronous control efficiency is improved. Therefore, high-efficiency and high-synchronism synchronous control is realized, and output oscillation is effectively reduced.

Description

Technical Field

[0001] The present application relates to the field of source-carrying equipment, and in particular to a method, device, equipment and medium for synchronously controlling a power supply. Background Art

[0002] At present, in order to meet the power requirements for large output in some scenarios, multiple power supply devices need to be paralleled. However, the existing paralleling method is to let the power supply device as the host directly communicate with each power supply device as the slave to transmit the adjustment parameters to the slave, and let the slave complete the output adjustment after receiving the adjustment parameters. This adjustment method will have poor synchronization due to large communication delay and slow response speed, which may cause output oscillation and affect the use effect. Summary of the invention

[0003] The present application aims to provide a power supply synchronization control method, device, equipment and medium, which can effectively improve the synchronization of the power supply device.

[0004] According to the power supply synchronization control method of the first aspect of the present application, a plurality of power supply devices are controlled in parallel, each of the power supply devices comprises a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules has a sampling module and a delayed output module built in, and the sampling module is used to collect the operation data outputted by the corresponding power supply device; the FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end, and the plurality of power supply devices are cyclically arranged in sequence through the FPGA optical fiber communication module, and the plurality of FPGA optical fiber communication modules are connected in series in sequence through the optical fiber transmitting end and the optical fiber receiving end to form a ring communication link; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; wherein each of the power supply devices has ID address information stored locally, and the ID address information corresponding to each of the power supply devices is different; The power supply synchronization control method is applied to the power supply device as a host, and the remaining power supply devices except the host are slaves. The power supply synchronization control method includes: At each interval of a preset parallel frame sending cycle, a parallel data frame is sent to the power supply device at the next position, the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address, and the echo acquisition address is sequentially updated according to the ID address information of multiple power supply devices at each interval of the preset parallel frame sending cycle; wherein, each of the slaves, upon receiving the parallel data frame, obtains the set current and the set voltage from the parallel data frame and stores them in a delay output module, and transmits the parallel data frame to the power supply device at the next position in the ring communication link, wherein, when the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used to delay the output of the set current and the set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; Acquire the operation data collected by the sampling module of the host; receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and acquiring the operating data from the parallel data frame; At each interval of a preset power control cycle, the set current and the set voltage are updated according to the acquired operating data corresponding to the plurality of power supply devices, wherein the preset power control cycle is determined according to the preset parallel frame sending cycle and the number of the power supply devices participating in the parallel operation.

[0005] According to the second aspect of the present application, the power synchronization control device is used to control multiple power devices in parallel, and each of the power devices includes a control module, an FPGA optical fiber communication module, and a power actuator connected in sequence; each of the FPGA optical fiber communication modules is built with a sampling module and a delayed output module, and the sampling module is used to collect the operation data output by the corresponding power device; the FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end, and multiple power devices are cyclically arranged in sequence through the FPGA optical fiber communication module, and multiple FPGA optical fiber communication modules are connected in series in sequence through the optical fiber transmitting end and the optical fiber receiving end to form a ring communication link; the power actuator is used to output voltage and current according to the power output setting parameters; wherein each of the power devices has ID address information stored locally, and the ID address information corresponding to each of the power devices is different; The power supply synchronization control device is applied to the power supply device as a host, and the remaining power supply devices except the host are slaves. The power supply synchronization control device includes: A parallel frame period sending module, used for sending a parallel data frame to the next power supply device at each preset parallel frame sending period, wherein the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address, and the echo acquisition address is sequentially updated according to the ID address information of multiple power supply devices at each preset parallel frame sending period; wherein each slave, upon receiving the parallel data frame, obtains the set current and the set voltage from the parallel data frame and stores them in a delay output module, and transmits the parallel data frame to the next power supply device in the ring communication link, wherein, when the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used for delaying the output of the set current and the set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; A host data acquisition module, used to acquire the operation data collected by the sampling module of the host; A slave data acquisition module, used for receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and acquiring the operating data from the parallel data frame; A parameter determination module is used to update the set current and the set voltage at each interval of a preset power control cycle according to the acquired operation data corresponding to the multiple power supply devices, wherein the preset power control cycle is determined according to the preset parallel frame sending cycle and the number of the power supply devices participating in the parallel operation.

[0006] According to an electronic device of a third aspect of the present application, the device includes: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the power supply synchronization control method as described in the first aspect is implemented.

[0007] According to the computer-readable storage medium of the fourth aspect embodiment of the present application, computer-executable instructions are stored, and the computer-executable instructions are used to execute the power supply synchronization control method as described in the first aspect embodiment.

[0008] The power supply synchronization control method, device, equipment and medium of the embodiments of the present application construct a complete unidirectional optical communication ring communication link through the FPGA optical fiber communication module, thereby effectively improving the communication efficiency. At the same time, by periodically updating the setting current and setting voltage, and using the PGA optical fiber communication module to periodically send parallel data frames, the entire synchronization control process can adapt to the high-speed communication environment provided by the ring communication link, and further use the delayed output module to complete the synchronization output, thereby realizing high-efficiency and high-synchronization synchronization control, thereby effectively reducing output oscillation.

[0009] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or may be understood by practicing the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A system schematic diagram of a parallel system provided in an embodiment of the present application; Figure 2 A flowchart of a power synchronization control method provided in an embodiment of the present application; Figure 3 A schematic diagram of a power synchronization control device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0011] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0012] In the description of this application, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0013] In the description of the present application, it should be understood that the descriptions involving orientation, such as the orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0014] In the description of this application, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution.

[0015] The technical solution of the present application will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments.

[0016] In order to better explain the power synchronization control method, device, equipment and medium of the embodiment of the present invention, a parallel system is proposed here, referring to Figure 1 The parallel system includes multiple power supply devices, each of which is a bidirectional power supply device, and each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each FPGA optical fiber communication module is built with a sampling module and a delayed output module, and the sampling module is used to collect the operating data output by the corresponding power supply device; the FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end, and multiple power supply devices are cyclically set in sequence through the FPGA optical fiber communication module, and multiple FPGA optical fiber communication modules are connected in series in sequence through the optical fiber transmitting end and the optical fiber receiving end to form a ring communication link; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; wherein each power supply device locally stores some ID address information, and the ID address information corresponding to each power supply device is different.

[0017] The control module can be connected to a human-machine interaction unit, and an operator can actively adjust the settings of each power supply device through the human-machine interaction unit.

[0018] The above-mentioned delayed output module can realize delayed output of data, and the specific delay time can be manually set in advance.

[0019] Each of the above-mentioned power supply devices includes an FPGA fiber optic communication module. The FPGA fiber optic communication module is constructed with FPGA as the core module. RAM units can be constructed in FPGA, and RAM units can be used to store data. In the embodiment of the present application, because high-speed data transmission is involved, RAM units are set for data caching, which plays an important role in preventing data loss.

[0020] The above-mentioned FPGA optical fiber communication module includes an acquisition module, through which the operation data such as voltage and current at the output end of the power supply device can be collected.

[0021] Specifically, the acquisition module can use a 16-bit ADC chip, or a higher-precision or lower-precision ADC chip according to actual needs.

[0022] In parallel operation, one power supply unit can be selected from multiple power supply units as the master (such as Figure 1 The remaining power supply units are slaves (such as Figure 1 Power supply units B, C) are shown.

[0023] The above-mentioned ring communication link can be understood as a loop for host data downlink. When the power supply device of the host needs to transmit data to each slave, it will write key information such as setting current, setting voltage, echo acquisition address, start-up instructions, etc. into the parallel data frame, and then transmit it to each slave in turn through the ring communication link.

[0024] Specifically, the first position of the ring communication link can be understood as the host, and from the next position to the last position are slaves. The communication process of the ring communication link will be carried out in a ring form. Taking the parallel data frame as an example, the parallel data frame will first be transmitted to the second slave. The second slave obtains the set current and voltage from the parallel data frame and transmits the parallel data frame to the third slave, and repeats the above-mentioned process of obtaining the current sharing information and the forwarding process until the parallel data frame is transmitted to the last slave, and the parallel data frame is transmitted back to the host through the last slave.

[0025] A preset buffer area can be set in the above control module, and the parallel data frame that the host needs to send can be stored in the preset buffer area. When the recalculated set current and set voltage change each time, the parallel data frame in the preset buffer area can be updated.

[0026] Each of the power supply devices has local stored ID address information, and the ID address information corresponding to each power supply device is different. The ID address information can be used to better complete the acquisition of slave operation data. The ID address information of the multiple power supply devices can be set in order, for example, starting from 1 and increasing one by one.

[0027] The following describes the power synchronization control method, device, equipment and medium of the embodiments of the present application based on the above-mentioned power supply system.

[0028] See also Figure 2 As shown, Figure 2 1 is a flow chart of a power synchronization control method provided by an embodiment of the present application. The power synchronization control method is used for synchronous discharge control of multiple power supply devices during battery simulation, and is applied to a power supply device as a host, including: A parallel frame sending cycle is preset at each interval, and a parallel data frame is sent to the next power supply device. The parallel data frame at least includes a set current, a set voltage, and an echo acquisition address. The echo acquisition address is updated in sequence according to the ID address information of multiple power supply devices at each interval of the preset parallel frame sending cycle; wherein, when each slave receives the parallel data frame, it obtains the set current and set voltage from the parallel data frame and stores them in the delay output module, and transmits the parallel data frame to the next power supply device in the ring communication link, wherein, when the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used to delay the output of the set current and set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; Obtain the operating data collected by the sampling module of the host; Receive the parallel data frame transmitted by the last power supply device in the ring communication link, and obtain the operation data from the parallel data frame; At each interval of a preset power control cycle, the set current and the set voltage are updated according to the acquired operation data corresponding to the multiple power supply devices, wherein the preset power control cycle is determined according to the preset parallel frame sending cycle and the number of power supply devices participating in the parallel operation.

[0029] In the embodiment of the present application, a complete unidirectional optical communication ring communication link is constructed through an FPGA fiber optic communication module, thereby effectively improving the communication efficiency. At the same time, by periodically updating the setting current and setting voltage, and using the PGA fiber optic communication module to periodically send parallel data frames, the entire synchronization control process can adapt to the high-speed communication environment provided by the ring communication link, and further use the delayed output module to complete the synchronization output, thereby realizing high-efficiency and high-synchronization synchronization control, thereby effectively reducing output oscillation.

[0030] The above-mentioned parallel data frame at least includes setting current, setting voltage, and echo acquisition address. After the setting current and setting voltage are transmitted to the power supply actuator, the power supply actuator can complete output adjustment according to the setting current and setting voltage. The echo acquisition address can be used for the slave to verify so as to write the corresponding slave's operating data.

[0031] The echo acquisition address can be updated once before each parallel data frame is sent, and is updated in a cyclic manner, so that the host can complete the polling of the operating data in all power supply devices after sending the parallel data frame the same number of times as the number of power supply devices participating in the parallel operation. In addition, it should be noted that when multiple echo acquisition addresses can be stored in one parallel data frame, the ID address information of multiple slaves can be processed in batches, so that the operating data of multiple slaves can be obtained by sending one parallel data frame, thereby reducing the number of parallel data frames that need to be sent.

[0032] When the slave obtains the parallel data frame, it will first obtain the set current and set voltage in the parallel data frame and store them in the delayed output module, and then check the echo acquisition address in the parallel data frame to determine whether it is consistent with the ID address information stored locally by the slave. If it is consistent, the collected operation data can be written into the parallel data frame, so that the operation data can be returned to the host through the parallel data frame. After polling all the ID address information in turn, the host can obtain the operation data of all power supply devices, so that the set current and set voltage can be updated, so as to update the set current and set voltage in the parallel data frame. It can be seen that the scheme in the embodiment of the present application can complete the synchronous control by using only one parallel data frame, and the entire data transmission logic is simpler, which can better ensure the reliability of synchronous control.

[0033] The above-mentioned delayed output module can delay the time for setting the current and setting the voltage to be output to the power actuator so that multiple power supply devices can complete the output synchronously. Specifically, for the delayed output module with a higher ranking, the set current and voltage will be written earlier, so a longer delay time is required. For the delayed output module with a lower ranking, the set current and voltage will be written later, so the delay time needs to be shortened. In some embodiments, the time from each slave receiving the parallel data frame using the FPGA optical fiber communication module to re-issuing the parallel data frame can be fixed, so that the fixed time can be multiplied by the ranking information to determine the time required for each delayed output module to be delayed.

[0034] The time when the power actuator receives the set current and the set voltage will maintain a high degree of synchronization due to the existence of the delayed output module, so that the output can be adjusted in real time after receiving the set current and the set voltage.

[0035] The sampling modules of the host and slave may collect the operation data periodically.

[0036] The operation data of the above host can be obtained when the acquisition address is updated to the ID address information in the parallel data frame, or it can be obtained before the current setting and setting current update in the parallel data frame.

[0037] The above host can obtain the parallel data frame sent back by the last slave, and the echo acquisition address in the parallel data frame will be polled and updated according to the ID address information, so that the operating data of all slaves can be obtained.

[0038] The above-mentioned preset power control period is determined according to the preset parallel frame transmission period and the number of power supply devices participating in the parallel operation. It can be understood that the preset parallel frame transmission period and the number of power supply devices participating in the parallel operation are still less than the preset power control period after multiplication. For example, when there are 10 power supply devices participating in the parallel operation, the host only needs a maximum of 10 parallel data frames to obtain the operating data of all slaves. Assuming that the preset parallel frame transmission period can be 512ns, the time to obtain the operating data of all power supply devices is about 5.12us, and the preset power control period can be 50us. And the preset power control period will be adaptively changed when the preset parallel frame transmission period changes and the number of parallel operations changes, so as to improve the real-time performance of synchronous control.

[0039] In some embodiments, the slave processing and forwarding time taken by each slave from receiving the parallel data frame transmitted by the previous power supply device to transmitting the parallel data frame to the next power supply device is less than the preset parallel frame transmission period, and the slave processing and forwarding time is a predetermined fixed duration; The delay duration of the delayed output module corresponding to each power supply device is determined according to the position of the power supply device in the ring communication link and the slave processing forwarding time. The higher the position of the power supply device in the ring communication link, the longer the delay duration of the corresponding delayed output module.

[0040] The above-mentioned slave machine processing forwarding time is a predetermined fixed duration. For example, in some scenarios, the slave machine processing forwarding time taken by the slave machine from receiving the parallel data frame transmitted by the previous power supply device to transmitting the parallel data frame to the next power supply device is approximately 128ns, but there may be certain fluctuations due to various reasons. In order to avoid the impact of this time fluctuation on data transmission, it can be avoided by setting a certain delay, for example, setting the slave machine processing forwarding time to 256ns.

[0041] The slave machine processing forwarding time is shorter than the preset parallel machine frame sending period, so that each power supply device has a certain time gap to perform other data processing, thereby realizing time-division multiplexing.

[0042] The delay time of the delay output module corresponding to each of the above-mentioned power supply devices is closely related to the position of the power supply device in the ring communication link. Due to the characteristics of the ring communication link, the power supply device with a higher position will receive the parallel data frame earlier. In order to enable multiple power supply devices to synchronously transmit the set current and set voltage to the power execution device, it is necessary to set different delays for the delay output modules in power supply devices with different positions. Taking N positions as an example, the power supply device in the first position, that is, the host, has a delay of N times 256ns for the delay output module, and the power supply device in the second position, that is, the first slave, has a delay of (N-1) times 256ns for the delay output module. And so on, the delay time of the delay output modules corresponding to all power supply devices can be determined.

[0043] In some implementations, the slave machine processing forwarding time is half of the preset parallel machine frame sending period.

[0044] In this implementation, the slave processing forwarding time is set to half of the preset parallel frame sending period, which can reserve general time for the slave to perform data processing other than synchronous operations, so that the slave has enough time to complete the remaining data processing processes not related to output control, and also allows the slave to have time to receive the remaining non-parallel related ordinary data frames sent by the host.

[0045] In some embodiments, the parallel data frame further includes the accumulated number of slave transmissions, and each slave updates the accumulated number of slave transmissions when receiving the parallel data frame; The power supply synchronization control method further includes: When the cumulative number of slave transmissions in the received parallel data frame is inconsistent with the number of power devices participating in the parallel operation, a communication loss alarm is generated.

[0046] When the above-mentioned slaves receive the parallel data frame, they will cumulatively update the accumulated number of slave transmissions before sending the parallel data frame. For example, the first slave will be updated to 1, and the second slave will be updated to 2. Each slave will complete the update in turn. When there is no problem in the entire data transmission process, the accumulated number of slave transmissions will be consistent with the number of slaves, so that after the host receives the parallel data frame, it can use the accumulated number of slave transmissions to determine whether it is consistent with the number of slaves to determine whether there is a problem with the transmission.

[0047] In this embodiment, by setting the cumulative number of slave transmissions in the parallel data frame, the cumulative number of slave transmissions can be used to determine whether the data is transmitted to each slave, and when the cumulative number of slave transmissions is inconsistent with the number of slaves, an alarm can be generated in time to remind the operator to handle the fault in time.

[0048] In some implementations, when no parallel data frame is received for more than a preset power control period, a communication failure alarm is generated.

[0049] In this implementation manner, if the host fails to receive the returned parallel data frame for a long time, it means that the communication link is disconnected, and a communication fault alarm can be generated in time to remind the operator to handle the fault in time.

[0050] The above parallel data frame may include the following parts: 1. Frame header: Special characters can be used, such as 0x55a105bc, 0x55a106bc. Note that the lowest byte is 0xbc, which uses K28.5 as the K code for data alignment control; 2. Flag: host ID (2B) + reserved (1B) + normal read / write / parallel data flag (1B, 0x00 indicates normal read / write, 0x01 indicates parallel data); 3. Data 1: The setting voltage sent by the host to each slave; 4. Data 2: The setting current sent by the host to each slave; 5. Data 3: The echo acquisition address (high 16 bits) + event (low 16 bits) corresponding to the currently polled slave; the event is mainly ON and OFF signals, that is, whether to perform parallel operation; 6. Data 4: working mode (high 16 bits) + number of slaves (16th bit): the working mode indicates the current working mode of the host (such as normal mode, sequence mode, etc.). The slave power actuator can select different loop parameters for output control according to the working mode of the host; the cumulative number of slave transmissions will increase by 1 each time it passes through a slave. Finally, the host determines whether the actual cumulative number of slave transmissions in the parallel network is consistent with the set number of slaves. If they are inconsistent, it means that the parallel configuration is wrong and an alarm prompt is issued; 7. Data 5: Echo current data of the polled slave: When the echo acquisition address in data 3 is consistent with the locally stored ID address information, the collected echo current data is filled into data 5; 8. Data 6-10: This data is reserved for extended data. When there are many parallel machines, the echo acquisition address of the currently polled slave in data 3 can be modified to represent polling a group of slave data, that is, add data 5, and every 6 slaves are represented as a slave group. The slaves belonging to the polling group will fill the echo current data into data 5-10 in the parallel data frame in turn. In this way, when a parallel data frame is looped back to the host, the current sampling data of 6 slaves can be obtained, thereby improving the acquisition efficiency of echo data; 9. Checksum: the sum of flag + data 1-10; 10. Frame tail: Use special characters such as 0x55a107bc, 0x55a108bc. Note that the lowest byte is 0xbc, which uses K28.5 as the K code for data alignment control.

[0051] In some embodiments, the operation data corresponding to each power supply device includes echo current data, and the operation data of the host also includes echo voltage data; According to the acquired operation data corresponding to the plurality of power supply devices, the set current and the set voltage are updated, including: Determine the setting current according to the preset parallel control current and the number of power supply devices involved in the parallel operation; Using the echoed current data corresponding to the plurality of power supply devices, the echoed total current data is obtained; Determine the state of charge based on the total current data displayed; According to the state of charge and charge voltage correspondence table, a first output setting voltage is obtained; According to the state of charge and charge internal resistance correspondence table, the real-time internal resistance is obtained; wherein the charge internal resistance correspondence table indicates the correspondence between multiple states of charge and multiple internal resistance information, and the charge voltage correspondence table indicates the correspondence between multiple states of charge and multiple voltage information; Obtaining a first output setting current according to the first output setting voltage, the echoed voltage data of the host and the real-time internal resistance; Determine the wire voltage drop according to the first output set current and the total current data; Determine the set voltage based on the wire voltage drop and the voltage data displayed by the host.

[0052] In the embodiment of the present application, a parallel control strategy is adopted. Therefore, the output ports of multiple power supply devices are set in parallel. In the parallel setting, the currents are superimposed and the voltages are the same. Therefore, the output voltage of each power supply device can be determined by only obtaining the echo voltage data of the host.

[0053] The above-mentioned preset parallel control current can be understood as the total demand for the output current of the power supply system after parallel operation. This embodiment is aimed at simulating the discharge process. At this time, the set current can be directly obtained by dividing the preset parallel control current and the number of power supply devices participating in the parallel operation.

[0054] The above-mentioned total echo current data can be understood as being obtained by summing up the echo current data of multiple power supply devices.

[0055] The above determination of the state of charge based on the total echo current data can be understood as being obtained by integrating the total echo current data. By setting the cycle for obtaining the total echo current data to a shorter time length, the determined state of charge can be made extremely close to the actual situation.

[0056] The charge-voltage correspondence table indicates the correspondence between a plurality of charge states and a plurality of voltage information, that is, after a charge state is determined, the corresponding voltage information can be obtained by looking up the table.

[0057] Specifically, the charged internal resistance correspondence table displays the relationship between the charged state and the corresponding voltage information with a certain proportional value, as shown in Table 1. The data in Table 1 can be expanded according to actual needs, and the specific number of rows is not limited.

[0058] Table 1

[0059] Soc1 in Table 1 can be understood as the state of charge amplified by 100 times, and the corresponding voltage ratio in Table 1 can be understood as voltage information, that is, the ratio value required for calculating the set voltage using the maximum open circuit voltage. For example, if the state of charge is 0.6080318193, the calculated Soc1 is 60.80318193, and the corresponding voltage ratio is 0.972853458. Assuming the open circuit voltage is 10 volts, the set voltage calculated using the voltage ratio is 9.72853458 volts.

[0060] The above maximum open circuit voltage can be obtained by inputting by the user through the human-computer interaction interface.

[0061] The above-mentioned charge-internal resistance correspondence table can indicate the correspondence between multiple charge states and multiple internal resistance information, that is, after determining a charge state, the corresponding internal resistance information can be obtained by looking up the table.

[0062] Specifically, the charge-to-internal resistance correspondence table can display the relationship between the charge state and the corresponding internal resistance information with a certain proportional value, as shown in Table 2. The data in Table 2 can be expanded according to actual needs, and the specific number of rows is not limited.

[0063] Table 2

[0064] Soc2 in Table 2 can be understood as the state of charge magnified 100 times, and the corresponding internal resistance ratio in Table 2 can be understood as the internal resistance information, that is, the ratio required for the subsequent calculation of the current internal resistance using the maximum internal resistance. For example, if the state of charge is 0.6080318193, the calculated Soc2 is 60.80318193. If the value cannot be found at this time, the closest Soc2 is selected for confirmation, that is, Soc2 is confirmed as 60.58506543, and the corresponding voltage ratio is 0.671063479. Assuming that the maximum internal resistance is 1 ohm, the current internal resistance calculated using the internal resistance ratio is 0.671063479 ohm.

[0065] The above maximum internal resistance can be input by the user through the human-computer interaction interface.

[0066] The first output setting voltage can be obtained by looking up a table using the state of charge to obtain a voltage ratio after determining the state of charge, and then multiplying the maximum open circuit voltage by the voltage ratio obtained by looking up the table.

[0067] After determining the state of charge, the real-time internal resistance can be obtained by looking up the table using the state of charge to obtain the internal resistance ratio, and then multiplying the maximum internal resistance by the internal resistance ratio obtained by looking up the table.

[0068] The first output setting current can be determined by performing an ohmic operation using the first output setting voltage, the echo voltage data of the host and the real-time internal resistance.

[0069] The above-mentioned wire voltage drop is obtained by using a PID algorithm. By taking the first output set current as the target value and the echoed total current data as the feedback value, the wire voltage drop can be quickly determined.

[0070] The above setting voltage takes into account the existence of wire voltage drop, and can be obtained by summing the wire voltage drop and the echo voltage data of the host.

[0071] In this embodiment, considering the influence of the wire voltage drop on the actual output adjustment control, the wire voltage drop is quickly determined by using the first output setting current and the total current data to obtain the setting voltage that best meets the control requirements. In addition, considering the influence of factors that are difficult to measure, such as wire length and conductivity, on wire resistance, a PID algorithm is used to confirm the wire voltage drop, thereby avoiding the difficulty of obtaining factors that are difficult to measure, such as wire length and conductivity.

[0072] In some implementations, obtaining the first output setting current according to the first output setting voltage, the echo voltage data of the host, and the real-time internal resistance includes: Obtaining a voltage difference between a first output setting voltage and the echoed voltage data of the host; The voltage difference and the real-time internal resistance are subjected to ohm calculation to obtain the real-time internal resistance.

[0073] In this implementation, an ohm calculation is performed on the real-time internal resistance using the voltage difference between the first output setting voltage and the echo voltage data of the host, so that the real-time internal resistance can be quickly obtained.

[0074] In some implementations, determining the wire voltage drop according to the first output set current and the total current data is echoed, including: Taking the first output set current as the reference value and the total current data displayed as the feedback value, an incremental PID operation is performed to obtain the conductor voltage drop increment; Update the wire voltage drop according to the wire voltage drop increment and the wire voltage drop obtained last time.

[0075] In this implementation, an incremental PID algorithm is adopted, and the first output setting current is used as a reference value and the total current data is echoed as a feedback value to obtain the conductor voltage drop increment, and then an incremental calculation is performed based on the conductor voltage drop obtained last time, so that a conductor voltage drop that is more in line with reality can be obtained.

[0076] In this implementation, the incremental PID algorithm can be referred to as follows: ; In the formula, is the conductor voltage drop increment; is the Kth current deviation, that is, the current deviation, is the k-1th deviation, is the k-2th deviation; , , It is a preset coefficient, which can be debugged according to the actual situation; The difference between the current set for the first output and the total current data echoed.

[0077] The power synchronization control method provided in the embodiment of the present application can be executed by a power synchronization control device. In the embodiment of the present application, the power synchronization control device provided in the embodiment of the present application is described by taking the power synchronization control method executed by the power synchronization control device as an example.

[0078] The present application also provides a power synchronization control device, such as Figure 3 As shown, the power supply synchronization control device comprises: A parallel frame period sending module is used to send a parallel data frame to the next power supply device at each preset parallel frame sending period, and the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address. The echo acquisition address is updated in sequence according to the ID address information of multiple power supply devices at each preset parallel frame sending period; wherein, when each slave receives the parallel data frame, it obtains the set current and set voltage from the parallel data frame and stores them in the delay output module, and transmits the parallel data frame to the next power supply device in the ring communication link, wherein, when the ID address information stored locally in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used to delay the output of the set current and set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; A host data acquisition module is used to acquire the operation data collected by the host sampling module; A slave data acquisition module is used to receive the parallel data frame transmitted by the last power supply device in the ring communication link, and obtain the operation data from the parallel data frame; The parameter setting module is used to update the set current and voltage according to the operation data corresponding to the multiple power supply devices obtained at each interval of the preset power supply control cycle, wherein the preset power supply control cycle is determined according to the preset parallel frame sending cycle and the number of power supply devices participating in the parallel operation.

[0079] The power synchronization control device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (Ultra-mobile per Sonal Computer, UMPC), a netbook or a personal digital assistant (per Sonal digital asSiStant, PDA), etc. It can also be a server, a network attached storage (Network AttaChed Storage, NAS), a personal computer (per Sonal Computer, PC), a television (teleViSion, tV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0080] The embodiment of the present application also provides an electronic device, including: a processor and a memory storing computer program instructions; when the processor executes the computer program instructions, the power synchronization control method as described above is implemented. The source meter provided in the embodiment of the present application can implement each process implemented in the embodiment of the power synchronization control method described above, and achieve the same beneficial effects, so to avoid repetition, it will not be repeated here.

[0081] An embodiment of the present application also provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or a control module, so that the above-mentioned processor can execute the power supply synchronization control method in the above-mentioned embodiment, for example, execute the method described above.

[0082] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0083] The functional blocks shown in the above structural block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier. "Machine-readable medium" may include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0084] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0085] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0086] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A power supply synchronization control method, characterized in that: Used to control multiple power supply devices in parallel, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module and a delayed output module, and the sampling module is used to collect the operation data output by the corresponding power supply device; the FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end, and multiple power supply devices are cyclically arranged in sequence through the FPGA optical fiber communication module, and multiple FPGA optical fiber communication modules are connected in series in sequence through the optical fiber transmitting end and the optical fiber receiving end to form a ring communication link; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; wherein each of the power supply devices has ID address information stored locally, and the ID address information corresponding to each of the power supply devices is different; The power supply synchronization control method is applied to the power supply device as a host, and the remaining power supply devices except the host are slaves. The power supply synchronization control method includes: At each interval of a preset parallel frame sending cycle, a parallel data frame is sent to the power supply device at the next position, the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address, and the echo acquisition address is sequentially updated according to the ID address information of multiple power supply devices at each interval of the preset parallel frame sending cycle; wherein, each of the slaves, upon receiving the parallel data frame, obtains the set current and the set voltage from the parallel data frame and stores them in a delay output module, and transmits the parallel data frame to the power supply device at the next position in the ring communication link, wherein, when the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used to delay the output of the set current and the set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; Acquire the operation data collected by the sampling module of the host; receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and acquiring the operating data from the parallel data frame; At each interval of a preset power control cycle, the set current and the set voltage are updated according to the acquired operating data corresponding to the plurality of power supply devices, wherein the preset power control cycle is determined according to the preset parallel frame sending cycle and the number of the power supply devices participating in the parallel operation.

2. The power supply synchronization control method according to claim 1, characterized in that: The slave processing and forwarding time taken by each of the slaves from receiving the parallel data frame transmitted by the previous power supply device to transmitting the parallel data frame to the next power supply device is less than the preset parallel frame sending cycle, and the slave processing and forwarding time is a predetermined fixed duration; The delay duration of the delayed output module corresponding to each of the power supply devices is determined according to the position of the power supply device in the ring communication link and the slave processing forwarding time, wherein the higher the position of the power supply device in the ring communication link, the longer the delay duration of the corresponding delayed output module.

3. The power supply synchronization control method according to claim 2, characterized in that: The slave machine processing forwarding time is half of the preset parallel machine frame sending period.

4. The power supply synchronization control method according to claim 1, characterized in that: The parallel data frame also includes a cumulative number of slave transmissions, and each of the slaves cumulatively updates the cumulative number of slave transmissions when receiving the parallel data frame; The power supply synchronization control method further includes: When the accumulated number of slave transmissions in the received parallel data frame is inconsistent with the number of the power supply devices participating in the parallel operation, a communication loss alarm is generated.

5. The power supply synchronization control method according to claim 1, characterized in that: The operation data corresponding to each of the power supply devices includes echo current data, and the operation data of the host also includes echo voltage data; The updating of the set current and the set voltage according to the acquired operation data corresponding to the plurality of power supply devices comprises: Determining the set current according to a preset parallel control current and the number of the power supply devices participating in the parallel operation; Using the echoed current data corresponding to the plurality of power supply devices, obtaining the echoed total current data; Determining the state of charge according to the total current data displayed; Obtaining a first output setting voltage according to the charge state and charge voltage correspondence table; According to the state of charge and charge internal resistance correspondence table, the real-time internal resistance is obtained; wherein the charge internal resistance correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of internal resistance information, and the charge voltage correspondence table indicates the correspondence between a plurality of the state of charge and a plurality of voltage information; Obtaining a first output setting current according to the first output setting voltage, the echoed voltage data of the host and the real-time internal resistance; Determine the wire voltage drop according to the first output set current and the echoed total current data; The set voltage is determined according to the wire voltage drop and the echoed voltage data of the host.

6. The power supply synchronization control method according to claim 5, characterized in that: The step of obtaining a first output setting current according to the first output setting voltage, the echoed voltage data of the host and the real-time internal resistance includes: Acquire a voltage difference between the first output setting voltage and the echo voltage data of the host; An ohmic operation is performed on the voltage difference and the real-time internal resistance to obtain the real-time internal resistance.

7. The power supply synchronization control method according to claim 5, characterized in that: The determining the wire voltage drop according to the first output setting current and the echoed total current data includes: Taking the first output setting current as a reference value and the total current data displayed as a feedback value, an incremental PID operation is performed to obtain a wire voltage drop increment; The wire voltage drop is updated according to the wire voltage drop increment and the wire voltage drop obtained last time.

8. A power supply synchronization control device, characterized in that: Used to control multiple power supply devices in parallel, each of which includes a control module, an FPGA optical fiber communication module, and a power supply actuator connected in sequence; each of the FPGA optical fiber communication modules is equipped with a sampling module and a delayed output module, and the sampling module is used to collect the operation data output by the corresponding power supply device; the FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end, and multiple power supply devices are cyclically arranged in sequence through the FPGA optical fiber communication module, and multiple FPGA optical fiber communication modules are connected in series in sequence through the optical fiber transmitting end and the optical fiber receiving end to form a ring communication link; the power supply actuator is used to output voltage and current according to the power supply output setting parameters; wherein each of the power supply devices has ID address information stored locally, and the ID address information corresponding to each of the power supply devices is different; The power supply synchronization control device is applied to the power supply device as a host, and the remaining power supply devices except the host are slaves. The power supply synchronization control device includes: A parallel frame period sending module, used for sending a parallel data frame to the next power supply device at each preset parallel frame sending period, wherein the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address, and the echo acquisition address is sequentially updated according to the ID address information of multiple power supply devices at each preset parallel frame sending period; wherein each slave, upon receiving the parallel data frame, obtains the set current and the set voltage from the parallel data frame and stores them in a delay output module, and transmits the parallel data frame to the next power supply device in the ring communication link, wherein, when the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame, the operating data collected by the acquisition module is written into the parallel data frame; the delay output module is used for delaying the output of the set current and the set voltage to the corresponding power actuator, so that multiple power actuators can adjust the output synchronously; A host data acquisition module, used to acquire the operation data collected by the sampling module of the host; A slave data acquisition module, used for receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and acquiring the operating data from the parallel data frame; A parameter determination module is used to update the set current and the set voltage at each interval of a preset power control cycle according to the acquired operation data corresponding to the multiple power supply devices, wherein the preset power control cycle is determined according to the preset parallel frame sending cycle and the number of the power supply devices participating in the parallel operation.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory storing computer program instructions; When the processor executes the computer program, the power supply synchronization control method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the power supply synchronization control method according to any one of claims 1 to 7.

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