Power supply synchronization control method and device, equipment and medium

Abstract

The application discloses a power supply synchronization control method and device, equipment and a medium, a complete one-way transmission optical communication ring communication link is constructed through an FPGA optical fiber communication module, so that the communication efficiency can be effectively improved, meanwhile, by periodically updating the setting current and the setting voltage, and by periodically sending and machine data frames by using the FPGA optical fiber communication module, the whole synchronization control process can adapt to the high-speed communication environment provided by the ring communication link, and further, a delay output module is used to complete synchronization output, so that efficient and high-synchronization synchronization control is realized, and output oscillation is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of source load equipment, in particular to a power supply synchronization control method and device, equipment and medium. BACKGROUND

[0002] At present, in order to solve the power requirement of large output demand in some scenarios, multiple power supply devices need to be parallelly connected. However, the existing parallel connection method is that the power supply device as the master directly communicates with each power supply device as the slave through 485 to transmit the adjustment parameters to the slave, and the slave completes the output adjustment after receiving the adjustment parameters. This adjustment method will cause poor synchronization due to large communication delay and slow response speed, and the slave may cause output oscillation, affecting the use effect. SUMMARY

[0003] The present application aims to provide a power supply synchronization control method, device, equipment and medium, which can effectively improve the synchronization of the power supply device.

[0004] The power supply synchronization control method according to the first aspect of the present application is used for parallel connection control of multiple power supply devices. Each power supply device includes a control module, an FPGA optical fiber communication module and a power supply execution mechanism connected in sequence. Each FPGA optical fiber communication module is internally provided with a sampling module and a delay output module. The sampling module is used for collecting operation data corresponding to the output of the power supply device. The FPGA optical fiber communication module has an optical fiber sending end and an optical fiber receiving end. Multiple power supply devices are sequentially and circularly arranged through the FPGA optical fiber communication module. Multiple FPGA optical fiber communication modules are sequentially connected through the optical fiber sending end and the optical fiber receiving end to form a ring communication link. The power supply execution mechanism is used for voltage and current output according to power output setting parameters. Each power supply device has locally stored ID address information, and the ID address information of each power supply device is different.

[0005] The power supply synchronization control method is applied to the power supply device as the master. The remaining power supply devices except the master are used as slaves. The power supply synchronization control method includes the following steps.

[0006] A slave machine receives the parallel data frame transmitted by the last power device in the ring communication link, and obtains the running data from the parallel data frame.

[0007] The running data collected by the sampling module of the master machine is obtained.

[0008] The running data collected by the sampling module of the master machine is obtained.

[0009] The running data collected by the sampling module of the master machine is obtained.

[0010] According to the second aspect of the present application, the power supply synchronization control device is used for parallel control of a plurality of power devices. Each of the power devices comprises a control module, an FPGA optical fiber communication module and a power execution mechanism connected in sequence. Each of the FPGA optical fiber communication modules is internally provided with a sampling module and a delay output module. The sampling module is used for collecting running data output by the corresponding power device. The FPGA optical fiber communication module has an optical fiber transmitting end and an optical fiber receiving end. A plurality of the FPGA optical fiber communication modules are sequentially and circularly arranged through the optical fiber transmitting end and the optical fiber receiving end, forming a ring communication link. The power execution mechanism is used for voltage and current output according to power output setting parameters. Each of the power devices locally stores ID address information, and the ID address information corresponding to each of the power devices is different.

[0011] The power supply synchronization control device is applied to the power device as the master machine, and the remaining power devices except the master machine are used as the slave machines. The power supply synchronization control device comprises:

[0012] The slave machine data acquisition module is configured to receive the parallel machine data frame transmitted by the last power device in the ring communication link, and acquire the running data from the parallel machine data frame.

[0013] The host machine data acquisition module is configured to acquire the running data collected by the sampling module of the host machine.

[0014] The slave machine data acquisition module is configured to receive the parallel machine data frame transmitted by the last power device in the ring communication link, and acquire the running data from the parallel machine data frame.

[0015] The setting parameter determination module is configured to update the setting current and the setting voltage according to the acquired running data of the plurality of power devices every preset power control period, wherein the preset power control period is determined according to the preset parallel machine frame transmission period and the number of the power devices participating in parallel machine.

[0016] The electronic device according to the third aspect of the present application comprises a processor and a memory storing computer program instructions.

[0017] The processor executes the computer program instructions to implement the power synchronization control method according to the first aspect.

[0018] The computer readable storage medium according to the fourth aspect of the present application stores computer executable instructions for executing the power synchronization control method according to the first aspect of the present application.

[0019] The power supply synchronization control method, device, equipment and medium provided by the embodiment of the present application can effectively improve the communication efficiency by constructing a complete one-way transmission optical communication ring communication link through the FPGA optical fiber communication module, and at the same time, by periodically updating the setting current and the setting voltage and periodically sending the data frame by the PGA optical fiber communication module, the whole synchronization control process can adapt to the high-speed communication environment provided by the ring communication link, and further, the delay output module is used to complete the synchronization output, so as to realize the high-efficiency and high-synchronization synchronization control, thereby effectively reducing the output oscillation.

[0020] Other features and advantages of the present application will be set forth in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the description of the embodiments, taken in conjunction with the following drawings in which:

[0022] Figure 1 A system schematic diagram of a parallel system provided by the embodiment of the present application;

[0023] Figure 2 A flowchart of a power supply synchronization control method provided by the embodiment of the present application;

[0024] Figure 3 A schematic diagram of a power supply synchronization control device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0025] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the drawings, in which the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation of the present application.

[0026] In the description of the present application, if the first, second, etc. are described, it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implying the number of the indicated technical features or the order of the indicated technical features.

[0027] In the description of the present application, it is understood that the position description, such as the position or location relationship indicated by up, down, etc. is based on the position or location relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation of the present application.

[0028] It should be noted that in the description of the present application, unless otherwise explicitly defined, the words such as setting, installing, connecting, etc. should be understood broadly, and the specific meanings of the above words in the present application can be determined by the person skilled in the art in combination with the specific content of the technical solutions.

[0029] The technical solutions of the present application will be described clearly and completely in combination with the drawings. Obviously, the following described embodiments are part of the embodiments of the present application, not all embodiments.

[0030] In order to better explain the power synchronization control method, device, equipment and medium of the embodiment of the present application, a parallel machine system is proposed here, referring to Figure 1 The parallel machine system includes a plurality of power supply devices, each power supply device being a bidirectional power supply device, each power supply device including a control module, an FPGA optical fiber communication module and a power supply execution mechanism connected in sequence; each FPGA optical fiber communication module is internally provided with a sampling module and a delay output module, the sampling module being used to collect running data output by the corresponding power supply device; the FPGA optical fiber communication module has an optical fiber sending end and an optical fiber receiving end, the plurality of power supply devices being sequentially and circularly arranged through the FPGA optical fiber communication module, the plurality of FPGA optical fiber communication modules being sequentially connected in series through the optical fiber sending end and the optical fiber receiving end to form a ring-shaped communication link; the power supply execution mechanism is used to output voltage and current according to power output setting parameters; wherein each power supply device has locally stored ID address information, and the ID address information corresponding to each power supply device is different.

[0031] The above-mentioned control module can be connected to a man-machine interaction unit, and an operator can actively adjust the settings of each power supply device through the man-machine interaction unit.

[0032] The above-mentioned delay output module can realize delay output of data, and the specific delay time can be manually set in advance.

[0033] Each power supply device includes an FPGA optical fiber communication module, which is constructed with FPGA as the core module. RAM units can be constructed in FPGA, and data storage can be completed by using the RAM units. In the embodiments of the present application, because high-speed data transmission is involved, RAM units are provided for data caching, which plays an important role in preventing data loss.

[0034] The above-mentioned FPGA optical fiber communication module includes a collection module, which can complete collection of voltage, current and other running data of the output end of the power supply device.

[0035] Specifically, the collection module can select a 16-bit ADC chip, or a higher precision or lower precision ADC chip can be selected according to actual needs.

[0036] In the parallel operation, one power supply device can be selected as the master (such as the power supply device A shown in Figure 1 , and the rest of the power supply devices are slaves (such as the power supply devices B and C shown in Figure 1 ).

[0037] The above-mentioned ring communication link can be understood as a ring for master data downlink. When the power supply device as the master needs to transmit data to each slave, it writes key information such as set current, set voltage, echo address, and start instruction into the parallel data frame, and then transmits it to each slave in turn through the ring communication link.

[0038] Specifically, the first position of the ring communication link can be understood as the master, and the next position until the last position are slaves. The communication process of the ring communication link is in the form of a ring. Taking the parallel data frame as an example, the parallel data frame is first transmitted to the slave at the second position. The slave at the second position obtains the set current and the set voltage from the parallel data frame and transmits the parallel data frame to the slave at the third position, and repeats the above-mentioned process of obtaining the current information and the process of forwarding, until the parallel data frame is transmitted to the slave at the last position, and the parallel data frame is transmitted back to the master through the slave at the last position.

[0039] The above-mentioned control module can be provided with a preset cache area. The parallel data frame to be issued by the master can be stored in the preset cache area. When the set current and the set voltage calculated each time change, the parallel data frame in the preset cache area can be updated.

[0040] Each power supply device has an ID address information stored locally, and the ID address information corresponding to each power supply device is different. The ID address information can be used to better obtain the running data of the slave. The ID address information of the above-mentioned multiple power supply devices can be set in order, for example, starting from 1 and increasing one by one.

[0041] The power supply synchronization control method, device, equipment and medium of the embodiments of the application based on the above-mentioned power supply system are described below.

[0042] Referring to Figure 2 , Figure 2 is a flowchart of a power supply synchronization control method provided by an embodiment of the application. The power supply synchronization control method is used for synchronous discharge control of multiple power supply devices in the battery simulation process, and is applied to a power supply device as a master, and includes the following steps.

[0043] The slave device receives the synchronization data frame transmitted by the master device, and acquires the setting current and the setting voltage from the synchronization data frame and stores them in a delay output module.

[0044] The sampling module of the master device acquires the running data.

[0045] The slave device receives the synchronization data frame transmitted by the master device, and acquires the setting current and the setting voltage from the synchronization data frame and stores them in a delay output module.

[0046] The slave device receives the synchronization data frame transmitted by the master device, and acquires the setting current and the setting voltage from the synchronization data frame and stores them in a delay output module.

[0047] The slave device receives the synchronization data frame transmitted by the master device, and acquires the setting current and the setting voltage from the synchronization data frame and stores them in a delay output module.

[0048] The slave device receives the synchronization data frame transmitted by the master device, and acquires the setting current and the setting voltage from the synchronization data frame and stores them in a delay output module.

[0049] The echo acquisition address can be updated once before each transmission of the parallel data frame, and is updated in a cyclic manner, so that the host can complete polling of the running data in all power supply devices after transmitting a number of parallel data frames equal to the number of power supply devices participating in parallel. In addition, it should be noted that in the case where multiple echo acquisition addresses can be stored in one parallel data frame, the ID address information of multiple slaves can be processed in batches, so that the running data of multiple slaves can be obtained by transmitting one parallel data frame, thereby reducing the number of parallel data frames to be transmitted.

[0050] When the slave acquires the parallel data frame, it first acquires the set current and set voltage in the parallel data frame and stores them in the delay output module, then checks the echo acquisition address in the parallel data frame to determine whether it is consistent with the ID address information stored locally, and in the case of consistency, writes the collected running data into the parallel data frame, so that the running data can be returned to the host through the parallel data frame. After polling all ID address information once, the host can acquire the running data of all power supply devices, thereby updating the set current and set voltage to update the set current and set voltage in the parallel data frame. As can be seen, the scheme in the embodiment of the application can complete synchronous control using only one parallel data frame, and the data transmission logic is simpler, which can better ensure the reliability of synchronous control.

[0051] The delay output module can delay the time of outputting the set current and set voltage to the power supply actuator, so that multiple power supply devices can complete the output synchronously. Specifically, the delay output module with an earlier bit position needs to be delayed for a longer time because it writes the set current and set voltage earlier, and the delay time for the delay output module with a later bit position needs to be shortened because it writes the set current and set voltage later. In some embodiments, the time from when each slave receives the parallel data frame using the FPGA fiber communication module to when it re-emits the parallel data frame can be fixed, so that the fixed time can be multiplied by the bit position information to determine the delay time for each delay output module.

[0052] The time at which the power supply actuator receives the set current and set voltage is kept highly synchronized due to the presence of the delay output module, so that it can adjust the output in real time after receiving the set current and set voltage.

[0053] The sampling module of the host and slave can be executed periodically.

[0054] The running data of the host can be obtained when the echo acquisition address in the parallel data frame is updated to the ID address information, or can be obtained before the current setting and the current setting update in the parallel data frame are set.

[0055] The host can obtain the parallel data frame returned by the last slave, and the echo acquisition address in the parallel data frame is updated by polling according to the ID address information, so that the running data of all slaves can be obtained.

[0056] The preset power supply control period is determined according to the preset parallel frame sending period and the number of power supply devices participating in parallel, which can be understood as the product of the preset parallel frame sending period and the number of power supply devices participating in parallel, which is still less than the preset power supply control period. For example, in the case of 10 power supply devices participating in parallel, the host obtains the running data of all slaves only needs up to 10 parallel data frames, assuming that the preset parallel frame sending period can be 512ns, then the time of obtaining all power supply device running data is about 5.12us, then the preset power supply control period can be 50us. And the preset power supply control period will change adaptively when the preset parallel frame sending period changes and the number of parallel changes, so as to improve the real-time performance of synchronous control.

[0057] In some embodiments, the slave processing and forwarding time spent by each slave from receiving the parallel data frame transmitted by the last power supply device to transmitting the parallel data frame to the next power supply device is less than the preset parallel frame sending period, and the slave processing and forwarding time is a predetermined fixed time length;

[0058] The delay time of the delay output module corresponding to each power supply device is determined according to the position of the power supply device in the ring communication link and the slave processing and forwarding time, wherein the earlier the position of the power supply device in the ring communication link, the longer the delay time of the corresponding delay output module.

[0059] The slave processing and forwarding time is a predetermined fixed time length, for example, in some scenarios, the slave processing and forwarding time spent by the slave from receiving the parallel data frame transmitted by the last power supply device to transmitting the parallel data frame to the next power supply device is about 128ns, but there may be some fluctuations due to various reasons. In order to avoid the influence of the time fluctuation on data transmission, a certain delay can be set to avoid it, for example, the slave processing and forwarding time is set to 256ns.

[0060] The slave processing and forwarding time is less than the preset parallel frame sending period, which can make each power supply device have a certain time gap for other data processing, realizing time division multiplexing.

[0061] The delay time of the delay output module corresponding to each power supply device is closely related to the bit position of the power supply device in the ring communication link. Due to the characteristics of the ring communication link, the power supply device with an earlier bit position receives the data frame of the master device earlier. In order to synchronize the setting current and the setting voltage transmitted to the power supply execution device, the delay time of the delay output module of the power supply device with different bit positions needs to be set differently. For example, for N bit positions, the delay time of the delay output module of the power supply device with the first bit position, i.e., the master device, is N times 256 ns, the delay time of the delay output module of the power supply device with the second bit position, i.e., the first slave device, is (N-1) times 256 ns, and so on. Thus, the delay time of the delay output module corresponding to all power supply devices can be determined.

[0062] In some embodiments, the forwarding time of the slave device is half of the preset data frame transmission period.

[0063] In the embodiment, the forwarding time of the slave device is set to half of the preset data frame transmission period, so that general time is reserved for the slave device to perform data processing other than synchronization operation. Thus, the slave device has sufficient time to complete the remaining data processing process irrelevant to output control, and has time to receive the remaining ordinary data frame irrelevant to data frame transmission irrelevant to data frame transmission.

[0064] In some embodiments, the data frame further includes a slave device transmission cumulative number, and each slave device updates the slave device transmission cumulative number when receiving the data frame.

[0065] The power supply synchronization control method further includes:

[0066] In the case that the slave device transmission cumulative number in the received data frame is inconsistent with the number of power supply devices participating in data frame transmission, a communication loss alarm is generated.

[0067] In the above embodiment, the slave device transmission cumulative number is updated when the slave device receives the data frame, for example, the first slave device is updated to 1, and the second slave device is updated to 2. Each slave device updates in turn. When no problem occurs in the entire data transmission process, the slave device transmission cumulative number is consistent with the number of slave devices, so that the master device can determine whether the transmission is problematic by determining whether the slave device transmission cumulative number is consistent with the number of slave devices after receiving the data frame.

[0068] In the embodiment, the slave device transmission cumulative number is set in the data frame, so that whether the data is transmitted to each slave device can be determined by the slave device transmission cumulative number. In the case that the slave device transmission cumulative number is inconsistent with the number of slave devices, an alarm is generated in time to remind the operator to handle the fault in time.

[0069] In some embodiments, a communication failure alarm is generated if no parallel data frame is received for more than a preset power supply control period.

[0070] In this embodiment, if the host cannot receive the returned parallel data frame for a long time, it indicates that the communication link is disconnected, and a communication failure alarm can be generated in time to remind the operator to handle the failure in time.

[0071] The above-mentioned parallel data frame can include the following parts:

[0072] 1. Frame header: special characters such as 0x55a105bc and 0x55a106bc can be used, and it should be noted that the lowest byte is 0xbc, which uses K28.5 as K code for data alignment control.

[0073] 2. Flag: host ID (2B) + reserved (1B) + normal read / write / parallel data flag (1B, 0x00 indicates normal read / write, and 0x01 indicates parallel data);

[0074] 3. Data 1: the set voltage sent by the host to each slave;

[0075] 4. Data 2: the set current sent by the host to each slave;

[0076] 5. Data 3: the echo acquisition address (high 16 bits) corresponding to the current polled slave + event (low 16 bits); the event is mainly ON and OFF signals, that is, whether to perform parallel operation;

[0077] 6. Data 4: working mode (high 16 bits) + slave number (16th bit): wherein the working mode indicates the current working mode of the host (such as normal mode, sequence mode, etc.), and the slave power supply actuator can select different loop parameters for output control according to the working mode of the host; the slave transmission cumulative number is increased by 1 every time a slave is passed, and finally the host judges whether the real slave transmission cumulative number in the parallel network is consistent with the set slave number, if not, it indicates that the parallel configuration is wrong, and an alarm is prompted;

[0078] 7. Data 5: echo current data of the polled slave: when the echo acquisition address in data 3 is consistent with the locally stored ID address information, the collected echo current data is filled into data 5;

[0079] 8、Data 6-10: This data is reserved extension data. When the number of parallel machines is large, the echo acquisition address of the current slave machine in the data 3 can be modified to indicate polling a group of slave machines, that is, adding the data 5. Every 6 slave machines are represented as a slave machine group. The slave machines belonging to the polling group fill the echo current data into the data 5-10 in the parallel machine data frame in turn. In this way, when a parallel machine data frame completes the loop back to the host, the current sampling data of 6 slave machines can be obtained, thereby improving the acquisition efficiency of echo data;

[0080] 9、Checksum: The cumulative sum of the flag and the data 1-10;

[0081] 10、Frame tail: Special characters such as 0x55a107bc and 0x55a108bc are used. Note that the lowest byte is 0xbc, which uses K28.5 as K code for data alignment control.

[0082] In some embodiments, the operating data corresponding to each power supply device includes echo current data, and the operating data of the host further includes echo voltage data;

[0083] According to the obtained operating data corresponding to the plurality of power supply devices, the set current and the set voltage are updated, comprising:

[0084] According to the preset parallel machine control current and the number of power supply devices participating in parallel machine, the set current is determined;

[0085] The echo total current data is obtained by using the echo current data corresponding to the plurality of power supply devices;

[0086] The state of charge is determined according to the echo total current data;

[0087] The first output set voltage is obtained according to the state of charge and the state of charge-voltage correspondence table;

[0088] The real-time internal resistance is obtained according to the state of charge and the state of charge-internal resistance correspondence table. The state of charge-internal resistance correspondence table indicates the correspondence between the plurality of states of charge and the plurality of internal resistance information, and the state of charge-voltage correspondence table indicates the correspondence between the plurality of states of charge and the plurality of voltage information;

[0089] The first output set current is obtained according to the first output set voltage, the echo voltage data of the host and the real-time internal resistance;

[0090] The wire voltage drop is determined according to the first output set current and the echo total current data;

[0091] The set voltage is determined according to the wire voltage drop and the echo voltage data of the host.

[0092] In the embodiment of the present application, the parallel machine control strategy is adopted, therefore, the output ports of the plurality of power supply devices are arranged in parallel, under the parallel arrangement, the current is superimposed and the voltage is the same, therefore, the output voltage of each power supply device can be determined by only obtaining the echo voltage data of the host.

[0093] The preset parallel machine control current can be understood as the total demand for the output current of the parallel machine control power supply system. In the present embodiment, the setting current is obtained by dividing the preset parallel machine control current by the number of power supply devices participating in the parallel machine control.

[0094] The echo total current data can be understood as the sum of the echo current data of the plurality of power supply devices.

[0095] The state of charge determined according to the echo total current data can be understood as the integral of the echo total current data, by determining the period for obtaining the echo total current data in a small time length, the determined state of charge can be extremely close to the actual situation.

[0096] The state of charge-voltage correspondence table indicates the correspondence between the plurality of states of charge and the plurality of voltage information, that is, after determining a state of charge, the corresponding voltage information can be obtained by table lookup.

[0097] Specifically, the state of charge-internal resistance correspondence table shows the relationship between the state of charge and the corresponding voltage information in a certain scale value, as shown in Table 1, the data in Table 1 can be expanded according to the actual situation, and the specific number of rows is not limited.

[0098] Table 1

[0099]

[0100] In Table 1, Soc1 can be understood as the state of charge amplified by 100 times, and the corresponding voltage scale in Table 1 can be understood as the voltage information, that is, the scale value required for subsequent calculation of the set voltage using the maximum open circuit voltage, for example, the state of charge is 0.6080318193, the calculated Soc1 is 60.80318193, and the corresponding voltage scale is 0.972853458, assuming that the open circuit voltage is 10 volts, then the set voltage calculated using the voltage scale is 9.72853458 volts.

[0101] The maximum open circuit voltage can be input by the user through the man-machine interaction interface.

[0102] The state of charge-internal resistance correspondence table can indicate the correspondence between the plurality of states of charge and the plurality of internal resistance information, that is, after determining a state of charge, the corresponding internal resistance information can be obtained by table lookup.

[0103] Specifically, the charging state and the corresponding internal resistance information can be displayed in a certain proportion value by the charging internal resistance corresponding table. As shown in Table 2, the data in Table 2 can be expanded according to actual situation needs, and the specific number of rows is not limited.

[0104] Table 2

[0105]

[0106] In Table 2, Soc2 can be understood as 100 times magnification of the charging state. The corresponding internal resistance proportion in Table 2 can be understood as internal resistance information, that is, the proportion required for subsequent maximum internal resistance calculation of the current internal resistance. For example, the charging state is 0.6080318193, and the calculated Soc2 is 60.80318193. At this time, the value cannot be found, and the closest Soc2 is selected for confirmation, that is, Soc2 is confirmed as 60.58506543, and the corresponding voltage proportion is 0.671063479. Assuming that the maximum internal resistance is 1 ohm, the current internal resistance calculated by the internal resistance proportion is 0.671063479 ohm.

[0107] The above maximum internal resistance can be obtained by user input through a man-machine interaction interface.

[0108] The above first output set voltage can be obtained by looking up the voltage proportion by the charging state after determining the charging state, and then multiplying the maximum open circuit voltage and the voltage proportion obtained by looking up the table.

[0109] The above real-time internal resistance can be obtained by looking up the internal resistance proportion by the charging state after determining the charging state, and then multiplying the maximum internal resistance and the internal resistance proportion obtained by looking up the table.

[0110] The above first output set current can be determined by Ohm operation using the first output set voltage, the echo voltage data of the host, and the real-time internal resistance.

[0111] The above wire voltage drop is obtained by using PID algorithm, taking the first output set current as the target value and the echo total current data as the feedback value, so that the wire voltage drop can be quickly determined.

[0112] The above set voltage considers the existence of the wire voltage drop, and can be obtained by summing the wire voltage drop and the echo voltage data of the host.

[0113] In the embodiment, the wire pressure drop is quickly determined by using the first output setting current and the echo total current data to obtain the setting voltage most suitable for the control requirement, considering the influence of the wire pressure drop on the actual output adjustment control. In addition, the PID algorithm is used to determine the wire pressure drop, considering the influence of the wire length, the conductive performance and other difficult-to-measure factors on the wire resistance, so that the difficulty of obtaining the wire length, the conductive performance and other difficult-to-measure factors can be avoided.

[0114] In some embodiments, the first output setting current is obtained according to the first output setting voltage, the echo voltage data of the host and the real-time resistance, including:

[0115] obtaining a voltage difference value of the first output setting voltage and the echo voltage data of the host;

[0116] performing ohm operation on the voltage difference value and the real-time resistance to obtain the real-time resistance.

[0117] In the embodiment, the ohm operation is performed on the voltage difference value of the first output setting voltage and the echo voltage data of the host and the real-time resistance, so that the real-time resistance can be quickly obtained.

[0118] In some embodiments, the wire pressure drop is determined according to the first output setting current and the echo total current data, including:

[0119] performing incremental PID operation on the first output setting current as a reference value and the echo total current data as a feedback value to obtain a wire pressure drop increment;

[0120] updating the wire pressure drop according to the wire pressure drop increment and the wire pressure drop obtained last time.

[0121] In the embodiment, the incremental PID algorithm is used, the wire pressure drop increment is obtained by using the first output setting current as a reference value and the echo total current data as a feedback value, and then the incremental operation is performed on the wire pressure drop obtained last time, so that the wire pressure drop more suitable for the actual situation can be obtained.

[0122] In the embodiment, the incremental PID algorithm can refer to the following:

[0123] ;

[0124] In the formula, is the wire pressure drop increment; is the Kth current deviation, i.e., the current deviation, is the k-1th deviation, is the k-2th deviation; , , is a preset coefficient, which can be obtained by debugging according to the actual situation;

[0125] Set the difference between the current and the echo total current data for the first output.

[0126] The power supply synchronization control method provided by the embodiments of the present application can be executed by a power supply synchronization control device. The power supply synchronization control device provided by the embodiments of the present application is described by taking the power supply synchronization control device executing the power supply synchronization control method as an example.

[0127] The embodiments of the present application further provide a power supply synchronization control device, as shown in the accompanying drawings, the power supply synchronization control device comprises: Figure 3

[0128] The parallel frame period sending module is configured to send a parallel data frame to a next-order power supply device every interval of a preset parallel frame sending period, and the parallel data frame at least includes a set current, a set voltage, and an echo acquisition address, and the echo acquisition address is updated according to ID address information of the plurality of power supply devices in sequence every interval of the preset parallel frame sending period; wherein, each slave machine acquires the set current and the set voltage from the parallel data frame and stores them to the delay output module under the condition of receiving the parallel data frame, and transmits the parallel data frame to the next-order power supply device in the ring communication link, and wherein, under the condition that the ID address information stored locally by the slave machine is consistent with the echo acquisition address in the received parallel data frame, the running data collected by the collection module is written into the parallel data frame; the delay output module is configured to delay outputting the set current and the set voltage to corresponding power supply actuators, so as to synchronize the output of the plurality of power supply actuators.

[0129] The host data acquisition module is configured to acquire running data collected by a sampling module of the host.

[0130] The slave machine data acquisition module is configured to receive a parallel data frame transmitted by the last power supply device in the ring communication link, and acquire running data from the parallel data frame.

[0131] The set parameter determination module is configured to update the set current and the set voltage according to the acquired running data of the plurality of power supply devices every interval of a preset power supply control period, and wherein, the preset power supply control period is determined according to the preset parallel frame sending period and the number of power supply devices participating in parallel operation.

[0132] ​The power supply synchronization control device in the embodiments of the present application can be an electronic device or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other device other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an Ultra-mobile Personal Computer (UMPC), a netbook, or a Personal Digital Assistant (PDA), and can also be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a television (TV), a teller machine, or a self-service machine, and the like, and the embodiments of the present application are not limited in this regard.

[0133] The embodiments of the present application also provide an electronic device, which comprises a processor and a memory storing computer program instructions; and the processor implements the power supply synchronization control method as described above when executing the computer program instructions. The power supply table provided by the embodiments of the present application can implement each process of the power supply synchronization control method embodiments and achieve the same beneficial effects, and to avoid repetition, details are not described herein.

[0134] The embodiments of the present application also provide a computer readable storage medium storing computer executable instructions, which are executed by a processor or a control module, and can enable the processor to execute the power supply synchronization control method in the above embodiments, for example, the method described above.

[0135] It should be noted that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted herein. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order of the steps, after understanding the spirit of the present application.

[0136] The functional blocks shown in the structural block diagrams above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, and the like. When implemented in software, the elements of the present application are program or code segments that are used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. A "machine-readable medium" includes any medium that can store or transfer information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, and the like. The code segments can be downloaded via computer networks such as the Internet, intranet, and the like.

[0137] It is also important to note that the examples mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the examples, or in a different order from the examples, or several steps can be performed simultaneously.

[0138] The above describes the aspects of the present application with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and the combination of blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus enable the implementation of the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams. Such a processor can be a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can also be implemented by special hardware that performs the specified functions or actions, or can be implemented by a combination of special hardware and computer instructions.

[0139] The above is only a specific embodiment of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, modules and units can refer to the corresponding processes in the foregoing method embodiments, which will not be described here. It should be understood that the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A power synchronization control method, characterized by, The application relates to a parallel control method for multiple power supply devices, each of which comprises a control module, an FPGA fiber communication module and a power supply execution mechanism connected in sequence; each of the FPGA fiber communication modules is internally provided with a sampling module and a delay output module, the sampling module is used for collecting operation data output by the corresponding power supply device; the FPGA fiber communication module has a fiber sending end and a fiber receiving end, the multiple power supply devices are sequentially and circularly arranged through the FPGA fiber communication modules, the multiple FPGA fiber communication modules are sequentially connected through the fiber sending end and the fiber receiving end to form a ring communication link; the power supply execution mechanism is used for outputting voltage and current according to power supply output setting parameters; wherein each of the power supply devices locally stores ID address information, and the ID address information corresponding to each of the power supply devices is different; The power supply synchronization control method is applied to the power supply device as a master, and the rest of the power supply devices except the master are slaves; the power supply synchronization control method comprises the following steps: Every interval preset parallel frame sending period, send parallel data frame to the next bit of the power supply device, the parallel data frame at least includes set current, set voltage, echo address, the echo address every interval preset parallel frame sending period according to the ID address information of multiple power supply devices is updated in turn; wherein, each of the slaves in the case of receiving the parallel data frame, from the parallel data frame, the set current and the set voltage are stored to the delay output module, and the parallel data frame is transmitted to the next bit of the power supply device in the ring communication link, wherein, in the case that the ID address information stored locally in the slave is consistent with the echo address in the received parallel data frame, the operation data collected by the collection module is written into the parallel data frame; the delay output module is used for delaying the output of the set current and the set voltage to the corresponding power supply execution mechanism, so that the multiple power supply execution mechanisms are synchronously adjusted and outputted; Collecting operation data collected by the sampling module of the master; Receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and obtaining the operation data from the parallel data frame; Every interval preset power supply control period, according to the obtained operation data corresponding to multiple power supply devices, updating the set current and the set voltage, wherein, the preset power supply control period is determined according to the preset parallel frame sending period and the number of power supply devices participating in parallel.

2. The power synchronization control method of claim 1, wherein Each of the slaves from receiving the parallel data frame transmitted by the last power supply device to transmitting the parallel data frame to the next power supply device takes a slave processing and forwarding time less than the preset parallel frame sending period, and the slave processing and forwarding time is a predetermined fixed time length. The delay time length of the delay output module corresponding to each power supply device is determined according to the position of the power supply device in the ring communication link and the slave processing forwarding time, wherein the earlier the position of the power supply device in the ring communication link, the longer the delay time length of the delay output module corresponding to the power supply device.

3. The power synchronization control method of claim 2, wherein The slave processing forwarding time is half of the preset parallel frame sending period.

4. The power synchronization control method of claim 1, wherein The parallel data frame further comprises a slave transmission cumulative number, and each slave updates the slave transmission cumulative number cumulatively upon receiving the parallel data frame. The power supply synchronization control method further comprises: In the case that the slave transmission cumulative number in the received parallel data frame is inconsistent with the number of power supply devices participating in parallel, a communication loss alarm is generated.

5. The power synchronization control method of claim 1, wherein The running data corresponding to each power supply device comprises echo current data, and the running data of the host further comprises echo voltage data. The updating of the setting current and the setting voltage according to the obtained running data corresponding to the plurality of power supply devices comprises: determining the setting current according to a preset parallel control current and the number of power supply devices participating in parallel; obtaining echo total current data by using echo current data corresponding to the plurality of power supply devices; determining a state of charge according to the echo total current data; obtaining a first output setting voltage according to a state of charge and voltage corresponding relationship table; obtaining a real-time internal resistance according to a state of charge and internal resistance corresponding relationship table; wherein the state of charge and internal resistance corresponding relationship table indicates the corresponding relationship between a plurality of states of charge and a plurality of internal resistance information, and the state of charge and voltage corresponding relationship table indicates the corresponding relationship between a plurality of states of charge and a plurality of voltage information; obtaining a first output setting current according to the first output setting voltage, echo voltage data of the host, and the real-time internal resistance; determining a wire voltage drop according to the first output setting current and the echo total current data; determining the setting voltage according to the wire voltage drop and the echo voltage data of the host.

6. The power synchronization control method of claim 5, wherein The obtaining of the first output setting current according to the first output setting voltage, the echo voltage data of the host, and the real-time internal resistance comprises: obtaining a voltage difference value of the first output setting voltage and the echo voltage data of the host; performing ohm operation on the voltage difference value and the real-time internal resistance to obtain the real-time internal resistance.

7. The power synchronization control method of claim 5, wherein The determination of the wire voltage drop according to the first output setting current and the echo total current data comprises: performing incremental PID operation by taking the first output setting current as a reference value and the echo total current data as a feedback value to obtain a wire voltage drop increment; and updating the wire voltage drop according to the wire voltage drop increment and the wire voltage drop obtained last time.

8. A power synchronization control device, characterized by comprising: The application relates to a parallel control device for multiple power supply devices, each of which comprises a control module, an FPGA fiber communication module and a power supply execution mechanism connected in sequence; each of the FPGA fiber communication modules is internally provided with a sampling module and a delay output module, the sampling module is used for collecting operation data output by the corresponding power supply device; the FPGA fiber communication module has a fiber sending end and a fiber receiving end, the multiple power supply devices are sequentially and circularly arranged through the FPGA fiber communication modules, the multiple FPGA fiber communication modules are sequentially connected through the fiber sending end and the fiber receiving end to form a ring communication link; the power supply execution mechanism is used for outputting voltage and current according to power supply output setting parameters; wherein each of the power supply devices locally stores ID address information, and the ID address information of each of the power supply devices is different. The power supply synchronous control device is applied to the power supply device as a master, and the rest of the power supply devices as slaves except the master; the power supply synchronous control device comprises: A parallel frame period sending module is used for sending a parallel data frame to the next order power supply device every interval of a preset parallel frame sending period, the parallel data frame at least comprises a setting current, a setting voltage and an echo acquisition address, the echo acquisition address is sequentially updated according to the ID address information of the multiple power supply devices every interval of the preset parallel frame sending period; wherein each of the slaves acquires the setting current and the setting voltage from the parallel data frame and stores them to a delay output module under the condition of receiving the parallel data frame, and transmits the parallel data frame to the next order power supply device in the ring communication link, wherein the operation data collected by the collection module is written into the parallel data frame under the condition that the ID address information locally stored in the slave is consistent with the echo acquisition address in the received parallel data frame; the delay output module is used for delaying the output of the setting current and the setting voltage to the corresponding power supply execution mechanism, so that the multiple power supply execution mechanisms synchronously adjust the output; A master data acquisition module is used for acquiring the operation data collected by the sampling module of the master; A slave data acquisition module is used for receiving the parallel data frame transmitted by the last power supply device in the ring communication link, and acquiring the operation data from the parallel data frame; A setting parameter determination module is used for updating the setting current and the setting voltage according to the acquired operation data of the multiple power supply devices every interval of a preset power supply control period, wherein the preset power supply control period is determined according to the preset parallel frame sending period and the number of the power supply devices participating in parallel connection.

9. An electronic device, comprising: The electronic device comprises a processor and a memory storing computer program instructions; The processor executes the computer program to realize the power supply synchronous control method in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions for causing a computer to perform the power synchronization control method according to any one of claims 1 to 7.

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