Memory device with vertical transistor and method of forming same

Abstract

A memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a memory device coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. A bit line is connected to a second end of the semiconductor body of the row of vertical transistors. The bit line includes a semiconductor epitaxial layer extending in a second direction and connected to a second end of the semiconductor body of the row of vertical transistors at a top surface of the semiconductor epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method of manufacturing the same. Background Art

[0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing techniques become challenging and costly. As a result, the storage density of planar memory cells approaches an upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuits for facilitating operation of the memory array. Summary of the invention

[0004] Aspects of the present disclosure provide a method for manufacturing a memory device. A stack including a first semiconductor layer is formed. The stack includes a second semiconductor layer above the first semiconductor layer, a third semiconductor layer above the second semiconductor layer, and a fourth semiconductor layer above the third semiconductor layer. The stack is etched through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to form a first trench along a first direction and on the first semiconductor layer. The first trench is filled with an insulating material to form a trench isolation. The fourth semiconductor layer, the third semiconductor layer, and the remaining portion of the second semiconductor layer are sandwiched by adjacent trench isolations. The remaining portion of the fourth semiconductor layer and the trench isolation are etched to form a second trench on the third semiconductor layer and along a second direction perpendicular to the first direction, and a semiconductor body of a vertical transistor extending in a third direction and surrounded by the second trench and the trench isolation. The third direction is perpendicular to the first direction and the second direction. The vertical transistor is located on top of the remaining portion of the third semiconductor layer. A gate structure of the vertical transistor is formed, the gate structure being along the second direction and coupled to at least one side of the semiconductor body.

[0005] In one aspect, a memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a storage element coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to the second end of the semiconductor body of a row of vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected to the second end of the semiconductor body of the row of vertical transistors at a top surface of the semiconductor epitaxial layer.

[0006] In one aspect, a memory system includes a memory controller and a memory device coupled to the memory controller. The memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body extending vertically in a first direction. Each memory cell includes a storage element coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to a second end of the semiconductor body of a row of vertical transistors. The bit line includes a semiconductor epitaxial layer extending in a second direction and connected to the second end of the semiconductor body of the row of vertical transistors at a top surface of the semiconductor epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be increased or reduced for clarity of discussion.

[0008] Figure 1 A block diagram of an exemplary system having a storage device according to some aspects of the present disclosure is shown.

[0009] Figure 2 A schematic diagram of a memory device including peripheral circuits and an array of memory cells each having a vertical transistor is shown according to some aspects of the present disclosure.

[0010] Figure 3 A schematic circuit diagram of a memory device including peripheral circuits and an array of dynamic random access memory (DRAM) cells according to some aspects of the present disclosure is shown.

[0011] Figure 4 A schematic circuit diagram of a memory device including peripheral circuits and an array of phase change memory (PCM) cells according to some aspects of the present disclosure is shown.

[0012] Figure 5A-5B A memory device manufacturing process is shown, wherein a semiconductor body 502 of a vertical transistor is formed without employing an etch stop layer.

[0013] Fig. 6A , Figure 6B and Figure 6C A memory device manufacturing process is shown, in which an etch stop layer is used to improve the bottom profile uniformity and etching depth uniformity of isolation trenches and word line trenches and back side bit line silicon recesses.

[0014] Figure 7 A plan view of an array of memory cells 702 each including a vertical transistor in a memory device 700 is shown in accordance with some aspects of the present disclosure.

[0015] Figure 8 A side view of a cross section of a memory device 800 made by employing an etch stop layer according to some aspects of the present disclosure is shown.

[0016] Figure 9A-1 / Figure 9A-2 Figure / 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figures 9D-9J A manufacturing process for forming a memory device, such as memory device 700 or 800 , by using several etch stop layers is shown in accordance with some aspects of the present disclosure.

[0017] Fig.10 A flow chart of a manufacturing process 1000 for forming a 3D memory device including vertical transistors according to some aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0018] Although specific configurations and arrangements have been discussed, it should be understood that this is done only for the purpose of illustration. Therefore, other configurations and arrangements may be used without departing from the scope of the present disclosure. In addition, the present disclosure may also be used for various other applications. Functions and structural features as described in the present disclosure may be combined, adjusted and modified with each other and in a manner not specifically shown in the accompanying drawings, so that these combinations, adjustments and modifications are within the scope of the present disclosure.

[0019] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one" or "the" can also be understood to express singular usage or to express plural usage. In addition, the term "based on" can be understood to not necessarily be intended to express a set of exclusive elements, but can allow the presence of other elements that are not necessarily explicitly described, which also depends at least in part on the context.

[0020] It should be readily understood that the meanings of “on,” “over,” and “over” in the present disclosure should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “over” means not only the meaning of “above something” or “on something,” but also includes the meaning of “it is over something” or “it is over something” without intervening features or layers therebetween (i.e., directly on something).

[0021] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or multiple) element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0023] As used herein, the term "layer" refers to a material portion including an area with a thickness. A layer may extend over the entire lower or upper structure, or may have a range that is less than the range of the lower or upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top surface and the bottom surface of a continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, wherein one or more layers may be included, and / or one or more layers may be provided on, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (wherein interconnect lines and / or vertical interconnect path (via) contacts are formed) and one or more dielectric layers.

[0024] I. Memory Device with Vertical Transistors

[0025] Transistors are used as switches or selection devices in memory cells of some memory devices, such as dynamic random access memory (DRAM), phase change memory (PCM), and ferroelectric DRAM (FRAM). However, planar transistors commonly used in existing memory cells generally have a horizontal structure, in which the buried word line is in the substrate and the bit line is above the substrate. Since the source and drain of the planar transistor are laterally arranged at different positions, this increases the area occupied by the transistor. The design of the planar transistor also complicates the arrangement of the interconnection structure (such as word lines and bit lines) coupled to the memory cell, for example, limiting the spacing of the word lines and / or bit lines, thereby increasing manufacturing complexity and reducing yield. In addition, because the bit line and the storage element (e.g., capacitor or PCM element) are arranged on the same side of the planar transistor (above the transistor and the substrate), the bit line process margin is limited by the storage element, and the coupling capacitance between the bit line and the storage element (such as a capacitor) increases. When the saturated drain current continues to increase, the planar transistor may also suffer from high leakage current, which is undesirable for the performance of the memory device.

[0026] On the other hand, the memory cell array and the peripheral circuits for controlling the memory cell array are usually arranged side by side in the same plane. As the number of memory cells continues to increase, in order to maintain the same chip size, the size of the components (such as transistors, word lines and / or bit lines) in the memory cell array needs to be continuously reduced so as not to significantly reduce the efficiency of the memory cell array.

[0027] In order to solve one or more of the aforementioned problems, vertical transistors can replace planar transistors as switches and selection devices in memory cell arrays of storage devices (e.g., DRAM, PCM, and FRAM). Compared with planar transistors, vertically arranged transistors (e.g., the drain and source overlap in a plan view) can reduce the area of ​​the transistor and simplify the layout of the interconnect structure (e.g., metal wiring for word lines and bit lines), which can reduce manufacturing complexity and increase yield. For example, the spacing of word lines and / or bit lines can be reduced for ease of manufacturing. The vertical structure of the transistor also allows the bit line and storage element (such as a capacitor) to be arranged on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor), so that the process margin of the bit line can be increased and the coupling capacitance between the bit line and the storage element can be reduced.

[0028] In addition, a memory cell array with vertical transistors and peripheral circuits of the memory cell array can be formed on different wafers and bonded together in a face-to-face manner. Therefore, the thermal budget for manufacturing the memory cell array does not affect the manufacture of the peripheral circuit. Compared with a side-by-side arrangement, the stacked memory cell array and peripheral circuit can also reduce the chip size, thereby improving the array efficiency. In some embodiments, more than one memory cell array is stacked on top of each other using bonding technology to further improve the array efficiency. In some embodiments, due to the vertically arranged transistors, word lines and bit lines are arranged close to the bonding interface, which can be coupled to the peripheral circuit through a large number (e.g., millions) of parallel bonding contacts across the bonding interface, and a direct short-distance (e.g., micrometer-level) electrical connection can be made between the memory cell array and the peripheral circuit to increase the throughput and input / output (I / O) speed of the storage device.

[0029] In some embodiments, the vertical transistors disclosed herein include multi-gate transistors (e.g., full-all-around gate (GAA) transistors, tri-gate transistors, or dual-gate transistors), which can have a larger gate control region to achieve better channel control with a smaller subthreshold swing. Since the channel is fully depleted, the leakage current of the multi-gate transistor can also be significantly reduced. Therefore, using multi-gate transistors instead of planar transistors can achieve better speed (saturated drain current) / leakage current performance.

[0030] In some embodiments, due to the use of trench isolation extending along the word line direction to divide the multi-gate transistor (e.g., double-gate transistor), the vertical transistor disclosed herein includes a single-gate transistor (also referred to as a single-side gate transistor) arranged in a mirror-symmetrical manner relative to an adjacent transistor in the bit line direction. Therefore, compared to using a process such as self-aligned double patterning (SADP), the memory cell density in the bit line direction can be significantly increased (e.g., doubled) without overly complicating the manufacturing process. In addition, compared to planar transistors or multi-gate vertical transistors (e.g., with double-side gates or full-ring gates), the mirror-symmetrical single-gate transistor has a larger process window for reducing the spacing between word lines, bit lines, and transistors.

[0031] Figure 1 A block diagram of a system 100 having a storage device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, the system 100 may include a host 108 and a memory system 102 having one or more storage devices 104 and a memory controller 106. The host 108 may be a processor such as a central processing unit (CPU) of an electronic device, or a system on a chip (SoC) such as an application processor (AP). The host 108 may be configured to send or receive data to or from the storage device 104.

[0032] The memory device 104 can be any memory device disclosed herein. In some implementations, the memory device 104 includes an array of memory cells, each memory cell including a vertical transistor, as described herein.

[0033] According to some embodiments, the memory controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The memory controller 106 can manage the data stored in the storage device 104 and communicate with the host 108. The memory controller 106 can be configured to control the operation of the storage device 104, such as read, write and refresh operations. The memory controller 106 can also be configured to manage various functions related to the data stored or to be stored in the storage device 104, including but not limited to refresh and timing control, command / request conversion, buffering and scheduling, and power management. In some embodiments, the memory controller 106 is also configured to determine the maximum memory capacity that can be used by the computer system, the number of memory groups, the memory type and speed, the memory particle data depth and data width, and other important parameters.

[0034] Any other suitable function may also be performed by the memory controller 106. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, an express PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0035] Figure 2A schematic diagram of a memory device 200 including a peripheral circuit and an array of memory cells each having a vertical transistor according to some aspects of the present disclosure is shown. The memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The memory cell array 201 may be any suitable memory cell array, wherein each memory cell 208 includes a vertical transistor 210 and a storage element 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the storage element 212 is a capacitor for storing charge as binary information stored by a corresponding DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage element 212 is a PCM element (e.g., including a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivities of the PCM element in an amorphous phase and a crystalline phase. In some embodiments, the memory cell array 201 is a FRAM cell array, and the storage element 212 is a ferroelectric capacitor for storing binary information of a corresponding FRAM cell based on switching between two polarization states of a ferroelectric material under an external electric field.

[0036] like Figure 2 As shown in , the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include a word line 204 coupling the peripheral circuit 202 and the memory cell array 201 for controlling the switching of the vertical transistors 210 in the memory cells 208 located in the row, and a bit line 206 coupling the peripheral circuit 202 and the memory cell array 201 for sending data to the memory cells 208 located in the column and / or receiving data from the memory cells 208 located in the column. That is, each word line 204 is coupled to a corresponding row of memory cells 208, and each bit line is coupled to a corresponding column of memory cells 208.

[0037] Vertical transistors 210 (such as vertical metal oxide semiconductor field effect transistors (MOSFETs)) may replace planar transistors as pass transistors of memory cell 208 to reduce the area occupied by the pass transistors, coupling capacitance, and interconnect wiring complexity. Figure 2 As shown, in some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor 210 includes a semiconductor body 214 extending vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body 214 can extend above the top surface of the substrate to allow a channel to be formed not only at the top surface of the semiconductor body 214 but also at one or more side surfaces thereof.

[0038] like Figure 2As shown, for example, the semiconductor body 214 may have a rectangular parallelepiped shape to expose its four sides. It should be understood that the semiconductor body 214 may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a plan view (e.g., in an xy plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape. It should be understood that for a semiconductor body whose cross-section has a circular or elliptical shape in a plan view, the semiconductor body may still be considered to have multiple sides so that the gate structure contacts more than one side of the semiconductor body. As described below with respect to the manufacturing process, in some cases, the semiconductor body 214 may be formed from a substrate (e.g., by etching or epitaxy) and therefore has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0039] like Figure 2 As shown in the example of , the vertical transistor 210 may further include a gate structure 216 that contacts one or more side surfaces of the semiconductor body 214, for example, in one or more planes of the side surface (s) of the active region. That is, the active region (e.g., the semiconductor body 214) of the vertical transistor 210 may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate dielectric 218 on one or more side surfaces of the semiconductor body 214, for example, in contact with four side surfaces of the semiconductor body 214, as shown in FIG. Figure 2 As shown. The gate structure 216 may also include a gate electrode 220 on and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, which is a form of gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon, which is a form of gate polysilicon. In some embodiments, the gate electrode 220 includes multiple conductive layers, such as a W layer on top of the TiN layer. It should be understood that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. That is, the gate electrode 220 may be considered as a portion of the word line 204 forming the gate structure 216 , or the word line 204 may be considered as an extension of the gate electrode 220 to be coupled to the peripheral circuit 202 .

[0040] like Figure 2As shown, the vertical transistor 210 may also include a pair of source and drain (S / D, doped regions, also referred to as source and drain electrodes) formed at both ends of the semiconductor body 214 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain may be separated by a gate structure 216 in the vertical direction (z direction). That is, the gate structure 216 is vertically formed between the source and the drain. As a result, when the gate voltage of the gate electrode 220 applied to the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be formed vertically in the semiconductor body 214 between the source and the drain. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 214 extends.

[0041] In some embodiments, Figure 2 As shown, the vertical transistor 210 is a multi-gate transistor. That is, the gate structure 216 can be connected to more than one side of the semiconductor body 214 (e.g., Figure 2 The four sides of the planar gate (in the planar transistor) are contacted to form more than one gate, so that more than one channel can be formed between the source and the drain in operation. That is, unlike a planar transistor that includes only a single planar gate (and produces a single planar channel), Figure 2 The vertical transistor 210 shown may include multiple vertical gates on multiple sides of the semiconductor body 214 due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214. As a result, compared to a planar transistor, Figure 2 The vertical transistor 210 shown in FIG. 1 can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. Since the channel is fully depleted, the leakage current (Ioff) of the vertical transistor 210 can be significantly reduced in the well. In various examples, the multi-gate vertical transistor can include a dual-gate vertical transistor (e.g., a dual-side gate vertical transistor), a tri-gate vertical transistor (e.g., a tri-side gate vertical transistor), and a GAA vertical transistor.

[0042] It should be understood that although the vertical transistor 210 is Figure 2214, but the vertical transistors disclosed herein may also include single-gate transistors. That is, the gate structure 216 may contact a single side of the semiconductor body 214, for example, for the purpose of increasing transistor and memory cell density. It should also be understood that although the gate dielectric 218 is shown as being separated (separate structure) from other gate dielectrics of adjacent vertical transistors (not shown), the gate dielectric 218 may be part of a continuous dielectric layer having multiple gate dielectrics of a vertical transistor.

[0043] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), an active region such as a semiconductor body (e.g., a fin) extends laterally (in the xy plane), and the source and drain are arranged at different positions in the same lateral plane (xy plane). In contrast, according to some embodiments, in a vertical transistor 210, a semiconductor body 214 extends vertically (in the z direction), and the source and drain are arranged in different lateral planes. In some embodiments, the source and drain are formed at both ends of the semiconductor body 214 in the vertical direction (z direction), respectively, so as to overlap in a plan view. As a result, the area occupied by the vertical transistor 210 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. In addition, the metal wiring coupled to the vertical transistor 210 can also be simplified because the interconnects can be routed in different planes. For example, the bit line 206 and the storage element 212 can be formed on opposite sides of the vertical transistor 210. In one example, the bit line 206 may be coupled to a source or a drain at an upper end of the semiconductor body 214 , and the memory element 212 may be coupled to another source or a drain at a lower end of the semiconductor body 214 .

[0044] like Figure 2 As shown, the storage element 212 can be coupled to the source or drain of the vertical transistor 210. The storage element 212 can include any device capable of storing binary data (e.g., 0 and 1), including but not limited to capacitors for DRAM cells and FRAM cells and PCM elements for PCM cells. In some embodiments, the vertical transistor 210 controls the selection and / or state switch of the corresponding storage element 212 coupled to the vertical transistor 210. In some embodiments, as Figure 3 As shown, each memory cell 208 is a DRAM cell 302 that includes a transistor 304 (e.g., using Figure 2 ) and capacitor 306 (eg, Figure 2A gate of transistor 304 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of a source and a drain of transistor 304 may be coupled to bit line 206, the other of the source and the drain of transistor 304 may be coupled to one electrode of capacitor 306, and the other electrode of capacitor 306 may be coupled to ground.

[0045] In some embodiments, Figure 4 As shown, each memory cell 208 is a PCM cell 402 that includes a transistor 404 (e.g., using Figure 2 ) and PCM element 406 (eg, Figure 2 A gate of transistor 404 (e.g., corresponding to gate electrode 220) may be coupled to word line 204, one of a source and a drain of transistor 404 may be coupled to ground, the other of the source and the drain of transistor 404 may be coupled to one electrode of PCM element 406, and the other electrode of PCM element 406 may be coupled to bit line 206.

[0046] The peripheral circuit 202 may be coupled to the memory cell array 201 through the bit lines 206, the word lines 204, and any other suitable metal wiring. As described above, the peripheral circuit 202 may include any suitable circuit for facilitating the operation of the memory cell array 201 by applying a voltage signal and / or a current signal to each memory cell 208 and sensing a voltage signal and / or a current signal from each memory cell 208 via the word lines 204 and the bit lines 206. For example, the peripheral circuit 202 may include various types of peripheral circuits formed using CMOS technology.

[0047] II. Formation of a Memory Device by Using an Etch Stop Layer

[0048] Figure 5A-5B FIG. 5 shows a memory device manufacturing process in which a semiconductor body 502 of a vertical transistor is formed without using an etch stop layer. Figure 5A In the embodiment, a plurality of first trenches (isolation trenches) 501 may be formed in the silicon substrate along the bit line direction (y direction). For example, a first photolithography process and a first etching process may be performed in the substrate to form the isolation trenches 501. An insulating material such as silicon oxide may be filled in the isolation trenches to form trench isolation. Figure 5B In the embodiment, a plurality of second trenches (referred to as word line trenches or gate trenches) 503 may be formed through the trench isolation along the word line direction (x direction). For example, a second photolithography patterning process and a second etching process may be performed for the word line trenches 503. As a result, a plurality of semiconductor bodies 502 surrounded by the trench isolation and the word line trenches 503 may be formed.

[0049] exist Figure 5A-5B In the manufacturing process, no etching stop layer is formed and used for the first etching process in the y direction and the second etching process in the x direction. Due to the high aspect ratio of the first trench and the second trench, it is difficult to control the bottom profile and etching depth uniformity of these trenches. In addition, in some embodiments, in a later manufacturing stage, a back silicon recess process is performed to remove silicon and form recesses below the semiconductor body 502 and between the trench isolations along the bit line direction. Source / drain region doping and bit line deposition can be performed in the recesses. Similarly, in order to form these recesses, it is difficult to control the uniformity of the recesses when an etching stop layer is not used.

[0050] Fig. 6A , Figure 6B and Figure 6C A memory device manufacturing process is shown, in which an etch stop layer is used to improve the bottom profile uniformity and etching depth uniformity of isolation trenches and word line trenches and back side bit line silicon recesses.

[0051] exist Fig. 6A In the embodiment of the present invention, the layer stack 600 can be formed in various ways. As an example, a semiconductor substrate 601 can be provided first. Subsequently, a first semiconductor layer 602, a second semiconductor layer 603, a third semiconductor layer 604, and a fourth semiconductor layer 605 can be formed in sequence. In some embodiments, the semiconductor substrate 601 can be a crystalline silicon substrate, and a plurality of layers 602-605 can be epitaxially grown. In some embodiments, other formation methods can be used to form the layer stack 600. In some embodiments, the two etching stop layers are silicon germanium (SiGe) epitaxial layers, and the two semiconductor layers 603 and 605 are silicon epitaxial layers.

[0052] exist Figure 6B In the embodiment of the present invention, an isolation trench 611 may be formed along the bit line direction. As shown, the first semiconductor layer 602 may be used as an etching stop layer for etching the isolation trench 611. The resulting isolation trench 611 passes downward through the fourth semiconductor layer 605, the third semiconductor layer 604, and the second semiconductor layer 603, and reaches or enters the first semiconductor layer 602. The isolation trench 611 may then be filled with an insulating material such as silicon dioxide to form a trench isolation.

[0053] exist Figure 6C In the embodiment of the present invention, a word line trench 621 may be formed along the word line direction. As shown, the third semiconductor layer 604 may be used as an etch stop layer for etching the word line trench 621. The resulting word line trench 621 passes downward through the fourth semiconductor layer 605 (the remaining portion sandwiched between adjacent trench isolations) and the trench isolations, and reaches or enters the third semiconductor layer 604. A vertically positioned semiconductor body 622 is formed accordingly.

[0054] Also like Figure 6C As shown, the remaining portion 623 of the third semiconductor layer 604 is located below the semiconductor body 622, sandwiched between adjacent trench isolations, and above the second semiconductor layer 603. In a later stage of the manufacturing process, the remaining portion 623 can be used as part of a bit line structure. Therefore, when SiGe is used in the third semiconductor layer 604, the remaining portion 623 (possibly with additional doping) can be referred to as a bit line SiGe structure.

[0055] The remaining portion 624 of the second semiconductor layer 603 is located between the remaining portion 623 and the first semiconductor layer 602, and is sandwiched between adjacent trench isolations. In a later stage of the manufacturing process, the substrate 601 and the first semiconductor layer 602 can be removed. Subsequently, the remaining portion 624 can be removed (silicon recess process), and a recess (called a bit line recess) is formed in the space of the remaining portion 624. The bit line metal can be deposited in the bit line recess and adjacent to the bottom surface of the bit line SiGe structure 623. In the silicon recess process, the third semiconductor layer 604 (bit line SiGe structure 623) can be used as an etching stop layer for etching the remaining portion 624.

[0056] As reference Figures 6A-6C As described above, a stack of Si-SiGe layers epitaxially grown on a silicon substrate may be introduced. The SiGe epitaxial layer may be used as an etch stop layer for forming isolation trenches, wordline trenches, and bitline silicon recesses, thereby improving the etch profile and etch depth uniformity.

[0057] refer to Figure 7-8 A memory device manufactured by using the etch stop layer introduced above is described. Figure 7 1 shows a plan view of an array of memory cells 702 each including a vertical transistor in a memory device 700 according to some aspects of the present disclosure. Figure 7 As shown, the memory device 700 may include a plurality of word lines 704, each word line 704 extending in a first lateral direction (x direction, referred to as a word line direction). The memory device 700 may also include a plurality of bit lines 706, each bit line 706 extending in a second lateral direction (y direction, referred to as a bit line direction) perpendicular to the first lateral direction. Figures 6A-6C In the example of , the bit line 706 may include the remaining portion 623 (bit line SiGe structure 623) of the third semiconductor layer 604. It should be understood that Figure 7 A cross section of the memory device 700 in the same lateral plane is not shown, and the word lines 704 and the bit lines 706 may be formed in different lateral planes to facilitate routing.

[0058] The memory cells 702 can be formed at the intersections of the word lines 704 and the bit lines 706. In some embodiments, each memory cell 702 includes a vertical transistor (eg, Figure 2 The semiconductor body 708 may extend in the substrate in a vertical direction (z direction, not shown) perpendicular to the first lateral direction and the second lateral direction. The vertical transistor may be a double-gate transistor in which two gate structures 710 are disposed on opposite sides (e.g., Figure 7 Two of the four sides of the Figure 7 As shown, each of the two gate structures 710 abuts one side of the semiconductor body 708 (having a rectangular or square cross-section) in the bit line direction (y direction) in a plan view. According to some embodiments, the gate structure 710 does not surround and contact the other two sides of the semiconductor body 708 in the word line direction.

[0059] The gate structure 710 may include a gate dielectric 712 adjacent to one side of the semiconductor body 708 in a plan view, and a gate electrode 714 in contact with the gate dielectric 712. In some embodiments, the gate dielectric 712 is laterally located between the gate electrode 714 and the semiconductor body 708 in the bit line direction (y direction). The gate electrode 714 may be part of the word line 704, and the word line 704 may be an extension of the gate electrode 714. That is, the gate electrodes 714 of adjacent vertical transistors in the word line direction (x direction) are continuous, for example, portions of a continuous conductive layer having the gate electrode 714. In some embodiments, the gate structures 710 of a row of vertical transistors are continuous in the x direction, such as Figure 7 shown.

[0060] In some other embodiments, the semiconductor body 708 can be divided into two sections using trench isolation extending in the word line direction (x direction) and parallel to the word line 704. The trench isolation and the word line 704 can be arranged in a staggered manner in the bit line direction. For example, a trench isolation is formed in the middle of a semiconductor column (not shown). As a result, the pair of semiconductor bodies are mirror-symmetrical to each other with respect to the trench isolation. A pair of single-gate vertical transistors corresponding to the pair of semiconductor bodies are mirror-symmetrical to each other with respect to the trench isolation. The corresponding gate structures 710 are also mirror-symmetrical to each other with respect to the trench isolation.

[0061] By using trench isolation to separate a double-gate vertical transistor into a single-gate vertical transistor, the number of memory cells (and cell density) in the bit line direction can be doubled compared to the double-gate vertical transistor without overly complicating the manufacturing process (e.g., compared to using a SADP process).

[0062] Figure 8 800 is an example of a memory device 700 including a dual-gate vertical transistor. Figure 8 For illustrative purposes only, and in practice may not necessarily reflect the actual device structure size or scale. Storage device 800 may include an array of memory cells (e.g., DRAM cells). A cross-section of storage device 800 may be obtained in a yz plane cutting through a row of memory cells and the bit lines below them. As shown, each memory cell in the row may include a vertical transistor 816 and a storage element 803 (e.g., including a capacitor) coupled to the vertical transistor 816. The row of memory cells is located on bit line 820.

[0063] In some embodiments, the bit line 820 includes a semiconductor line 821 (or semiconductor layer 821), a contact line 822 (first connection layer 822), and a metal line 823 (second connection layer 823). The semiconductor line 821 may be similar to that produced by an etch stop layer in a stack of Si-SiGe layers. Figure 6C The remaining portion (or bit line SiGe structure) 623 in the semiconductor line 821. For example, the semiconductor line 821 may include SiGe. The semiconductor line 821 may be an epitaxially grown semiconductor layer (or semiconductor epitaxial layer). For example, the semiconductor line 821 may be an epitaxially grown SiGe layer (or SiGe epitaxial layer), as opposed to a SiGe layer formed by implanting Ge into a silicon layer. Various growth techniques may be used to form the SiGe semiconductor line 821, such as molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD), and ultra-high vacuum chemical vapor deposition (UHV-CVD).

[0064] In some embodiments, the Ge concentration in the SiGe semiconductor line 821 is optimized to obtain a specific concentration distribution in the vertical direction. For example, the Ge concentration can be controlled at a lower level near the interface between the SiGe layer and the adjacent lower or upper silicon layer compared to a position far from the interface. In this way, the SiGe lattice can closely match the lattice constant of the silicon layer, reducing strain and defects and contact resistance at the Si-SiGe interface, thereby improving the electrical and structural properties of the device. At a position far from the interface, the Ge concentration can be controlled at a desired level to achieve the desired electrical and structural properties.

[0065] Therefore, in some embodiments, the concentration of Ge decreases upward in the vertical direction at the upper side of the SiGe semiconductor line 821. In some embodiments, the first Ge concentration at the first position is greater than the second Ge concentration at the second position, and the first position is located below the second position in the vertical direction at the upper side of the SiGe semiconductor line 821. In some embodiments, the concentration of Ge decreases from 20% to 5% upward in the vertical direction at the upper side of the SiGe semiconductor line 821. In some embodiments, the first Ge concentration at the first position is in the range of 25%-15%, and the second Ge concentration at the second position is in the range of 10%-2%, and the first position is located below the second position in the vertical direction at the upper side of the SiGe semiconductor line 821.

[0066] In some embodiments, the Ge concentration near the upper and lower surfaces of the SiGe semiconductor line 821 is low, while the Ge concentration in the middle of the SiGe semiconductor line 821 is high. Therefore, in the direction from top to bottom, the Ge concentration initially increases and then decreases in the SiGe semiconductor line 821. In some embodiments, in the direction from top to bottom, the Ge concentration initially increases in the SiGe semiconductor line 821 and then maintains the concentration level. In some embodiments, in the direction from top to bottom, the Ge concentration continuously increases until the lower surface of the SiGe semiconductor line 821.

[0067] In some embodiments, silicon and germanium are miscible over a full range of compositions and thus can be combined to form Si 1-x Ge x Alloys wherein the germanium content x is in the range of 0 to 1 (0-100%). Si 1-x Ge x It has a diamond-like lattice structure. When Si is grown on a silicon substrate 1-x Ge x Layer, adapt to Si 1-x Ge x The lattice mismatch at the interface with silicon can be overcome by compressing the Si 1-x Ge x The layer is then adapted to the silicon lattice or by creating misfit dislocations at the interface. 1-x Ge x The layers are spaced in the silicon lattice in the growth plane, so the Si is usually cubic. 1-x Ge x The crystal deforms. 1- x Ge x When growth occurs in this way, Si 1-x Ge x The layer is under compressive strain and the layer is described as pseudomorphic.1-x Ge x The layers are unstrained or relaxed, and the lattice mismatch at the interface is accommodated by the formation of misfit dislocations. These misfit dislocations are usually located in the plane of the interface, but dislocations can also be perpendicular to the Si 1-x Ge x layer.

[0068] In some embodiments, the semiconductor line 821 can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping profile. For example, the semiconductor line 821 can be a doped SiGe line. The doped semiconductor line 821 can be used as a source / drain region of a vertical transistor above it. In some embodiments, a SiGe layer formed by implanting Ge into a silicon layer (optionally followed by annealing) can be used instead of the SiGe epitaxial layer in the semiconductor line 821.

[0069] In some embodiments, the contact line 822 covers the semiconductor line 821. The contact line 822 (or the connection layer 822) can be an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, the contact line 822 can include a metal silicide, such as NiSi, TiSi, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. In some embodiments, the metal line 823 can include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the contact line 822 can be omitted, and the metal line 823 is in direct contact with the semiconductor line 821. In some embodiments, the contact line 822 and the metal line 823 do not exist and are not configured for the memory device 800. The semiconductor line 821 is used as a bit line connecting the vertical transistors described above. In some embodiments, an additional semiconductor is positioned below the semiconductor line 821 and in contact with the semiconductor line 821. The two semiconductor lines are used together as a bit line.

[0070] The vertical transistor 816 may be a MOSFET for switching the corresponding memory cell. In some embodiments, the vertical transistor 816 includes a semiconductor body 815 (in which an active region of a channel may be formed) extending vertically (in the z direction), and two gate structures 810 contacting each opposite side of the semiconductor body 815 in the bit line direction (y direction). The semiconductor body 815 may have a rectangular parallelepiped shape or a cylindrical shape, and the gate structure 810 may be adjacent to one side of the semiconductor body 815 in a plan view, for example, as shown in FIG. Figure 8According to some embodiments, the gate structure 810 includes a gate electrode 814 and a gate dielectric 812 laterally located between the gate electrode 814 and the semiconductor body 815 in the bit line direction. In some embodiments, the gate dielectric 812 abuts one side of the semiconductor body 815, and the gate electrode 814 abuts the gate dielectric 812.

[0071] like Figure 8 As shown, in some embodiments, the semiconductor body 815 has two ends (an upper end and a lower end) in the vertical direction (z direction), and at least one end (eg, Figure 8 In some embodiments, one end of the semiconductor body 815 (eg, the lower end in the vertical direction (z direction) extends beyond the gate dielectric 812. Figure 8 ) and the corresponding end of the gate dielectric 812 (eg, Figure 8 In some embodiments, both ends (upper end and lower end) of the semiconductor body 815 extend beyond the gate electrode 814 in the vertical direction (z direction), respectively. That is, the semiconductor body 815 (e.g., in the z direction) may have a vertical dimension greater than a vertical dimension (e.g., depth) of the gate electrode 814, and neither the upper end nor the lower end of the semiconductor body 815 is flush with the corresponding end of the gate electrode 814. Therefore, a short circuit between the bit line 820 and the word line / gate electrode 814 or between the word line / gate electrode 814 and the storage element 803 may be avoided.

[0072] The vertical transistor 816 may further include a source and a drain (their positions may be interchanged) disposed at two ends (upper end and lower end) of the semiconductor body 815 in the vertical direction (z direction). In some embodiments, one of the source and the drain (e.g., Figure 8 ) is coupled to the storage element 803, and the other of the source and the drain (for example, Figure 8 That is, the vertical transistor 816 may have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction, such as Figure 8 In some implementations, a bit line 820 is coupled to a second terminal of the vertical transistor 816 .

[0073] In some embodiments, the semiconductor body 815 includes a semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 815 may include single crystal silicon. The source and drain may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping profile. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain of the vertical transistor 816 and the bit line 820 (if implemented as a metal line) as a bit line contact, or is formed between the source / drain of the vertical transistor 816 and the first electrode of the storage element 803 to reduce contact resistance.

[0074] In some embodiments, the gate dielectric 812 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al 2 O 3 , HfO 2 、 2 O 5 、ZrO 2 、TiO 2 or any combination thereof. In some embodiments, the gate electrode 814 comprises a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 814 comprises a plurality of conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 810 can be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 812 comprises silicon oxide, and the gate electrode 814 comprises doped polysilicon. In another example, the gate structure 810 can be HKMG, wherein the gate dielectric 812 comprises a high-k dielectric, and the gate electrode 814 comprises a metal.

[0075] As described above, since the gate electrode 814 may be part of a word line or in the direction of the word line (eg, Figure 8 In the x direction in FIG. 1 , as a word line extending, Figure 8As shown, the memory device 800 may also include a plurality of word lines (referred to as 814), each word line extending in the word line direction (x direction). Each word line 814 may be coupled to a row of memory cells. That is, the bit line 820 and the word line 814 may extend in two perpendicular lateral directions, and the semiconductor body 815 of the vertical transistor 816 may extend in a vertical direction perpendicular to the two lateral directions extending from the bit line 820 and the word line 814. According to some embodiments, the word line 814 is in contact with a word line contact (not shown). In some embodiments, the word line 814 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 814 includes a plurality of conductive layers, such as a W layer on a TiN layer.

[0076] like Figure 8 As shown, in some embodiments, the storage element 803 includes a first electrode above the source or drain of the vertical transistor 816 and coupled to the source or drain of the vertical transistor 816 (e.g., the upper end of the semiconductor body 815) via the storage element contact 802. In some embodiments, the storage element contact 802 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, the storage element 803 can be a capacitor having a capacitor dielectric above and in contact with the first electrode, and a second electrode above and in contact with the capacitor dielectric. That is, the storage element 803 can be a vertical capacitor in which the electrodes and the capacitor dielectric are stacked vertically (in the z direction), and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to the source or drain of a corresponding vertical transistor 816 in the same memory cell, and all second electrodes are coupled to a common plate coupled to ground (e.g., a common ground). The storage element 803 can have a first end in the negative z direction and a second end opposite to the first end in the positive z direction, such as Figure 8 shown.

[0077] It should be understood that the structure and configuration of the storage element 803 is not limited to Figure 8 Examples of the present invention include, but are not limited to, Al2O3 ... 2 O 3 , HfO 2 、 2 O 5 、ZrO 2 、TiO 2Or any combination thereof. It should be understood that in some examples, the storage element 803 can be a ferroelectric capacitor used in a FRAM cell, and the capacitor dielectric can be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrode includes a conductive material including, but not limited to, W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0078] like Figure 8 As shown, according to some embodiments, the vertical transistor 816 extends vertically through and contacts the word line 814, the source or drain of the vertical transistor 816 at its lower end contacts the bit line 820, and the source or drain of the vertical transistor 816 at its upper end is coupled to the storage element 803. That is, due to the vertical arrangement of the vertical transistor 816, the bit line 820 and the storage element 803 can be arranged in different planes in the vertical direction and coupled to the opposite ends of the vertical transistor 816 of the memory cell in the vertical direction. In some embodiments, the bit line 820 and the storage element 803 are arranged on opposite sides of the vertical transistor 816 in the vertical direction, which simplifies the wiring of the bit line 820 and reduces the coupling capacitance between the bit line 820 and the storage element 803 compared to a memory cell in which the bit line and the capacitor are arranged on the same side of a planar transistor.

[0079] III. Manufacturing Process of Memory Device Using Etch Stop Layer

[0080] Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Figures 9D-9J A manufacturing process for forming a memory device, such as memory device 700 or 800, by using several etch stop layers according to some aspects of the present disclosure is shown. The memory device may include an array of memory cells, each memory cell including a vertical transistor and a storage element coupled to the vertical transistor.

[0081] exist Figure 9A-1 and Figure 9A-2 In the embodiment, a plurality of parallel trenches 904 are formed in the y direction (eg, the bit line direction) to form a plurality of parallel trenches 904 in the stack of semiconductor layers (films) (eg, Fig. 6A A plurality of parallel semiconductor walls 905 are formed in the stack 600 in the y-direction.

[0082] exist Figure 9A-1 and Figure 9A-2Before the processing steps in , a stack 600 may be first formed. As shown, the stack 600 includes a semiconductor substrate 601, a first semiconductor layer 602, a second semiconductor layer 603, a third semiconductor layer 604, and a fourth semiconductor layer 605. For example, the process of forming the stack 600 may include epitaxially growing the first semiconductor layer 602 on the semiconductor substrate 601, epitaxially growing the second semiconductor layer 603 on the first semiconductor layer 602, epitaxially growing the third semiconductor layer 604 on the second semiconductor layer 603, and epitaxially growing the fourth semiconductor layer 605 on the third semiconductor layer 604. The semiconductor substrate 601 may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material.

[0083] In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 include SiGe epitaxially grown on the lower layer (semiconductor substrate 601 or second semiconductor layer 603). Various growth techniques can be used to form the SiGe epitaxial layer, such as molecular beam epitaxy (MBE), low pressure chemical vapor deposition (LPCVD) and ultra-high vacuum chemical vapor deposition (UHV-CVD). In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 include SiGe formed by implanting Ge into a silicon layer. For example, Ge pre-amorphization implantation (PAI) using Ge ions with certain energy can be performed to form SiGe. An annealing process can be performed after the Ge implantation.

[0084] In some embodiments, the Ge concentration in the SiGe layer (first semiconductor layer 602 and / or third semiconductor layer 604) decreases upward on the upper side of the SiGe layer adjacent to the upper semiconductor layer 603 or 605. For example, the Ge concentration decreases upward from 20% to 5%.

[0085] In some embodiments, the Ge concentration near the upper and lower surfaces of the SiGe layer 602 and / or 604 is low, while the Ge concentration in the middle of the SiGe layer 602 and / or 604 is high. Therefore, in the direction from top to bottom, the Ge concentration initially increases in the SiGe layer 602 and / or 604 and then decreases. In some embodiments, in the direction from top to bottom, the Ge concentration initially increases in the SiGe layer 602 and / or 604 and then maintains the concentration level. In some embodiments, in the direction from top to bottom, the Ge concentration continuously increases until the lower surface of the SiGe layer 602 and / or 604.

[0086] In some embodiments, the first semiconductor layer 602 and / or the third semiconductor layer 604 are doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level or doping profile. For example, the first semiconductor layer 602 and / or the third semiconductor layer 604 may be epitaxially grown using in-situ doping. For example, the first semiconductor layer 602 and / or the third semiconductor layer 604 may be doped by performing an implantation process and / or a thermal diffusion process.

[0087] In some embodiments, semiconductor layers 603 and / or 605 may include epitaxially grown silicon or other epitaxially grown semiconductor materials. Generally, high etch selectivity between layers 602 and 603, between layers 605 and 604, and between layers 603 and 604 is desired.

[0088] To form the trench 904, for example, based on the design of the bit line, a photolithography process is performed to pattern the trench 904 and the semiconductor wall 905 using an etching mask (e.g., a photoresist mask and / or a hard mask). One or more dry etching and / or wet etching processes, such as reactive ion etching (RIE), are performed to etch the trench 904 in the stack 600. The first semiconductor layer 602 is used to ensure the uniformity of the etching depth and bottom profile of the trench 904. The semiconductor wall 905 extends vertically and passes through the second etch stop layer 604 in the stack 600, and is located on the top of the first semiconductor layer 602. The upper surface of the first semiconductor layer 602 forms the bottom of the trench 904.

[0089] Figure 9A-1 shows the x-direction (the word line direction, for example, Figure 9A-2 Side view of a cross section (in the BB plane shown). Figure 9A-2 In the xy plane (e.g., Figure 9A-1 A plan view of a cross section through the semiconductor wall 905 in the AA plane is shown. Figure 9B-1 and Figure 9B-2 The same drawing layout is also arranged in .

[0090] exist Figure 9B-1 and Figure 9B-2 , trench isolation 908 (e.g., STI) is formed in the trench 904. In some embodiments, a dielectric such as silicon oxide is deposited using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof) to completely fill the trench 904. In some embodiments, a planarization process (such as CMP) is performed to remove excess dielectric deposited beyond the top surface of the stack 600. As a result, the parallel semiconductor walls 905 can be separated by the trench isolation 908.

[0091] exist Figure 9C-1 and Figure 9C-2 In the embodiment of the present invention, a plurality of parallel trenches 910 are formed in the x-direction (eg, the word line direction) to form an array of semiconductor pillars 906 each extending vertically in the stack 600 .

[0092] In some embodiments, for example, based on the design of the word line, a photolithography process is performed to pattern the trench 910 using an etching mask (e.g., a photoresist mask and / or a hard mask) to be perpendicular to the trench isolation 908. One or more dry etching and / or wet etching processes (such as RIE) are performed on the semiconductor wall 905 and the trench isolation 908 to etch the trench 910 in the stack 600. As a result, the semiconductor wall 905 ( Figure 9B-1 and Figure 9B-2 906) can be cut by the trench 910 to form an array of semiconductor pillars 906 each extending vertically in the stack 600. The third semiconductor layer 604 is used to etch the semiconductor wall 905 to ensure the uniformity of the etching depth and bottom profile of the portion of the trench 910 between two adjacent semiconductor pillars 906. The array of semiconductor pillars 906 is located on the third semiconductor layer 604.

[0093] Figure 9C-1 The y direction (bit line direction, for example, in Figure 9C-2 Side view of a cross section (in the CC plane shown in ). Figure 9C-2 In the xy plane (e.g., Figure 9C-1 A plan view of a cross section (in the AA plane) through the semiconductor pillar 906 is shown in FIG.

[0094] As shown in the plan view, two opposite sides of the semiconductor pillar 906 in the y direction are exposed by the trench 910, and the other two opposite sides of the semiconductor pillar 906 in the x direction are in contact with the trench isolation 908. That is, the semiconductor pillar 906 is surrounded by the trench 910 and the trench isolation 908.

[0095] exist Fig.9D In the embodiment, a plurality of vertical transistors 936 and corresponding storage elements 923 are formed. Fig.9D A side view of a cross section along the bit line direction in the yz plane is shown.

[0096] A gate structure is formed in contact with the opposite side of the semiconductor pillar. In some embodiments, to form the gate structure, a gate dielectric is formed on the opposite side of the semiconductor pillar, and a gate electrode is formed on the gate dielectric. In some embodiments, to form the gate electrode, a conductive layer is deposited on the gate dielectric and the conductive layer is etched back.

[0097] exist Fig.9D, a gate dielectric 932 is formed over two opposite sides of a semiconductor pillar 906 (shown as a semiconductor body 935) exposed from a trench 910. In some embodiments, the gate dielectric 932 is formed by depositing a dielectric layer such as silicon oxide over the sidewalls of the trench 910 but not completely filling the trench 910 using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that in some examples, the gate dielectric 932 may not be part of a continuous dielectric layer. For example, a wet oxidation and / or dry oxidation process (e.g., in-situ steam generation (ISSG) oxidation) is performed to form a native oxide (e.g., silicon oxide) as the gate dielectric 932 on the semiconductor pillar 906 (e.g., single crystal silicon).

[0098] A conductive layer 934 is formed over the gate dielectric 932 in the trench 910. In some embodiments, the conductive layer 934 is formed by depositing one or more conductive materials such as metals and / or metal compounds (e.g., W and TiN) over the gate dielectric 932 to partially fill the trench 910 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. For example, TiN and W layers may be deposited sequentially to form the conductive layer 934. A planarization process (e.g., CMP) may be performed to remove excess conductive material over the top surface of the stack 600.

[0099] In some embodiments, the conductive layer 934 is etched back, for example using dry etching and / or wet etching (e.g., RIE) to form a dent, so that the upper end of the conductive layer 934 is below the top surface of the semiconductor pillar 906. In some embodiments, since the gate dielectric 932 is not etched back (not shown), the upper end of the conductive layer 934 is also below the upper end of the gate dielectric 932, and the upper end of the gate dielectric 932 is flush with the top surface of the semiconductor pillar 906. As a result, the etched-back conductive layer 934 can become word lines each extending in the word line direction (x direction), and the portion of the etched-back conductive layer 934 facing the semiconductor pillar 906 can become a gate electrode. Thus, gate structures each including a corresponding gate dielectric 932 on the exposed side of the semiconductor pillar 906 and a corresponding gate electrode (a portion of the conductive layer 934) on the gate dielectric 932 can be formed. In some embodiments, a dielectric layer is formed in the remaining space of the trench 910 and in the indentation (not shown) created by the etch-back of the conductive layer 934, for example by depositing a dielectric (such as silicon oxide) using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). It should be understood that, depending on the pitch of the word lines (the size of the trench 910), air gaps may be formed in the dielectric layer.

[0100] The upper end of the semiconductor body 935 away from the substrate is doped. The exposed upper end of each semiconductor body 935 is doped to form a source / drain (e.g., a source terminal of a vertical transistor). In some embodiments, an implantation process and / or a thermal diffusion process is performed to dope a P-type dopant or an N-type dopant into the exposed upper end of the semiconductor body 935 to form a source / drain. In some embodiments, a silicide layer is formed on the source / drain by performing a silicide process at the exposed upper end of the semiconductor body 935.

[0101] A storage element is formed in contact with the semiconductor body (e.g., a doped first end thereof). The storage element may include a capacitor or a PCM element. In some embodiments, to form the storage element as a capacitor, a first electrode is formed on the doped upper end of the semiconductor body, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0102] For example, one or more interlayer dielectric (ILD) layers are formed over the top surface of the stack 600 by depositing dielectrics using one or more thin film deposition processes (including but not limited to CVD, PVD, ALD, or any combination thereof). Subsequently, a storage element contact (capacitor contact) 922 to be coupled to the semiconductor body 935, a first electrode of the storage element (capacitor) 923, a capacitor dielectric and a second electrode, and a common plate 924 are formed in the ILD layer. In some embodiments, the capacitor contact 922 is formed on the corresponding source / drain (e.g., the doped upper end of the corresponding semiconductor body 935) by patterning and etching electrode holes aligned with the corresponding source / drain using photolithography and etching processes and depositing a conductive material using a thin film deposition process to fill the electrode holes. In some embodiments, the common plate 924 is formed on the second electrode of the capacitor 923 by patterning and etching electrode trenches aligned with the capacitor 923 using photolithography and etching processes and depositing a conductive material using a thin film deposition process to fill the electrode trenches.

[0103] Figures 9E-9J Shown for Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Fig.9D After the manufacturing steps in , a backside manufacturing process is performed to form the bit lines from the backside of the semiconductor substrate 602 . Figures 9E-9J Each of the diagrams shows a side view of a cross section in the xz plane along the word line direction (x direction). The cross section cuts through a row of vertical semiconductor bodies 935 of corresponding vertical transistors 936 arranged in the x direction. Figure 9A-1 / Figure 9A-2 / Figure 9B-1 / Figure 9B-2 / Figure 9C-1 / Figure 9C-2 and Fig.9D compared to, Figures 9E-9J The side view in FIG. 6 is flipped, and substrate 601 becomes the top layer in stack 600. In addition, Figures 9E-9J Only a partial cross-sectional view of the storage device is shown, and the storage element is not shown.

[0104] Fig.9E Shows the corresponding Fig.9D , and for simplicity only two semiconductor bodies 935 are shown. The remaining portion 623 of the third semiconductor layer 604 is on top of the corresponding semiconductor body 935. The remaining portion 624 of the second semiconductor layer 603 is on top of the corresponding remaining portion 623. The structures 623 and 624 extend in the bit line direction (y direction). The semiconductor body 935 and the structures 623 and 624 on top thereof are sandwiched between two adjacent trench isolations 908 extending in the bit line direction.

[0105] exist Fig.9F In the process, the semiconductor substrate 601 and the first semiconductor layer 602 are removed, for example, by performing a planarization process (eg, CMP), an etching process, or any suitable process. The top surface of the trench isolation 908 and the remaining portion 624 of the second semiconductor layer 603 are exposed.

[0106] exist Figure 9G In the embodiment of the present invention, the remaining portion 624 of the second semiconductor layer 603 is removed during the recess process to expose the top surface of the remaining portion 623 of the third semiconductor layer 604. As a result of the recess process, a bit line recess 930 is formed. The recess process may be a dry or wet etching process or any suitable process for removing the remaining portion 624. The remaining portion 623 of the third semiconductor layer 604 is used as an etching stop layer during the recess process. Therefore, the uniformity of the etching depth and the bottom etching profile of the bit line recess 930 can be ensured.

[0107] The remaining portion 623 of the third semiconductor layer 604 can be used to form a bit line together with a metal line formed later, and is therefore referred to as a semiconductor line 623 in the following description, in contrast to the metal line formed later. After forming the bit line recess 930, the semiconductor line 623 can be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) at a desired doping level by performing an implantation process, a thermal diffusion process, a combination thereof, or any suitable process. In some embodiments, the third semiconductor layer 604 is doped when the stack 600 of Si-SiGe layers is formed. Figure 9G The doping in can be used to further adjust the doping level of semiconductor line 623. In some embodiments, the doping in can be skipped. Figure 9G Doping operation in .

[0108] Figures 9H-9J A process for forming a metal line on top of semiconductor line 623 within bit line recess 930 is shown.

[0109] exist Figure 9H In the embodiment, a silicide layer 931, such as a metal silicide layer, is formed at the top surface of the semiconductor line 623 by performing a silicide process. The silicide layer may include a metal silicide, such as NiSi, TiSi, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Fig.9I In the embodiment of the present invention, a metal layer 938 may be deposited on top of the silicide layer 931 to fill the bit line recess 930. The metal layer 938 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. Figure 9J In the embodiment of the present invention, a planarization process (e.g., CMP) may be performed to remove excess portions of the metal layer 938 that exceed the top surface of the trench isolation 908. The remaining portion of the metal layer 938 within the bit line recess 930 may be further recessed by a dry / wet etching process to form a metal line 933 on top of the silicide layer 931. In some embodiments, an insulating layer is further formed on top of the metal line 933 to surround the metal line 933.

[0110] In some embodiments, the semiconductor line 623 , the silicide layer 931 , and the metal line 933 together form a bit line extending in the y-direction. The bit line is located on top of the semiconductor body 935 and is sandwiched between two adjacent trench isolations 908 .

[0111] IV. Flowchart of a Manufacturing Process Using an Etch Stop Layer

[0112] Fig.10 A flowchart of a manufacturing process 1000 for forming a 3D memory device including a vertical transistor according to some aspects of the present disclosure is shown. The manufacturing process 1000 may employ an etch stop layer as described herein. The manufacturing process 1000 starts from S1001 and proceeds to S1010.

[0113] At S1010 , a stack of semiconductor layers may be formed on a substrate, and the stack may include a first semiconductor layer, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a fourth semiconductor layer on the third semiconductor layer.

[0114] At S1012, the stack is etched through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to form a first trench along a first direction and on the first semiconductor layer. The second semiconductor layer and the first semiconductor layer may have different etching rates during the etching process, so that the first semiconductor layer may be used as an etching stop layer during the etching process. It is desirable to have a high etching selectivity between the second semiconductor layer and the first semiconductor layer.

[0115] At S1014, the first trench is filled with an insulating material to form a trench isolation. The fourth semiconductor layer, the third semiconductor layer, and the remaining portion of the second semiconductor layer are sandwiched by adjacent trench isolations.

[0116] At S1016, the remaining portion of the fourth semiconductor layer and the trench isolation are etched to form a second trench on the third semiconductor layer and along a second direction perpendicular to the first direction. In addition, a semiconductor body of a vertical transistor extending in a third direction and surrounded by the second trench and the trench isolation is formed. The third direction is perpendicular to the first direction and the second direction. The vertical transistor is located on top of the remaining portion of the third semiconductor layer.

[0117] During the etching process of S1016, the fourth semiconductor layer and the third semiconductor layer may have different etching rates, so that the third semiconductor layer may be used as an etching stop layer during the etching process of S1016. It is desirable to have a high etching selectivity between the fourth semiconductor layer and the third semiconductor layer.

[0118] At S1018, a gate structure of the vertical transistor coupled to at least one side surface of the semiconductor body along the second direction is formed. The gate structures may each include a dielectric layer and a gate electrode.

[0119] At S1020 , the substrate and the first semiconductor layer are removed to expose the trench isolation and remaining portions of the second semiconductor layer.

[0120] At S1022, for example, by performing an etching process, the remaining portion of the second semiconductor layer is removed to expose the remaining portion of the third semiconductor layer at the bottom of the recess between adjacent trench isolations. During the etching process of S1022, the second semiconductor layer and the third semiconductor layer may have different etching rates, so that the third semiconductor layer may be used as an etching stop layer during the etching process of S1022. It is desirable to have a high etching selectivity between the second semiconductor layer and the third semiconductor layer.

[0121] At S1024 , the remaining portion of the third semiconductor layer is doped to form a source-drain region of the vertical transistor.

[0122] At S1026 , a first connection layer, such as a silicide layer, is formed on the surface of the third semiconductor layer at the bottom of the recess between adjacent trench isolations.

[0123] At S1028, a second layer, such as a bit line metal, is formed on the first connection layer in the recess between adjacent trench isolations. The process proceeds to S1099 and terminates at S1099.

[0124] Although the various aspects of the present disclosure have been described in conjunction with the specific embodiments of the present disclosure proposed as examples, the examples may be substituted, modified and varied. Therefore, the embodiments set forth herein are intended to be illustrative rather than restrictive. Changes may be made without departing from the scope of the claims set forth below.

Claims

1. A method for manufacturing a storage device, comprising: A stacked body is formed, the stacked body comprising: The first semiconductor layer, a second semiconductor layer on top of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a fourth semiconductor layer on the third semiconductor layer; etching the stack through the fourth semiconductor layer, the third semiconductor layer, and the second semiconductor layer to form a first trench along a first direction and on the first semiconductor layer; Filling the first trench with an insulating material to form a trench isolation, wherein the fourth semiconductor layer, the third semiconductor layer and the remaining portion of the second semiconductor layer are sandwiched by adjacent trench isolations; etching the remaining portion of the fourth semiconductor layer and the trench isolation to form a second trench on the third semiconductor layer and along a second direction perpendicular to the first direction, and a semiconductor body of a vertical transistor extending in a third direction perpendicular to the first direction and surrounded by the second trench and the trench isolation, the third direction being perpendicular to the first direction and the second direction, the vertical transistor being located on top of the remaining portion of the third semiconductor layer; and A gate structure of the vertical transistor is formed, the gate structure being along the second direction and coupled to at least one side surface of the semiconductor body.

2. The method according to claim 1, further comprising: removing the first semiconductor layer to expose the second semiconductor layer; removing the second semiconductor layer to expose the third semiconductor layer at the bottom of the recess between the adjacent trench isolations; as well as The third semiconductor layer is doped to form source-drain regions of the vertical transistor.

3. The method according to claim 2, further comprising: forming a silicide layer on a surface of the third semiconductor layer at the bottom of the recess between the adjacent trench isolations; as well as A bit line metal layer is formed on the silicide layer within the recess between the adjacent trench isolations.

4. The method according to claim 1, wherein: Forming the stack includes: The first semiconductor layer, the second semiconductor layer on the first semiconductor layer, the third semiconductor layer on the second semiconductor layer, and the fourth semiconductor layer on the third semiconductor layer are epitaxially grown.

5. The method according to claim 1, wherein: Forming the stack includes: A silicon germanium (SiGe) layer is epitaxially grown as the third semiconductor layer.

6. The method according to claim 1, wherein: Forming the stack includes: A SiGe layer is epitaxially grown as the third semiconductor layer such that a concentration of germanium (Ge) decreases upward at an upper side of the SiGe layer adjacent to the fourth semiconductor layer.

7. The method according to claim 1, wherein: Forming the stack includes: A SiGe layer is epitaxially grown as the third semiconductor layer such that the concentration of Ge decreases upward from 20% to 5% at the upper side of the SiGe layer adjacent to the fourth semiconductor layer.

8. The method according to claim 1, wherein: Forming the stack includes: A SiGe layer is grown by in-situ doping epitaxially as the third semiconductor layer.

9. The method according to claim 1, wherein: Forming the stack includes: A SiGe layer is epitaxially grown as the first semiconductor layer.

10. A storage device, comprising: an array of memory cells, each memory cell comprising a vertical transistor having a semiconductor body extending vertically in a first direction, each memory cell comprising a storage element coupled to a first end of the semiconductor body; as well as A bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second end of the semiconductor body of a row of the vertical transistors, the bit line comprising a semiconductor epitaxial layer extending in the second direction and connected to the second end of the semiconductor body of the row of the vertical transistors at a top surface of the semiconductor epitaxial layer.

11. The storage device according to claim 10, wherein: The bit line further comprises: a first connection layer extending in the second direction and covering a bottom surface of the semiconductor epitaxial layer, and A third connection layer is below the first connection layer and adjacent to the first connection layer, and extends in the second direction.

12. The storage device according to claim 10, wherein: The bit line further comprises: a silicide layer extending in the second direction and covering a bottom surface of the semiconductor epitaxial layer, and A metal layer is below and adjacent to the silicide layer and extends in the second direction.

13. The storage device according to claim 10, wherein: The semiconductor epitaxial layer is a silicon germanium (SiGe) epitaxial layer.

14. The storage device according to claim 10, wherein: The concentration of germanium (Ge) decreases upward in the first direction at the upper side of the semiconductor epitaxial layer.

15. The storage device according to claim 10, wherein: A first concentration of germanium (Ge) at a first location is greater than a second concentration of Ge at a second location, the first location being below the second location along the first direction at an upper side of the semiconductor epitaxial layer.

16. The storage device according to claim 10, wherein: The concentration of Ge decreases from 20% to 5% upward in the first direction at the upper side of the semiconductor epitaxial layer.

17. The storage device according to claim 10, wherein: A first concentration of Ge at a first position is in the range of 25%-15%, and a second concentration of Ge at a second position is in the range of 10%-2%, the first position being below the second position in the first direction at an upper side of the semiconductor epitaxial layer.

18. The storage device according to claim 10, wherein: The semiconductor epitaxial layer is doped with n-type or p-type dopants.

19. The storage device according to claim 10, further comprising: A plurality of word lines are provided, each word line extending in a third direction perpendicular to the first direction and the second direction, and each word line is coupled to a gate structure of a corresponding vertical transistor.

20. A memory system comprising: Memory controller; as well as A storage device, the storage device being coupled to the memory controller, the storage device comprising: an array of memory cells, each memory cell comprising a vertical transistor having a semiconductor body extending vertically in a first direction, each memory cell comprising a storage element coupled to a first end of the semiconductor body; as well as A bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second end of the semiconductor body of a row of the vertical transistors, the bit line comprising a semiconductor epitaxial layer extending in the second direction and connected to the second end of the semiconductor body of the row of the vertical transistors at a top surface of the semiconductor epitaxial layer.

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