Three-dimensional semiconductor device

Abstract

A semiconductor device includes a first bit line, a second bit line, a word line, a first channel, a second channel, and a capacitor. The first bit line and the second bit line extend mainly in a first direction on the substrate and are spaced apart from each other in a second direction. The word line includes a first extension portion extending mainly in the third direction between the first bit line and the second bit line, and a second extension portion extending mainly in the second direction at the same height as the first extension portion and connected to the first extension portion. The first channel and the second channel both extend through the first extension portion. The capacitor includes a first capacitor electrode electrically connected to the first channel, a dielectric pattern disposed on a surface of the first capacitor electrode, and a second capacitor electrode disposed on a surface of the dielectric pattern and electrically connected to the second channel.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly, to a three-dimensional DRAM device. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory used to store data for active use or processing. Unlike static random access memory (RAM), DRAM stores each bit of data in a separate capacitor. DRAM devices typically include word lines, bit lines, channels, and capacitors, and in order to increase the integration of DRAM devices, a method for efficiently arranging word lines, bit lines, channels, and capacitors is required. Summary of the invention

[0003] A semiconductor device includes a first bit line, a second bit line, a word line, a first channel, a second channel, and a capacitor. The first bit line and the second bit line are located on a substrate. Each of the first bit line and the second bit line extends in a first direction substantially perpendicular to the upper surface of the substrate. The first bit line and the second bit line are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate. The word line includes a first extension portion and a second extension portion. The first extension portion is arranged between the first bit line and the second bit line, and each of the first extension portions mainly extends in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction. The second extension portion extends along the second direction at the same height as the first extension portion and is connected to the first extension portion. The first channel and the second channel both extend through the first extension portion of the word line. The capacitor includes a first capacitor electrode, a dielectric pattern, and a second capacitor electrode, the first capacitor electrode is electrically connected to the first channel, the dielectric pattern is arranged on the surface of the first capacitor electrode, and the second capacitor electrode is arranged on the surface of the dielectric pattern and is electrically connected to the second channel.

[0004] A semiconductor device includes a bit line, a first transistor, a capacitor, a second transistor and a word line. The bit line is arranged on a substrate, each of the bit lines mainly extends in a first direction, and the bit lines are spaced apart from each other in a second direction substantially perpendicular to the first direction. The first transistor, the capacitor and the second transistor are sequentially arranged between the bit lines along the two directions. The word line includes a first extension portion and a second extension portion. The first extension portion is electrically connected to the first transistor and the second transistor, respectively, and each of the first extension portions extends in a third direction substantially perpendicular to the first direction and the second direction. The second extension portion extends in the second direction and is connected to the first extension portion. Each of the first transistor and the second transistor includes a gate electrode, a channel, and a first source / drain layer and a second source / drain layer, the gate electrode is electrically connected to each of the first extension portions of the word line, the channel is electrically connected to the gate electrode, and the first source / drain layer and the second source / drain layer are respectively located on opposite sides of the channel in the second direction. The capacitor includes a first capacitor electrode, a dielectric pattern and a second capacitor electrode stacked sequentially. The first source / drain layer of the first transistor and the first source / drain layer of the second transistor are electrically connected to the bit line, respectively, and the second source / drain layer of the first transistor and the second source / drain layer of the second transistor are electrically connected to the first capacitor electrode and the second capacitor electrode, respectively.

[0005] A semiconductor device includes a first bit line, a second bit line, a word line, a first channel and a second channel, a first source / drain layer, a second source / drain layer, a capacitor, a third source / drain layer, a fourth source / drain layer, a connection pattern, and an insulation pattern. The first bit line and the second bit line are arranged on a substrate, each of the first bit line and the second bit line mainly extends in a first direction substantially perpendicular to the upper surface of the substrate, and the first bit line and the second bit line are spaced apart from each other in a second direction substantially parallel to the upper surface of the substrate. The word line includes a first extension portion and a second extension portion. The first extension portion is arranged between the first bit line and the second bit line, and each of the first extension portions extends in a third direction substantially parallel to the upper surface of the substrate and intersecting the second direction. The second extension portion extends along the second direction at the same height as the first extension portion and is connected to the first extension portion. The first channel and the second channel both extend through the first extension portion of the word line. The first source / drain layer is arranged between the first bit line and the first channel and contacts both the first bit line and the first channel. The second source / drain layer is disposed between the second bit line and the second channel and contacts both the second bit line and the second channel. The capacitor includes a first capacitor electrode, a dielectric pattern, and a second capacitor electrode, the dielectric pattern being disposed on a surface of the first capacitor electrode, and the second capacitor electrode being disposed on a surface of the dielectric pattern. The third source / drain layer is disposed between the first channel and the first capacitor electrode and contacts both the first channel and the first capacitor electrode. The fourth source / drain layer is disposed between the second channel and the second capacitor electrode. The connection pattern contacts both the second capacitor electrode and the fourth source / drain layer. The insulation pattern is disposed between the second capacitor electrode and the connection pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] A more complete understanding of the present disclosure and its many attendant aspects will be readily obtained as the disclosure and its many attendant aspects become better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 is an equivalent circuit diagram illustrating a sub-cell array included in a cell array of a semiconductor device;

[0008] Figure 2 is a graph illustrating a voltage variation of a bit line included in a semiconductor device;

[0009] Figure 3 is a perspective view illustrating a semiconductor device according to example embodiments;

[0010] Figure 4 is a top view illustrating a semiconductor device according to example embodiments;

[0011] Figure 5 is a perspective view illustrating a semiconductor device according to example embodiments;

[0012] Figure 6 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0013] Figure 7 is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0014] Figure 8 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0015] Fig. 9 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0016] Fig.10 is a top view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0017] Fig.11 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0018] Fig.12 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0019] Fig.13 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0020] Fig.14 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0021] Fig.15 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0022] Fig.16 is a top view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0023] Fig.17 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0024] Fig.18 is a top view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0025] Fig.19is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0026] Fig. 20 is a top view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0027] Fig.21 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0028] Fig. 22 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0029] Fig.23 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0030] Fig.24 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0031] Fig.25 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0032] Fig.26 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0033] Fig. 27 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0034] Fig.28 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0035] Fig.29 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0036] Fig.30 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0037] Fig.31 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0038] Fig.32 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0039] Fig.33 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0040] Fig.34is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0041] Fig.35 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0042] Fig.36 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0043] Fig.37 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0044] Fig.38 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0045] Fig.39 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0046] Fig.40 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0047] Fig.41 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0048] Fig.42 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0049] Fig.43 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0050] Fig.44 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0051] Fig.45 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0052] Fig.46 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0053] Fig.47 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0054] Fig.48 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0055] Fig.49is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0056] Fig.50 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0057] Fig.51 is a perspective view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0058] Fig.52 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments;

[0059] Fig.53 is a perspective view illustrating a semiconductor device according to example embodiments;

[0060] Fig.54 is a perspective view illustrating a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0061] According to the detailed description below with reference to the accompanying drawings, the above and other aspects and features of the semiconductor device and its manufacturing method according to the example embodiments will become easy to understand. It will be understood that although the terms "first", "second" and / or "third" can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not necessarily be limited to these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the inventive concept, the first element, component, region, layer or part discussed below can be referred to as the second or third element, component, region, layer or part.

[0062] Hereinafter, in the specification (and not necessarily in the claims), a vertical direction substantially perpendicular to the upper surface of the substrate may be referred to as a first direction D1, and two intersecting directions among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as a second direction D2 and a third direction D3, respectively. In example embodiments, the second direction D2 and the third direction D3 are substantially perpendicular to each other. Each of the first direction D1, the second direction D2, and the third direction D3 may include not only the directions shown in the drawings, but also the directions opposite thereto.

[0063] Figure 1 is an equivalent circuit diagram illustrating a sub-cell array included in a cell array of a semiconductor device, and Figure 2 is a graph illustrating voltage variation of a bit line included in a semiconductor device.

[0064] refer to Figure 1, the cell array of the semiconductor device may include a plurality of sub-cell arrays SCA arranged along the second direction D2, and each sub-cell array SCA may include a plurality of first bit lines BL1, a plurality of second bit lines BL2, a plurality of word lines WL, and a plurality of memory cells MC.

[0065] In each subcell array SCA, each of the first bit line BL1 and the second bit line BL2 may extend mainly in the first direction D1, and the plurality of first bit lines BL1 may be spaced apart from each other in the third direction D3, and the plurality of second bit lines BL2 may be spaced apart in the third direction D3. The first bit line BL1 and the second bit line BL2 adjacent in the second direction D2 may form a bit line pair.

[0066] In each sub cell array SCA, memory cells MC may be disposed between a first bit line BL1 and a second bit line BL2 included in a bit line pair, and in each bit line pair, a plurality of memory cells MC may be spaced apart from each other in the first direction D1 .

[0067] In example embodiments, each memory cell MC may include a first transistor TR1, a second transistor TR2, and a capacitor CAP disposed between the first transistor TR1 and the second transistor TR2. The first transistor TR1 may include a first gate electrode and first and second source / drain layers on opposite sides of the first gate electrode, and the second transistor TR2 may include a second gate electrode and first and second source / drain layers on opposite sides of the second gate electrode.

[0068] The first source / drain layer included in the first transistor TR1 may be electrically connected to the first bit line BL1, and the second source / drain layer included in the first transistor TR1 may be electrically connected to the first electrode of the capacitor CAP. Additionally, the first source / drain layer included in the second transistor TR2 may be electrically connected to the second bit line BL2, and the second source / drain layer included in the second transistor TR2 may be electrically connected to the second electrode of the capacitor CAP.

[0069] In example embodiments, first gate electrodes included in a plurality of first transistors TR1 respectively disposed at a first level along a third direction D3 may be electrically connected to first word lines among word lines WL extending at a first level along the third direction D3, and second gate electrodes included in a plurality of second transistors TR2 respectively disposed at a second level along the third direction D3 may be electrically connected to second word lines among word lines WL extending mainly along the third direction D3 at a second level.

[0070] As used herein, the phrase "mainly extending along a certain direction (mainly in a certain direction)" is understood to mean that the element so extended is an element that occupies two or three dimensions in space, so its main direction of extension is the direction in which the element extends to the greatest extent, for example, the length direction. Therefore, in the case where the word line WL mainly extends along the third direction D3, the longest dimension of the word line WL is aligned with the third direction D3.

[0071] In an example embodiment, when a first word line among word lines WL electrically connected to a first gate electrode and a second word line among word lines WL electrically connected to a second gate electrode are set at the same height, the first word line among word lines WL and the second word line among word lines WL can be electrically connected to each other, and thus the first gate electrode and the second gate electrode at the same height can be electrically connected to the same word line WL.

[0072] refer to Figure 1 as well as Figure 2 , when the memory cell MC is turned on, the source voltage may be supplied to the second bit line BL2 and the ground voltage may be supplied to the first bit line BL1, so that charges may be stored in the capacitor CAP. When the memory cell MC is turned off, the voltage of the second bit line BL2 may become a second saturation voltage VLB2 having a positive value by the charges stored in the capacitor CAP, and the voltage of the first bit line BL1 may become a first saturation voltage VLB1 having a negative value. The bit line sense amplifier may sense a first saturation voltage difference ΔV1 which is a difference between the first bit line saturation voltage VBL1 and the second bit line saturation voltage VBL2, and may amplify the first saturation voltage difference ΔV1.

[0073] The memory cell MC of the semiconductor device may have a 2T-1C structure including two transistors (e.g., a first transistor TR1 and a second transistor TR2) and a capacitor CAP disposed therebetween, so a first saturation voltage difference ΔV1 between a first saturation voltage VBL1 of a first bit line BL1 and a second saturation voltage VBL2 of a second bit line BL2 may be greater than a second saturation voltage difference ΔV2 between the first bit line BL1 and the second bit line BL2 in the semiconductor device including the memory cell having the 1T-1C structure. Therefore, the bit line sense amplifier of the semiconductor device may have an increased sensing margin.

[0074] Figures 3 to 7 1 is a perspective view, a top view, and a cross-sectional view illustrating a semiconductor device according to an example embodiment. In particular, Figure 3 and Figure 5 It is a stereogram. Figure 4 It is a top view. Figure 6 yes Figure 3 A cross-sectional view of a region X taken along a vertical direction, and Figure 7 yes Figure 3 A cross-sectional view of region Y taken along the vertical direction. Figure 5 is a perspective view of a portion of a semiconductor device, which is based on Figure 3 Perspective of different angles of the stereogram.

[0075] Figures 3 to 7 It's a picture. Figure 1 FIG. 1 is a diagram showing a portion of a subcell array SCA of a semiconductor device.

[0076] refer to Figures 3 to 7 The semiconductor device may include a gate structure 230 , a channel 125 , a first source / drain layer 520 and a second source / drain layer 490 , a capacitor 470 , a first bit line 532 and a second bit line 534 , a contact plug 600 , a connection pattern 127 , and an insulation pattern 360 on a substrate 100 .

[0077] The semiconductor device may further include an insulating interlayer disposed on the substrate 100 and covering the above structure.

[0078] The substrate 100 may include a semiconductor material (eg, silicon, germanium, silicon germanium, etc.) or a III-V compound semiconductor (eg, GaP, GaAs, GaSb, etc.) In example embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0079] The substrate 100 may include a first region I and a second region II. The first region I may be a cell region where a memory cell is formed, and the second region II may be an extension region where a contact plug 600 for transmitting an electrical signal to the memory cell is formed. In example embodiments, the second region II may be disposed on one side of the first region I in the third direction D3. However, the inventive concept is not necessarily limited thereto, and for example, the second region II may be disposed on each of opposite sides of the first region I in the third direction D3, or may at least partially surround the first region I.

[0080] The substrate 100 may also include a third region, which is a peripheral circuit region in which a peripheral circuit pattern is formed. The third region may at least partially surround the first region I and the second region II, or may be disposed below or above the substrate 100, so that the semiconductor device may have a cell over periphery (COP) structure or a periphery over cell (POC) structure. As used herein, the phrase "at least partially surrounding" is understood to mean that the surrounding element may contact the surrounded element on at least one side or part thereof, may contact the surrounded element on both sides (whether the two sides are opposite sides or adjacent sides), may contact the surrounded element on more than two sides, or may even completely surround the surrounded element.

[0081] Each of the first bit line 532 and the second bit line 534 may extend mainly along the first direction D1 on the first region I of the substrate 100, and the plurality of first bit lines 532 may be spaced apart from each other in the third direction D3, and the plurality of second bit lines 534 may be spaced apart from each other in the third direction D3. The first bit line 532 and the second bit line 534 adjacent in the second direction D2 may form a bit line pair. In example embodiments, the plurality of bit line pairs may be spaced apart from each other in the third direction D3. Each of the first bit line 532 and the second bit line 534 may have a shape such as a polygon, a rounded polygon, a circle, an ellipse, etc.

[0082] The memory cell may extend mainly in the second direction D2 between the first bit line 532 and the second bit line 534. In example embodiments, the memory cell may include a capacitor 470, a first transistor between the capacitor 470 and the first bit line 523, and a second transistor between the capacitor 470 and the second bit line 534. The first transistor may include a second source / drain layer 490, a channel 125, and a first source / drain layer 520 sequentially disposed between the capacitor 470 and the first bit line 532, and a gate structure 230 surrounding the channel 125, and the second transistor may include a second source / drain layer 490, a channel 125, and a first source / drain layer 520 sequentially disposed between the capacitor 470 and the second bit line 534, and a gate structure 230 surrounding the channel 125.

[0083] In example embodiments, the plurality of memory cells may be spaced apart from each other in the first direction D1 between the bit line pairs. Since the plurality of bit line pairs are spaced apart from each other in the third direction D3, the plurality of memory cells may be spaced apart from each other in the third direction D3. Figures 3 to 7Three memory cells spaced apart from each other in the third direction D3 at each of three heights spaced apart from each other in the first direction D1 on the substrate 100 are illustrated, however, the inventive concept is not necessarily limited thereto.

[0084] In example embodiments, the capacitor 470 may include a first capacitor electrode 380 having a columnar shape extending mainly in the second direction D2, a dielectric pattern 440 having a hollow cylindrical shape that may surround a surface (e.g., a lower surface and an upper surface) of the first capacitor electrode 380 and opposite sidewalls in a third direction D3, and a second capacitor electrode 460 having a hollow cylindrical shape that may surround a surface (e.g., a lower surface and an upper surface) of the dielectric pattern 440 and opposite outer sidewalls in the third direction D3. However, the inventive concept is not necessarily limited thereto, and for example, the first capacitor electrode 380 may have a hollow cylindrical shape instead of a columnar shape, and the second capacitor electrode 460 may have a hollow cylindrical shape.

[0085] In example embodiments, the dielectric pattern 440 may not cover surfaces (eg, upper and lower surfaces) of portions of the first capacitor electrode 380 adjacent to the second source / drain layer 490 included in the first transistor and opposite sidewalls in the third direction D3 .

[0086] In example embodiments, the cross-section of the first capacitor electrode 380 in the third direction D3 may have a rectangular shape. However, the inventive concept is not necessarily limited thereto, and the cross-section of the first capacitor electrode 380 in the third direction D3 may have a shape such as a polygon, a rounded polygon, a circle, an ellipse, etc.

[0087] In example embodiments, a first sidewall of the first capacitor electrode 380 in the second direction D2 may contact a sidewall of a second source / drain layer 490 included in the first transistor in the second direction D2 and may be electrically connected to the sidewall. A second sidewall of the first capacitor electrode 380 in the second direction D2 may not contact a sidewall of the second source / drain layer 490 included in the second transistor in the second direction D2.

[0088] In example embodiments, the insulating pattern 360 and the connecting pattern 127 may be sequentially disposed between and contact the second sidewall of the first capacitor electrode 380 and the sidewall of the second source / drain layer 490 included in the second transistor in the second direction D2. Each of the insulating pattern 360 and the connecting pattern 127 may have a column shape mainly extending in the second direction D2, and an extending length of each of the insulating pattern 360 and the connecting pattern 127 in the second direction D2 may be smaller than an extending length of the first capacitor electrode 380.

[0089] A cross-section of each of the insulating pattern 360 and the connecting pattern 127 in the third direction D3 may be substantially the same as a cross-section of the first capacitor electrode 380. In example embodiments, a thickness of the insulating pattern 360 in the first direction D1 and a width in the third direction D3 may be substantially the same as a thickness of the first capacitor electrode 380 in the first direction D1 and a width in the third direction D3, and a thickness of the connecting pattern 127 in the first direction D1 and a width in the third direction D3 may be substantially the same as a thickness of a structure including the first capacitor electrode 380 and the dielectric pattern 440 in the first direction D1 and a width in the third direction D3, however, the inventive concept is not necessarily limited thereto.

[0090] As used herein, the phrase "substantially the same" may mean that the two elements being compared are equal in the stated aspect, or nearly equal so that they appear equal, but may vary by an imperceptible and / or insignificant degree, for example, by 10%, 5%, 2%, 1% or less than 1%.

[0091] The insulating pattern 360 may include an insulating material. The connection pattern 127 may include a semiconductor material doped with n-type or p-type impurities, for example, silicon doped with n-type or p-type impurities or silicon germanium doped with n-type or p-type impurities. Alternatively, the connection pattern 127 may include an oxide semiconductor material doped with n-type or p-type impurities, for example, IGZO doped with n-type or p-type impurities.

[0092] Since the insulating pattern 360 is disposed between the second sidewall of the first capacitor electrode 380 in the second direction D2 and the sidewall of the second source / drain layer 490 included in the second transistor in the second direction D2, the first capacitor electrode 380 may not be electrically connected to the second source / drain layer 490 included in the second transistor.

[0093] The dielectric pattern 440 may cover not only lower and upper surfaces and opposite sidewalls in the third direction D3 of the first capacitor electrode 380 but also surfaces (eg, lower and upper surfaces) and opposite sidewalls in the third direction D3 of the insulating pattern 360 .

[0094] The second capacitor electrode 460 may cover not only the lower and upper surfaces and the opposite outer sidewalls in the third direction D3 of the dielectric pattern 440, but also the surface (e.g., the lower and upper surfaces) and the opposite sidewalls in the third direction D3 of the connection pattern 127. Therefore, the second capacitor electrode 460 may contact the connection pattern 127 so as to be electrically connected to the second source / drain layer 490 included in the second transistor, wherein the second source / drain layer 490 may contact the connection pattern 127. The second capacitor electrode 460 may be spaced apart from the second source / drain layer 490 included in the first transistor so as not to be electrically connected to the second source / drain layer 490 included in the first transistor.

[0095] Each of the first capacitor electrode 380 and the second capacitor electrode 460 may include a conductive material, for example, a metal, a metal nitride, a metal silicide, doped silicon germanium, etc. The dielectric pattern 440 may include a metal oxide (for example, hafnium oxide, zirconium oxide, etc.) or a ferroelectric material having a high dielectric constant. As used herein, the phrase "high dielectric constant" may be understood as a dielectric constant greater than that of silicon oxide.

[0096] The channel 125 may include a semiconductor material, such as silicon, germanium, silicon germanium, etc. Alternatively, the channel 125 may include an oxide semiconductor material, such as zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), or the like. x ), Indium Gallium Zinc Oxide (IGZO), Indium Gallium Silicon Oxide (IGSO), Indium Oxide (InO x 、In 2 O 3 ), tin oxide (SnO 2 ), titanium oxide (TiO x ), zinc oxynitride (Zn x O y N z ), magnesium zinc oxide (Mg x Zn y O z ), Indium Zinc Oxide (In x Zn y O a ), Indium Gallium Zinc Oxide (In x Ga y Zn z O a ), zirconium indium zinc oxide (Zr x In y Zn z O a ), Hafnium Indium Zinc Oxide (Hf x In y Zn z O a), tin indium zinc oxide (Sn x In y Zn z O a ), aluminum oxide, tin, indium, zinc (Al x Sn y In z Zn a O d ), Silicon Indium Zinc Oxide (Si x In y Zn z O a ), zinc tin oxide (Zn x Sn y O z ), aluminum zinc tin oxide (Al x Zn y Sn z O a ), gallium zinc tin oxide (Ga x Zn y Sn z O a )、Zirconium oxide zinc tin (Zr x Zn y Sn z O a ) and / or indium gallium silicon oxide (InGaSiO).

[0097] Each of the first source / drain layer 520 and the second source / drain layer 490 may include substantially the same material as the channel 125, however, n-type or p-type impurities may be doped therein. The first source / drain layer 520 and the second source / drain layer 490 may include impurities of the same conductivity type.

[0098] In example embodiments, the gate structure 230 may include a gate insulating pattern 210 covering a surface (e.g., a lower surface and an upper surface) and opposite sidewalls in a third direction D3 of the channel 125, and a gate electrode 220 covering a surface (e.g., a lower surface and an upper surface) and opposite outer sidewalls in the third direction D3 of the gate insulating pattern 210. Therefore, the channel 125 may extend through the gate structure 230 in the second direction D2, and the gate structure 230 may have a gate all around (GAA) structure surrounding the channel 125.

[0099] Alternatively, the gate structure 230 may have a single gate structure or a dual gate structure instead of a GAA structure. For example, the gate structure 230 may be disposed on or below the channel 125 , or two gate structures 230 may be disposed on and below the channel 125 , respectively, instead of surrounding the channel 125 .

[0100] As a result, if only the gate structure 230 is electrically connected to the channel 125 , the gate structure 230 may have various other types of structures.

[0101] In an example embodiment, the gate electrodes 220 disposed adjacent to each other in the third direction D3 and the gate insulating pattern 210 covering the channel 125 at the same height may be connected to each other, so that a word line extending mainly in the third direction D3 may be formed on the first region I and the second region II of the substrate 100. In addition, the word lines spaced apart from each other in the second direction D2 at the same height (each of which may extend mainly in the third direction D3) may extend to connect to each other on the second region II of the substrate 100. The connected word lines may be formed integrally. As used herein, the phrase "integrally formed" may mean that two elements are formed together as a single, continuous and uninterrupted structure.

[0102] Hereinafter, in a word line that may be integrally formed of two connected word lines at the same height, portions extending mainly in the third direction D3 may be respectively referred to as first extension portions 222, and portions extending mainly in the second direction D2 to contact the first extension portions 222 may be referred to as second extension portions 224. A portion of each of the first extension portions of the word line that may at least partially surround a channel 125 included in a single memory cell may be defined as a gate electrode 220.

[0103] As a result, two gate electrodes 220 located at opposite sides of the capacitor 470 in the second direction D2 at the same height may be electrically connected to the same word line, and gate electrodes 220 disposed at the same height along the third direction D3 may also be electrically connected to the same word line.

[0104] In example embodiments, the second extending portion 224 of the word line may be disposed in a stepped manner along the third direction D3 on the second region II of the substrate 100 .

[0105] In example embodiments, the length of the first extending portion 222 of the word line connected to the second extending portion 224 of the word line may increase from a highest height to a lowest height in the third direction D3.

[0106] Alternatively, the length of the first extending portion 222 of the word line connected to the second extending portion 224 of the word line in the third direction D3 may decrease from the highest height to the lowest height.

[0107] Alternatively, the length of the first extending portion 222 of the word line connected to the second extending portion 224 of the word line in the third direction D3 may increase from the highest height to the lowest height and then decrease, or decrease from the highest height to the lowest height and then increase.

[0108] The gate electrode 220 may include a conductive material, for example, a metal, a metal nitride, a metal silicide, or the like, and the gate insulating pattern 210 may include an oxide, for example, silicon oxide, a metal oxide, or the like.

[0109] On the second region II of the substrate 100, a contact plug 600 may be disposed on and may contact the second extending portion 224 of the word line. In example embodiments, one contact plug 600 or a plurality of contact plugs 600 may be disposed on the second extending portion 224 of the word line in various layouts.

[0110] Figures 3 to 7 It is shown that each contact plug 600 is disposed on the interface between the first extension portion 222 and the second extension portion 224, and the contact plug 600 is arranged in a zigzag pattern in a top view, however, the inventive concept is not necessarily limited thereto. For example, each contact plug 600 may also be disposed on, for example, the central portion of the second extension portion 224, and the contact plug 600 may be arranged in a zigzag pattern in a top view. The contact plug 600 may include a conductive material, for example, a metal, a metal nitride, a metal silicide, etc.

[0111] In the semiconductor device, the gate electrode 220, the channel 125, and the first source / drain layer 520 and the second source / drain layer 490 may form each of the first transistor and the second transistor. The first source / drain layer 520 of the first transistor may be electrically connected to the first bit line 532, and the second source / drain layer 490 of the first transistor may be electrically connected to the first capacitor electrode 380 included in the capacitor 470. Additionally, the first source / drain layer 520 of the second transistor may be electrically connected to the second bit line 534, and the second source / drain layer 490 of the second transistor may be electrically connected to the second capacitor electrode 460 included in the capacitor 470 through the connection pattern 127. The gate electrodes 220 respectively included in the first transistor and the second transistor may be connected to the same word line.

[0112] Therefore, each memory cell of the semiconductor device can have a 2T-1C structure including a first transistor and a second transistor and a capacitor 470 located therebetween, and a bit line sense amplifier can have a high sense margin.

[0113] Additionally, when the semiconductor device has a COP structure or a POC structure, the bit line sense amplifier may be disposed below or above the first bit line 532 and the second bit line 534, which may be disposed at the same height, and thus may be spaced apart by the same distance from the first bit line 532 and the second bit line 534. For example, if the first bit line 532 and the second bit line 534 extend in a horizontal direction at different heights, respectively, distances from the bit line sense amplifier, which may be disposed below or above the first bit line 532 and the second bit line 534, to the first bit line 532 and the second bit line 534 may be different from each other, and thus a signal delay may occur.

[0114] However, in example embodiments, the first bit line 532 and the second bit line 534 may extend the same length at substantially the same height so that the distances from the bit line sense amplifier to the first bit line 532 and the second bit line 534 may be the same, thereby not causing signal delay.

[0115] Figures 8 to 52 are a perspective view, a top view, a front view, and a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments.

[0116] In particular, Figure 8 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 , Fig.19 , Fig. 22 , Figure 25-29 , Fig.31 , Figure 33-Figure 35 , Fig.37 , Figure 39-Figure 42 and Figure 45-Figure 50 It is a stereogram. Fig.10 , Fig.16 , Fig.18 and Fig. 20 They are the top views corresponding to the stereograms, Fig.12 , Fig.14 , Fig.21 , Fig.23 and Fig.51 They are the front views of the corresponding stereograms, Fig.24 and Fig.52 are cross-sectional views taken along the line AA' of the corresponding stereogram, Fig.30 and Fig.32 are cross-sectional views taken along line BB' of the corresponding stereogram, Fig.36 and Fig.38 are cross-sectional views taken along the line CC' of the corresponding stereogram, Fig.43 is a cross-sectional view taken along line EE' of the corresponding stereogram, and Fig.44 It is a cross-sectional view taken along the line FF' of the corresponding perspective view.

[0117] Figures 8 to 52 is a diagram illustrating a first region of a substrate, and in particular, Figure 26 to Figure 46 It's a picture. Fig.25 FIG. 2 is a diagram of a region Z of FIG.

[0118] refer to Figure 8 The first sacrificial layer 110 and the semiconductor layer 120 may be alternately and repeatedly stacked along the first direction D1 in the region including the first region I and the second region II (refer to Figure 3 and Figure 4 ) on a substrate 100 to form a molding layer.

[0119] In example embodiments, the semiconductor layer 120 may include, for example, silicon, and the first sacrificial layer 110 may include a material having an etching selectivity with respect to the semiconductor layer 120, for example, silicon germanium. Alternatively, the semiconductor layer 120 may include silicon germanium, and the first sacrificial layer 110 may include silicon. Alternatively, the semiconductor layer 120 may include an oxide semiconductor material such as IGZO.

[0120] refer to Fig. 9 and Fig.10 , for example, a dry etching process may be performed on the mold layer to form the first hole 130 and the second hole 140 passing through the mold layer, which may expose the upper surface of the substrate 100 .

[0121] Each of the first hole 130 and the second hole 140 may extend mainly in the first direction D1, a plurality of the first holes 130 may be spaced apart from each other in the second direction D2 and the third direction D3, and a plurality of the second holes 140 may be spaced apart from each other in the second direction D2 and the third direction D3. In example embodiments, the second holes 140 and the first holes 130 may be arranged in this order along the second direction D2 from a central portion (hereinafter, referred to as a first portion) of the mold layer in the second direction D2, and the first holes 130 and the second holes 140 adjacent in the second direction D2 may form a hole pair.

[0122] The mold layer may include a plurality of areas, each of which may include a first portion and opposite edge portions (hereinafter, respectively referred to as second portions) located at opposite sides of the first portion in the second direction D2 and forming the hole pairs. Figures 8 to 52 A first region among the plurality of regions and portions of a second region among the plurality of regions, respectively located on the opposite side of the first region in the third direction D3 , are respectively shown.

[0123] refer to Fig.11 and Fig.12 , portions of the first sacrificial layer 110 adjacent to the first and second holes 130 and 140 may be removed by an etching process to form a first sacrificial pattern 115 .

[0124] In example embodiments, the etching process may include a wet etching process, and through the etching process, the first sacrificial pattern 115 may remain only in the first portion of the mold layer. Additionally, in each second portion of the mold layer and a portion of the first portion of the mold layer adjacent to each second portion of the mold layer, a first gap 150 may be formed between adjacent semiconductor layers of the semiconductor layer 120 in the first direction D1.

[0125] refer to Fig.13 and Fig.14 , a first sacrificial insulating pattern 160 and a second sacrificial insulating pattern 170 may be formed in the first gap 150 .

[0126] In example embodiments, a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, etc., may be performed to form a first sacrificial insulating layer on inner walls of the first hole 130 and the second hole 140 and inner walls of the first gap 150, a second sacrificial insulating layer may be formed on the first sacrificial insulating layer to fill a portion or the entire portion of the first gap 150 and each of the first hole 130 and the second hole 140, a planarization process may be performed on the first sacrificial insulating layer and the second sacrificial insulating layer until an upper surface of the mold layer is exposed, and portions of the first sacrificial insulating layer and the second sacrificial insulating layer in each of the first hole 130 and the second hole 140 may be removed by, for example, a dry etching process to form a first sacrificial insulating pattern 160 and a second sacrificial insulating pattern 170 in the first gap 150.

[0127] The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process. The first sacrificial insulating pattern 160 may include an insulating nitride, such as silicon nitride, and the second sacrificial insulating pattern 170 may include an oxide, such as silicon oxide.

[0128] As the first sacrificial insulating pattern 160 and the second sacrificial insulating pattern 170 are formed in the first gap 150, the first sacrificial insulating pattern 160, the second sacrificial insulating pattern 170, the first sacrificial insulating pattern 160 and the semiconductor layer 120 can be alternately and repeatedly stacked along the first direction D1 on each second portion of the mold layer and on portions of the first portion of the mold layer adjacent to each second portion of the mold layer in the second direction D2.

[0129] refer to Fig.15 and Fig.16 , portions of the semiconductor layer 120 adjacent to the first hole 130 and the second hole 140 may be removed by, for example, a wet etching process, and thus the first hole 130 and the second hole 140 may be expanded in a horizontal direction at a height at which each semiconductor layer 120 is formed.

[0130] In example embodiments, the first hole 130 and the second hole 140 included in each hole pair at a height where each semiconductor layer 120 is formed may be enlarged to merge with each other to form a third hole 180 connected to the first hole 130 and the second hole 140 at a height where the first sacrificial insulating pattern 160 and the second sacrificial insulating pattern 170 are formed. Hereinafter, a portion of each of the first hole 130 and the second hole 140 where each semiconductor layer 120 is formed may be referred to as a third hole 180. A lower surface and an upper surface of a portion of the first sacrificial insulating pattern 160 in the first gap 150 (particularly, a portion of the first sacrificial insulating pattern 160 adjacent to each of the first hole 130 and the second hole 140) may be exposed by the third hole 180.

[0131] refer to Fig.17 and Fig.18 , the first sacrificial insulating interlayer pattern 190 may fill the first hole 130 and a portion of the third hole 180 overlapping the first hole 130 in the first direction D1.

[0132] In example embodiments, a first sacrificial insulating interlayer may be formed on the substrate 100 and the mold layer to fill the first hole 130, the second hole 140, and the third hole 180, a planarization process may be performed on the first sacrificial insulating interlayer until an upper surface of the mold layer is exposed, and, for example, a dry etching process may be performed on the first sacrificial insulating interlayer to form a first sacrificial insulating interlayer pattern 190.

[0133] The first sacrificial insulating interlayer pattern 190 may mainly extend in the first direction D1, and a plurality of first sacrificial insulating interlayer patterns 190 may be spaced apart from each other along the third direction D3 on each second portion of the mold layer. The first sacrificial insulating interlayer pattern 190 may include oxide, eg, silicon oxide.

[0134] As the first insulating interlayer pattern 190 is formed, portions of the second hole 140 and the third hole 180 that do not overlap with the first hole 130 in the first direction D1 may remain.

[0135] refer to Figures 19 to 21 Among the portions of the first sacrificial insulating pattern 160 located on each second portion of the mold layer, portions of the first sacrificial insulating pattern 160 that are not covered by the first insulating interlayer pattern 190 may be removed by an etching process.

[0136] In example embodiments, the etching process may include a wet etching process and / or a dry etching process, and a portion of the first sacrificial insulating pattern 160 overlapping the remaining portion of the third hole 180 in the first direction D1 may be removed by the etching process. Thus, a second gap 200 may be formed between each second sacrificial insulating pattern 170 and the semiconductor layer 120, and a lower surface and an upper surface of a portion of each semiconductor layer 120 overlapping the remaining portion of the third hole 180 in the first direction D1 may be exposed by the second gap 200.

[0137] refer to Figure 22 to Figure 24 A gate insulating layer may be formed on inner walls of the second hole 140, the third hole 180 and the second gap 200, a gate electrode layer may be formed on the gate insulating layer to fill the second hole 140, the third hole 180 and the second gap 200, a planarization process may be performed on the gate electrode layer and the gate insulating layer until the upper surface of the mold layer is exposed, and other portions of the gate electrode layer and the gate insulating layer except for portions of the gate electrode layer and the gate insulating layer adjacent to the first portion of the semiconductor layer 120 between the first sacrificial insulating interlayer patterns 190 in the second direction D2 may be removed by an etching process.

[0138] Therefore, a gate insulation pattern 210 covering a surface (e.g., a lower surface and an upper surface) of a second portion of the semiconductor layer 120 adjacent to the first portion of the semiconductor layer 120 in the second direction D2 and opposite sidewalls in the third direction D3 and a gate electrode 220 covering the gate insulation pattern 210 may be formed.

[0139] In example embodiments, the plurality of gate insulating patterns 210 may be spaced apart from each other in the third direction D3 at a height at which each semiconductor layer 120 is formed at each second portion of the mold layer, and may also be spaced apart from each other along the first direction D1.

[0140] A plurality of gate electrodes 220 spaced apart from each other in the first direction D1 may be formed at a plurality of heights at each second portion of the mold layer, respectively. The gate electrodes 220 and the gate insulating pattern 210 may collectively form a gate structure 230 .

[0141] In example embodiments, the gate electrode 220 may extend mainly in the third direction D3 on the first region I and the second region II of the substrate 100 to form a first extension portion 222 (see FIG. 2 ). Figure 3 and Figure 4 ), and may extend mainly in the second direction D2 on the second region II of the substrate 100 to form a second extension portion 224 (refer to Figure 3 and Figure 4). The first extension portions 222 , each at the second portion of the mold layer, may contact the second extension portion 244 on the second region II of the substrate 100 .

[0142] In an example embodiment, the second extension portion 224 of the word line may be arranged in a stepped manner along the third direction D3 on the second region II of the substrate 100, so that the length of the first extension portion 222 of the word line connected to the second extension portion 224 of the word line in the third direction D3 may increase in a stepped manner from the highest height to the lowest height.

[0143] During the etching process, portions of the second sacrificial insulating pattern 170 that are not covered by the gate insulating pattern 210 and the gate electrode 220, for example, portions of the second sacrificial insulating pattern 170 adjacent to the second hole 140 in the third direction D3, may also be removed, so that the second gaps 200 located above and below the second sacrificial insulating pattern 170, respectively, may be expanded along the first direction D1 so as to merge into the third gap 205.

[0144] refer to Fig.25 , a second sacrificial insulating interlayer pattern 250 may be formed on the substrate 100 to fill the second and third holes 140 and 180 and the third gap 205 and cover the semiconductor layer 120 .

[0145] The second sacrificial insulating interlayer pattern 250 may include oxide, for example, silicon oxide.

[0146] refer to Fig.26 , a fourth hole 310 may be formed through a central portion of the first portion of the mold layer in the second direction D2.

[0147] The fourth hole 310 may mainly extend in the first direction D1 and may expose the upper surface of the substrate 100 .

[0148] In example embodiments, the fourth hole 310 may be formed through a dry etching process on the mold layer.

[0149] refer to Fig. 27 A portion of the first sacrificial pattern 115 adjacent to the fourth hole 310 in the third direction D3 may be removed to form a fourth gap 320 adjacent to the fourth hole 310 in the third direction D3 between portions of the semiconductor layer 120 adjacent to the semiconductor layer in the first direction D1.

[0150] In example embodiments, a plurality of fourth gaps 320 may be spaced apart from each other in the first direction D1 on the substrate 100, and each fourth gap 320 may be connected to the fourth hole 310. The fourth gap 320 may be formed by a wet etching process and / or a dry etching process on the first sacrificial pattern 115.

[0151] refer to Fig.28 , a second sacrificial pattern 330 may be formed in the fourth gap 320 .

[0152] In example embodiments, the second sacrificial pattern 330 may be formed by forming a second sacrificial layer on the substrate 100 to fill a portion or the entire portion of the fourth gap 320 and the fourth hole 310, performing a planarization process on the second sacrificial layer until an upper surface of the mold layer is exposed, and removing a portion of the second sacrificial layer in the fourth hole 310 by, for example, a dry etching process.

[0153] Thus, the plurality of second sacrificial patterns 330 may be spaced apart from each other in the first direction D1 at each of opposite sides of the fourth hole 310 in the third direction D3. The second sacrificial patterns 330 may include insulating nitride, for example, silicon nitride.

[0154] refer to Fig.29 and Fig.30 , a third sacrificial insulating interlayer pattern 340 can be formed in the fourth hole 310, and the mold layer can be partially removed by, for example, a dry etching process to form a fifth hole 350, which mainly extends in the first direction D1 and exposes the first end of the sidewall of the second sacrificial pattern 330 in the third direction D3 in the second direction D2 without contacting the sidewall of the third sacrificial insulating interlayer pattern 340.

[0155] In example embodiments, the third sacrificial insulating interlayer pattern 340 may be formed by forming a third sacrificial insulating interlayer on the substrate 100 to fill the fourth hole 310, and performing a planarization process on the third sacrificial insulating interlayer until an upper surface of the mold layer is exposed. The third sacrificial insulating interlayer pattern 340 may include an oxide, such as silicon oxide.

[0156] A portion of the semiconductor layer 120 adjacent to the fifth hole 350 in the third direction D3 may be removed by, for example, a wet etching process to form a fifth gap 355 exposing a sidewall of the third sacrificial insulating interlayer pattern 340 in the third direction D3 between the first sacrificial patterns 115 adjacent in the first direction D1. In example embodiments, a plurality of fifth gaps 355 may be spaced apart from each other in the first direction D1, and each fifth gap 355 may be connected to the fifth hole 350.

[0157] refer to Fig.31 and Fig.32 , a fourth sacrificial insulating interlayer pattern 360 may be formed in the fifth hole 350 and the fifth gap 355 .

[0158] In example embodiments, the fourth sacrificial insulating interlayer pattern 360 may be formed by forming a fourth sacrificial insulating interlayer on the substrate 100 to fill the fifth hole 350 and the fifth gap 355, and performing a planarization process on the fourth sacrificial insulating interlayer until the upper surface of the mold layer is exposed. The fourth sacrificial insulating interlayer pattern 360 may include a material having an etching selectivity with respect to the semiconductor layer 120, the first sacrificial pattern 115, the second sacrificial pattern 330, and the fourth sacrificial insulating interlayer pattern 360.

[0159] refer to Fig.33 , the third sacrificial insulating interlayer pattern 340 may be removed by an etching process to form the fourth hole 310 again, and a portion of the semiconductor layer 120 adjacent to the fourth hole 310 in the third direction D3 may be removed to form a sixth gap 370 between the second sacrificial patterns 330 adjacent in the first direction D1. In example embodiments, a plurality of sixth gaps 370 may be spaced apart from each other in the first direction D1, and each of the sixth gaps 370 may be connected to the fourth hole 310.

[0160] refer to Fig.34 , a first capacitor electrode 380 may be formed in the sixth gap 370 .

[0161] In example embodiments, the first capacitor electrode 380 may be formed by forming a first capacitor electrode layer on the substrate 100 to fill a portion or the entire portion of the fourth hole 310 and the sixth gap 370, performing a planarization process on the first capacitor electrode layer until an upper surface of the mold layer is exposed, and removing a portion of the first capacitor electrode layer in the fourth hole through an etching process.

[0162] The first capacitor electrode 380 may include a conductive material, for example, a metal, a metal nitride, a metal silicide, or the like.

[0163] refer to Fig.35 and Fig.36 , a fifth sacrificial insulating interlayer pattern 390 can be formed in the fourth hole 310, and the mold layer can be partially removed by, for example, a dry etching process to form a sixth hole 400, which mainly extends in the first direction D1 and exposes the second end of the sidewall of the second sacrificial pattern 330 in the third direction D3 in the second direction D2 without contacting the sidewall of the fifth sacrificial insulating interlayer pattern 390.

[0164] In example embodiments, the fifth sacrificial insulating interlayer pattern 390 may be formed by forming a fifth sacrificial insulating interlayer on the substrate 100 to fill the fourth hole 310, and performing a planarization process on the fifth sacrificial insulating interlayer until the upper surface of the mold layer is exposed. The fifth sacrificial insulating interlayer pattern 390 may include an oxide, such as silicon oxide.

[0165] A portion of the second sacrificial pattern 330 adjacent to the sixth hole 400 in the third direction D3 may be removed by, for example, a wet etching process to form a seventh gap 405 exposing a sidewall of the fifth sacrificial insulating interlayer pattern 390 in the third direction D3 between the first capacitor electrodes 380 adjacent in the first direction D1. In example embodiments, a plurality of seventh gaps 405 may be spaced apart from each other in the first direction D1, and each of the seventh gaps 405 may be connected to the sixth hole 400.

[0166] refer to Fig.37 and Fig.38 , a sixth sacrificial insulating interlayer pattern 410 may be formed in the sixth hole 400 and the seventh gap 405 .

[0167] In example embodiments, the sixth sacrificial insulating interlayer pattern 410 may be formed by forming a sixth sacrificial insulating interlayer on the substrate 100 to fill the sixth hole 400 and the seventh gap 405, and performing a planarization process on the sixth sacrificial insulating interlayer until the upper surface of the mold layer is exposed. The sixth sacrificial insulating interlayer pattern 410 may include an oxide, such as silicon oxide.

[0168] refer to Fig.39 , a dry etching process can be performed to remove: other portions of the fifth sacrificial insulating interlayer pattern 390 except for the portion of the fifth sacrificial insulating interlayer pattern 390 adjacent to the sixth sacrificial insulating interlayer pattern 410 in the third direction D3, and portions of the mold layer and the fourth sacrificial insulating interlayer pattern 360 on one side of the second sacrificial pattern 330 in the third direction D3.

[0169] Thus, the seventh hole 420 exposing the upper surface of the substrate 100 may be formed on each of the opposite sides of the second sacrificial pattern 330 in the third direction D3. The fourth sacrificial insulating interlayer pattern 360 may remain only on one side of the second sacrificial pattern 330 in the second direction D2, and hereinafter, may be referred to as an insulating pattern 360.

[0170] refer to Fig.40 , the second sacrificial pattern 330 exposed by the seventh hole 420 may be removed by, for example, a wet etching process.

[0171] Thus, the eighth gap 430 may be formed between the first capacitor electrodes 380 adjacent in the first direction D1 and between the fourth sacrificial insulating interlayer patterns 360 adjacent in the first direction D1.

[0172] refer to Fig.41 , a dielectric pattern 440 may be formed on surfaces (eg, lower and upper surfaces) of the first capacitor electrode 380 and the insulation pattern 360 and opposite sidewalls in the third direction D3 through a deposition process.

[0173] The dielectric pattern 440 may include a metal oxide having a high dielectric constant, for example, hafnium oxide, zirconium oxide, or the like.

[0174] A portion of the mold layer adjacent to the seventh hole 420 in the second direction D2 may be removed through an etching process to expand the seventh hole 420 in the second direction D2.

[0175] In example embodiments, the etching process may include a wet etching process and / or a dry etching process. As the etching process is performed, the connection pattern 127 may be formed at the sidewall in the second direction D2 of each of the insulating pattern 360 and the dielectric pattern 440. Impurities may be doped into the connection pattern 127 by, for example, a slope ion implantation process, and thus the connection pattern 127 may include a semiconductor material doped with impurities.

[0176] In example embodiments, the thickness of the connection pattern 127 in the first direction D1 and the width in the third direction D3 may be substantially the same as the thickness of the structure including the insulation pattern 360 and the dielectric pattern 440 in the first direction D1 and the width in the third direction D3, however, the inventive concept is not necessarily limited thereto.

[0177] refer to Figure 42 to Figure 44 The second capacitor electrode 460 may cover surfaces (eg, lower and upper surfaces) of the dielectric pattern 440 and the connection pattern 127 and opposite sidewalls in the third direction D3 through a deposition process.

[0178] The second capacitor electrode 460 may include a conductive material, for example, metal, metal nitride, metal silicide, doped silicon germanium, or the like.

[0179] The first capacitor electrode 380 , the dielectric pattern 440 , and the second capacitor electrode 460 , which are sequentially stacked, may form a capacitor 470 .

[0180] refer to Fig.45 For example, a dry etching process may be performed to partially remove the mold layer and the first and second sacrificial insulating patterns 160 and 170 .

[0181] In an exemplary embodiment, the thickness of the first sacrificial pattern 115 and the semiconductor layer 120 included in the first portion of the mold layer on each of the opposite sides of the capacitor 470 in the second direction D2 in the first direction D1 and the width in the third direction D3 may be substantially the same as the thickness of the first capacitor electrode 380 included in the capacitor 470 in the first direction D1 and the width in the third direction D3, however, the present inventive concept is not necessarily limited to this, for example, may be substantially the same as the thickness of the capacitor 470 in the first direction D1 and the width in the third direction D3.

[0182] refer to Fig.46 , the first sacrificial pattern 115 and the sixth sacrificial insulating interlayer pattern 410 may be removed by, for example, a wet etching process, so that the semiconductor layer 120 may remain on each of opposite sides of the capacitor 470 in the second direction D2.

[0183] refer to Fig.47 , a seventh sacrificial insulating interlayer pattern 480 may be formed on the substrate 100 to cover the capacitors 470, the second sacrificial insulating interlayer pattern 250 may be removed, and a second impurity region 490 may be formed at a corresponding portion of the semiconductor layer 120 adjacent to each capacitor 470 in the second direction D2 by, for example, a slope ion implantation process.

[0184] In example embodiments, the plurality of second impurity regions 490 may be spaced apart from each other in the first direction D1 and the third direction D3 at each of opposite sides of each capacitor 470 in the second direction D2 .

[0185] The seventh sacrificial insulating interlayer pattern 480 may include oxide, for example, silicon oxide.

[0186] refer to Fig.48 An eighth sacrificial insulating interlayer pattern 500 may be formed on the substrate 100 to cover the second impurity region 490 , and, for example, a dry etching process may be performed on each second portion of the mold layer to form an eighth hole 510 exposing the upper surface of the substrate 100 .

[0187] In example embodiments, the eighth hole 510 may expose: the sidewalls of the semiconductor layer 120 in the second direction D2 between the first sacrificial insulating interlayer patterns 190, and the sidewalls of the first sacrificial insulating layer 160 and the second sacrificial insulating layer pattern 170 in the second direction D2 between the semiconductor layers 120 adjacent in the first direction D1. Therefore, the eighth hole 510 may extend at each second portion of the mold layer, and a plurality of the eighth holes 510 may be spaced apart from each other in the third direction D3.

[0188] The first impurity regions 520 may be formed in corresponding portions of the semiconductor layer 120 exposed by the eighth hole 510 by, for example, a slope ion implantation process. In example embodiments, a plurality of first impurity regions 520 may be spaced apart from each other in the first and third directions D1 and D3 at each second portion of the mold layer.

[0189] refer to Fig.49 , a first bit line 532 and a second bit line 534 may be formed in the eighth hole 510 .

[0190] The first bit line 532 and the second bit line 534 can be formed by the following operations: forming a bit line layer on the substrate 100, the mold layer, the first sacrificial insulating interlayer pattern 190, the seventh sacrificial insulating interlayer pattern 480 and the eighth sacrificial insulating interlayer pattern 500, the gate structure 230, the capacitor 470, and the first impurity region 520 and the second impurity region 490, and performing a planarization process on the bit line layer until the upper surface of the mold layer is exposed.

[0191] In example embodiments, each of the first bit lines 532 and the second bit lines 534 may extend primarily in the first direction D1 at each second portion of the mold layer, and a plurality of the first bit lines 532 may be spaced apart from each other in the third direction D3, and a plurality of the second bit lines 534 may be spaced apart from each other in the third direction D3.

[0192] refer to Figure 50 to Figure 52 , a portion of the mold layer disposed between the first bit line 532 and the second bit line 534, the first sacrificial insulating pattern 160 and the second sacrificial insulating pattern 170, and the first sacrificial insulating interlayer pattern 190, the seventh sacrificial insulating interlayer pattern 480 and the eighth sacrificial insulating interlayer pattern 500 can be removed by, for example, a wet etching process and / or a dry etching process, and a portion of the semiconductor layer 120 in the mold layer surrounded by the gate structure 230 can be retained as a channel 125.

[0193] Therefore, a capacitor 470 including a first capacitor electrode 380 and a second capacitor electrode 460 and a dielectric pattern 440, a second impurity region 490, a channel 125 and a first impurity region 520 sequentially arranged on each of the opposite sides of the capacitor 470 in the second direction D2, a gate structure 230 surrounding the channel 125 and mainly extending in the third direction D3, and a first bit line 532 and a second bit line 534 respectively contacting the sidewalls of the first impurity region and mainly extending in the first direction D1 can be formed on the substrate 100.

[0194] The gate structure 230 and the first impurity region 520 and the second impurity region 490 located at the respective opposite sides of the gate structure 230 in the second direction D2 may form a transistor, and each of the first impurity region 520 and the second impurity region 490 may serve as a source / drain of the transistor. Therefore, the first impurity region 520 and the second impurity region 490 may also be referred to as a first source / drain layer 520 and a second source / drain layer 490, respectively.

[0195] Reference again Figures 3 to 7 The contact plug 600 may contact the upper surface of the second extending portion of the word line to complete the fabrication of the semiconductor device.

[0196] Fig.53 is a perspective view illustrating a semiconductor device according to an example embodiment. In addition to some components, the semiconductor device can be Figures 3 to 7 The semiconductor devices of the present invention are substantially the same or similar, so to the extent that an element is not described in detail with respect to this figure, it can be understood that the element is at least similar to a corresponding element that has been described elsewhere in the present disclosure.

[0197] refer to Fig.53 , the first source / drain layer 520 may surround the entire sidewalls of the first and second bit lines 532 and 534 instead of contacting only the sidewall of each of the first and second bit lines 532 and 534 in the second direction D2.

[0198] Fig.54 is a perspective view illustrating a semiconductor device according to an example embodiment. In addition to some components, the semiconductor device can be Figures 3 to 7 or Fig.53 The semiconductor devices of the present invention are substantially the same or similar, so to the extent that an element is not described in detail with respect to this figure, it is understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure.

[0199] refer to Fig.54 , each of the first bit line 532 and the second bit line 534 may extend mainly in the third direction D3 substantially parallel to the upper surface of the substrate 100 , rather than mainly extending in the first direction D1 substantially perpendicular to the upper surface of the substrate 100 .

[0200] In example embodiments, the plurality of first bit lines 532 may be spaced apart from each other in the first direction D1, and the plurality of second bit lines 534 may be spaced apart from each other in the first direction D1. Additionally, the first bit lines 532 and the second bit lines 534 may be spaced apart from each other in the second direction D2.

[0201] The word line may include a first extending portion 222 extending mainly in the first direction D1 and a second extending portion 224 extending mainly in the second direction D2, and the first extending portion may contact the second extending portion 224 to be electrically connected to each other.

[0202] In example embodiments, a plurality of word lines may be spaced apart from each other in the third direction D3, and lengths of the first extending portions 222 of the respective word lines in the first direction D1 may be substantially the same as each other, and heights of upper surfaces of the second extending portions 224 of the respective word lines may be substantially the same as each other.

[0203] The contact plugs 600 may be disposed on upper surfaces of the second extending portions of the word lines, and may be arranged in a zigzag pattern in a plan view.

[0204] While the inventive concepts have been shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concepts.

Claims

1. A semiconductor device, comprising: a first bit line and a second bit line, the first bit line and the second bit line are both disposed on a substrate, each of the first bit line and the second bit line mainly extends in a first direction perpendicular to an upper surface of the substrate, and the first bit line and the second bit line are spaced apart from each other in a second direction parallel to the upper surface of the substrate; a word line, the word line comprising a first extension portion and a second extension portion, the first extension portion being disposed between the first bit line and the second bit line, each of the first extension portions extending mainly in a third direction parallel to the upper surface of the substrate and intersecting the second direction, and the second extension portion extending mainly along the second direction at the same height as the first extension portion and connected to the first extension portion; a first channel and a second channel, each of the first channel and the second channel extending through the first extension portion of the word line; as well as A capacitor comprising a first capacitor electrode, a dielectric pattern, and a second capacitor electrode, wherein the first capacitor electrode is electrically connected to the first channel, the dielectric pattern is arranged on a surface of the first capacitor electrode, and the second capacitor electrode is arranged on a surface of the dielectric pattern and electrically connected to the second channel.

2. The semiconductor device according to claim 1, further comprising: a first source / drain layer disposed between the first bit line and the first channel and contacting both the first bit line and the first channel; as well as A second source / drain layer is disposed between the first channel and the first capacitor electrode and contacts both the first channel and the first capacitor electrode.

3. The semiconductor device according to claim 1, further comprising: a first source / drain layer disposed between the second bit line and the second channel and contacting both the second bit line and the second channel; as well as A second source / drain layer is disposed between the second channel and the second capacitor electrode. 4 . The semiconductor device according to claim 3 , further comprising a connection pattern provided between the second capacitor electrode and the second source / drain layer.

5. The semiconductor device according to claim 4, wherein: The second capacitor electrode covers a surface of the connection pattern. 6 . The semiconductor device according to claim 3 , further comprising an insulating pattern disposed between the second capacitor electrode and the second source / drain layer.

7. The semiconductor device according to claim 6, wherein: The dielectric pattern covers a surface of the insulating pattern.

8. The semiconductor device according to claim 1, wherein The first channel surrounds a sidewall of the first bit line, and the second channel surrounds a sidewall of the second bit line.

9. The semiconductor device according to claim 1, wherein: A portion of each of the first extension portions of the word line surrounding a corresponding one of the first channel and the second channel defines a gate electrode, and The semiconductor device further includes a gate insulating pattern, which covers a lower surface, an upper surface, and opposite sidewalls in the third direction of each of the first channel and the second channel and contacts the gate electrode.

10. The semiconductor device according to claim 1, further comprising: a plurality of word lines, the plurality of word lines being spaced apart from each other in the first direction, the word line being one of the plurality of word lines; a plurality of first channels, the plurality of first channels being spaced apart from each other in the first direction, the first channel being one of the plurality of first channels; a plurality of second channels, the plurality of second channels being spaced apart from each other in the first direction, the second channel being one of the plurality of second channels; as well as A plurality of capacitors are provided, the plurality of capacitors being spaced apart from each other in the first direction, the capacitor being one of the plurality of capacitors.

11. The semiconductor device according to claim 10, wherein: The lengths of the first extending portions of the plurality of word lines in the third direction increase or decrease in a step-wise manner from a highest height to a lowest height.

12. The semiconductor device according to claim 10, wherein: The second extending portions of the plurality of word lines are respectively arranged in a step manner along the third direction.

13. The semiconductor device according to claim 1, further comprising: a plurality of first bit lines, the plurality of first bit lines being spaced apart from each other in the third direction, the first bit line being one of the plurality of first bit lines; a plurality of second bit lines, the plurality of second bit lines being spaced apart from each other in the third direction, the second bit line being one of the plurality of second bit lines; a plurality of first channels, the plurality of first channels being spaced apart from each other in the third direction, the first channel being one of the plurality of first channels; a plurality of second channels, the plurality of second channels being spaced apart from each other in the third direction, the second channel being one of the plurality of second channels; as well as a plurality of capacitors, the plurality of capacitors being spaced apart from each other in the third direction, the capacitor being one of the plurality of capacitors, and The plurality of first channels extend through a first one of the first extending portions of the word lines, and the plurality of second channels extend through a second one of the first extending portions of the word lines.

14. A semiconductor device, comprising: bit lines, the bit lines being disposed on a substrate, each of the bit lines extending mainly in a first direction, and the bit lines being spaced apart from each other in a second direction perpendicular to the first direction; A first transistor, a capacitor, and a second transistor, wherein the first transistor, the capacitor, and the second transistor are sequentially arranged between the bit lines along the second direction; as well as a word line, the word line comprising a first extension portion and a second extension portion, the first extension portions being electrically connected to the first transistor and the second transistor, respectively, each of the first extension portions extending mainly in a third direction perpendicular to the first direction and the second direction, and the second extension portion extending mainly in the second direction and connected to the first extension portion, Each of the first transistor and the second transistor includes a gate electrode, a channel, and a first source / drain layer and a second source / drain layer, the gate electrode is electrically connected to each of the first extension portions of the word line, the channel is electrically connected to the gate electrode, and the first source / drain layer and the second source / drain layer are respectively arranged on opposite sides of the channel in the second direction, wherein the capacitor comprises a first capacitor electrode, a dielectric pattern, and a second capacitor electrode stacked sequentially, and wherein the first source / drain layer of the first transistor and the first source / drain layer of the second transistor are electrically connected to the bit line, respectively, and the second source / drain layer of the first transistor and the second source / drain layer of the second transistor are electrically connected to the first capacitor electrode and the second capacitor electrode, respectively.

15. The semiconductor device according to claim 14, wherein: The first direction is perpendicular to an upper surface of the substrate, and the second direction and the third direction are parallel to the upper surface of the substrate.

16. The semiconductor device according to claim 15, further comprising: a plurality of word lines spaced apart from each other in the first direction, the word line being one of the plurality of word lines, The lengths of the first extension parts of the plurality of word lines in the third direction increase or decrease in a step-by-step manner from a highest height to a lowest height.

17. The semiconductor device according to claim 14, wherein: The third direction is perpendicular to an upper surface of the substrate, and the first direction and the second direction are parallel to the upper surface of the substrate.

18. The semiconductor device according to claim 17, further comprising: a plurality of word lines spaced apart from each other in the first direction, the word line being one of the plurality of word lines, The lengths of the first extending portions of the plurality of word lines in the third direction are substantially the same as each other.

19. A semiconductor device, comprising: a first bit line and a second bit line, the first bit line and the second bit line being located on a substrate, each of the first bit line and the second bit line extending mainly in a first direction perpendicular to an upper surface of the substrate, and the first bit line and the second bit line being spaced apart from each other in a second direction parallel to the upper surface of the substrate; a word line, the word line comprising a first extension portion and a second extension portion, the first extension portion being located between the first bit line and the second bit line, each of the first extension portions extending mainly in a third direction parallel to the upper surface of the substrate and intersecting the second direction, and the second extension portion extending mainly along the second direction at the same height as the first extension portion and connected to the first extension portion; a first channel and a second channel, each of the first channel and the second channel extending through the first extension portion of the word line; a first source / drain layer disposed between the first bit line and the first channel and contacting both the first bit line and the first channel; a second source / drain layer disposed between the second bit line and the second channel and contacting both the second bit line and the second channel; A capacitor, the capacitor comprising a first capacitor electrode, a dielectric pattern, and a second capacitor electrode, the dielectric pattern being disposed on a surface of the first capacitor electrode, and the second capacitor electrode being disposed on a surface of the dielectric pattern; a third source / drain layer disposed between the first channel and the first capacitor electrode and contacting both the first channel and the first capacitor electrode; a fourth source / drain layer disposed between the second channel and the second capacitor electrode; a connection pattern contacting both the second capacitor electrode and the fourth source / drain layer; as well as An insulating pattern is provided between the second capacitor electrode and the connecting pattern.

20. The semiconductor device according to claim 19, further comprising: a plurality of word lines, the plurality of word lines being spaced apart from each other in the first direction, the word line being one of the plurality of word lines; a plurality of first channels, the plurality of first channels being spaced apart from each other in the first direction, the first channel being one of the plurality of first channels; a plurality of second channels, the plurality of second channels being spaced apart from each other in the first direction, the second channel being one of the plurality of second channels; as well as a plurality of capacitors, the plurality of capacitors being spaced apart from each other in the first direction, the capacitor being one of the plurality of capacitors, wherein the lengths of the first extension portions of the plurality of word lines in the third direction increase or decrease in a stepwise manner from a highest height to a lowest height, and Wherein, the second extending portions of the plurality of word lines are respectively arranged in a stepped manner along the third direction.

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