Chip structure and memory

Abstract

The embodiments of the present disclosure disclose a chip structure and a memory. The chip structure includes: a stacked first chip and a second chip. The first chip includes: a plurality of storage array groups arranged along a first direction; each storage array group includes: N storage array sections arranged along a second direction. The second chip includes: a plurality of first sensing amplifiers and a plurality of second sensing amplifiers. In each storage array group, two adjacent storage array sections are electrically connected to a corresponding first sensing amplifier; two adjacent first sensing amplifiers are electrically connected to the same storage array section. The first storage array section in two adjacent storage array groups is electrically connected to a corresponding second sensing amplifier; the Nth storage array section in two adjacent storage array groups is electrically connected to another corresponding second sensing amplifier; the storage array sections electrically connected to different second sensing amplifiers are different from each other.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a chip structure and a memory. Background Art

[0002] With the development of semiconductor technology, the integration level of memory and the performance standards are becoming increasingly higher. Therefore, it is necessary to further optimize the structure of memory. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a chip structure and a memory that can more fully utilize the chip area and improve chip performance.

[0004] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] An embodiment of the present disclosure provides a chip structure, comprising: a stacked first chip and a second chip; the first chip comprising: a plurality of storage array groups arranged along a first direction; each storage array group comprising: N storage array sections arranged along a second direction; the first direction being perpendicular to the second direction; the second chip comprising: a plurality of first sense amplifiers and a plurality of second sense amplifiers; wherein, in each storage array group, two adjacent storage array sections are electrically connected to a corresponding first sense amplifier; two adjacent first sense amplifiers are electrically connected to the same storage array section; the first storage array section in two adjacent storage array groups is electrically connected to a corresponding second sense amplifier; the Nth storage array section in two adjacent storage array groups is electrically connected to a corresponding second sense amplifier; and the storage array sections electrically connected to different second sense amplifiers are different from each other.

[0006] In some embodiments, in every two of the memory array groups, the first memory array section in one of the memory array groups and the Nth memory array section in the other memory array group share the same set of row addresses.

[0007] In some embodiments, in every two storage array groups, the i-th storage array section in one storage array group and the i-th storage array section in the other storage array group share a set of row addresses; i is greater than or equal to 2 and less than or equal to N-1.

[0008] In some embodiments, in the vertical direction, the orthographic projections of the two second sense amplifiers electrically connected to the same pair of the storage array groups are respectively located on opposite sides of the orthographic projections of the same pair of the storage array groups along the second direction; and the first direction and the second direction are both perpendicular to the vertical direction.

[0009] In some embodiments, in the vertical direction, an orthographic projection of each of the second sense amplifiers at least partially overlaps with orthographic projections of two correspondingly connected storage array sections.

[0010] In some embodiments, in the vertical direction, the orthographic projections of the two second sense amplifiers electrically connected to the same pair of the memory array groups and the orthographic projections of the same pair of the memory array groups have the same symmetry axis; the symmetry axis extends along the second direction.

[0011] In some embodiments, each of the memory array groups further comprises: at least one redundant array section; the redundant array section is located at least on one of two opposite sides of the memory array group along the second direction; in the vertical direction, the orthographic projection of the second sense amplifier at least partially overlaps with the redundant array section located on the same side, and in the second direction, the edge of the orthographic projection of the second sense amplifier does not exceed the edge of the orthographic projection of the redundant array section.

[0012] In some embodiments, in the vertical direction, the orthographic projection of the first sense amplifier is located between the orthographic projections of the two correspondingly connected storage array portions, or the orthographic projection of the first sense amplifier is located in the orthographic projection of one of the two correspondingly connected storage array portions.

[0013] In some embodiments, in the vertical direction, an orthographic projection of each of the first sense amplifiers at least partially overlaps with orthographic projections of two correspondingly connected storage array sections.

[0014] In some embodiments, each of the first sense amplifiers is electrically connected to the corresponding two storage array sections through a first bit line of equal length; each of the second sense amplifiers is electrically connected to the corresponding two storage array sections through a second bit line of equal length.

[0015] An embodiment of the present disclosure further provides a memory, which includes the chip structure as described in the above solution.

[0016] It can be seen that the embodiments of the present disclosure provide a chip structure and a memory. The chip structure includes: a stacked first chip and a second chip. The first chip includes: a plurality of storage array groups arranged along a first direction; each storage array group includes: N storage array sections arranged along a second direction; the first direction is perpendicular to the second direction. The second chip includes: a plurality of first sensing amplifiers and a plurality of second sensing amplifiers. In each storage array group, two adjacent storage array sections are electrically connected to a corresponding first sensing amplifier; two adjacent first sensing amplifiers are electrically connected to the same storage array section. The first storage array section in two adjacent storage array groups is electrically connected to a corresponding second sensing amplifier; the Nth storage array section in two adjacent storage array groups is electrically connected to another corresponding second sensing amplifier; the storage array sections electrically connected to different second sensing amplifiers are different from each other.

[0017] It is understood that the first and Nth memory array sections located at the edge of the memory array group are electrically connected to corresponding second sense amplifiers. Thus, in the memory array sections located at the edge (i.e., the first and Nth memory array sections), a portion of the memory cells are electrically connected to a corresponding first sense amplifier, and another portion of the memory cells are electrically connected to a corresponding second sense amplifier. This avoids the presence of unconnected memory cells in the memory array sections located at the edge, thus avoiding waste. This allows for more efficient utilization of chip area and improves chip performance. Furthermore, because each first sense amplifier is electrically connected to two adjacent memory array sections, and each second sense amplifier is electrically connected to two memory array sections located at the edge, the bit line length between the sense amplifier and the corresponding memory array section is shorter, saving data transmission time in the bit line and reducing the chip area occupied by the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 1 ;

[0019] Figure 2 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 2 ;

[0020] Figure 3 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 3 ;

[0021] Figure 4 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 4 ;

[0022] Figure 5 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 5 ;

[0023] Figure 6 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 6 ;

[0024] Figure 7 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 7 ;

[0025] Figure 8 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 8 ;

[0026] Figure 9 A schematic diagram of the chip structure provided in the embodiment of the present disclosure Figure 9 ;

[0027] Figure 10 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0029] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0031] Herein, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or intervening layers / element may be present therebetween. Also, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0033] In related technologies, an Open BL (open bit line) architecture is used. To ensure symmetry between the two bit lines connected to the sense amplifiers, a complete memory array chip (MAT) needs to be placed at each edge of the array. However, since there are no sense amplifiers outside the edge memory array chips, some memory cells in the edge memory array chips are left unused, resulting in a waste of chip area and hindering the improvement of chip integration.

[0034] Figure 1 and Figure 2 This is an optional structural diagram of the chip structure provided in the embodiment of the present disclosure.

[0035] like Figure 1 As shown, the chip structure includes: a stacked first chip D1 and a second chip D2, wherein the width of the first chip D1 is consistent with the width of the second chip D2.

[0036] In the embodiments of the present disclosure, reference Figure 1 , the first chip D1 and the second chip D2 are electrically connected by hybrid bonding (HybridBonding), which can achieve higher integration and performance while reducing chip size and power consumption. The CMOS wafer (CMOS Wafer) can be bonded to the memory array wafer (Array Wafer) through a wafer-on-wafer hybrid bonding manufacturing process; then, the CMOS wafer is cut into the second chip D2, and the memory array wafer is cut into the first chip D1. Alternatively, the CMOS wafer can be cut into the second chip D2 first; then, the second chip D2 can be bonded to the memory array wafer through a die-on-wafer hybrid bonding manufacturing process; and then, the memory array wafer can be cut into the first chip D1.

[0037] Combine Figure 1 and Figure 2 The first chip D1 includes a plurality of memory array groups 101 arranged along a first direction X. Each memory array group 101 includes N memory array sections 102 arranged along a second direction Y. The first direction X is perpendicular to the second direction Y. The second chip D2 includes a plurality of first sense amplifiers 201 and a plurality of second sense amplifiers 202.

[0038] It should be noted that a bank can be divided into two half-banks along the wordline extension direction. Each memory array group 101 can be composed of one or multiple half-banks arranged along the second direction Y. Each half-bank includes multiple memory array units 102. In other words, the storage capacity of each memory array group 101 can be divided according to needs.

[0039] In the present disclosure, continue to refer to Figure 2 On the one hand, in each memory array group 101, two adjacent memory array sections 102 are electrically connected to a corresponding first sense amplifier 201; and, two adjacent first sense amplifiers 201 are electrically connected to the same memory array section 102. On the other hand, the first memory array section 102 in two adjacent memory array groups 101 is electrically connected to a corresponding second sense amplifier 202; and, the Nth memory array section 102 in two adjacent memory array groups 101 is electrically connected to another corresponding second sense amplifier 202; and the memory array sections 102 electrically connected to different second sense amplifiers 202 are different from each other. The first and Nth memory array sections 102 in each memory array group 101 are respectively located at the outermost edges of the memory array group 101 along the second direction Y.

[0040] In the present disclosure, continue to refer to Figure 2 The sense amplifier (the first sense amplifier 201 or the second sense amplifier 202) is electrically connected to the memory cell in the memory array unit 102, so that the sense amplifier can amplify the data in the memory cell during the process of reading or writing the data in the memory cell.

[0041] Furthermore, each sense amplifier (first sense amplifier 201 or second sense amplifier 202) can be electrically connected to an equal number of memory cells in two memory array sections 102. That is, for the memory array sections 102 located at non-edge locations in each memory array group 101 (i.e., the 2nd to N-1th memory array sections 102), half of the memory cells in each memory array section 102 are electrically connected to a corresponding first sense amplifier 201, and the other half of the memory cells in each memory array section 102 are electrically connected to a corresponding other first sense amplifier 201. On the other hand, for the memory array sections 102 located at edge locations in each memory array group 101 (i.e., the 1st and Nth memory array sections 102), half of the memory cells in each memory array section 102 are electrically connected to a corresponding first sense amplifier 201, and the other half of the memory cells in each memory array section 102 are electrically connected to a corresponding second sense amplifier 202.

[0042] It is understandable that the first and Nth memory array sections 102 located at the outermost edges of the memory array group 101 are electrically connected to corresponding second sense amplifiers 202. Thus, in the memory array sections located at the edge (i.e., the first and Nth memory array sections 102), a portion of the memory cells are electrically connected to a corresponding first sense amplifier 201, and another portion of the memory cells are electrically connected to a corresponding second sense amplifier 202. This avoids unused memory cells in the memory array sections located at the edge, thus preventing waste. This allows for more efficient use of chip area and improved chip performance.

[0043] At the same time, since each first sense amplifier 201 is electrically connected to two adjacent memory array sections 102, and each second sense amplifier 202 is electrically connected to two memory array sections 102 at the edge, the bit line length between the sense amplifier and the corresponding memory array section is shortened, which saves data transmission time in the bit line and reduces the chip area occupied by the bit line.

[0044] In some embodiments of the present disclosure, reference Figure 3 and Figure 4 In every two storage array groups U and V, the first storage array unit in one storage array group and the Nth storage array unit in the other storage array group share the same set of row addresses.

[0045] refer to Figure 3 The row address RA_1 is decoded into a group of row addresses through the row address decoder XDEC_N. This group of row addresses can simultaneously select the Nth storage array unit in the storage array group U and the 1st storage array unit in the storage array group V, so that the corresponding word lines (Word Line, WL) in these two storage array units can be opened at the same time.

[0046] refer to Figure 4 The row address RA_2 is decoded into another set of row addresses through the row address decoder XDEC_1. This set of row addresses can simultaneously select the first storage array part in the storage array group U and the Nth storage array part in the storage array group V, so that the corresponding word lines in these two storage array parts can be opened at the same time.

[0047] It is understandable that, in the two memory array groups U and V, the first memory array section in one memory array group and the Nth memory array section in the other memory array group share the same set of row addresses. This allows word lines in both memory array groups U and V to be activated at the same time, meaning that both memory array groups can read and write data based on the same activation command and the same read and write command, improving read and write efficiency.

[0048] It can be understood that each row address corresponds to a word line. Since the two storage array groups U and V share the same row address, a word line in each of the two storage array groups U and V will be activated when an activation command containing a row address is received. At the same time, since the activated word lines are located in different storage array portions in the two storage array groups U and V, the correspondingly connected second sensing amplifier 202 can operate normally, so that when a read or write command is received, the charge discharged from the storage cell to the bit line is sensed and amplified based on the column address in the read or write command.

[0049] refer to Figure 3 and Figure 4 , the memory array sections at the edge of the two memory array groups U and V are connected to the second sense amplifier 202. Specifically, the first memory array section in the two memory array groups U and V is connected to the same second sense amplifier 202; correspondingly, the Nth memory array section in the two memory array groups U and V is connected to the same second sense amplifier 202.

[0050] It can be understood that, in the two memory array groups U and V, the first memory array section in one memory array group and the Nth memory array section in the other memory array group share the same set of row addresses. Thus, the word lines of the two memory array sections connected to the same second sense amplifier 202 are not simultaneously turned on. That is, before the second sense amplifier 202 begins operating, only the bit line potential of one of the two memory array sections connected to the second sense amplifier changes, while the bit line potential of the other remains unchanged, thereby serving as a reference bit line for sensing and amplification. This facilitates accurate amplification of data in memory array sections located at the edge, avoiding errors during data reading and writing.

[0051] In some embodiments of the present disclosure, reference Figure 5 In every two storage array groups U and V, the i-th storage array section in one storage array group and the i-th storage array section in the other storage array group share a set of row addresses; where i is greater than or equal to 2 and less than or equal to N-1.

[0052] Continue to refer Figure 5 The address decoder XDEC_i decodes a set of row addresses, which can simultaneously select the i-th storage array part in the storage array group U and the i-th storage array part in the storage array group V, so that the word lines in these two storage array parts can be opened at the same time.

[0053] It is understandable that for the storage array sections located at non-edge locations in the two storage array groups U and V (i.e., the 2nd to N-1th storage array sections), the relatively close storage array sections (i.e., the i-th storage array section located in the same row in the two storage array groups U and V) are set to share the same set of row addresses. This reduces the wiring length, saves data transmission time in the wiring, and reduces the area occupied by the wiring on the chip.

[0054] Furthermore, because each first sense amplifier is connected to two adjacent memory array sections within the same memory array group, the word lines of the two memory array sections connected to the same first sense amplifier are not simultaneously enabled. This allows for accurate amplification of data in non-edge memory array sections, preventing errors during data reading and writing.

[0055] In some embodiments of the present disclosure, reference Figure 2 or Figure 6 In the vertical direction Z, the orthographic projections of the two second sense amplifiers 202 electrically connected to the same pair of memory array groups 101 are located on opposite sides of the orthographic projections of the same pair of memory array groups 101 along the second direction Y. Both the first direction X and the second direction Y are perpendicular to the vertical direction Z.

[0056] It is understood that the second sense amplifiers 202 are positioned so that the orthographic projections of the two second sense amplifiers 202 electrically connected to the same pair of memory array groups 101 are located on opposite sides of the orthographic projections of the same pair of memory array groups 101 along the second direction Y. In this way, the second sense amplifiers 202 can be connected to the memory array sections 102 at the edge of the memory array group 101, reducing the wiring length between the second sense amplifiers 202 and the edge memory array sections 102, saving data transmission time in the wiring, and reducing the chip area occupied by the wiring.

[0057] In some embodiments of the present disclosure, reference Figure 6 In the vertical direction Z, the orthographic projection of each second sense amplifier 202 at least partially overlaps with the orthographic projections of the two correspondingly connected storage array portions 102 .

[0058] It is understood that the positions of the second sense amplifiers 202 are set so that the orthographic projection of each second sense amplifier 202 at least partially overlaps with the orthographic projections of the two corresponding memory array sections 102. In this way, the sense amplifiers on the second chip can be arranged more compactly, thereby improving the chip's integration.

[0059] In some embodiments of the present disclosure, reference Figure 6In the vertical direction Z, the orthographic projections of the two second sense amplifiers 202 electrically connected to the same pair of storage array groups 101 and the orthographic projections of the same pair of storage array groups 101 have the same symmetry axis; the symmetry axis extends along the second direction Y.

[0060] In some embodiments of the present disclosure, reference Figure 7 Each memory array group 101 further includes: at least one redundant array section 103. The redundant array section 103 is located on at least one of two opposite sides of the memory array group 101 along the second direction Y. In the vertical direction Z, the orthographic projection of the second sense amplifier 202 at least partially overlaps with the redundant array section 103 located on the same side, and in the second direction Z, the edge of the orthographic projection of the second sense amplifier 202 does not exceed the edge of the orthographic projection of the redundant array section 103.

[0061] It should be noted that the redundant array section 103 is not electrically connected to the second sense amplifier 202. The redundant array section 103 may be a redundant design in a chip design. The sum of the number of memory array sections 102 and the number of redundant array sections 103 in the disclosed embodiment can be compared to the number of memory array sections in a conventional chip design.

[0062] It is understood that the second sense amplifier 202 is positioned so that its orthographic projection at least partially overlaps with the redundant array portion 103 on the same side. This allows the sense amplifiers on the second chip to be arranged more compactly, thereby improving chip integration.

[0063] In some embodiments of the present disclosure, reference Figure 8 , in the vertical direction Z, the orthographic projection of the first sense amplifier 201 is located between the orthographic projections of the two correspondingly connected storage array sections 102. Or, referring to Figure 9 In the vertical direction Z, the orthographic projection of the first sense amplifier 201 is located in the orthographic projection of one of the two correspondingly connected storage array portions 102 .

[0064] In some embodiments of the present disclosure, reference Figure 8 or Figure 9 In the vertical direction Z, the orthographic projection of each first sense amplifier 201 at least partially overlaps with the orthographic projections of the two correspondingly connected storage array portions 102 .

[0065] It is understood that the position of the first sense amplifier 201 is set so that the orthographic projection of the first sense amplifier 201 is located between the orthographic projections of the two correspondingly connected memory array sections 102, or the orthographic projection of the first sense amplifier 201 is located within the orthographic projection of one of the two correspondingly connected memory array sections 102. In this way, the sense amplifiers on the second chip can be arranged more compactly, thereby improving the chip's integration density.

[0066] In some embodiments of the present disclosure, continue to refer to Figure 2 Each first sense amplifier 201 is electrically connected to two corresponding memory array sections 102 via first bit lines (not shown) of equal length. Each second sense amplifier 202 is electrically connected to two corresponding memory array sections 102 via second bit lines (not shown) of equal length. The lengths of each first bit line and each second bit line can be equal. This ensures that the bit lines connected to both ends of each sense amplifier have equal lengths, and the coupling capacitances on the bit lines are the same, thereby ensuring data reading and writing.

[0067] In the disclosed embodiment, for each sense amplifier, the memory cell electrically connected to its first end stores first data, and the memory cell electrically connected to its second end stores second data; the first data and the second data may be the same or different. When the sense amplifier is amplifying, only the memory cell electrically connected to one end is turned on, and the memory cell electrically connected to the other end is actually in a closed state; however, the bit line electrically connected to the other end is charged to a preset potential, where the preset potential can be expressed as logic 0.5, that is, between a high level (logic 1) and a low level (logic 0). In this way, one end of the sense amplifier receives a data signal (including a data signal to be written or a data signal to be read), and the other end is at a preset potential, so that sense amplification can be performed to complete the reading or writing of data.

[0068] Figure 10 is a schematic diagram of the structure of a memory provided by an embodiment of the present disclosure, such as Figure 10 As shown, the memory 90 includes a chip structure 80. The chip structure 80 includes the structure of the aforementioned embodiment.

[0069] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0070] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments when there is no conflict. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined to obtain new product embodiments when there is no conflict. The features disclosed in the several method or device embodiments provided in the present disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments when there is no conflict.

[0071] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A chip structure, characterized in that: The chip structure includes: a first chip and a second chip that are stacked; The first chip includes: a plurality of memory array groups arranged along a first direction; each of the memory array groups includes: N memory array sections arranged along a second direction; the first direction is perpendicular to the second direction; The second chip includes: a plurality of first sense amplifiers and a plurality of second sense amplifiers; Wherein, in each of the storage array groups, two adjacent storage array sections are electrically connected to a corresponding first sensing amplifier; and two adjacent first sensing amplifiers are electrically connected to the same storage array section; The first storage array section in two adjacent storage array groups is electrically connected to a corresponding second sensing amplifier; the Nth storage array section in two adjacent storage array groups is electrically connected to another corresponding second sensing amplifier; the storage array sections electrically connected to different second sensing amplifiers are different from each other.

2. The chip structure according to claim 1, characterized in that: In every two memory array groups, the first memory array unit in one memory array group and the Nth memory array unit in the other memory array group share the same set of row addresses.

3. The chip structure according to claim 2, characterized in that: In every two storage array groups, the i-th storage array section in one storage array group and the i-th storage array section in the other storage array group share a set of row addresses; i is greater than or equal to 2 and less than or equal to N-1.

4. The chip structure according to claim 1, wherein: In the vertical direction, the orthographic projections of the two second sense amplifiers electrically connected to the same pair of the storage array groups are respectively located on opposite sides of the orthographic projections of the same pair of the storage array groups along the second direction; the first direction and the second direction are both perpendicular to the vertical direction.

5. The chip structure according to claim 4, characterized in that: In the vertical direction, the orthographic projection of each of the second sense amplifiers at least partially overlaps with the orthographic projections of the two correspondingly connected storage array sections.

6. The chip structure according to claim 4 or 5, characterized in that: In the vertical direction, the orthographic projections of the two second sense amplifiers electrically connected to the same pair of the storage array groups and the orthographic projections of the same pair of the storage array groups have the same symmetry axis; the symmetry axis extends along the second direction.

7. The chip structure according to claim 4, characterized in that: Each of the storage array groups further comprises: at least one redundant array unit; The redundant array portion is located at least on one of two opposite sides of the storage array group along the second direction; In the vertical direction, the orthographic projection of the second sense amplifier at least partially overlaps with the redundant array portion located on the same side, and in the second direction, the edge of the orthographic projection of the second sense amplifier does not exceed the edge of the orthographic projection of the redundant array portion.

8. The chip structure according to claim 1, wherein: In the vertical direction, the orthographic projection of the first sense amplifier is located between the orthographic projections of the two correspondingly connected storage array portions, or the orthographic projection of the first sense amplifier is located in the orthographic projection of one of the two correspondingly connected storage array portions.

9. The chip structure according to claim 8, characterized in that: In the vertical direction, the orthographic projection of each of the first sense amplifiers at least partially overlaps with the orthographic projections of the two correspondingly connected storage array sections.

10. The chip structure according to claim 1, wherein: Each of the first sense amplifiers is electrically connected to two corresponding storage array sections via a first bit line of equal length; Each of the second sense amplifiers is electrically connected to two corresponding memory array sections through second bit lines of equal length.

11. A memory, characterized in that: The memory comprises the chip structure according to any one of claims 1 to 10.

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