Display panel and display device

Abstract

A display panel and a display device are provided. The display panel includes: a substrate substrate; a plurality of light emitting elements located in a first display area and a second display area, including a plurality of groups of light emitting elements, the light emitting elements in each group of the plurality of groups of light emitting elements are arranged along a first direction, the plurality of groups of light emitting elements are arranged along a second direction, at least one group of the plurality of groups of light emitting elements includes a plurality of first area light emitting elements and a plurality of second area light emitting elements; a plurality of pixel circuits, including a plurality of groups of pixel circuits, the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along the first direction, the plurality of groups of pixel circuits are arranged along the second direction, at least one group of the plurality of groups of pixel circuits includes a plurality of first type pixel circuits and a plurality of second type pixel circuits, in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first pixel circuits connected with the plurality of first light emitting elements is closer to the second display area than each of the plurality of second pixel circuits connected with the plurality of second light emitting elements.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application is a divisional application of the patent application with the application number 202180000474.4, which was filed on March 12, 2021, the patent application with the application number 202180000474.4 is the entry into China national phase of the PCT patent application No. PCT / CN2021 / 080494, which was filed on March 12, 2021, the PCT patent application No. PCT / CN2021 / 080494 claims priority to the PCT patent application No. PCT / CN2020 / 119673, which was filed on September 30, 2020, the content of the above-mentioned PCT patent application is hereby incorporated by reference in its entirety as part of this application. TECHNICAL FIELD

[0003] At least one embodiment of the present disclosure relates to a display panel and a display device. BACKGROUND

[0004] With the continuous development of display technology, the active-matrix organic light-emitting diode (AMOLED) display technology has been more and more applied in display devices such as mobile phones, tablet computers, digital cameras and the like due to its advantages of self-emission, wide viewing angle, high contrast, low power consumption, high response speed and the like.

[0005] The under-screen camera technology is a brand-new technology proposed to improve the screen ratio of the display device. SUMMARY

[0006] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0007] At least one embodiment of the present disclosure provides a display panel, comprising: a substrate substrate having a first display area and a second display area, the first display area being located at least one side of the second display area; a plurality of light emitting elements located in the first display area and the second display area, the plurality of light emitting elements comprising a plurality of groups of light emitting elements, the light emitting elements in each group of the plurality of groups of light emitting elements being arranged along a first direction, the plurality of groups of light emitting elements being arranged along a second direction, at least one group of the plurality of groups of light emitting elements comprising a plurality of first area light emitting elements and a plurality of second area light emitting elements, the plurality of first area light emitting elements being located in the first display area, the plurality of second area light emitting elements being located in the second display area; a plurality of pixel circuits located in the first display area, the plurality of pixel circuits comprising a plurality of groups of pixel circuits, the pixel circuits in each group of the plurality of groups of pixel circuits being arranged along the first direction, the plurality of groups of pixel circuits being arranged along the second direction, at least one group of the plurality of groups of pixel circuits comprising a plurality of first type pixel circuits and a plurality of second type pixel circuits, the plurality of second type pixel circuits being distributed between the plurality of first type pixel circuits; at least one first type pixel circuit of the plurality of first type pixel circuits is connected with at least one first area light emitting element of the plurality of first area light emitting elements, and the orthographic projection of the at least one first type pixel circuit on the substrate substrate at least partially overlaps with the orthographic projection of the at least one first area light emitting element on the substrate substrate; at least one second type pixel circuit of the plurality of second type pixel circuits is connected with at least one second area light emitting element of the plurality of second area light emitting elements through a conductive wire; the plurality of second area light emitting elements comprises a plurality of first light emitting elements and a plurality of second light emitting elements, the first light emitting elements being configured to emit light of a first color, the second light emitting elements being configured to emit light of a second color, the plurality of second type pixel circuits comprising a plurality of first pixel circuits and a plurality of second pixel circuits, the conductive wire comprising a plurality of first conductive wires and a plurality of second conductive wires, the plurality of first light emitting elements being connected with the plurality of first pixel circuits through the plurality of first conductive wires, the plurality of second light emitting elements being connected with the plurality of second pixel circuits through the plurality of second conductive wires, in the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected with the plurality of first light emitting elements are closer to the second display area than each of the plurality of second pixel circuits connected with the plurality of second light emitting elements.

[0008] For example, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other second type pixel circuits are arranged between two first pixel circuits connected with two adjacent first conductive wires.

[0009] For example, one end of the conductive line is connected to the second area light emitting element, and the other end of the conductive line is connected to the second type of pixel circuit through a connection element.

[0010] For example, in the at least one group of light emitting elements and the at least one group of pixel circuits, at least one of the plurality of first type of pixel circuits is arranged between two adjacent second type of pixel circuits.

[0011] For example, in the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first conductive lines are arranged at intervals in the plurality of first type of pixel circuits, and the plurality of second pixel circuits connected to the plurality of second conductive lines are arranged at intervals in the plurality of first type of pixel circuits.

[0012] For example, a portion of one of the plurality of first conductive lines extending in the first direction on the substrate substrate and a portion of another first conductive line different from the first conductive line extending in the first direction on the substrate substrate at least partially overlap in a projection, or a portion of one of the plurality of first conductive lines extending in the first direction on the substrate substrate and a portion of one of the plurality of fourth conductive lines different from the first conductive line extending in the first direction on the substrate substrate at least partially overlap in a projection.

[0013] For example, the plurality of second area light emitting elements further include a plurality of third light emitting elements configured to emit light of a third color, the plurality of second type of pixel circuits further include a plurality of third pixel circuits, the conductive line further includes a plurality of third conductive lines, the plurality of third light emitting elements are connected to the plurality of third pixel circuits through the plurality of third conductive lines, and in the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first conductive lines are closer to the second display area than each of the plurality of third pixel circuits connected to the plurality of third conductive lines.

[0014] For example, in the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of second pixel circuits connected to the plurality of second conductive lines and the plurality of third pixel circuits connected to the plurality of third conductive lines are arranged alternately.

[0015] For example, the plurality of second area light emitting elements further comprises a plurality of fourth light emitting elements configured to emit light of a fourth color, the plurality of second type of pixel circuits further comprises a plurality of fourth pixel circuits, the plurality of conductive lines further comprises a plurality of fourth conductive lines, the plurality of fourth light emitting elements are connected with the plurality of fourth pixel circuits through the plurality of fourth conductive lines, and in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of fourth pixel circuits connected with the plurality of fourth conductive lines is closer to the second display area than each of the plurality of second pixel circuits connected with the plurality of second conductive lines.

[0016] For example, the plurality of fourth pixel circuits connected with the plurality of fourth conductive lines and the plurality of first pixel circuits connected with the plurality of first conductive lines are arranged alternately.

[0017] For example, a portion of one of the plurality of second conductive lines extending along the first direction at least partially overlaps a portion of one of the plurality of third conductive lines different from the second conductive line and extending along the first direction in a projection of the portion of the second conductive line on the substrate.

[0018] For example, at least one of the groups of light emitting elements comprises, in sequence along the first direction, a first sub-group of light emitting elements, a second sub-group of light emitting elements, and a third sub-group of light emitting elements, at least one of the groups of pixel circuits comprises, in sequence along the first direction, a first sub-group of pixel circuits to a seventh sub-group of pixel circuits, the seventh sub-group of pixel circuits is closer to the second display area than the first sub-group of pixel circuits, the conductive lines connected to the first sub-group of light emitting elements are located at the third pattern layer, the conductive lines connected to the second sub-group of light emitting elements are located at the second pattern layer, the conductive lines connected to the third sub-group of light emitting elements comprise the conductive lines located at the first pattern layer and also comprise the segmented conductive lines, the segmented conductive lines comprise a first conductive part located at the first pattern layer and a second conductive part located at the second pattern layer, the second and third light emitting elements in the first sub-group of light emitting elements are connected to the second sub-group of pixel circuits, the second and third light emitting elements in the second sub-group of light emitting elements are connected to the first sub-group of pixel circuits, the second and third light emitting elements in the third sub-group of light emitting elements that are close to the second sub-group of light emitting elements are connected to the fourth sub-group of pixel circuits, the second and third light emitting elements in the third sub-group of light emitting elements that are away from the second sub-group of light emitting elements are connected to the fifth sub-group of pixel circuits, the first and fourth light emitting elements in the first sub-group of light emitting elements are connected to the seventh sub-group of pixel circuits, the first and fourth light emitting elements in the second sub-group of light emitting elements are connected to the sixth sub-group of pixel circuits, and the first and fourth light emitting elements in the third sub-group of light emitting elements are connected to the third sub-group of pixel circuits.

[0019] For example, the second conductive line and the third conductive line located at different layers have at least partial overlap in the projection of the part of the second conductive line extending along the first direction on the substrate and the part of the third conductive line extending along the first direction on the substrate.

[0020] For example, the part of the conductive line connected to the second sub-group of light emitting elements extending along the first direction does not overlap with the part of other conductive lines extending along the first direction.

[0021] For example, the part of the conductive line connected to the second sub-group of pixel circuits extending along the first direction and the part of the conductive line connected to the fourth sub-group of pixel circuits extending along the first direction have overlap, the part of the conductive line connected to the first sub-group of pixel circuits extending along the first direction does not have overlap with the part of the conductive line connected to the second sub-group of pixel circuits extending along the first direction, and does not have overlap with the part of the conductive line connected to the fourth sub-group of pixel circuits extending along the first direction.

[0022] For example, the fourth light emitting element and the first light emitting element are configured to emit light of the same color.

[0023] For example, the fourth light emitting element and the first light emitting element are configured to emit green light, one of the second light emitting element and the third light emitting element is configured to emit red light, and the other of the second light emitting element and the third light emitting element is configured to emit blue light.

[0024] For example, at least one of one of the plurality of first conductive lines, one of the plurality of second conductive lines, one of the plurality of third conductive lines, and one of the plurality of fourth conductive lines is formed integrally by one conductive line, or is formed by conductive portions located at different layers.

[0025] For example, at least one of the first conductive line, the second conductive line, the third conductive line, and the fourth conductive line is made of a transparent conductive material.

[0026] For example, the second display area is an axisymmetric shape having a first axis of symmetry extending in the first direction and a second axis of symmetry extending in the second direction, and the conductive lines are provided in a plurality of lines, the plurality of conductive lines being axisymmetric with respect to the first axis of symmetry and axisymmetric with respect to the second axis of symmetry.

[0027] For example, the plurality of second area light emitting elements are axisymmetric with respect to the first axis of symmetry and axisymmetric with respect to the second axis of symmetry.

[0028] For example, the first display area includes an auxiliary area, and the plurality of pixel circuits of the second type are located in the auxiliary area, and an area of the auxiliary area is smaller than an area of a region of the first display area excluding the auxiliary area.

[0029] For example, a size of the pixel circuit of the first type in the first direction is smaller than a size of the first area light emitting element in the first direction.

[0030] For example, in the auxiliary area, a normal projection of the conductive line on the substrate and a normal projection of the pixel circuit of the first type on the substrate partially overlap.

[0031] For example, a light emitting area of the first area light emitting element is larger than a light emitting area of the second area light emitting element, the second display area includes a light transmissive area, a resolution of the first display area is the same as a resolution of the second display area, and a density of the first area light emitting element is the same as a density of the second area light emitting element.

[0032] For example, the pixel circuit comprises a driving transistor and a reset transistor, the display panel further comprises a reset control signal line, a gate of the reset transistor is connected with the reset control signal line, a first electrode of the reset transistor is connected with an initialization signal line, a second electrode of the reset transistor is connected with a first electrode of the light emitting element, the initialization signal line is configured to provide a constant voltage, and the constant voltage is greater than or equal to -2V.

[0033] At least one embodiment of the present disclosure further provides a display device comprising any of the display panels.

[0034] For example, the display device further comprises a photosensitive sensor, and the photosensitive sensor is located on one side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, and not limit the present disclosure.

[0036] Figure 1A is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0037] Figure 1B is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0038] Figure 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure.

[0039] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0040] Figure 4 is a schematic diagram of a first display area and a second display area in a display panel provided by an embodiment of the present disclosure.

[0041] Figures 5A to 5C is a partial plan view of a display panel provided by an embodiment of the present disclosure.

[0042] Figures 5D to 5F is a structural schematic diagram of a display panel provided by some embodiments of the present disclosure.

[0043] Figure 6A is a schematic diagram of a row of light emitting elements located in a second display area and a second type of pixel circuit connected therewith in a display panel.

[0044] Figure 6B is a schematic diagram of a capacitance of a conductive line in a display panel.

[0045] Figure 6C A display panel is shown in the display defect diagram.

[0046] Figures 6D to 6F A display panel is shown in the display defect diagram.

[0047] Figure 7A A display panel is shown in the display defect diagram.

[0048] Figure 7B A display panel is shown in the display defect diagram.

[0049] Figure 7C A display panel is shown in the display defect diagram.

[0050] Figure 8A A display panel is shown in the display defect diagram.

[0051] Figure 8B A display panel is shown in the display defect diagram. Figure 8A A display panel is shown in the display defect diagram.

[0052] Figure 8C A display panel is shown in the display defect diagram. Figure 8A A display panel is shown in the display defect diagram.

[0053] Figure 8D A display panel is shown in the display defect diagram. Figure 8A A display panel is shown in the display defect diagram.

[0054] Figure 8E A display panel is shown in the display defect diagram.

[0055] Figure 9A A display panel is shown in the display defect diagram.

[0056] Figure 9B A display panel is shown in the display defect diagram.

[0057] Figures 10A to 10E A display panel is shown in the display defect diagram.

[0058] Figure 10F A display panel is shown in the display defect diagram.

[0059] Figure 10GThis is a schematic diagram of conductive lines connected to a column of second-area light-emitting elements in a display panel, provided as an embodiment of the present disclosure.

[0060] Figure 10H This is a schematic diagram of connecting elements in a column of second-type pixel circuits in a display panel, provided for embodiments of the present disclosure.

[0061] Figure 11 This is a schematic diagram of a display panel provided for one embodiment of the present disclosure.

[0062] Figure 12A This is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure.

[0063] Figure 12B This is a layout diagram of pixel circuits in a display panel according to an embodiment of the present disclosure.

[0064] Figure 12C for Figure 12B A sectional view along line AB.

[0065] Figure 12D This is a layout diagram of pixel circuits in a display panel provided in another embodiment of this disclosure.

[0066] Figure 12E This is a layout diagram of pixel circuits in a display panel provided in another embodiment of this disclosure.

[0067] Figure 13A and Figure 13B This is a schematic diagram of a display device provided according to an embodiment of the present disclosure.

[0068] Figure 14 for Figure 12A The timing diagram of the pixel circuit shown is shown.

[0069] Figure 15 This is a schematic diagram of the structure of a display panel provided in one embodiment of the present disclosure. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0071] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning commonly understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Also, the terms "include", "comprise", and the like are intended to mean that the elements or components appearing before the terms encompass the elements or components listed after the terms and equivalents thereof, without excluding other elements or components. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections or couplings, but can include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0072] With the development of display technology, the existing notch screen or water drop screen design gradually cannot meet the user's demand for high screen-to-body ratio of the display panel, and a series of display panels with a light-transmitting display area emerge as the times require. In such a display panel, a hardware such as a photosensitive sensor (e.g., a camera) can be arranged in the light-transmitting display area, so that the true full-screen is possible under the premise of ensuring the practicability of the display panel without the need for punching.

[0073] In the related art, a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for arranging the camera. The second display area generally includes a plurality of light emitting elements and a plurality of pixel circuits, each pixel circuit is connected with a light emitting element and is used to drive the light emitting element to emit light, and the pixel circuits and the light emitting elements connected with each other overlap in a direction perpendicular to the display panel.

[0074] Since the pixel circuit is also arranged in the second display area in the related art, the light transmittance of the second display area is poor, and accordingly, the display effect of the display panel is poor.

[0075] Figure 1A is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 1B is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. As Figure 1A and Figure 1BAs shown, the display panel can include a substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 can be located at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 can be surrounded by the first display area R1. The second display area R2 can also be provided at other positions, and the setting position of the second display area R2 can be determined as needed. For example, the second display area R2 can be located at the top center position of the substrate BS, or at the upper left corner or upper right corner of the substrate BS. For example, a hardware such as a photosensitive sensor (e.g., a camera) is provided at the second display area R2 of the display panel. For example, the second display area R2 is a light-transmissive display area, and the first display area R1 is a display area. For example, the first display area R1 is not light-transmissive and is only used for display. Figure 1B As shown, the first display area R1 includes an auxiliary area Ra.

[0076] Figure 2 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a substrate. As shown, Figure 2 As shown, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b, and the pixel circuit 100a is configured to drive the light emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current to drive the light emitting element 100b to emit light. For example, the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit 100a. The color of the light emitted by the light emitting element 100b can be determined as needed.

[0077] In order to improve the light transmittance of the second display area R2, only the light emitting element can be provided in the second display area R2, and the pixel circuit for driving the light emitting element of the second display area R2 is provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by the separate arrangement of the light emitting element and the pixel circuit. That is, in the second display area R2, the pixel circuit 100a is not provided.

[0078] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown, Figure 3 The display panel includes a plurality of first type pixel circuits 10, a plurality of second type pixel circuits 20, and a plurality of first area light emitting elements 30 located in the first display area R1, and a plurality of second area light emitting elements 40 located in the second display area R2. For example, the plurality of second type pixel circuits 20 can be distributed between the plurality of first type pixel circuits 10.

[0079] For example, as Figure 3As shown, at least one first-type pixel circuit 10 in the plurality of first-type pixel circuits 10 can be connected with at least one first-area light emitting element 30 in the plurality of first-area light emitting elements 30, and the orthographic projection of the at least one first-type pixel circuit 10 on the substrate BS can at least partially overlap with the orthographic projection of the at least one first-area light emitting element 30 on the substrate BS. The at least one first-type pixel circuit 10 can be configured to provide a driving signal for the connected first-area light emitting element 30 to drive the first-area light emitting element 30 to emit light.

[0080] For example, as shown in FIG. 1, the plurality of first-type pixel circuits 10 can be connected with the plurality of first-area light emitting elements 30 through the conductive lines L1. The plurality of first-type pixel circuits 10 can be configured to provide driving signals for the plurality of first-area light emitting elements 30 to drive the plurality of first-area light emitting elements 30 to emit light. Figure 3 As shown, at least one second-type pixel circuit 20 in the plurality of second-type pixel circuits 20 can be connected with at least one second-area light emitting element 40 in the plurality of second-area light emitting elements 40 through the conductive lines L1. The at least one second-type pixel circuit 20 can be configured to provide a driving signal for the connected second-area light emitting element 40 to drive the second-area light emitting element 40 to emit light. As shown in FIG. 1, the plurality of second-type pixel circuits 20 can be connected with the plurality of second-area light emitting elements 40 through the conductive lines L1. The plurality of second-type pixel circuits 20 can be configured to provide driving signals for the plurality of second-area light emitting elements 40 to drive the plurality of second-area light emitting elements 40 to emit light. Figure 3 As shown, because the second-area light emitting elements 40 and the second-type pixel circuits 20 are located in different areas, the orthographic projection of the at least one second-type pixel circuit 20 on the substrate BS does not overlap with the orthographic projection of the at least one second-area light emitting element 40 on the substrate BS.

[0081] For example, in the embodiments of the present disclosure, the first display area R1 can be set as a non-light-transmitting display area, and the second display area R2 can be set as a light-transmitting display area. For example, the first display area R1 is not light-transmitting, and the second display area R2 is light-transmitting. In this way, the display panel provided by the embodiments of the present disclosure does not need to be subjected to a hole digging process, and the required hardware structures such as a photosensitive sensor can be directly arranged at a position corresponding to the second display area R2 on one side of the display panel, thereby laying a solid foundation for the realization of a true full-screen. Moreover, because the second display area R2 only includes light emitting elements but does not include pixel circuits, the light transmittance of the second display area R2 can be improved, so that the display panel has a better display effect.

[0082] As shown in FIG. 1, the display panel 100 can include a substrate BS, a plurality of first-type pixel circuits 10, a plurality of first-area light emitting elements 30, a plurality of second-type pixel circuits 20, and a plurality of second-area light emitting elements 40. Figure 3As shown, pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102. The pixel circuit 100a and light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1. The pixel circuit 100a of the second pixel unit 101 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In the embodiments of this disclosure, the pixel circuit 100a of the first pixel unit 101 is a first-type pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is a first-area light-emitting element 30, the pixel circuit 100a of the second pixel unit 101 is a second-type pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is a second-area light-emitting element 40. For example, the first-area light-emitting element 30 can be called an in-situ light-emitting element. For example, the first-type pixel circuit 10 can be called an in-situ pixel circuit, and the second-type pixel circuit 20 can be called a non-in-situ pixel circuit.

[0083] For example, such as Figure 3 As shown, the second-region light-emitting element 40 and the second-type pixel circuit 20 connected to the second-region light-emitting element 40 are located in the same row. That is, the light emission signal of the second-region light-emitting element 40 comes from the second-type pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0084] like Figure 3 As shown, the pixel circuit (second type pixel circuit 20) of the second pixel unit 102 is connected to the light-emitting element (second region light-emitting element 40) of the second pixel unit 102 via a conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited to this.

[0085] like Figure 3 As shown, one end of the conductive line L1 is connected to the second type of pixel circuit 20, and the other end of the conductive line L1 is connected to the second region light-emitting element 40. Figure 3 As shown, the conductive line L1 extends from the first display area R1 to the second display area R2.

[0086] like Figure 1B and Figure 3As shown, in some embodiments, the first display region R1 can include an auxiliary region Ra, which can be provided with the second type of pixel circuit 20 connected with the second area light emitting element 40. For example, in the region of the first display region R1 except the auxiliary region Ra, a plurality of dummy pixel circuits can be provided. The dummy pixel circuit is not connected with any light emitting element. The dummy pixel circuit is provided to facilitate the uniformity of the components of each film layer in the etching process. For example, the dummy pixel circuit has the same structure as the second type of pixel circuit 20 in the row or column where the dummy pixel circuit is located, except that the dummy pixel circuit is not connected with any light emitting element. For example, in the first display region R1, the pixel density or the resolution of the auxiliary region Ra and the region of the first display region R1 except the auxiliary region Ra (non-auxiliary region) is the same, but is not limited thereto.

[0087] Figure 3 Three rows of light emitting elements 100b are shown. Figure 3 The first row of light emitting elements 100b shown passes through the first display region R1 and the second display region R2, and is a row of light emitting elements 100b passing through two regions. Figure 3 The second row of light emitting elements 100b shown passes through the first display region R1 and the second display region R2, and is a row of light emitting elements 100b passing through two regions. Figure 3 The third row of light emitting elements 100b shown only passes through the first display region R1 and does not pass through the second display region R2, and is a row of light emitting elements 100b passing through one region. For example, in some embodiments, the light emitting elements 100b are divided into two types of row light emitting elements, i.e., a row of light emitting elements passing through two regions and a row of light emitting elements passing through one region.

[0088] Figure 4 A schematic diagram of the first display region and the second display region in a display panel according to an embodiment of the present disclosure is shown. As shown, Figure 4 In the second display region R2, a light transmission region R0 is provided between adjacent second area light emitting elements 40. For example, as shown, Figure 4 A plurality of light transmission regions R0 are connected with each other to form a continuous light transmission region spaced by a plurality of second area light emitting elements 40. The conductive line L1 is made of a transparent conductive material to improve the light transmission rate of the light transmission region R0 as much as possible. As shown, Figure 4 The region of the second display region R2 except the second area light emitting element 40 can be a light transmission region.

[0089] Figures 5A to 5C A partial plan view of a display panel according to an embodiment of the present disclosure is shown. The following is described. Figures 5A to 5C

[0090] Figure 5A A schematic diagram of the first display region and the second display region of a display panel according to an embodiment of the present disclosure is shown. As shown,​ Figure 5A As shown, the second display area R2 is a light-transmissive display area, and the first display area R1 is a display area.

[0091] Figure 5B A schematic view of a first area light emitting element in a first display area and a second area light emitting element in a second display area of a display panel is provided for an embodiment of the present disclosure. Figure 5B The first area light emitting element 30 and the second area light emitting element 40 are shown.

[0092] Referring to Figure 5A , Figure 5B and Figure 3 , in order to improve the display effect, the density of the second area light emitting element 40 can be equal to the density of the first area light emitting element 30. That is, the resolution of the second display area R2 is the same as the resolution of the first display area R1. Of course, in other embodiments, the density of the second area light emitting element 40 can be greater than or less than the density of the first area light emitting element 30. That is, the resolution of the second display area R2 can be greater than or less than the resolution of the first display area R1. For example, as shown in Figure 5B and Figure 4 , the light emitting area of the second area light emitting element 40 is smaller than the light emitting area of the first area light emitting element 30. That is, the light emitting area of the first area light emitting element 30 is greater than the light emitting area of the second area light emitting element 40, Figure 4 The light emitting area of the second area light emitting element 40 and the light emitting area of the first area light emitting element 30 are shown with dashed lines. For example, the light emitting area of the light emitting element can correspond to the area of the opening of the pixel definition layer.

[0093] Figure 5C The first area light emitting element 30, the second area light emitting element 40, the first type of pixel circuit 10, the second type of pixel circuit 20, the connection element CE0, and the conductive line L1 are shown. Each pixel circuit is connected to the light emitting element through the connection element CE0. That is, each pixel unit has one connection element CE0. That is, the first type of pixel circuit 10 is connected to the first area light emitting element 30 through the connection element CE0, and the second type of pixel circuit 20 is connected to the second area light emitting element 40 through the connection element CE0.

[0094] For example, as shown in Figure 5CAs shown, one end of the conductive line Ll is connected to the second region light emitting element 40, and the other end of the conductive line Ll is connected to the second type pixel circuit 20 through the connection element CE0. For example, the connection element CE0 is connected to the pixel circuit 100a and the light emitting element 100b, respectively. For example, the connection element CE0 is connected to the light emitting control transistor in the pixel circuit 100a and the first electrode of the light emitting element 100b, respectively. For example, the connection element CE0 can be formed by a single conductive member, or can include two different conductive members located in different layers. For example, the connection element CE0 can include one conductive member located in one conductive layer and another conductive member located in another conductive layer.

[0095] As shown in FIG. 1, the conductive line Ll is connected to the second type pixel circuit 20 and the second region light emitting element 40 on both sides of the pixel unit, respectively. Figure 5C As shown, one conductive line Ll passes through the region where the pixel circuit of the pixel unit is located to connect the second type pixel circuit 20 and the second region light emitting element 40 on both sides of the pixel unit, respectively. For example, the region where the pixel circuit of the pixel unit is located overlaps with multiple conductive lines Ll passing through the region. The region where the second type pixel circuit 20 is provided in the first display area Rl can be referred to as an auxiliary area Ra (as shown in FIG. 1). Figure 1B As shown, the auxiliary area Ra can also be referred to as a transition area. Figure 3 Figure 5C In other embodiments, a first type pixel circuit 10 can also overlap with more conductive lines Ll. For example, in some embodiments, a first type pixel circuit 10 can overlap with 10-15 conductive lines Ll. The number of conductive lines Ll that a first type pixel circuit 10 overlaps with can be determined as needed. Figure 5C As shown, the second type pixel circuit 20 can also overlap with conductive lines Ll that are not connected thereto.

[0096] In some embodiments, the region where the second type pixel circuit 20 is provided can be obtained by compressing the size of the first type pixel circuit 10 in the first direction X. For example, as shown in FIG. 1, in the auxiliary area, a column of second type pixel circuits 20 is provided every set of columns of first type pixel circuits 10. For example, the number of columns of first type pixel circuits 10 between two adjacent columns of second type pixel circuits 20 can be determined as needed. Figure 5C

[0097] ​​For example, in some embodiments, the area where the second type of pixel circuit 20 is arranged can be obtained by reducing the size of the first type of pixel circuit 10 in the first direction X. For example, the size of the first type of pixel circuit 10 in the first direction X is smaller than the size of the first area light emitting element 30 in the first direction X. The first direction X is, for example, the row direction, but is not limited thereto, and in other embodiments, the first direction X can also be the column direction. Embodiments of the present disclosure are described by taking the first direction X as the row direction as an example.

[0098] Figures 5D to 5F is a structural schematic diagram of a display panel provided by some embodiments of the present disclosure. In order to further embody that after compressing the pixel circuit, more columns of pixel circuits are added, Figure 5D a first area light emitting element structural schematic diagram of a first display area R1 is shown. Figure 5E a partial structure (only including the pixel circuit) schematic diagram in Figure 5A is shown, Figure 5F a partial structure (only including the light emitting element) schematic diagram in Figure 5A is shown.

[0099] Referring to Figures 5D to 5F It can be seen that the width of the pixel circuit is smaller than the width of the light emitting element, so that the pixel circuits in the second column and the ninth column from right to left are not connected to any first area light emitting element 30, which belong to the more columns of pixel circuits, and can be used as the second type of pixel circuit 20 to connect the second area light emitting element 40 in the second display area R2. For example, as shown in Figure 5F , the first area light emitting element 30 can include four first poles E1 of four light emitting elements RG1BG2, and the first pole E1 of the light emitting element is connected to the first type of pixel circuit 10 through the connecting element CE0. R represents a red light emitting element, G1 represents a green light emitting element, B represents a blue light emitting element, and G2 represents a green light emitting element. For example, the connecting element CE0 includes two connecting electrodes, which can be the connecting electrode CE01 (as shown in Figure 5E or Figure 12B ) and the connecting electrode CE02 (as shown in Figure 5F or Figure 12B ), but are not limited thereto. For example, in order to have sufficient space to arrange the conductive wire L1, the axes of the connecting electrodes CE01 in the same row of pixel units can be located on a straight line.

[0100] Figure 5F Four rows of connecting elements CE0 / connecting electrodes CE02 are shown, that is, Figure 5FFour rows of light emitting elements are shown. For example, the light emitting elements in each row are arranged in the order of RGBG or BGRG along the first direction X. Of course, the light emitting colors of the light emitting elements are not limited to RGB, and the arrangement of the light emitting elements is not limited to Figure 5F As shown, embodiments of the present disclosure are described by way of example with the light emitting elements including RGBG. For example, as shown in FIG. 1A, the light emitting elements in each row are arranged in the order of RGBG along the first direction X. Of course, the light emitting colors of the light emitting elements are not limited to RGB, and the arrangement of the light emitting elements is not limited to Figure 5F As shown, G includes G1 or G2. For example, Figure 5F As shown in the pixel arrangement, one repeating unit RP includes two Gs arranged along the second direction Y and R and B arranged on both sides of the two Gs along the first direction X, where R and G constitute one pixel and display by borrowing B in another repeating unit adjacent thereto to constitute a virtual pixel, and B and G constitute one pixel and display by borrowing R in another repeating unit adjacent thereto to constitute a virtual pixel, but are not limited thereto.

[0101] Referring to Figure 3 , Figure 4 , Figures 5A to 5C , some embodiments of the present disclosure provide a display panel including a substrate BS, a plurality of light emitting elements 100b, and a plurality of pixel circuits 100a. The substrate BS has a first display area R1 and a second display area R2, and the first display area R1 is located on at least one side of the second display area R2. The plurality of light emitting elements 100b are arranged in a plurality of rows and a plurality of columns.

[0102] Referring to Figure 3 , Figure 4 , Figure 5C and Figure 5F , the plurality of light emitting elements 100b includes a plurality of groups of light emitting elements, and the light emitting elements in each group of the plurality of groups of light emitting elements are arranged along the first direction X, and the plurality of groups of light emitting elements are arranged along the second direction Y. Figure 3 and Figure 5C both show three groups of light emitting elements GP, which are a group of light emitting elements GPx, a group of light emitting elements GPy, and a group of light emitting elements GPz, respectively; the group of light emitting elements GPx and the group of light emitting elements GPy pass through the first display area R1 and the second display area R2, and the group of light emitting elements GPz only passes through the first display area R1. Figure 4 At least four groups of light emitting elements GP arranged along the second direction Y are shown. Figure 5F At least four groups of light emitting elements GP arranged along the second direction Y are shown. In the display panel, the number of groups of light emitting elements passing through the first display area R1 and the second display area R2 and the number of groups of light emitting elements only passing through the first display area R1 can be determined as needed.

[0103] For example, in some embodiments, a group of light emitting elements can be a row of light emitting elements, of course, a group of light emitting elements can not completely correspond to a column of light emitting elements. In other embodiments, a group of light emitting elements can be a column of light emitting elements, of course, a group of light emitting elements can not completely correspond to a column of light emitting elements. Embodiments of the present disclosure take a group of light emitting elements as an example of a row of light emitting elements.

[0104] For example, referring to Figure 3 and Figure 5C , at least one of the plurality of groups of light emitting elements includes a plurality of first area light emitting elements 30 and a plurality of second area light emitting elements 40. That is, at least one of the plurality of groups of light emitting elements passes through the first display area R1 and the second display area R2.

[0105] For example, referring to Figure 3 , Figure 4 , and Figure 5C , the plurality of light emitting elements 100b includes at least one row of two-area light emitting elements 100b passing through the first display area R1 and the second display area R2, and any one of the at least one row of two-area light emitting elements 100b includes a plurality of first area light emitting elements 30 and a plurality of second area light emitting elements 40.

[0106] For example, referring to Figure 3 , Figure 4 , and Figure 5C , the plurality of first area light emitting elements 30 is located in the first display area R1, and the plurality of second area light emitting elements 40 is located in the second display area R2.

[0107] For example, referring to Figure 3 , Figure 5C and Figure 5E , the plurality of pixel circuits includes a plurality of groups of pixel circuits GR, the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along a first direction X, and the plurality of groups of pixel circuits are arranged along a second direction Y. For example, at least one of the plurality of groups of pixel circuits 100a includes a plurality of first type pixel circuits 10 and a plurality of second type pixel circuits 20. Figure 3 and Figure 5C respectively show three groups of pixel circuits GR. Figure 5E show four groups of pixel circuits GR. As shown in Figure 3 and Figure 5C , the pixel circuits are only located in the first display area R1, and no pixel circuits are arranged in the second display area R2.

[0108] For example, referring to Figure 3 and Figure 5CThe plurality of pixel circuits 100a are arranged in a plurality of rows and a plurality of columns, and the plurality of pixel circuits 100a include a plurality of pixel circuits 10 of the first type and a plurality of pixel circuits 20 of the second type in the same row. Alternatively, at least one of the plurality of groups of pixel circuits includes the plurality of pixel circuits 10 of the first type and the plurality of pixel circuits 20 of the second type.

[0109] For example, referring to Figure 3 and Figure 5C The plurality of pixel circuits 100a are arranged in a plurality of rows and a plurality of columns, and the plurality of pixel circuits 100a include a plurality of pixel circuits 10 of the first type and a plurality of pixel circuits 20 of the second type in the same row. Alternatively, at least one of the plurality of groups of pixel circuits includes the plurality of pixel circuits 10 of the first type and the plurality of pixel circuits 20 of the second type.

[0110] Figure 6A FIG. 6 is a schematic view of a row of light emitting elements in a second display area and pixel circuits of the second type connected thereto in a display panel according to an embodiment of the present disclosure. Figure 6B FIG. 7 is a schematic view of capacitance of a conductive line in a display panel according to an embodiment of the present disclosure. Figure 6C FIG. 8 is a schematic view of display failure of a display panel according to an embodiment of the present disclosure. Figures 6D to 6F FIG. 9 is a schematic view of display failure at a low gray scale. Figure 7A FIG. 10 is a schematic view of a row of light emitting elements in a second display area and pixel circuits of the second type connected thereto in a display panel according to an embodiment of the present disclosure. Figure 7B FIG. 11 is a schematic view of capacitance of light emitting elements emitting different colors of light in the same row of light emitting elements in a second display area in a display panel according to an embodiment of the present disclosure.

[0111] For example, in an embodiment of the present disclosure, a row of light emitting elements can refer to pixel circuits connected to the row of light emitting elements all being connected to the same gate line, but is not limited thereto. For example, in an embodiment of the present disclosure, a row of pixel circuits can refer to pixel circuits connected to the row of pixel circuits all being connected to the same gate line, but is not limited thereto. For example, in an embodiment of the present disclosure, a row of pixel units can refer to pixel circuits connected to the row of pixel units all being connected to the same gate line, but is not limited thereto.

[0112] For example, as Figure 6A and Figure 7AAs shown, in at least one set of light-emitting elements 100b, a plurality of second-region light-emitting elements 40 include a plurality of first light-emitting elements 41 and a plurality of second light-emitting elements 42. The first light-emitting elements 41 are configured to emit light of a first color, and the second light-emitting elements 42 are configured to emit light of a second color. A plurality of second-type pixel circuits 20 include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22. The conductive line L1 includes a plurality of first conductive lines La and a plurality of second conductive lines Lb. The plurality of first light-emitting elements 41 are connected to the plurality of first pixel circuits 21 through the plurality of first conductive lines La, and the plurality of second light-emitting elements 42 are connected to the plurality of second pixel circuits 22 through the plurality of second conductive lines Lb. For example, a first light-emitting element 41 is connected to a first pixel circuit 21 through a first conductive line La, and a second light-emitting element 42 is connected to a second pixel circuit 22 through a second conductive line Lb.

[0113] For example, such as Figure 6A and Figure 7A As shown, the plurality of second-region light-emitting elements 40 also include a plurality of third light-emitting elements 43, which are configured to emit a third color of light. The plurality of second-type pixel circuits 20 also include a plurality of third pixel circuits 23. The conductive line L1 also includes a plurality of third conductive lines Lc. The plurality of third light-emitting elements 43 and the plurality of third pixel circuits 23 are connected through the plurality of third conductive lines Lc. For example, one third light-emitting element 43 is connected to one third pixel circuit 23 through one third conductive line Lc.

[0114] For example, such as Figure 6A and Figure 7A As shown, the plurality of second-region light-emitting elements 40 also include a plurality of fourth light-emitting elements 44, which are configured to emit a fourth color of light. The plurality of second-type pixel circuits 20 also include a plurality of fourth pixel circuits 24. The conductive line L1 also includes a plurality of fourth conductive lines Ld. The plurality of fourth light-emitting elements 44 and the plurality of fourth pixel circuits 24 are connected through the plurality of fourth conductive lines Ld. For example, one fourth light-emitting element 44 is connected to one fourth pixel circuit 24 through one fourth conductive line Ld.

[0115] For example, the first and fourth colors of light are both green, one of the second and third colors of light is red, and the other of the second and third colors of light is blue.

[0116] For example, the fourth light-emitting element 44 and the first light-emitting element 41 are configured to emit the same color of light. For example, the fourth light-emitting element 44 and the first light-emitting element 41 are configured to emit green light, one of the second light-emitting element 42 and the third light-emitting element 43 is configured to emit red light, and the other of the second light-emitting element 42 and the third light-emitting element 43 is configured to emit blue light. The embodiments of this disclosure are illustrated by taking the fourth light-emitting element 44 and the first light-emitting element 41 emitting green light, the second light-emitting element 42 emitting red light, and the third light-emitting element 43 emitting blue light as an example. In other embodiments, the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43, and the fourth light-emitting element 44 may also emit other colors of light, not limited to red, green, and blue. The color of the light emitted by the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43, and the fourth light-emitting element 44 can be determined as needed.

[0117] like Figure 6B As shown, the horizontal axis represents the position of the second display area of ​​the display panel in the first direction, and the vertical axis represents the ratio of the capacitance of the conductive lines connected to the light-emitting elements at that position to the total capacitance. In the display panel, the capacitance of the conductive lines varies considerably. Because the lengths of the conductive lines connecting the various light-emitting elements in the second display area are different, the capacitance differences among light-emitting elements emitting different colors of light vary. The capacitance difference of the conductive lines connected to red-emitting light-emitting elements is greater than that of the conductive lines connected to blue-emitting light-emitting elements. Because of this greater capacitance difference, the light-emitting time of the green-emitting light-emitting elements is reduced, resulting in brightness differences in the display panel and causing display defects. For example, as... Figure 6C As shown, stripes appear when the display panel is shown. For example, as... Figure 6C As shown, purple stripes appear when the display panel is shown. Figure 6C (This is a grayscale image, not color-coded). For example, purple vertical stripes appear when the display panel is shown. For example, as... Figures 6D to 6F As shown, at low grayscale, the defect rate of green-emitting light-emitting elements is greater than that of red-emitting light-emitting elements, and the defect rate of red-emitting light-emitting elements is greater than that of blue-emitting light-emitting elements. For example, at the same grayscale, the driving current for driving blue-emitting light-emitting elements is greater than that for driving red-emitting light-emitting elements, and the driving current for driving red-emitting light-emitting elements is greater than that for driving green-emitting light-emitting elements.

[0118] Figure 7B for Figure 7A A schematic diagram showing the capacitance distribution of the conductive lines connected to light-emitting elements emitting different colors of light in a row of light-emitting elements located in the second display area. (See diagram below.) Figure 7BAs shown, the capacitance of the conductive wire connected to the light-emitting element emitting green light is the smallest, and as shown in the left half Figure 7B , the capacitance of the conductive wire connected to the light-emitting element emitting green light shows a gradually increasing trend, so that the capacitance difference between the two conductive wires connected to the adjacent light-emitting elements emitting green light is small. Since the structure of the second display area of the display panel is symmetrically arranged, Figure 7B , the right half is not described in detail. As shown in Figure 7B , the capacitance of the conductive wire connected to the light-emitting element emitting green light is smaller than the capacitance of the conductive wire connected to the light-emitting element emitting red light, and the capacitance of the conductive wire connected to the light-emitting element emitting green light is smaller than the capacitance of the conductive wire connected to the light-emitting element emitting blue light. As shown in Figure 7B , the capacitance of the conductive wire connected to the light-emitting element emitting red light shows a gradually increasing trend, and the capacitance of the conductive wire connected to the light-emitting element emitting blue light shows a gradually increasing trend, and the capacitance of the conductive wire connected to the light-emitting element emitting red light and the capacitance of the conductive wire connected to the light-emitting element emitting blue light are not much different.

[0119] The display panel provided by the embodiments of the present disclosure adjusts the arrangement order of the second type of pixel circuit connected to the light-emitting element emitting different colors of light in order to improve display defects, so as to alleviate or eliminate display defects caused by large length difference of the conductive wire. That is, when designing the second type of pixel circuit connected to the first light-emitting element, the length of the conductive wire and the length difference of the conductive wire are considered, for example, a G-priority order is adopted. For example, G-priority refers to that the second type of pixel circuit connected to the light-emitting element emitting green light is preferentially arranged close to the second display area.

[0120] As shown in Figure 7A , in at least one group of light-emitting elements and at least one group of pixel circuits, the plurality of first pixel circuits 21 connected to the plurality of first light-emitting elements 41 are closer to the second display area R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light-emitting elements 42. That is, Figure 7A , the display panel adjusts the arrangement position of the first pixel circuit 21 connected to the first light-emitting element 41, so that the first pixel circuit 21 connected to the first light-emitting element 41 is closer to the second display area R2 than other second type of pixel circuit, so as to reduce the length difference of the first conductive wire La connected to the first light-emitting element 41, and alleviate or avoid display defects. Figure 6A For example, in the embodiments of the present disclosure, at least one group of light-emitting elements and at least one group of pixel circuits can refer to a row of light-emitting elements 100b passing through two areas, or can refer to a row of pixel units passing through two areas, but are not limited thereto.

[0121] ​

[0122] For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other pixel circuit 20 of the second type is arranged between two first pixel circuits 21 connected with two adjacent first conductive lines La. Figure 7A For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other pixel circuit 20 of the second type is arranged between two first pixel circuits 21 connected with two adjacent first conductive lines La.

[0123] It should be noted that, in the display panel provided by the embodiments of the present disclosure, the element A and the element B are adjacent, or the adjacent element A and the element B refer to that the element A and the element B do not have other element A and other element B, but can have other elements in addition to the element A and the element B. The element A and the element B can be the same element or different elements.

[0124] For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other pixel circuit 20 of the second type is arranged between two first pixel circuits 21 connected with two adjacent first conductive lines La. Figure 5C Figure 5E Figure 7A For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, at least one of the plurality of first pixel circuits 10 is arranged between two adjacent second pixel circuits 20 of the second type.

[0125] For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other pixel circuit 20 of the second type is arranged between two first pixel circuits 21 connected with two adjacent first conductive lines La. Figure 7A

[0126] Only one row of light emitting elements passing through the two regions is shown, and it can be understood that, on the upper side, the lower side, or the upper side and the lower side of the row of light emitting elements shown in FIG. 1A, there are also a plurality of rows of light emitting elements which are the same as the row of light emitting elements shown in FIG. 1A. Thus, Figure 7A Each light emitting element shown in FIG. 1A is one of a column of light emitting elements, Figure 7A Each pixel circuit shown in FIG. 1A is one of a column of pixel circuits. Figure 7A Figure 7A For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first pixel circuits 21 connected with the plurality of first conductive lines La is closer to the second display area R2 than each of the plurality of third pixel circuits 23 connected with the plurality of third conductive lines Lc.

[0127] For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first pixel circuits 21 connected with the plurality of first conductive lines La is closer to the second display area R2 than each of the plurality of third pixel circuits 23 connected with the plurality of third conductive lines Lc. Figure 7A For example, as shown in FIG. 1A, in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first pixel circuits 21 connected with the plurality of first conductive lines La is closer to the second display area R2 than each of the plurality of third pixel circuits 23 connected with the plurality of third conductive lines Lc.

[0128] Figure 7A ​​​​As shown, in at least one group of light emitting elements and at least one group of pixel circuits, the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb and the plurality of third pixel circuits 23 connected to the plurality of third conductive lines Lc are alternately arranged.

[0129] For example, as shown in FIG. 1, the plurality of second conductive lines Lb and the plurality of third conductive lines Lc are arranged in the same direction. Figure 7A As shown, in at least one group of light emitting elements and at least one group of pixel circuits, the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld are closer to the second display area R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb. In an embodiment of the present disclosure, the fourth light emitting element 44 and the first light emitting element 41 emit light of the same color, so that the plurality of fourth pixel circuits 24 are also preferentially arranged, i.e., the plurality of fourth pixel circuits 24 are arranged closer to the second display area. Of course, in other embodiments, the fourth light emitting element 44 can not be arranged, so that the fourth pixel circuit 24 also does not need to be arranged. For example, in this case, the pixel can be in the form of true RGB, but is not limited thereto.

[0130] For example, as shown in FIG. 1, the plurality of second conductive lines Lb and the plurality of third conductive lines Lc are arranged in the same direction. Figure 7A As shown, in at least one group of light emitting elements and at least one group of pixel circuits, the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld and the plurality of first pixel circuits 21 connected to the plurality of first conductive lines La are alternately arranged, so that the first conductive lines La have smaller capacitance differences and the fourth conductive lines Ld have smaller capacitance differences.

[0131] For example, at least one of the first conductive lines La, the second conductive lines Lb, the third conductive lines Lc, and the fourth conductive lines Ld is made of a transparent conductive material.

[0132] Figure 7C A schematic view of a display panel is provided for an embodiment of the present disclosure. As shown in FIG. 1, the display panel includes a plurality of first conductive lines L1, a plurality of second conductive lines Lb, a plurality of third conductive lines Lc, and a plurality of fourth conductive lines Ld. Figure 7C As shown, the second display area R2 of the display panel is an axisymmetric shape, having a first axis of symmetry X1 extending along the first direction X and a second axis of symmetry X2 extending along the second direction Y. For example, as shown in FIG. 1, the second display area R2 is a circular shape. Figure 7C As shown, the conductive lines L1 are arranged in a plurality of lines, and the plurality of conductive lines L1 are axisymmetric with respect to the first axis of symmetry X1 and axisymmetric with respect to the second axis of symmetry X2. Figure 7C Only four conductive lines L1 are shown schematically. Figure 7CThe second display area R2 is shown to include a first sub-area R21, a second sub-area R22, a third sub-area R23, and a fourth sub-area R24. The first sub-area R21 and the second sub-area R22 are axially symmetrical with respect to a second axis of symmetry X2; the third sub-area R23 and the fourth sub-area R24 are axially symmetrical with respect to the second axis of symmetry X2; the first sub-area R21 and the third sub-area R23 are axially symmetrical with respect to a first axis of symmetry X1; and the second sub-area R22 and the fourth sub-area R24 are axially symmetrical with respect to the first axis of symmetry X1. For example, multiple second-area light-emitting elements are axially symmetrical with respect to the first axis of symmetry X1 and with respect to the second axis of symmetry X2. Figure 7A The row of light-emitting elements shown can be located in the first sub-region R21 or the third sub-region R23.

[0133] Figure 8A This is a schematic diagram of a light-emitting element located in a second display area and a second type of pixel circuit connected thereto in a display panel according to an embodiment of the present disclosure. Figure 8A The diagram shows some of the light-emitting elements located in the second display area. For clarity, the light-emitting elements located in the first display area and the first type of pixel circuitry are omitted. Figure 7A and Figure 8A It is understood that one or more first-type pixel circuits and a first-area light-emitting element connected to the first-type pixel circuits are arranged between two adjacent second-type pixel circuits.

[0134] Figure 8A Two rows of light-emitting elements are shown in the left half of the second display area R2. The structure in the second display area R2 is symmetrical about the vertical axis X1 and about the horizontal axis X2. Figure 8A Two rows of light-emitting elements r1 and r2 are shown, in order to Figure 8A One row of light-emitting elements r1 is used as the main descriptor. For example, two rows of light-emitting elements r1 and r2 are symmetrical about the first axis of symmetry X1. Figure 8A The two rows of light-emitting elements r1 and r2 shown are located at... Figure 7C The first sub-region R21 or the third sub-region R23 shown.

[0135] Figure 8B for Figure 8A A schematic diagram of the first conductive line La and the fourth conductive line Ld in the diagram. Figure 8C for Figure 8A A schematic diagram of the second conductive line Lb in the diagram. Figure 8D for Figure 8A A schematic diagram of the third conductive line Lc in the diagram.

[0136] For example, in some embodiments, the first conductive line La and the fourth conductive line Ld are located in the same pattern layer, the second conductive line Lb is located in one pattern layer, and the third conductive line Ld is located in another pattern layer, thus forming three pattern layers. For example, in some embodiments, the first conductive line La and the fourth conductive line Ld are located in the third pattern layer, the second conductive line Lb is located in the second pattern layer, and the third conductive line Ld is located in the first pattern layer. For example, the third pattern layer, the second pattern layer, and the first pattern layer are arranged sequentially in a direction perpendicular to the substrate, and the first pattern layer is closer to the substrate than the second pattern layer, and the second pattern layer is closer to the substrate than the third pattern layer. When the number of conductive lines required for each group of light-emitting elements is small, the conductive lines for that group of light-emitting elements can be arranged in one layer. When the number of conductive lines required for each group of light-emitting elements is large, the conductive lines can be arranged in several different layers. As needed, some conductive lines can be formed in segments, that is, formed by conductive portions located in different layers. A segmented arrangement is used when there are many conductive lines to be arranged.

[0137] For example, such as Figure 8A , Figures 8B to 8D As shown, the conductive lines connected to the two rows of adjacent light-emitting elements 100b passing through the two regions are axially symmetrical.

[0138] For example, such as Figure 8A , Figures 8B to 8D As shown, the structure within the second display area R2 is axially symmetrical.

[0139] Figure 8E This is a schematic diagram of a row of light-emitting elements r1 in a display panel provided according to another embodiment of this disclosure. Figure 8E As shown in the diagram, solid lines represent the second pattern layer, dashed lines represent the first pattern layer, and dashed lines represent the third pattern layer. Conductive portions of the same conductive line located on different layers are connected vias. For example... Figure 8E As shown, in densely wired areas, adjacent conductive lines are located on different pattern layers in the second direction Y. This arrangement helps to reduce interference between conductive lines.

[0140] For example, at least one of the multiple first conductive lines La, the multiple second conductive lines Lb, the multiple third conductive lines Lc, and the multiple fourth conductive lines Ld is formed entirely by a single conductive line, or is formed by conductive portions located in different layers.

[0141] like Figure 8E As shown, conductive line Lb1 is formed from conductive parts located in different layers, and conductive line Lc1 is formed from conductive parts located in different layers. Figure 8E The other conductive lines are all formed by a single conductive line and are distributed in three different pattern layers.

[0142] For example, such as Figure 1B As shown, the first display area R1 includes an auxiliary area Ra, and a plurality of second-type pixel circuits 20 are located in the auxiliary area Ra. The area of ​​the auxiliary area Ra is smaller than the area of ​​the area of ​​the first display area R1 excluding the auxiliary area Ra.

[0143] For example, to facilitate the placement of the second type of pixel circuit 20 in the first display area R1, the size of the first type of pixel circuit 10 in the first direction is smaller than the size of the first area light-emitting element 30 in the first direction. For example, the size of the second type of pixel circuit 20 in the first direction is smaller than the size of the first area light-emitting element 30 in the first direction. For example, the size of the first type of pixel circuit 10 in the first direction is equal to or approximately equal to the size of the second type of pixel circuit 20 in the first direction.

[0144] Figure 8A The display panel shown includes a fourth light-emitting element; however, in some embodiments, the display panel may not include the fourth light-emitting element. In cases where the display panel does not include the fourth light-emitting element, it can be removed... Figure 8A The fourth light-emitting element and the pixel circuit connected to the fourth light-emitting element are shown, and the positions of other components are adjusted accordingly.

[0145] Figure 9A This is a schematic diagram of another display panel provided in an embodiment of the present disclosure. Figure 9B This is a schematic diagram of a display panel provided for another embodiment of the present disclosure. (See diagram below.) Figure 9A As shown, the fourth conductive line Ld and the first conductive line La are located on the same side of the row of light-emitting elements. Figure 9A The following explanation uses an example where the fourth conductive line Ld and the first conductive line La are located above the row of light-emitting elements. Figure 9A As shown, the fourth conductive line Ld and the first conductive line La partially overlap. That is, the orthographic projection of the fourth conductive line Ld onto the substrate and the orthographic projection of the first conductive line La onto the substrate partially overlap. Figure 9B As shown, the second conductive line Lb and the third conductive line Lc partially overlap. That is, the orthographic projections of the second conductive line Lb and the third conductive line Lc on the substrate partially overlap. This overlapping arrangement of conductive lines helps to reduce the space occupied by the conductive lines connected to the light-emitting elements in the second direction Y within the second display area, facilitating the arrangement of more conductive lines. Figure 9A and Figure 9BAs shown, the same line type represents the same layer. For example, the portion shown by the single-dot chain line represents the first pattern layer L11, the portion shown by the solid line represents the second pattern layer L12, and the portion shown by the broken line represents the third pattern layer L13. For example, the first pattern layer L11 is closer to the substrate than the second pattern layer L12, and the second pattern layer L12 is closer to the substrate than the third pattern layer L13, but the present disclosure is not limited thereto, and the manufacturing order of each pattern layer can be adjusted as needed so that the distance between each pattern layer and the substrate is different from the above description.

[0146] Figures 10A to 10E A schematic diagram of a display panel is provided for an embodiment of the present disclosure. As shown, a row of light emitting elements includes 48 second region light emitting elements, and all the second region light emitting elements are not shown in the single drawing for the sake of clarity. The marks of the circles and the numbers in the circles represent the second region light emitting elements, and the numbers in the circles represent the serial numbers of the second region light emitting elements. The marks of the brackets and the numbers in the brackets represent the second type of pixel circuits, and the numbers in the brackets represent the serial numbers of the second type of pixel circuits. As shown, Figures 10A to 10E As shown, the 48th column of second region light emitting elements is connected to the 25th column of second type of pixel circuits through conductive lines, and the connection of the remaining second region light emitting elements and the second type of pixel circuits can be referred to the above description. Figure 10A As shown, the 48th column of second region light emitting elements is connected to the 25th column of second type of pixel circuits through conductive lines, and the connection of the remaining second region light emitting elements and the second type of pixel circuits can be referred to the above description. Figures 10A to 10E For example, the fourth light emitting element 44 and the first light emitting element 41 emit green light, the second light emitting element 42 emits red light, and the third light emitting element 43 emits blue light. The second region light emitting elements arranged in the order of RGBG are shown in the drawing. Figure 10E G1 (which can refer to the first light emitting element 41) and G2 (which can refer to the fourth light emitting element 44) are shown, thereby forming the form of RG1BG2. In Figures 10A to 10E In the drawing, the conductive line connected to the first light emitting element 41 (G1 or G adjacent to B and located on the left side of B) is the first conductive line La, the conductive line connected to the second light emitting element 42 (R) is the second conductive line Lb, the conductive line connected to the third light emitting element 43 (B) is the third conductive line Lc, and the conductive line connected to the fourth light emitting element 44 (G2 or G adjacent to B and located on the right side of B) is the fourth conductive line Ld.

[0147] Figure 10A The conductive lines located in the first pattern layer L11 are shown, Figure 10A The entire conductive line and the first conductive part L01 for forming the entire conductive line are shown, and the first conductive part L01 is connected to the second type of pixel circuits in the 14th column and the 22nd column, respectively, Figure 10A Thirteen entire conductive lines and nine first conductive parts L01 are shown.

[0148] Figure 10BThe conductive lines in the second pattern layer L12 are shown, Figure 10B The whole conductive line and the second conductive part L02 for forming the whole conductive line are shown, and the second conductive part L02 is connected to the second area light emitting element in the first column respectively. Figure 10A The nine second area light emitting elements (the odd column light emitting elements in the 31st column to the 47th column light emitting elements) shown in the middle are connected, Figure 10B Thirteen whole conductive lines and nine second conductive parts L02 are shown.

[0149] Figure 10C The conductive lines in the third pattern layer L13 are shown, Figure 10C Thirteen whole conductive lines are shown, and the thirteen conductive lines are connected to the second area light emitting elements in the first column to the thirteenth column respectively.

[0150] Figure 10D The first conductive part L01 in Figure 10A and the second conductive part L02 in Figure 10B are connected by the via V0 penetrating the insulating layer to form a whole conductive line. As shown in Figure 10D , the third conductive line Lc can include the first conductive part L01 and the second conductive part L02 connected to each other, and the fourth conductive line Ld can include the first conductive part L01 and the second conductive part L02 connected to each other. As shown in Figure 10D , the first conductive part L01 extends along the second direction Y, and the second conductive part L02 extends along the first direction X, and in order to make the adjacent conductive lines have smaller capacitance difference, the ends of the plurality of second conductive parts L02 away from the second area light emitting element are flush. For example, as shown in Figure 10D , the plurality of first conductive parts L01 have different lengths along the second direction Y.

[0151] Referring to Figure 10E , a group of light emitting elements includes a plurality of subgroups of light emitting elements arranged in sequence along the first direction X, and the plurality of subgroups of light emitting elements are located on the same side of the symmetry axis of the second display area extending along the second direction Y. For example, referring to Figure 10E , a group of light emitting elements includes a first subgroup of light emitting elements GP01, a second subgroup of light emitting elements GP02, and a third subgroup of light emitting elements GP03. Of course, other groups of light emitting elements can also refer to the above-mentioned manner of being divided into a plurality of subgroups of light emitting elements.

[0152] For example, as shown in Figure 10EAs shown, the first sub-group of light emitting elements GP01 includes the first to thirteenth light emitting elements in the same group of light emitting elements (the same group of second region light emitting elements), the second sub-group of light emitting elements GP02 includes the fourteenth to twenty-sixth light emitting elements in the same group of light emitting elements (the same group of second region light emitting elements), and the third sub-group of light emitting elements GP03 includes the twenty-seventh to forty-eighth light emitting elements in the same group of light emitting elements (the same group of second region light emitting elements). Of course, in other embodiments, the same group of light emitting elements (the same group of second region light emitting elements) can also be provided with other numbers of light emitting elements, which can be set as needed, and reference is made to Figure 7C and Figure 10E Embodiments of the present disclosure are described by way of example with the same group of light emitting elements (the same group of second region light emitting elements) including forty-eight light emitting elements on the left side of the second symmetry axis X2.

[0153] For example, referring to Figure 10C and Figure 10E Each light emitting element in the first sub-group of light emitting elements GP01 is connected to the conductive wire L1 in the third pattern layer L13; referring to Figure 10B and Figure 10E The light emitting elements in the second sub-group of light emitting elements GP02 are connected to the conductive wire L1 in the second pattern layer L12; referring to Figure 10A , 10B and Figure 10E Some of the light emitting elements in the third sub-group of light emitting elements GP03 are connected through the conductive wire L1 in the first pattern layer L11, and the other light emitting elements in the third sub-group of light emitting elements GP03 are connected through the segmented conductive wire formed by the first conductive part L01 in the first pattern layer L11 and the second conductive part L02 in the second conductive layer L12.

[0154] Referring to Figure 10E A group of pixel circuits includes a plurality of sub-groups of pixel circuits arranged in sequence along the first direction X, and the plurality of sub-groups of pixel circuits are located on the same side of the symmetry axis extending along the second direction Y in the second display area. For example, referring to Figure 10E A group of pixel circuits includes the first sub-group of pixel circuits GR01 to the seventh sub-group of pixel circuits GR07, and the seventh sub-group of pixel circuits GR07 is closer to the second display area than the first sub-group of pixel circuits GR01. Of course, other groups of pixel circuits can also be divided into a plurality of sub-groups of pixel circuits in the manner described above.

[0155] Referring to Figure 10EThe conductive lines connected to the first sub-group of light emitting elements GP01 are located in the same layer, the conductive lines connected to the second sub-group of light emitting elements GP02 are located in the same layer, the conductive lines connected to the third sub-group of light emitting elements GP03 include conductive lines located in the same layer and also include segmented conductive lines, the segmented conductive lines include parts located in different layers.

[0156] Referring to Figure 10E The conductive lines connected to the first sub-group of light emitting elements GP01 are located in the third pattern layer L13, the conductive lines connected to the second sub-group of light emitting elements GP02 are located in the second pattern layer L12, and the conductive lines connected to the third sub-group of light emitting elements GP03 include conductive lines located in the first pattern layer L11 and also include segmented conductive lines, the segmented conductive lines include a first conductive part L01 located in the first pattern layer L11 and a second conductive part L02 located in the second pattern layer L12.

[0157] Referring to Figure 10E The second light emitting element 42 and the third light emitting element 43 in the first sub-group of light emitting elements GP01 are connected to the second sub-group of pixel circuits GR02, the second light emitting element 42 and the third light emitting element 43 in the second sub-group of light emitting elements GP02 are connected to the first sub-group of pixel circuits GR01, the second light emitting element 42 and the third light emitting element 43 in the third sub-group of light emitting elements GP03 close to the second sub-group of light emitting elements GP02 are connected to the fourth sub-group of pixel circuits GR04, the second light emitting element 42 and the third light emitting element 43 in the third sub-group of light emitting elements GP03 away from the second sub-group of light emitting elements GP02 are connected to the third sub-group of pixel circuits GR03, the first light emitting element 41 and the fourth light emitting element 44 in the first sub-group of light emitting elements GP01 are connected to the seventh sub-group of pixel circuits GR07, the first light emitting element 41 and the fourth light emitting element 44 in the second sub-group of light emitting elements GP02 are connected to the sixth sub-group of pixel circuits GR06, and the first light emitting element 41 and the fourth light emitting element 44 in the third sub-group of light emitting elements GP03 are connected to the fifth sub-group of pixel circuits GR05.

[0158] As Figure 10E shown, in order to reduce the occupied area of the conductive lines, the parts of the two fourth conductive lines Ld located in different layers and extending along the first direction X can at least partially overlap. That is, the parts of the two fourth conductive lines Ld located in different layers and extending along the first direction X at least partially overlap in the orthographic projection on the substrate.

[0159] For example, in order to reduce the occupied area of the conductive lines, the parts of the two first conductive lines La located in different layers and extending along the first direction X can at least partially overlap. That is, the parts of the two first conductive lines La located in different layers and extending along the first direction X at least partially overlap in the orthographic projection on the substrate.

[0160] As Figure 10E As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate.

[0161] As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate. Figure 10E As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate.

[0162] Figure 10E As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate.

[0163] As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate. Figure 10E Figure 10E As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate.

[0164] As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate. Figure 10E As shown, in order to reduce the footprint of the conductive lines, the portion of the fourth conductive line Ld extending along the first direction X can at least partially overlap with the portion of the first conductive line La extending along the first direction X which is located at a different layer. That is, the orthogonal projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate can at least partially overlap with the orthogonal projection of the portion of the first conductive line La extending along the first direction X on the substrate.

[0165] Figure 10E ​​​As shown, the portion of the conductive line L1 connected to the second sub-group of light emitting elements GP02 extending in the first direction does not overlap with the portion of other conductive lines extending in the first direction. Of course, the portion of the conductive line L1 connected to the second sub-group of light emitting elements GP02 extending in the first direction can overlap with the portion of other conductive lines extending in the second direction. For example, the conductive line L1 connected to the second sub-group of light emitting elements GP02 is located in the second pattern layer L12, and the conductive line L1 connected to the first sub-group of light emitting elements GP01 is located in the third pattern layer L13; the conductive line L1 connected to the second and third light emitting elements 42 and 43 of the third sub-group of light emitting elements GP03 close to the second sub-group of light emitting elements GP02 is located in the first pattern layer L11. As shown in FIG. 6, the portion of the conductive line L1 connected to the second sub-group of light emitting elements GP02 extending in the first direction and the overlapping portion of the two conductive lines extending in the first direction are arranged alternately. For example, the portion of the conductive line L1 connected to the second sub-group of pixel circuits GR02 extending in the first direction and the portion of the conductive line L1 connected to the fourth sub-group of pixel circuits GR04 extending in the first direction overlap with each other, and the portion of the conductive line L1 connected to the first sub-group of pixel circuits GR01 extending in the first direction does not overlap with the portion of the conductive line L1 connected to the second sub-group of pixel circuits GR02 extending in the first direction, and does not overlap with the portion of the conductive line L1 connected to the fourth sub-group of pixel circuits GR04 extending in the first direction. Figure 10E As shown, the portion of the conductive line L1 connected to the second sub-group of light emitting elements GP02 extending in the first direction and the overlapping portion of the two conductive lines extending in the first direction are arranged alternately. For example, the portion of the conductive line L1 connected to the second sub-group of pixel circuits GR02 extending in the first direction and the portion of the conductive line L1 connected to the fourth sub-group of pixel circuits GR04 extending in the first direction overlap with each other, and the portion of the conductive line L1 connected to the first sub-group of pixel circuits GR01 extending in the first direction does not overlap with the portion of the conductive line L1 connected to the second sub-group of pixel circuits GR02 extending in the first direction, and does not overlap with the portion of the conductive line L1 connected to the fourth sub-group of pixel circuits GR04 extending in the first direction. Figure 10E The conductive line includes a portion extending in the first direction X and portions extending in the second direction Y located on both sides of the portion extending in the first direction.

[0166] Referring to Figure 10C and Figure 10E The conductive line connected to the second sub-group of pixel circuits GR02 is located in the third pattern layer L13, and the conductive line connected to the seventh sub-group of pixel circuits GR07 is located in the second pattern layer L12.

[0167] Referring to Figure 10B , Figure 10D and Figure 10E The conductive line connected to the first sub-group of pixel circuits GR01 is located in the second pattern layer L12, and the conductive line connected to the sixth sub-group of pixel circuits GR06 is located in the second pattern layer L12. The second conductive portion L02 of the conductive line connected to the third sub-group of pixel circuits GR03 is located in the second pattern layer L12.

[0168] Referring to Figure 10A and Figure 10E The conductive line connected to the fifth sub-group of pixel circuits GR05 is located in the first pattern layer L11, and the conductive line connected to the fourth sub-group of pixel circuits GR04 is located in the first pattern layer L11. The first conductive portion L01 of the conductive line connected to the third sub-group of pixel circuits GR03 is located in the first pattern layer L11.

[0169] Referring to Figures 10A to 10E , the number of pixel circuits included in each sub-group pixel circuit is shown as the pixel circuits between the two vertical dotted lines, and it should be noted that the number of pixel circuits included in each sub-group pixel circuit can be set as needed by those skilled in the art. Figures 10A to 10E Take the case where the second display area includes 48 second-area light emitting elements as an example for description, but it can be set as needed.

[0170] Referring to Figures 10A to 10E , for the sake of clarity, the first-type pixel circuits between the two second-type pixel circuits are omitted in the figure, and the first-area light emitting elements connected to the first-type pixel circuits are also omitted.

[0171] Referring to Figure 8A , Figure 9A , Figure 9B , Figures 10A to 10E In a group of pixel units, or in a row of pixel units, the distance between the two adjacent second-type pixel circuits is greater than the distance between the two adjacent second-area light emitting elements.

[0172] Regarding Figures 10A to 10E the arrangement of the second-type pixel circuits in the display panel shown, reference can be made to the arrangement of the second-type pixel circuits and the related description shown in Figure 7A , Figure 8A , Figure 9A and Figure 9B , which will not be described here in detail. Figures 10A to 10E The arrangement of the pixel circuits connected to the first light emitting elements in the display panel shown is closer to the second display area than other second-type pixel circuits, which is conducive to reducing the capacitance of the conductive lines of the first light emitting elements, and is conducive to reducing the capacitance difference of the conductive lines of adjacent first light emitting elements, improving display defects, and achieving better display effects. Figures 10A to 10E The arrangement of the pixel circuits connected to the second light emitting elements in the display panel shown is also conducive to reducing the capacitance of the conductive lines of the second light emitting elements, and is conducive to reducing the capacitance difference of the conductive lines of adjacent second light emitting elements, improving display defects. Figures 10A to 10E The arrangement of the conductive lines connected to the third light emitting elements in the display panel shown is also conducive to reducing the capacitance of the conductive lines of the third light emitting elements, and is conducive to reducing the capacitance difference of the conductive lines of adjacent third light emitting elements, improving display defects. In the case where a large number of conductive lines need to be arranged, the overlapping manner of the portions of the conductive lines extending in the first direction shown in Figures 10A-10G can be used to reduce the occupied area of the conductive lines.

[0173] Figure 10FThis is a schematic diagram of connecting elements in a column of second-type pixel circuits in a display panel, provided as an embodiment of the present disclosure. (See diagram below.) Figure 10F As shown, the second type of pixel circuit in this column can be... Figure 10E The third subgroup pixel circuit GR03 shown is a column of second-type pixel circuits. (As shown...) Figure 10F As shown, the multiple connecting elements CE0 located in different groups of pixel circuits have the same size in the first direction X to facilitate fabrication. Figure 10F The image shows a pixel circuit in one column of eight pixel circuits GR arranged along the second direction Y, corresponding to eight connecting elements CE0. Figure 10F The explanation will take the second type of pixel circuit in column 22 as an example.

[0174] Figure 10G This is a schematic diagram of conductive lines connected to a column of second-region light-emitting elements in a display panel, as provided in an embodiment of this disclosure. Figure 10G As shown, the light-emitting element in the second region of this column can be... Figure 10E The third subgroup of light-emitting elements shown is a column of light-emitting elements in GP03. Figure 10F The following explanation uses the light-emitting element in the second region of column 31 as an example. Figure 10F As shown, in the same column of light-emitting elements, the connection position between the first electrode of the light-emitting element and the conductive line L1 gradually moves away from the second axis of symmetry X2 and then gradually moves closer to the second axis of symmetry X2.

[0175] Figure 10H This is a schematic diagram of connecting elements in a column of second-type pixel circuits in a display panel, provided as an embodiment of the present disclosure. (See diagram below.) Figure 10H As shown, the second type of pixel circuit in this column can be... Figure 10E The third subgroup pixel circuit GR03 shown is a column of second-type pixel circuits. (As shown...) Figure 10H As shown, the dimensions of multiple connecting elements CE0 located in different groups of pixel circuits gradually change in the first direction X, for example, gradually decreasing and then gradually increasing, in order to facilitate the arrangement of the conductive line L1 / the first conductive part L01 of the conductive line L1. Figure 10H The image shows a pixel circuit in one column of eight pixel circuits GR arranged along the second direction Y, corresponding to eight connecting elements CE0. Figure 10H The explanation will take the second type of pixel circuit in column 22 as an example.

[0176] pass Figure 10F and Figure 10G ,or Figure 10H and Figure 10G The setup shown allows the conductive lines corresponding to different groups of light-emitting elements to be located on the same layer. Through... Figures 10A-10G ,or Figure 10H andFigure 10G The person skilled in the art can know the arrangement of the conductive lines in the display panel shown, and can know the arrangement of each group of light emitting elements passing through the first display area and the second display area. For example, the above-described overlapping of the conductive lines is the overlapping of the portions of the conductive lines extending along the first direction X, that is, the conductive lines have a larger overlapping area or a larger overlapping length.

[0177] As shown in Figure 10E , the entire conductive line located in the second pattern layer L12 does not overlap with other conductive lines in a large area. For example, the portion of the entire conductive line located in the second pattern layer L12 extending along the first direction does not overlap with other conductive lines.

[0178] Referring to Figure 8A , Figure 8E , Figure 9A , Figure 9B and Figure 10E , the second display area includes a first edge R2a, a second edge R2b, a third edge R2c, and a fourth edge R2d. For example, the first edge R2a, the second edge R2b, the third edge R2c, and the fourth edge R2d are edges of a quadrilateral, respectively. A row of light emitting elements overlaps with the first edge R2a. A portion of the plurality of conductive lines passes from the second display area to the first display area through the second edge R2b intersecting the first edge R2a. For example, the conductive line formed in segments passes from the second display area to the first display area through the second edge R2b intersecting the first edge R2a.

[0179] For example, in an embodiment of the present disclosure, the conductive lines are not electrically connected between each other, and the two conductive lines overlapping with each other are located in different layers. An insulating layer is provided between the first pattern layer L11 and the second pattern layer L12, an insulating layer is provided between the third pattern layer L13 and the second pattern layer L12, and an insulating layer is provided between the first pattern layer L11 and the pixel circuit.

[0180] In an embodiment of the present disclosure, the row of light emitting elements or the row of light emitting elements can also be replaced by a group of light emitting elements or a group of pixel units. The row of pixel circuits or the row of pixel circuits can also be replaced by a group of pixel circuits or a group of pixel units.

[0181] Figure 11 A schematic diagram of a display panel is provided for an embodiment of the present disclosure. For example, as shown in Figure 11 , in the auxiliary area Ra, the orthogonal projection of the conductive line L1 on the substrate BS overlaps with the orthogonal projection of the pixel circuit 10 of the first type on the substrate BS. Figure 11 The arrangement of G priority is shown. The auxiliary area Ra can also be regarded as an area where the conductive line L1 is arranged.

[0182] In embodiments of the present disclosure, the first direction X and the second direction Y are both directions parallel to a main surface of the substrate, and the third direction Z is a direction perpendicular to the main surface of the substrate. For example, the main surface of the substrate refers to a surface used for manufacturing various elements.

[0183] Embodiments shown in various drawings of the present disclosure provide a display panel in which one conductive line L1 is connected to one pixel circuit of a second type and to one second-area light emitting element. In other embodiments, one conductive line can be connected to a plurality of second-area light emitting elements.

[0184] Figure 12A is a schematic diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. Figure 12B is a layout diagram of a pixel circuit in a display panel according to an embodiment of the present disclosure. Figure 12C Figure 12B is a cross-sectional view along line A-B of Figure 12D is a layout diagram of a pixel circuit in a display panel according to another embodiment of the present disclosure. Figure 12E is a layout diagram of a pixel circuit in a display panel according to another embodiment of the present disclosure.

[0185] Figure 12A The pixel circuit shown in FIG. 1 can be a pixel circuit of a Low Temperature Poly-silicon (LTPS) AMOLED commonly used in the related art.

[0186] Figure 12A shows a pixel circuit of a pixel unit of a display panel, as Figure 12A As shown in FIG. 1, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b. The pixel circuit 100a includes six switching transistors (T2-T7), a driving transistor T1, and a storage capacitor Cst. The six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7, respectively. The light emitting element 100b includes a first electrode E1 and a second electrode E2, and a light emitting functional layer between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode, and the second electrode E2 is a cathode. Generally, the threshold compensation transistor T3 and the first reset transistor T6 adopt a double-gate thin film transistor (TFT) to reduce leakage.

[0187] As shown in FIG. 2, the pixel unit 200 includes a pixel circuit 200a and a light emitting element 200b. The pixel circuit 200a includes six switching transistors (T2-T7), a driving transistor T1, and a storage capacitor Cst. The six switching transistors are a data writing transistor T2, a threshold compensation transistor T3, a first light emitting control transistor T4, a second light emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7, respectively. The light emitting element 200b includes a first electrode E1 and a second electrode E2, and a light emitting functional layer between the first electrode E1 and the second electrode E2. For example, the first electrode E1 is an anode, and the second electrode E2 is a cathode. Generally, the threshold compensation transistor T3 and the first reset transistor T6 adopt a double-gate thin film transistor (TFT) to reduce leakage. Figure 12A ​As shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light emission control signal line EML, an initialization signal line INT, and a reset control signal line RST. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, and the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, wherein the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light emission control signal line EML is configured to provide a light emission control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. For example, in a row of pixel units, the second reset control signal line RST2 can be connected to the gate line GT to be input to the scan signal SCAN. Alternatively, the second reset control signal line RST2 can also be input to the second reset control signal RESET2. The first initialization signal line INT1 is configured to provide a first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide a second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, the magnitude of which can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but is not limited thereto. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 can both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 are connected and both are configured to provide the initialization signal Vinit to the pixel unit 100; that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both called initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both being Vinit.

[0188] like Figure 12A As shown, the driving transistor T1 is electrically connected to the light-emitting element 100b, and outputs a driving current to drive the light-emitting element 100b to emit light under the control of signals such as the scan signal SCAN, the data signal DATA, the first voltage signal VDD, and the second voltage signal VSS.

[0189] For example, the light emitting element 100b includes an organic light emitting diode (OLED), and emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel circuit 100a. For example, one pixel includes a plurality of pixel units. One pixel can include a plurality of pixel units emitting different colors of light. For example, one pixel includes a pixel unit emitting red light, a pixel unit emitting green light, and a pixel unit emitting blue light, but is not limited thereto. The number of pixel units included in one pixel and the light emission of each pixel unit can be determined as needed.

[0190] For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2. Figure 12A For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2.

[0191] For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2. Figure 12A For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2.

[0192] For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2. Figure 12A For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2.

[0193] For example, as shown in FIG. 1, the gate T10 of the driving transistor T1 is connected to the gate line GT, the first electrode T11 of the driving transistor T1 is connected to the first electrode T21 of the data writing transistor T2, and the second electrode T12 of the driving transistor T1 is connected to the second electrode T22 of the data writing transistor T2. Figure 12AAs shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1. The second reset transistor T7 is connected to the first terminal E1 of the light-emitting element 100b and is configured to reset the first terminal E1 of the light-emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first terminal E1 of the light-emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected so that they are input with the same initialization signal, but this is not a limitation. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 may also be isolated from each other and configured to input signals separately.

[0194] For example, such as Figure 12A As shown, the first terminal T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, and the second terminal T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1. The first terminal T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second terminal T72 of the second reset transistor T7 is connected to the first terminal E1 of the light-emitting element 100b. For example, as... Figure 12A As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0195] like Figure 12A As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, the first terminal Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and the second terminal Cb of the storage capacitor Cst is connected to the first power line PL1.

[0196] For example, such as Figure 12A As shown, the display panel also includes a second power line PL2, which is connected to the second electrode E2 of the light-emitting element 100b.

[0197] Figure 12A The diagram illustrates a first node N1, a second node N2, a third node N3, and a fourth node N4. For example, in some embodiments, reference is made to... Figure 12B A capacitor is formed between the first node N1 and the conductive line L1, and a capacitor is formed between the conductive line L1 and the fourth node N4. The conductive line L1 is coupled to the first node N1 and the fourth node N4 respectively, which causes brightness differences and creates display defects such as mura, affecting display quality.

[0198] likeFigure 12B As shown, the pixel circuit includes a driving transistor T1, and the driving transistor includes a gate T10. (Reference) Figure 12B and 12C The storage capacitor Cst has a second electrode Cb with an opening OPN1. One end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connecting electrode CE1 can also be called the first gate signal line SL1. Figure 12B As shown, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0199] like Figure 12B As shown, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute the gate signal section PT1. The potentials on the gate signal section PT1 are the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal section PT1. For example, the second gate signal line SL2 is the second terminal T62 of the first reset transistor T6.

[0200] refer to Figure 12B and 12C To stabilize the potential on the gate signal section PT1, the display panel provided in the embodiments of this disclosure provides a shielding electrode SE and a constant voltage line L0, wherein the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shielding electrode SE is connected to the constant voltage line L0, thereby stabilizing the voltage on the shielding electrode SE and providing a shielding effect to prevent the conductive line L1 from affecting the potential on the gate signal section PT1. The orthographic projection of the first gate signal line SL1 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0201] refer to Figures 12D-12E , Figure 12B In order to make the shielding electrode play a better shielding role and increase the shielding amount, the orthogonal projection of the first gate signal line SL1 on the substrate BS falls completely within the orthogonal projection of the shielding electrode SE on the substrate BS.

[0202] For example, to mitigate mura and improve display quality, the distance between the orthographic projection of the first gate signal line SL1 onto the substrate BS and the boundary of the orthographic projection of the shielding electrode SE onto the substrate BS is greater than or equal to 1.75 μm. Because the area occupied by a pixel unit is limited, the distance of the shielding electrode SE extending beyond the first gate signal line SL1 can be limited. For example, in some embodiments, to achieve better shielding, the distance between the boundary of the orthographic projection of the first gate signal line SL1 onto the substrate BS and the boundary of the orthographic projection of the shielding electrode SE onto the substrate BS is greater than or equal to 2.33 μm.

[0203] As shown in Figure 12B , the display panel further comprises a block BK connected with the first power line PL1, the threshold compensation transistor T3 comprises a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected through a conductive connection part CP; the orthographic projection of the block BK on the substrate BS at least partially overlaps the orthographic projection of the conductive connection part CP of the threshold compensation transistor T3 on the substrate BS. As shown in Figure 12B , the block BK of the adjacent column pixel unit is used to shield the conductive connection part CP of the threshold compensation transistor T3 of the column pixel unit.

[0204] For example, as shown in Figure 12B , in the case that the display panel comprises a second gate signal line SL2, the second gate signal line SL2 is connected with the first gate signal line SL1, the orthographic projection of the second gate signal line SL2 on the substrate BS falls within the orthographic projection of the block BK on the substrate BS. Further for example, the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance by which the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75 μm. For example, the distance by which the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33 μm. Of course, in other embodiments, a shielding electrode SE can also be used instead of the block BK, or the orthographic projection of the second gate signal line SL2 on the substrate BS falls within both the orthographic projection of the block BK on the substrate BS and the orthographic projection of the shielding electrode SE on the substrate BS.

[0205] For example, the material of the first gate signal line SL1 and the material of the second gate signal line SL2 are different. For example, the material of the first gate signal line SL1 comprises metal, and the material of the second gate signal line SL2 comprises conductive material formed by semiconductor material being conductive.

[0206] For example, as shown in Figure 12BAs shown, in order to save wiring, the first power supply line PL1 is used as the constant voltage line L0. In other embodiments, in order to save wiring, the first initialization signal line INL1 or the second initialization signal line INL2 can also be used as the constant voltage line. The example of the constant voltage line L0 is not limited to the first power supply line PL1, the first initialization signal line INL1, and the second initialization signal line INL2, and any signal line that provides a constant voltage in the pixel circuit can be used as the constant voltage line L0. Embodiments of the present disclosure are described by way of example using the first power supply line PL1 as the constant voltage line L0, and in cases where a signal line other than the first power supply line PL1 that provides a constant voltage is used as the constant voltage line L0, the shape of the shield electrode SE can be adjusted so that it is connected to the signal line that provides a constant voltage.

[0207] For example, the orthogonal projection of the conductive line L1 on the substrate BS partially overlaps the orthogonal projection of the pixel circuit (the first type of pixel circuit 10) of the first pixel unit 101 on the substrate BS. For example, the shield electrode SE is located between the conductive line L1 and the first gate signal line SL1. In embodiments of the present disclosure, the shield electrode SE is formed after the pixel circuit is formed, the conductive line L1 is then formed, and the light emitting element is then formed, so that the shield electrode SE is located between the conductive line L1 and the first gate signal line SL1, and the shield electrode SE is located between the conductive line L1 and the gate T10 of the drive transistor.

[0208] For example, the conductive line L1 is provided in the auxiliary area, and the conductive line L1 is not provided in the area of the first display area other than the auxiliary area, so that the orthogonal projection of the pixel circuit (the first type of pixel circuit) in the area of the first display area other than the auxiliary area on the substrate BS does not overlap the orthogonal projection of the conductive line L1 on the substrate BS.

[0209] For example, the orthogonal projection of the conductive line L1 on the substrate BS partially overlaps the orthogonal projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101.

[0210] Referring to 12C and Figure 12BA buffer layer BL is disposed on the substrate BS, an isolation layer BR is disposed on the buffer layer BL, an active layer LY0 is disposed on the isolation layer BR, a first insulating layer ISL1 is disposed on the active layer LY0, a first conductive layer LY1 is disposed on the first insulating layer ISL1, a second insulating layer ISL2 is disposed on the first conductive layer LY1, a second conductive layer LY2 is disposed on the second insulating layer ISL2, a third insulating layer ISL3 is disposed on the second conductive layer LY2, and a third conductive layer LY3 is disposed on the third insulating layer ISL3. The third conductive layer LY3 includes a connection electrode CE01, which passes through the first insulating layer ISL1. The via H3 of the second insulating layer ISL2 and the third insulating layer ISL3 is connected to the second electrode T52 of the second light-emitting control transistor T5. A fourth insulating layer and a fifth insulating layer are disposed on the third conductive layer LY3. A fourth conductive layer LY4 is disposed on the fourth and fifth insulating layers. The fourth conductive layer LY4 includes a connecting electrode CE02, which is connected to a connecting electrode CE01 through a via H22 penetrating the fourth and fifth insulating layers. A sixth insulating layer is disposed on the fourth conductive layer LY4. The light-emitting element 100b (second region light-emitting element 30) is connected to the connecting electrode CE02 through a via penetrating the sixth insulating layer. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the connecting element CE0 includes connecting electrodes CE01 and CE02.

[0211] like Figure 12B As shown, one end of the connecting electrode CE1 is connected to the gate T10 of the driving transistor T1 through via H1, and the other end of the connecting electrode CE1 is connected to the second terminal T62 of the first reset transistor T6 through via H2. One end of the connecting electrode CE2 is connected to the first initialization signal line INL1 through via H4, and the other end of the connecting electrode CE2 is connected to the first terminal T61 of the first reset transistor T6 through via H5. One end of the connecting electrode CE3 is connected to the second initialization signal line INL2 through via H6, and the other end of the connecting electrode CE3 is connected to the first terminal T71 of the second reset transistor T7 through via H7. The first power line PL1 is connected to the first terminal T41 of the first light-emitting control transistor T4 through via H8. The first power line PL1 is connected to the second terminal Cb of the storage capacitor Cst through via H9. The first power line PL1 is connected to the stop block BK through via Hk. The data line DT is connected to the first terminal T21 of the data writing transistor T2 through via H0.

[0212] For example, in the manufacturing process of the display panel, a self-alignment process is used to conductive process the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is heavily doped by ion implantation, so that the portions of the semiconductor pattern layer not covered by the first conductive layer LY1 are conductive, forming the source region (first electrode T11) and the drain region (second electrode T12) of the driving transistor T1, the source region (first electrode T21) and the drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and the drain region (second electrode T32) of the threshold compensation transistor T3, the source region (first electrode T41) and the drain region (second electrode T42) of the first light-emitting control transistor T4, the source region (first electrode T51) and the drain region (second electrode T52) of the second light-emitting control transistor T5, the source region (first electrode T61) and the drain region (second electrode T62) of the first reset transistor T6, and the source region (first electrode T71) and the drain region (second electrode T72) of the second reset transistor T7. The portions of the semiconductor pattern layer covered by the first conductive layer LY1 retain the semiconductor properties, forming the channel region of the driving transistor T1, the channel region of the data writing transistor T2, the channel region of the threshold compensation transistor T3, the channel region of the first light-emitting control transistor T4, the channel region of the second light-emitting control transistor T5, the channel region of the first reset transistor T6, and the channel region of the second reset transistor T7. For example, as shown in FIG. 8, the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are integrally formed; the first electrode T51 of the second light-emitting control transistor T5, the second electrode T12 of the driving transistor T1, and the first electrode T31 of the threshold compensation transistor T3 are integrally formed; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2, and the second electrode T42 of the first light-emitting control transistor T4 are integrally formed; and the second electrode T32 of the threshold compensation transistor T3 and the second electrode T62 of the first reset transistor T6 are integrally formed. In some embodiments, as shown in FIG. 9, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be integrally formed. Figure 12B Figure 12D

[0213] ​​For example, the channel region of the transistor employed in the embodiments of the present disclosure can be single crystal silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon), or metal oxide semiconductor material (e.g., IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, i.e., the channel material of the transistors is metal oxide semiconductor material (e.g., IGZO, AZO, etc.), and the metal oxide semiconductor thin film transistors have lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0214] For example, the transistor employed in the embodiments of the present disclosure can include various structures, such as top gate type, bottom gate type, or double gate structure. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are double gate type thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0215] For example, the display panel further includes a pixel definition layer and a spacer. The pixel definition layer has an opening, and the opening of the pixel definition layer is configured to define the light emitting area (light emitting region, effective light emitting area) of the pixel unit. The spacer is configured to support the fine metal mask when the light emitting functional layer is formed.

[0216] For example, the opening of the pixel definition layer is the light emitting region of the pixel unit. The light emitting functional layer is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting functional layer. For example, an encapsulation layer is provided on the light emitting element 100b. The encapsulation layer includes a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. For example, the first encapsulation layer and the third encapsulation layer are inorganic material layers, and the second encapsulation layer is an organic material layer. For example, the first electrode E1 is the anode of the light emitting element 100b, and the second electrode E2 is the cathode of the light emitting element 100b, but not limited thereto.

[0217] Figure 12D A layout diagram of the first type of pixel circuit or the second type of pixel circuit in the display panel provided by an embodiment of the present disclosure is provided. For example, as shown in FIG. 1, the normal projection of the gate T10 of the driving transistor T1 on the substrate BS falls within the normal projection of the shielding electrode SE on the substrate BS. Figure 12D

[0218] For example, as shown in FIG. 1, the normal projection of the gate T10 of the driving transistor T1 on the substrate BS falls within the normal projection of the shielding electrode SE on the substrate BS. Figure 12D ​As shown, when the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS also falls within the orthographic projection of the shielding electrode SE on the substrate BS. Further, for example, the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance by which the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75 μm. For example, the distance by which the boundary of the orthographic projection of the shielding electrode SE on the substrate BS extends beyond the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33 μm.

[0219] For example, such as Figure 12D As shown, the orthographic projections of the gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 on the substrate BS all fall within the orthographic projection of the shielding electrode SE on the substrate BS.

[0220] For example, such as Figure 12D As shown, the orthographic projection of the shielding electrode SE on the substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate BS, and the orthographic projection of the block BK on the substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the substrate BS. Therefore, in Figure 12D In the display panel shown, the shielding electrode SE and the stop block BK form a double layer of shielding for the second gate signal line SL2.

[0221] For example, such as Figure 12E As shown, the orthographic projection of the shielding electrode SE on the substrate BS overlaps with the orthographic projection of the block BK on the substrate BS.

[0222] Of course, in other embodiments, the stop block BK may not be provided, or the orthographic projection of the stop block BK on the substrate BS may not overlap with the orthographic projection of the second gate signal line SL2 on the substrate BS.

[0223] Figure 12E This is a layout diagram of a first type or a second type of pixel circuit in a display panel provided according to an embodiment of this disclosure. For example... Figure 12E As shown, the fourth conductive layer LY4 also includes a third power line PL3, which is integrally formed with the shielding electrode SE. The third power line PL3 is connected to the first power line PL1 through a via H21, forming a parallel structure to reduce resistance. The third power line PL3 extends along the second direction Y. Figure 12BAs shown, the dimension of the third power line PL3 in the second direction Y is greater than the dimension of the shield electrode SE in the second direction Y.

[0224] As shown, for example, the front projection of the block BK on the substrate Figure 12E , Figure 12B board BS partially overlaps the front projection of the second gate signal line SL2 on the substrate board BS, and the front projection of the shield electrode SE on the substrate board BS partially overlaps the front projection of the first gate signal line SL1 on the substrate board BS, so that the block BK and the shield electrode SE jointly function as a shield for the gate signal portion PT1. Of course, in other embodiments, the block BK can not be provided, or the front projection of the block BK on the substrate board BS can not overlap the front projection of the second gate signal line SL2 on the substrate board BS.

[0225] As shown, for example, the front projection of the block BK on the substrate Figure 12E , Figure 12B board BS partially overlaps the front projection of the second gate signal line SL2 on the substrate board BS, and the front projection of the shield electrode SE on the substrate board BS partially overlaps the front projection of the first gate signal line SL1 on the substrate board BS, so that the block BK and the shield electrode SE jointly function as a shield for the gate signal portion PT1. Of course, in other embodiments, the block BK can not be provided, or the front projection of the block BK on the substrate board BS can not overlap the front projection of the second gate signal line SL2 on the substrate board BS.

[0226] As shown, for example, the front projection of the block BK on the substrate Figure 12D , Figure 12E , and Figure 12E the channel of each transistor and the first and second poles located on both sides of the channel are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate of the drive transistor T10 (the first pole Ca of the storage capacitor Cst), the light-emitting control signal line EML, and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second pole Cb of the storage capacitor Cst, and the second initialization signal line INL2 are located in the second conductive layer LY2; the data line DT, the first power line PL1, the connection electrode CE1, the connection electrode CE2, the connection electrode CE3, and the connection electrode CE01 are located in the third conductive layer LY3; and the shield electrode SE is located in the fourth conductive layer LY4. Figure 12B As shown, the shield electrode SE and the third power line PL3 are located in the fourth conductive layer LY4.

[0227] As shown, for example, the front projection of the block BK on the substrate Figure 12D , Figure 12E , and Figure 12B the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light-emitting control signal line EML, the second initialization signal line INL2, and the second reset control signal line RST2 all extend along the first direction X, as shown, for example, Figure 12D , Figure 12E , and Figure 13AAs shown, the data line DT and the first power line PL1 both extend along the second direction Y.

[0228] In the embodiments of the present disclosure, the orthogonal projection of the element A on the substrate BS falling within the orthogonal projection of the element B on the substrate BS means that the orthogonal projection of the element A on the substrate BS completely falls within the orthogonal projection of the element B on the substrate BS, i.e., the orthogonal projection of the element A on the substrate BS covers the orthogonal projection of the element B on the substrate BS, and the area of the orthogonal projection of the element A on the substrate BS is less than or equal to the area of the orthogonal projection of the element B on the substrate BS.

[0229] For example, in some embodiments of the present disclosure, each pixel circuit 100a is provided with any shielding electrode SE as described above. That is, whether the pixel circuit 10 of the first type of the first pixel unit 101 or the pixel circuit 20 of the second type of the second pixel unit 102 is provided with any shielding electrode SE as described above. However, it is not limited thereto, for example, in some embodiments, no shielding electrode SE is provided in each pixel circuit 100a.

[0230] For example, the transistors in the pixel circuit of the embodiments of the present disclosure are all thin film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed by using metal materials such as nickel and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed by using materials such as titanium and aluminum, but are not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are respectively structures formed by three sub-layers of Ti / AL / Ti, but are not limited thereto. For example, the substrate can be a glass substrate or a polyimide substrate, but is not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer, and the sixth insulating layer are all made of insulating materials. The materials of the first electrode E1 and the second electrode E2 of the light emitting element can be selected as needed. In some embodiments, the first electrode E1 can be at least one of transparent conductive metal oxide and silver, but is not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 can be a structure provided by stacking three sub-layers of ITO-Ag-ITO. In some embodiments, the second electrode E2 can be a metal with a low work function, and can be at least one of magnesium and silver, but is not limited thereto.

[0231] For example, with reference to the layout diagram and the cross-sectional view of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure can be made by the following method.

[0232] (1) A buffer layer BL and an isolation layer BR are formed on a substrate BS.

[0233] (2) A semiconductor thin film is formed on the isolation layer BR.

[0234] (3) The semiconductor thin film is patterned to form a semiconductor pattern layer.

[0235] (4) A first insulating thin film is formed on the semiconductor pattern layer.

[0236] (5) A first conductive thin film is formed on the first insulating thin film, and the first conductive thin film is patterned to form a first conductive layer LY1.

[0237] (6) The semiconductor pattern layer is doped using the first conductive layer LY1 as a mask to form an active layer LY0.

[0238] (7) A second insulating thin film is formed on the first conductive layer LY1.

[0239] (8) A second conductive thin film is formed on the second insulating layer ISL2, and the second conductive thin film is patterned to form a second conductive layer LY2.

[0240] (9) A third insulating thin film is formed on the second conductive layer LY2.

[0241] (10) At least one of the first, second, and third insulating thin films is patterned to form a via hole, and a first, second, and third insulating layer ISL1, ISL2, and ISL3 are formed.

[0242] (11) A third conductive thin film is formed, and the third conductive thin film is patterned to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to an element below it through a via hole.

[0243] (12) A fourth and fifth insulating thin film are formed, and the fourth and fifth insulating thin films are patterned to form a via hole, and a fourth and fifth insulating layer are formed.

[0244] (13) A fourth conductive thin film is formed, and the fourth conductive thin film is patterned to form a fourth conductive layer LY4.

[0245] (14) At least one insulating layer is formed, and at least one transparent conductive layer is formed, the transparent conductive layer including a conductive line L1.

[0246] (15) A first electrode E1 of a light emitting element is formed.

[0247] (16) A pixel definition layer and a spacer layer PS are formed.

[0248] (17) Form a light-emitting functional layer.

[0249] (18) Forms the second electrode E2 of the light-emitting element.

[0250] (19) Form an encapsulation layer.

[0251] Of course, in the display panel provided in the embodiments of this disclosure, the shielding electrode SE may not be provided.

[0252] At least one embodiment of this disclosure provides a display device including any of the above-described display panels.

[0253] Figure 13B and Figure 13A This is a schematic diagram of a display device provided according to an embodiment of the present disclosure. Figure 13B and Figure 13B As shown, the sensor SS is located on one side of the display panel DS and within the second display area R2. Ambient light can be transmitted through the second display area R2 and sensed by the sensor SS. Figure 14 As shown, the side of the display panel without the sensor SS is the display side, which can display images. For example, the sensor includes a photosensor located on one side of the display panel.

[0254] For example, the second display area R2 can be rectangular, and the area of ​​the sensor SS projected onto the substrate BS can be less than or equal to the area of ​​the inscribed circle of the second display area R2. That is, the size of the area where the sensor SS is located can be less than or equal to the size of the inscribed circle of the second display area R2. For example, if the size of the area where the sensor SS is located is equal to the size of the inscribed circle of the second display area R2, then the shape of the area where the sensor SS is located can be circular, and correspondingly, the area where the sensor SS is located can also be called a light-transmitting hole. Of course, in some embodiments, the second display area R2 can also be other shapes besides rectangles, such as circles or ellipses.

[0255] For example, the display device is a full-screen display device with an under-display camera. For example, the display device includes OLED or products that include OLED. For example, the display device includes any product or component with display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, which contains the above-mentioned display panel.

[0256] Figure 12A for Figure 14 The timing diagram of the pixel circuit shown is as follows. Figure 12AAs shown, for a display time frame, the pixel unit driving method includes a first reset phase t1, data writing and threshold compensation, a second reset phase t2, and a light emission phase t3. When the reset control signal RESET is low, the gate of the driving transistor T1 is reset; when the scan signal SCAN is low, the first electrode E1 (e.g., the anode) of the light-emitting element 100b is reset. For example, as... Figure 14 As shown, when the scan signal SCAN is low, the data voltage VDATA is written, and the threshold voltage Vth of the driving transistor T1 is acquired. The data voltage VDADA, containing data information from the data line, is stored in the capacitor Cst. When the light emission control signal line EML is low, the light-emitting element 100b emits light, and the voltage of the first node N1 (gate point) is maintained (the light emission stability of the light-emitting element 100b) by the storage capacitor Cst. During the driving process of the pixel circuit 10, in the light emission stage, the storage capacitor is used to maintain the voltage signal, keeping the potential at its signal holding terminal constant. This forms a voltage between the gate and source of the driving transistor, thereby controlling the driving transistor to generate a driving current, which in turn drives the light-emitting element 100b to emit light.

[0257] like Figure 14 As shown, during the reset phase t1, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the on voltage, and the scan signal SCAN is set to the off voltage.

[0258] like Figure 14 As shown, during the data writing and threshold compensation stage and the second reset stage t2, the light emission control signal EM is set to the off voltage, the reset control signal RESET is set to the off voltage, and the scan signal SCAN is set to the on voltage.

[0259] like Figure 14 As shown, during the light emission stage t3, the light emission control signal EM is set to the turn-on voltage, the reset control signal RESET is set to the turn-off voltage, and the scan signal SCAN is set to the turn-off voltage.

[0260] like Figure 14 As shown, the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0261] For example, the turn-on voltage in the embodiments of the present disclosure refers to a voltage capable of turning on the first electrode and the second electrode of the corresponding transistor, and the turn-off voltage refers to a voltage capable of turning off the first electrode and the second electrode of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (for example, 5 V), and the turn-off voltage is a low voltage (for example, 0 V). Figure 12A The driving waveforms shown are all described by taking a P-type transistor as an example. For example, the turn-on voltage is a low voltage (for example, 0 V), and the turn-off voltage is a high voltage (for example, 5 V), but the present disclosure is not limited thereto.

[0262] Please refer to Figure 14 and Figure 12A In the first reset stage t1, the light-emitting control signal EM is the turn-off voltage, the reset control signal RESET is the turn-on voltage, and the scan signal SCAN is the turn-off voltage. At this time, the first reset transistor T6 is in a turned-on state, and the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light-emitting control transistor T4, and the second light-emitting control transistor T5 are in a turned-off state. The first reset transistor T6 transmits the first initialization signal (the initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resets the driving transistor T1, and eliminates the data stored during the last (previous frame) light-emitting.

[0263] In the data writing and threshold compensation and second reset phase t2, the emission control signal EM is the off voltage, the reset control signal RESET is the off voltage, and the scan signal SCAN is the on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in the on state, and the second reset transistor T7 is in the on state, and the second reset transistor T7 transmits the second initialization signal (the initialization voltage Vinit) Vinit2 to the first electrode E1 of the light emitting element 100b to reset the light emitting element 100b. The first light emitting control transistor T4, the second light emitting control transistor T5, and the first reset transistor T6 are in the off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first electrode of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first electrode of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 connects the driving transistor T1 into a diode structure, so that the gate of the driving transistor T1 can be charged. After the charging is completed, the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and compensates the threshold voltage of the gate voltage of the driving transistor T1 according to the scan signal SCAN. In this phase, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.

[0264] In the light emitting phase t3, the emission control signal EM is the on voltage, the reset control signal RESET is the off voltage, and the scan signal SCAN is the off voltage. The first light emitting control transistor T4 and the second light emitting control transistor T5 are in the on state, and the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6, and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first light emitting control transistor T4, the gate voltage of the driving transistor T1 remains VDATA+Vth, the light emitting current I flows into the light emitting element 100b through the first light emitting control transistor T4, the driving transistor T1, and the second light emitting control transistor T5, and the light emitting element 100b emits light. That is, the first light emitting control transistor T4 and the second light emitting control transistor T5 receive the emission control signal EM and control the light emitting element 100b to emit light according to the emission control signal EM. The light emitting current I satisfies the following saturation current formula:

[0265] K(Vgs-Vth) 2 = K(VDATA+Vth-ELVDD-Vth) 2 = K(VDATA-ELVDD) 2

[0266] wherein, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source of the driving transistor T1 (i.e. the first electrode of the driving transistor T1 in this embodiment).

[0267] It can be seen from the above formula that the current flowing through the light emitting element 100b is independent of the threshold voltage of the driving transistor T1. Therefore, the threshold voltage of the driving transistor T1 is compensated very well by the present pixel circuit.

[0268] For example, the proportion of the duration of the light emitting stage t3 to the frame display period can be adjusted. In this way, the light emitting brightness can be controlled by adjusting the proportion of the duration of the light emitting stage t3 to the frame display period. For example, the proportion of the duration of the light emitting stage t3 to the frame display period can be adjusted by controlling the scan driving circuit in the display panel or by an additional driving circuit.

[0269] For example, the embodiments of the present disclosure are not limited to Figure 15 The specific pixel circuit shown can be replaced by other pixel circuits that can compensate for the driving transistor. Other arrangements that can be easily thought of by those skilled in the art without creative effort based on the description and teaching of the implementation in the present disclosure are within the scope of protection of the present disclosure.

[0270] The above is described by taking the 7T1C pixel circuit as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel can also be a structure including other number of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, which are not limited by the embodiments of the present disclosure. Of course, the display panel can also include a pixel circuit with less than 7 transistors.

[0271] Generally, for example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are both constant voltages of -3V. In the display panel provided in some embodiments of the present disclosure, the second initialization signal Vinit2 can be a constant voltage greater than or equal to -2V, i.e. the second initialization signal Vinit2 is raised from -3V to -2V or above, thereby increasing the light emitting time of the first light emitting element and improving the display defects. In the case where the display panel has a fourth light emitting element, the light emitting time of the first light emitting element and the fourth light emitting element is increased. For example, the light emitting time of the first light emitting element and the fourth light emitting element can be increased by 12%.

[0272] In the related art, the size (pitch) of the pixel circuit (including the first type of pixel circuit 10 and the second type of pixel circuit 20) and the first area light emitting element 30 are the same. For example, the general width is about 30 microns (pm) to 32 pm, and the length is about 60 pm to 65 pm. In the embodiments of the present disclosure, in order to be able to provide sufficient space for the second type of pixel circuit 20 on the premise that the number of pixels in the first display area R1 is not reduced, the width of the pixel circuit in the first direction X (for example, the direction in which the gate line extends, which can also be referred to as the horizontal direction) can be compressed, so that the width of the pixel circuit in the first direction X is smaller than the width of the first area light emitting element 30; or the first area light emitting element 30 in the first direction X can be extended, so that the width of the first area light emitting element 30 in the first direction X is larger than the width of the first area light emitting element 30. In this way, under the premise that the size of the substrate BS is the same, more areas can be obtained in the first display area R1, and accordingly, the second type of pixel circuit 20 for driving the second light emitting element 40 located in the second display area R2 can be arranged in the more areas.

[0273] For example, the width of each pixel circuit and the width of the first area light emitting element 30 can differ by about 4 pm. Taking the example of compressing the pixel circuit and the width difference being 4 pm, Figure 15 The structure layout of the pixel circuit before and after compression is shown. Referring to ​As can be seen, the pixel circuit can include a driving structure and a connection element CE0 for connecting to the first electrode (anode) of the light emitting element, and the size of the connection element CE0 can represent the size of the pixel circuit. The size of the pixel circuit and the light emitting element before compression is 1-100 μm in width and 2-100 μm in height. The size of the light emitting element after compression can be the same as that before compression. For example, the size of the second region light emitting element 40 can be equal to or smaller than the size of the first region light emitting element 20. The height of the pixel circuit after compression is the same, but the width is narrowed by 1-20 μm. In this way, every several columns of compressed pixel circuits will have one or more columns of compressed pixel circuits added, and the entire screen is designed in this way to achieve full-screen compression. Among them, these additional columns can be selected to connect the second region light emitting element 40 in the second display area R2 to control the second region light emitting element 40 to emit light. In some embodiments, the additional column of pixel circuits close to the periphery of the second display area R2 is selected as the second type of pixel circuit 20 to connect the second region light emitting element 40. In this way, normal display can be achieved without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to achieve normal display. The effect achieved by compressing the size of the pixel circuit is that the number of light emitting elements (including the first region light emitting element 30 and the second light emitting element 40) remains unchanged, and thus, compared with before compression, there is no obvious difference in display effect, and the display effect of the display panel is better.

[0274] In embodiments of the present disclosure, elements located in the same layer can be formed by the same film layer through the same patterning process. For example, elements located in the same layer can be located on the surface of the same element away from the substrate.

[0275] It should be noted that, for the sake of clarity, the thickness of a layer or region is exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0276] In embodiments of the present disclosure, the patterning or patterning process can only include a photolithography process, or include a photolithography process and an etching step, or can include printing, inkjet and other processes for forming a predetermined pattern. The photolithography process refers to a process including film forming, exposure, development and the like, and a pattern is formed using photoresist, mask, exposure machine and the like. The corresponding patterning process can be selected according to the structure formed in embodiments of the present disclosure.

[0277] The features in the same embodiment and different embodiments of the present disclosure can be combined with each other without conflict.

[0278] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: a substrate, having a first display area and a second display area, the first display area being located at least one side of the second display area; a plurality of light emitting elements, located in the first display area and the second display area, the plurality of light emitting elements comprising a plurality of groups of light emitting elements, light emitting elements in each group of the plurality of groups of light emitting elements being arranged along a first direction, the plurality of groups of light emitting elements being arranged along a second direction, at least one group of the plurality of groups of light emitting elements comprising a plurality of first area light emitting elements and a plurality of second area light emitting elements, the plurality of first area light emitting elements being located in the first display area, the plurality of second area light emitting elements being located in the second display area; a plurality of pixel circuits, located in the first display area, the plurality of pixel circuits comprising a plurality of groups of pixel circuits, pixel circuits in each group of the plurality of groups of pixel circuits being arranged along the first direction, the plurality of groups of pixel circuits being arranged along the second direction, at least one group of the plurality of groups of pixel circuits comprising a plurality of first type pixel circuits and a plurality of second type pixel circuits, the plurality of second type pixel circuits being distributed between the plurality of first type pixel circuits, wherein at least one first type pixel circuit of the plurality of first type pixel circuits is connected with at least one first area light emitting element of the plurality of first area light emitting elements, and a projection of the at least one first type pixel circuit on the substrate at least partially overlaps with a projection of the at least one first area light emitting element on the substrate; at least one second type pixel circuit of the plurality of second type pixel circuits is connected with at least one second area light emitting element of the plurality of second area light emitting elements through a conductive wire; the plurality of second area light emitting elements comprises a plurality of first light emitting elements and a plurality of second light emitting elements, the first light emitting elements being configured to emit light of a first color, the second light emitting elements being configured to emit light of a second color, the plurality of second type pixel circuits comprises a plurality of first pixel circuits and a plurality of second pixel circuits, the conductive wire comprises a plurality of first conductive wires and a plurality of second conductive wires, the plurality of first light emitting elements being connected with the plurality of first pixel circuits through the plurality of first conductive wires, the plurality of second light emitting elements being connected with the plurality of second pixel circuits through the plurality of second conductive wires, in the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first pixel circuits connected with the plurality of first light emitting elements is closer to the second display area than each of the plurality of second pixel circuits connected with the plurality of second light emitting elements, each first area light emitting element of the plurality of first area light emitting elements has a light emitting area greater than a light emitting area of at least one second area light emitting element of the plurality of second area light emitting elements.

2. The display panel of claim 1, wherein, in the at least one group of light emitting elements and the at least one group of pixel circuits, no other second type pixel circuit is arranged between two first pixel circuits connected with two adjacent first conductive wires.

3. The display panel of claim 1, wherein, One end of the conductive line is connected to the second area light emitting element, and the other end of the conductive line is connected to the second type of pixel circuit through a connection element.

4. The display panel of claim 1, wherein, In the at least one group of light emitting elements and the at least one group of pixel circuits, at least one of the plurality of first type of pixel circuits is arranged between two adjacent second type of pixel circuits.

5. The display panel of claim 4, wherein, In the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of first type of pixel circuits are arranged in a staggered manner, wherein the plurality of first type of pixel circuits connected to the plurality of first conductive lines are arranged in a staggered manner, and the plurality of second type of pixel circuits connected to the plurality of second conductive lines are arranged in a staggered manner.

6. The display panel according to any one of claims 1-5, wherein, A portion of one of the plurality of first conductive lines extending in the first direction at least partially overlaps a portion of another first conductive line different from the first conductive line and extending in the first direction on the substrate.

7. The display panel according to any one of claims 1-5, wherein, The plurality of second area light emitting elements further include a plurality of third light emitting elements configured to emit light of a third color, The plurality of second type of pixel circuits further include a plurality of third pixel circuits, The conductive line further includes a plurality of third conductive lines, and the plurality of third light emitting elements are connected to the plurality of third pixel circuits through the plurality of third conductive lines, In the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of first type of pixel circuits connected to the plurality of first conductive lines is closer to the second display area than each of the plurality of third type of pixel circuits connected to the plurality of third conductive lines. In the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of second type of pixel circuits connected to the plurality of second conductive lines and the plurality of third type of pixel circuits connected to the plurality of third conductive lines are arranged in a staggered manner.

8. The display panel of claim 7, wherein, The plurality of second area light emitting elements further include a plurality of fourth light emitting elements configured to emit light of a fourth color, The plurality of second type of pixel circuits further include a plurality of fourth pixel circuits, The conductive line further includes a plurality of fourth conductive lines, and the plurality of fourth light emitting elements are connected to the plurality of fourth pixel circuits through the plurality of fourth conductive lines, In the at least one group of light emitting elements and the at least one group of pixel circuits, each of the plurality of fourth type of pixel circuits connected to the plurality of fourth conductive lines is closer to the second display area than each of the plurality of second type of pixel circuits connected to the plurality of second conductive lines.

9. The display panel of claim 8, wherein, The plurality of fourth type of pixel circuits connected to the plurality of fourth conductive lines and the plurality of first type of pixel circuits connected to the plurality of first conductive lines are arranged in a staggered manner, A portion of one of the plurality of second conductive lines extending in the first direction at least partially overlaps a portion of one of the plurality of third conductive lines different from the second conductive line and extending in the first direction on the substrate.

10. The display panel of claim 8 or 9, wherein, At least one of the groups of light emitting elements comprises a first sub-group of light emitting elements, a second sub-group of light emitting elements and a third sub-group of light emitting elements arranged in sequence along the first direction, at least one of the groups of pixel circuits comprises a first sub-group of pixel circuits to a seventh sub-group of pixel circuits arranged in sequence along the first direction, the seventh sub-group of pixel circuits is closer to the second display area than the first sub-group of pixel circuits, The conductive lines connected with the first sub-group of light emitting elements are located on the third pattern layer, the conductive lines connected with the second sub-group of light emitting elements are located on the second pattern layer, the conductive lines connected with the third sub-group of light emitting elements comprise the conductive lines located on the first pattern layer and the segmented conductive lines, the segmented conductive lines comprise a first conductive part located on the first pattern layer and a second conductive part located on the second pattern layer, The second light emitting element and the third light emitting element in the first sub-group of light emitting elements are connected with the second sub-group of pixel circuits, the second light emitting element and the third light emitting element in the second sub-group of light emitting elements are connected with the first sub-group of pixel circuits, the second light emitting element and the third light emitting element in the third sub-group of light emitting elements close to the second sub-group of light emitting elements are connected with the fourth sub-group of pixel circuits, the second light emitting element and the third light emitting element in the third sub-group of light emitting elements away from the second sub-group of light emitting elements are connected with the third sub-group of pixel circuits, the first light emitting element and the fourth light emitting element in the first sub-group of light emitting elements are connected with the seventh sub-group of pixel circuits, the first light emitting element and the fourth light emitting element in the second sub-group of light emitting elements are connected with the sixth sub-group of pixel circuits, the first light emitting element and the fourth light emitting element in the third sub-group of light emitting elements are connected with the fifth sub-group of pixel circuits.

11. The display panel of claim 10, wherein, The second conductive line has a part extending along the first direction, and the part has a projection on the substrate, and the projection at least partially overlaps with a projection on the substrate of a part of a third conductive line which is located on a layer different from the second conductive line, The part of the conductive line connected with the second sub-group of light emitting elements extending along the first direction does not overlap with the part of other conductive lines extending along the first direction.

12. The display panel of claim 10, wherein, The part of the conductive line connected with the second sub-group of pixel circuits extending along the first direction and the part of the conductive line connected with the fourth sub-group of pixel circuits extending along the first direction overlap, the part of the conductive line connected with the first sub-group of pixel circuits extending along the first direction does not overlap with the part of the conductive line connected with the second sub-group of pixel circuits extending along the first direction, and does not overlap with the part of the conductive line connected with the fourth sub-group of pixel circuits extending along the first direction.

13. The display panel of claim 8 or 9, wherein, The fourth light emitting element and the first light emitting element are configured to emit light of the same color, The fourth light emitting element and the first light emitting element are configured to emit green light, one of the second light emitting element and the third light emitting element is configured to emit red light, and the other of the second light emitting element and the third light emitting element is configured to emit blue light.

14. The display panel of claim 8 or 9, wherein, A portion of one of the plurality of first conductive lines extending in the first direction has an orthogonal projection on the substrate that at least partially overlaps with an orthogonal projection on the substrate of a portion of one of the plurality of fourth conductive lines in a different layer than the first conductive line extending in the first direction.

15. The display panel of any of claims 1-5, wherein, The second display area is an axisymmetric shape having a first axis of symmetry extending in the first direction and a second axis of symmetry extending in the second direction, the conductive lines are provided as a plurality of conductive lines, the plurality of conductive lines are axisymmetric with respect to the first axis of symmetry and axisymmetric with respect to the second axis of symmetry, The plurality of second area light emitting elements are axisymmetric with respect to the first axis of symmetry and axisymmetric with respect to the second axis of symmetry.

16. The display panel of any of claims 1-5, wherein, The first display area includes an auxiliary area, the plurality of pixel circuits of the second type are located in the auxiliary area, an area of the auxiliary area is less than an area of a region of the first display area other than the auxiliary area, Within the auxiliary area, an orthogonal projection on the substrate of the conductive lines partially overlaps with an orthogonal projection on the substrate of the pixel circuits of the first type.

17. The display panel of claim 16, wherein, A size of the pixel circuits of the first type in the first direction is less than a size of the first area light emitting elements in the first direction.

18. The display panel of claim 5, wherein, The second display area includes a light-transmissive area, a resolution of the first display area is the same as a resolution of the second display area, and a density of the first area light emitting elements is the same as a density of the second area light emitting elements.

19. The display panel of any one of claims 1-5, wherein, The pixel circuit includes a drive transistor and a reset transistor, the display panel further includes a reset control signal line, a gate of the reset transistor is connected to the reset control signal line, a first electrode of the reset transistor is connected to an initialization signal line, a second electrode of the reset transistor is connected to a first electrode of the light emitting element, the initialization signal line is configured to provide a constant voltage, and the constant voltage is greater than or equal to -2V.

20. A display device, comprising the display panel according to any one of claims 1-19.

21. The display device of claim 20, further comprising a photosensor, wherein, The photosensitive sensor is located on one side of the display panel.

Images