Field programmable gate array (FPGA) general physical test system

Abstract

The invention relates to the technical field of safety-critical electronic equipment, and particularly discloses an FPGA general physical test system which comprises a power supply system, a temperature and humidity test box, a tested FPGA connection tool, a test excitation generation and test response acquisition module and an industrial personal computer, the tested FPGA connection tool is placed in the temperature and humidity test box, the power supply system is electrically connected with the tested FPGA connection tool, and the industrial personal computer is electrically connected with the tested FPGA connection tool. The tested FPGA connection tool is electrically connected with the test excitation generation and test response acquisition module, the test excitation generation and test response acquisition module is electrically connected with the industrial personal computer, the FPGA general physical test system is used for testing a tested FPGA loaded on the tested FPGA connection tool, and the power supply system is used for providing power supply voltage of a specified working condition for the tested FPGA; and the temperature and humidity test box is used for providing a temperature and humidity test environment of a specified working condition for the tested FPGA. The method is wide in applicable test range, high in test efficiency and clear and complete in test result.

Description

Technical Field

[0001] The present invention relates to the technical field of safety-critical electronic equipment, and more specifically, to a general-purpose physical test system for FPGA. Background Art

[0002] In the field of safety-critical electronic equipment technology, FPGAs are often used for communication, redundancy, key algorithm processing and other functions. The current physical testing method for FPGAs is mainly to build a device-level test environment and conduct physical testing of FPGAs in electronic equipment. The physical testing system described above has the following deficiencies: 1. The physical test system is complex and costly to build. The whole physical test equipment usually includes a power supply system, an industrial computer, a test board, many connecting cables, and a host computer test software. It takes a lot of time and cost to build the entire test system. 2. It is difficult to implement fault injection. In the physical test system, a large number of commercial shelf boards and test instruments are sampled. Such test equipment cannot simulate the faults that need to be prevented and handled in safety-critical areas, resulting in inadequate testing; 3. Irreversible damage to the equipment. When certain faults are injected, such as overcurrent faults, components of the electronic equipment under test may be damaged, causing the equipment to fail. Summary of the invention

[0003] In order to solve the deficiencies in the prior art, the present invention provides a universal physical test system for FPGA to solve the problems in the prior art that the physical test system is complex and costly to build, difficult to implement fault injection, and causes irreversible damage to the equipment.

[0004] As a first aspect of the present invention, a general FPGA physical test system is provided, the general FPGA physical test system comprising a power supply system, a temperature and humidity test chamber, a tested FPGA connection tooling, a test stimulus generation and test response acquisition module, and an industrial control computer, the tested FPGA connection tooling is placed in the temperature and humidity test chamber, the power supply system is electrically connected to the tested FPGA connection tooling, the tested FPGA connection tooling is electrically connected to the test stimulus generation and test response acquisition module, the test stimulus generation and test response acquisition module is electrically connected to the industrial control computer, the general FPGA physical test system is used to test the tested FPGA loaded on the tested FPGA connection tooling, wherein: The power supply system is used to provide a power supply voltage of a specified working condition to the FPGA under test; The temperature and humidity test box is used to provide a temperature and humidity test environment of specified working conditions for the FPGA under test; The industrial computer is used to compile FPGA physical test case data, and perform format conversion on the FPGA physical test case data, and then send the converted FPGA physical test case data to the test stimulus generation and test response acquisition module; The test stimulus generation and test response acquisition module is used to output test stimulus data to the FPGA under test when reading the converted FPGA physical test case data, and then collect the test response data sent by the FPGA under test, and send the test response data to the industrial computer after format conversion, and the industrial computer analyzes the converted test response data.

[0005] Furthermore, the power supply system is connected to the FPGA connection tooling under test via a cable, and the FPGA connection tooling under test is connected to the test stimulus generation and test response acquisition module via a cable.

[0006] Further, the power supply system includes a first power supply adjustment circuit, a second power supply adjustment circuit, a 3.3V power supply module, a 1.5V power supply module and a power socket, the first power supply adjustment circuit and the second power supply adjustment circuit each include a plurality of switches, one end of the 3.3V power supply module and one end of the 1.5V power supply module are both connected to the power socket, the other end of the 3.3V power supply module is connected to the first power supply adjustment circuit, and the other end of the 1.5V power supply module is connected to the second power supply adjustment circuit; wherein, The 3.3V power supply module and the 1.5V power supply module can provide the 3.3V power supply voltage and the 1.5V power supply voltage required for typical operating conditions to the FPGA under test through the power socket, and perform voltage regulation through the first power supply adjustment circuit and the second power supply adjustment circuit to provide the 3.6V power supply voltage and the 1.575V power supply voltage required for the minimum operating conditions to the FPGA under test, or provide the 3V power supply voltage and the 1.425V power supply voltage required for the maximum operating conditions to the FPGA under test.

[0007] Furthermore, the industrial computer is used to run test data management software, and the test data management software is used for compiling the FPGA physical test case data, converting the format of the FPGA physical test case data, collecting test response data, and analyzing the test response data; wherein the test data management software compiles the FPGA physical test case data through an FPGA verification language, and converts the FPGA physical test case data into a prescribed file format for the test stimulus generation and test response collection module to read and output the test stimulus data; The test stimulus generation and test response acquisition module is used to generate the test stimulus data after receiving the converted FPGA physical test case data sent by the test data management software, and send the test stimulus data to the FPGA under test in the form of pin-to-pin; then collect the test response data sent by the FPGA under test, and send it to the test data management software for analysis after performing format conversion; wherein, after receiving the converted test response data, the test data management software summarizes and displays the converted test response data in a graphical form, and analyzes the waveform of the converted test response data.

[0008] Furthermore, the test data management software uses the SystemVerilog language to compile the FPGA physical test case data, and saves the FPGA physical test case data as a VCD file through the Questasim desktop simulation software. The test data management software reads the VCD file and sends it to the test stimulus generation and test response acquisition module via Ethernet.

[0009] Furthermore, the test stimulus generation and test response acquisition module includes a high-performance FPGA, a storage unit and a connection socket, wherein the first end of the high-performance FPGA is connected to the industrial computer via an Ethernet interface, the second end of the high-performance FPGA is connected to the storage unit, the third end of the high-performance FPGA is connected to one end of the connection socket, and the other end of the connection socket is connected to the FPGA connection tooling under test; wherein, The high-performance FPGA receives the converted FPGA physical test case data sent by the industrial computer through Ethernet, and saves the converted FPGA physical test case data to the storage unit; When the high-performance FPGA receives the test start instruction, it reads the converted FPGA physical test case data from the storage unit, and then outputs the test stimulus data to the connection socket, thereby stimulating the FPGA under test; then the high-performance FPGA reads the test response data sent by the FPGA under test through the connection socket, and stores the test response data in the storage unit; When the high-performance FPGA receives the test end instruction, it converts the format of the test response data in the storage unit and sends it to the industrial computer via Ethernet.

[0010] Furthermore, the temperature in the temperature and humidity test box can be set to -40°C, 25°C and 85°C to meet the temperature requirements of the minimum operating condition, typical operating condition and maximum operating condition of the FPGA under test.

[0011] Furthermore, the model of the FPGA under test is A3P1000-PQ208, which can receive instructions sent by the CPU to realize communication function, signal output function and over-current shutdown function. The FPGA general physical test system tests the communication function, signal output function and over-current shutdown function of the FPGA under test.

[0012] Furthermore, the temperature and humidity test box has an area for placing the FPGA connection tooling under test, and a space is reserved for a standard connector interface of the connection cable.

[0013] Furthermore, the FPGA under test connection tooling is loaded with the FPGA under test via a detachable connector interface.

[0014] The FPGA universal physical test system provided by the present invention has the following advantages: (1) High versatility, capable of performing physical tests on various FPGAs, various functions, and various working conditions; (2) High testing efficiency and comprehensive test data analysis. It can generate test cases using standard file formats and conduct comprehensive analysis of test data. (3) The test coverage is comprehensive and can quickly test various faults, communication deviations, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention.

[0016] Figure 1 It is a principle block diagram of the FPGA universal physical test system of the present invention.

[0017] Figure 2 It is a structural block diagram of the power supply system of the present invention.

[0018] Figure 3 This is a structural block diagram of the test stimulus generation and test response acquisition module of the present invention. DETAILED DESCRIPTION

[0019] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the specific implementation method, structure, characteristics and effects of a FPGA universal physical test system proposed by the present invention are described in detail below in combination with the accompanying drawings and preferred embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0021] In the interpretation of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense unless otherwise specified. For example, the connection can be a fixed connection, or it can be connected through a special interface, or it can be indirectly connected through an intermediate medium. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] In this embodiment, a general FPGA physical test system is provided. Figure 1 As shown, the FPGA universal physical test system includes a power supply system, a temperature and humidity test chamber, a tested FPGA connection tooling, a test stimulus generation and test response acquisition module, and an industrial computer. The tested FPGA connection tooling is placed in the temperature and humidity test chamber, the power supply system is electrically connected to the tested FPGA connection tooling, the tested FPGA connection tooling is electrically connected to the test stimulus generation and test response acquisition module, the test stimulus generation and test response acquisition module is electrically connected to the industrial computer, and the FPGA universal physical test system is used to test the tested FPGA loaded on the tested FPGA connection tooling, wherein, The power supply system is used to provide a power supply voltage of a specified working condition to the FPGA under test; The temperature and humidity test box is used to provide a temperature and humidity test environment of specified working conditions for the FPGA under test; The industrial computer is used to compile FPGA physical test case data, and perform format conversion on the FPGA physical test case data, and then send the converted FPGA physical test case data to the test stimulus generation and test response acquisition module; The test stimulus generation and test response acquisition module is used to output test stimulus data to the FPGA under test when reading the converted FPGA physical test case data, and then collect the test response data sent by the FPGA under test, and send the test response data to the industrial computer after format conversion, and the industrial computer analyzes the converted test response data.

[0023] Specifically, the power supply system is connected to the FPGA connection tool under test through a cable, and the FPGA connection tool under test is connected to the test stimulus generation and test response acquisition module through a cable.

[0024] Preferably, Figure 2 As shown, the power supply system includes a first power supply adjustment circuit, a second power supply adjustment circuit, a 3.3V power supply module, a 1.5V power supply module and a power socket, the first power supply adjustment circuit and the second power supply adjustment circuit each include a plurality of switches, one end of the 3.3V power supply module and one end of the 1.5V power supply module are both connected to the power socket, the other end of the 3.3V power supply module is connected to the first power supply adjustment circuit, and the other end of the 1.5V power supply module is connected to the second power supply adjustment circuit; wherein, The 3.3V power module and the 1.5V power module can provide the 3.3V IO voltage and 1.5V core voltage required for typical operating conditions to the FPGA under test through the power socket, and perform voltage regulation through the first power adjustment circuit and the second power adjustment circuit to provide the FPGA under test with the 3.6V power supply voltage and 1.575V power supply voltage required for the minimum operating conditions, or provide the FPGA under test with the 3V power supply voltage and 1.425V power supply voltage required for the maximum operating conditions.

[0025] It should be noted that the power module can meet the power supply requirements of mainstream FPGAs in the industry, such as the power supply requirements of multiple series of FPGAs from manufacturers such as Xilinx, Atlera, Actel, etc. At the same time, the power adjustment circuit can fine-tune the core power supply of the FPGA to meet the maximum operating conditions (specified minimum power supply voltage), typical operating conditions (specified power supply voltage), and minimum operating conditions (specified maximum power supply voltage) of the FPGA.

[0026] Preferably, the industrial computer is used to run test data management software, and the test data management software is used for compiling the FPGA physical test case data, converting the format of the FPGA physical test case data, collecting test response data, and analyzing the test response data; wherein, the test data management software compiles the FPGA physical test case data through an FPGA verification language, and converts the FPGA physical test case data into a prescribed file format for the test stimulus generation and test response collection module to read and output the test stimulus data; The test stimulus generation and test response acquisition module is used to generate the test stimulus data after receiving the converted FPGA physical test case data sent by the test data management software, and send the test stimulus data to the FPGA under test in the form of pin-to-pin; then collect the test response data sent by the FPGA under test, and send it to the test data management software for analysis after performing format conversion; wherein, after receiving the converted test response data, the test data management software summarizes and displays the converted test response data in a graphical form, and analyzes the waveform of the converted test response data.

[0027] Preferably, the test data management software uses the SystemVerilog language to compile the FPGA physical test case data, and saves the FPGA physical test case data as a VCD (ValueChange Dump) file through Questasim desktop simulation software. The test data management software reads the VCD file and sends it to the test stimulus generation and test response acquisition module via Ethernet.

[0028] Preferably, Figure 3 As shown, the test stimulus generation and test response acquisition module includes a high-performance FPGA, a storage unit and a connection socket. The first end of the high-performance FPGA is connected to the industrial computer through an Ethernet interface, the second end of the high-performance FPGA is connected to the storage unit, the third end of the high-performance FPGA is connected to one end of the connection socket, and the other end of the connection socket is connected to the FPGA connection tooling under test; wherein, The high-performance FPGA receives the converted FPGA physical test case data sent by the industrial computer through Ethernet, and saves the converted FPGA physical test case data to the storage unit; When the high-performance FPGA receives the test start instruction, it reads the converted FPGA physical test case data from the storage unit, and then outputs the test stimulus data to the connection socket, thereby stimulating the FPGA under test; then the high-performance FPGA reads the test response data sent by the FPGA under test through the connection socket, and stores the test response data in the storage unit; When the high-performance FPGA receives the test end instruction, it converts the format of the test response data in the storage unit and sends it to the industrial computer via Ethernet.

[0029] Specifically, the temperature in the temperature and humidity test box can be set to -40°C, 25°C and 85°C to meet the temperature requirements of the minimum operating condition, typical operating condition and maximum operating condition of the FPGA under test.

[0030] Preferably, the model of the FPGA under test is A3P1000-PQ208, which can receive instructions sent by the CPU to realize communication function, signal output function and over-current shutdown function. The FPGA universal physical test system tests the communication function, signal output function and over-current shutdown function of the FPGA under test.

[0031] Preferably, the temperature and humidity test chamber has an area for placing the FPGA connection tooling under test, and reserves space for a standard connector interface of the connection cable.

[0032] Preferably, the FPGA under test connection tooling is loaded with the FPGA under test via a detachable connector interface.

[0033] It should be noted that the test stimulus generation and test response acquisition module mainly completes the output and acquisition of test stimulus data and test response data between the FPGA under test, and interacts with the test data management software through the specified file format. The connection between the FPGA under test connection fixture and the cable adopts a standard connector interface to meet different FPGA models and different functional test scenarios; the connection between the FPGA under test connection fixture and the FPGA under test adopts a detachable connector interface to facilitate the replacement of FPGA chips.

[0034] In this embodiment, the test process of the RS422 communication function in the tested FPGA is taken as an example for explanation. The requirement of the RS422 communication function in the tested FPGA is to invert the received data bit by bit and send it. The test process is as follows: 1. Compile a test case for the RS422 communication function in the FPGA under test on the industrial computer, set the baud rate to 115200*1.02bps and 115200*0.98bps, and send four groups of data: 0x55, 0xAA, 0x5A, and 0xA5. Use Questasim to generate a VCD file; 2. Click "Test Data Download" in the test data management software to send the VCD file to the test stimulus generation and test response acquisition module via Ethernet; 3. Click "Start Test" in the test data management software. The high-performance FPGA reads the test case data one by one from the storage unit and transmits the generated test stimulus data to the FPGA under test. At the same time, the high-performance FPGA stores the test response data of the FPGA under test in the storage unit. 4. Wait for the test to complete, click "End Test" in the test data management software, and the high-performance FPGA will send the test response data back to the industrial computer via Ethernet; 5. Analyze the data in the test data management software to confirm whether the test response data sent back by the FPGA under test is 0xAA, 0x55, 0xA5, or 0x5A.

[0035] The FPGA general physical test system provided by the present invention includes test stimulus injection, fault simulation, data acquisition and display, working condition simulation, etc., and can perform comprehensive pin-to-pin testing on the FPGA under test, covering various working conditions, functional performance tests, fault injection, etc. of the FPGA under test. It has a wide range of applicable tests, high test efficiency, and clear and complete test results.

[0036] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A general-purpose physical test system for FPGA, characterized in that: The FPGA universal physical test system includes a power supply system, a temperature and humidity test chamber, a tested FPGA connection tooling, a test stimulus generation and test response acquisition module, and an industrial control computer. The tested FPGA connection tooling is placed in the temperature and humidity test chamber, the power supply system is electrically connected to the tested FPGA connection tooling, the tested FPGA connection tooling is electrically connected to the test stimulus generation and test response acquisition module, the test stimulus generation and test response acquisition module is electrically connected to the industrial control computer, and the FPGA universal physical test system is used to test the tested FPGA loaded on the tested FPGA connection tooling, wherein: The power supply system is used to provide a power supply voltage of a specified working condition to the FPGA under test; The temperature and humidity test box is used to provide a temperature and humidity test environment of specified working conditions for the FPGA under test; The industrial computer is used to compile FPGA physical test case data, and perform format conversion on the FPGA physical test case data, and then send the converted FPGA physical test case data to the test stimulus generation and test response acquisition module; The test stimulus generation and test response acquisition module is used to output test stimulus data to the FPGA under test when reading the converted FPGA physical test case data, and then collect the test response data sent by the FPGA under test, and send the test response data to the industrial computer after format conversion, and the industrial computer analyzes the converted test response data.

2. The FPGA universal physical test system according to claim 1, characterized in that: The power supply system is connected to the FPGA connection tool under test through a cable, and the FPGA connection tool under test is connected to the test stimulus generation and test response acquisition module through a cable.

3. The FPGA universal physical test system according to claim 1, characterized in that: The power supply system includes a first power supply adjustment circuit, a second power supply adjustment circuit, a 3.3V power supply module, a 1.5V power supply module and a power socket, wherein the first power supply adjustment circuit and the second power supply adjustment circuit each include a plurality of switches, one end of the 3.3V power supply module and one end of the 1.5V power supply module are both connected to the power socket, the other end of the 3.3V power supply module is connected to the first power supply adjustment circuit, and the other end of the 1.5V power supply module is connected to the second power supply adjustment circuit; wherein, The 3.3V power supply module and the 1.5V power supply module can provide the 3.3V power supply voltage and the 1.5V power supply voltage required for typical operating conditions to the FPGA under test through the power socket, and perform voltage regulation through the first power supply adjustment circuit and the second power supply adjustment circuit to provide the 3.6V power supply voltage and the 1.575V power supply voltage required for the minimum operating conditions to the FPGA under test, or provide the 3V power supply voltage and the 1.425V power supply voltage required for the maximum operating conditions to the FPGA under test.

4. The FPGA universal physical test system according to claim 1, characterized in that: The industrial computer is used to run the test data management software, and the test data management software is used for the preparation of the FPGA physical test case data, the format conversion of the FPGA physical test case data, the collection of test response data, and the analysis of the test response data; wherein, the test data management software prepares the FPGA physical test case data through the FPGA verification language, and converts the FPGA physical test case data into a prescribed file format for the test stimulus generation and test response collection module to read and output the test stimulus data; The test stimulus generation and test response acquisition module is used to generate the test stimulus data after receiving the converted FPGA physical test case data sent by the test data management software, and send the test stimulus data to the FPGA under test in the form of pin-to-pin; then collect the test response data sent by the FPGA under test, and send it to the test data management software for analysis after performing format conversion; wherein, after receiving the converted test response data, the test data management software summarizes and displays the converted test response data in a graphical form, and analyzes the waveform of the converted test response data.

5. The FPGA universal physical test system according to claim 4, characterized in that: The test data management software uses the SystemVerilog language to compile the FPGA physical test case data, and saves the FPGA physical test case data as a VCD file through the Questasim desktop simulation software. The test data management software reads the VCD file and sends it to the test stimulus generation and test response acquisition module through Ethernet.

6. The FPGA universal physical test system according to claim 1, characterized in that: The test stimulus generation and test response acquisition module includes a high-performance FPGA, a storage unit and a connection socket. The first end of the high-performance FPGA is connected to the industrial computer through an Ethernet interface, the second end of the high-performance FPGA is connected to the storage unit, the third end of the high-performance FPGA is connected to one end of the connection socket, and the other end of the connection socket is connected to the FPGA connection tooling under test; wherein, The high-performance FPGA receives the converted FPGA physical test case data sent by the industrial computer through Ethernet, and saves the converted FPGA physical test case data to the storage unit; When the high-performance FPGA receives the test start instruction, it reads the converted FPGA physical test case data from the storage unit, and then outputs the test stimulus data to the connection socket, thereby stimulating the FPGA under test; then the high-performance FPGA reads the test response data sent by the FPGA under test through the connection socket, and stores the test response data in the storage unit; When the high-performance FPGA receives the test end instruction, it converts the format of the test response data in the storage unit and sends it to the industrial computer via Ethernet.

7. The FPGA universal physical test system according to claim 1, characterized in that: The temperature in the temperature and humidity test box can be set to -40°C, 25°C and 85°C to meet the temperature requirements of the minimum operating condition, typical operating condition and maximum operating condition of the FPGA under test.

8. The FPGA universal physical test system according to claim 1, characterized in that: The model of the FPGA under test is A3P1000-PQ208, which can receive instructions sent by the CPU to realize communication function, signal output function and over-current shutdown function. The FPGA universal physical test system tests the communication function, signal output function and over-current shutdown function of the FPGA under test.

9. The FPGA universal physical test system according to claim 1, characterized in that: The temperature and humidity test box has an area for placing the FPGA connection tooling under test, and a space is reserved for a standard connector interface of a connecting cable.

10. The FPGA universal physical test system according to claim 1, characterized in that: The FPGA under test connection tool is loaded with the FPGA under test through a detachable connector interface.

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