PUF (Physical Unclonable Function) tag generation method and verification system based on MOS (Metal Oxide Semiconductor) type anti-fuse breakdown characteristic
Through the PUF tag generation method based on the MOS type antifuse breakdown characteristics, the gate current-gate voltage characteristic value of the chip is recorded, and the problem of imitation and pirated CMOS integrated circuits is solved, thereby realizing low-cost and high-reliability anti-counterfeiting verification.
Patent Information
- Application Number
- CN202411805887.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-10
- Publication Date
- 2025-05-16
AI Technical Summary
The prior art is difficult to effectively prevent CMOS integrated circuits from being copied and pirated, and lacks a low-cost and high-reliability anti-counterfeiting measure.
The PUF tag generation method based on the MOS type antifuse breakdown characteristics is adopted. The MOS type antifuse unit is broken down by gradually increasing voltage, and the gate current-gate voltage characteristic value after breakdown is recorded as the PUF tag to verify the authenticity of the chip.
It effectively prevents integrated circuits from being copied and pirated, ensures the safety and legality of the product, and has low cost and high reliability.
Smart Images
Figure CN120012173A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a technology for preventing CMOS integrated circuits from being copied. Background Art
[0002] PUF, the full name of which is Physical Unclonable Functions, is a hardware security technology. PUF uses the inherent properties of silicon-based semiconductors to randomly extract physical features that cannot be cloned. These features are similar to biological fingerprints and are the unique identifiers of each chip. In the process of silicon-based chip manufacturing, process changes caused by semiconductor process fluctuations will produce differences in inherent properties such as path delay and transistor threshold voltage, resulting in each physical chip being unique after tape-out. PUF uses this naturally occurring inherent difference to generate a unique identification code, or "digital fingerprint," for each chip.
[0003] MOS type antifuse is a device that uses the gate oxide layer in the MOS (metal-oxide-semiconductor) structure as a dielectric layer to form an antifuse. Before programming, the gate and source and drain are in a high resistance state due to the blocking of the gate oxide dielectric layer. When electric field stress is applied, local defects or traps are generated in the gate oxide layer. As the electric field stress increases, the number of defects or traps generated increases and gathers at the strongest electric field. When the electric field stress increases to a certain extent, the gathered defects or traps overlap each other and form a conductive channel. Once the conductive channel is formed, current passes through, generating a large amount of heat, causing the gate oxide dielectric near the channel to melt, forming a permanent and fine breakdown path, and the current between the gate and the source and drain rises sharply, forming electrical connectivity. Due to the influence of process factors, there are great differences in the characteristics of MOS after breakdown, which is reflected in the great difference in the IV characteristics of MOS after breakdown. Summary of the invention
[0004] The technical solution adopted by the present invention to solve the technical problem is to provide a PUF verification technology based on the breakdown characteristics of a MOS anti-fuse, which can effectively and cost-effectively prevent the counterfeiting of integrated circuits and other commodities.
[0005] The technical solution adopted by the present invention to solve the technical problem is a PUF tag generation method based on the breakdown characteristics of a MOS type anti-fuse, characterized in that it includes the following steps:
[0006] a. Using a gradually increasing voltage to perform a breakdown operation on the MOS type anti-fuse unit;
[0007] b. Apply voltage to the MOS anti-fuse unit after breakdown to measure, and record the gate current-gate voltage characteristic value as the characteristic information of the MOS anti-fuse unit. The MOS anti-fuse unit becomes a PUF tag.
[0008] Furthermore, the step a is: using a linearly increasing standard ramp voltage to perform a breakdown operation on the MOS anti-fuse unit.
[0009] In the step b, the gate current-gate voltage characteristic value is a preset number of gate current-gate voltage characteristic value points sampled on the gate current-gate voltage characteristic curve.
[0010] Furthermore, for chip products, step a includes:
[0011] a1. Before the chip is taped out as a commodity, a preset number of MOS anti-fuse units are added to the circuit, and the MOS anti-fuse units serve as PUF tags;
[0012] a2. Use a gradually increasing voltage to perform a breakdown operation on the MOS anti-fuse unit.
[0013] The present invention also provides a PUF verification system based on the breakdown characteristics of a MOS type anti-fuse, characterized in that it includes the following parts:
[0014] A PUF tag, wherein the PUF tag is obtained by breaking down a MOS anti-fuse unit with a gradually increasing voltage;
[0015] A database stores characteristic information of a PUF tag attached to a commodity, wherein the characteristic information is a gate current-gate voltage characteristic value of the PUF tag.
[0016] The device also includes a detection device, which includes an adjustable voltage output unit and a current measurement unit.
[0017] The database also stores the commodity ID corresponding to the PUF tag. The database also stores the distribution channel information corresponding to the commodity ID.
[0018] The beneficial effects of the present invention are that it can effectively prevent the integrated circuit from being counterfeited and pirated, ensure the safety and legality of the product, and has the characteristics of low cost and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 This is a system block diagram of Example 1.
[0020] Figure 2 This is the workflow diagram of Example 1.
[0021] Figure 3It is a schematic diagram of the principle of the present invention.
[0022] Figure 4 This is the programming voltage curve.
[0023] Figure 5 It is a gate current-gate voltage characteristic curve of the MOS antifuse after breakdown. DETAILED DESCRIPTION
[0024] After in-depth research on MOS anti-fuse devices, it was found that after breakdown, the MOS anti-fuse device exhibits resistance characteristics, but the resistance value is not constant and is related to voltage, that is, it exhibits a voltage-dependent variable resistance characteristic. Based on this characteristic, the present invention provides a PUF tag generation method and verification system.
[0025] Taking chip products as an example, the following steps are used to implement anti-counterfeiting verification:
[0026] 1. Before the chip is taped out, an anti-counterfeiting test circuit module is added to the circuit (layout), that is, one or more MOS anti-fuse units are specially made for anti-counterfeiting authentication.
[0027] 2. After the chip is manufactured, a programming voltage is applied to the MOS anti-fuse unit in the chip to make it break down before the chip is released. The programming voltage is a standard ramp voltage, that is, the programming voltage is linearly increased from zero. After the voltage increases to a certain level, the gate oxide layer of the MOS structure will undergo irreversible breakdown.
[0028] 3. Measure the gate current-gate voltage characteristic curve after the MOS anti-fuse unit is broken down, and select the current and voltage values of several characteristic points on the curve as the chip ID and upload them to the database of the server.
[0029] 4. After purchasing the chip, the user can send a test request, test the circuit operation and measure the IV characteristics of the corresponding characteristic points of the MOS anti-fuse, and compare the results with the information in the database to verify the authenticity of the chip. If the test results match the information entered in the database, it proves that the chip is a genuine product; otherwise, it is a counterfeit product.
[0030] Example: See Figure 1 to Figure 5 .
[0031] This embodiment includes the following steps:
[0032] 1. Add a MOS anti-fuse test area to the layout. Based on the CMOS process, the source and drain of the manufactured MOS tube are short-circuited as one pole and the gate as the other pole to apply the programming voltage. The test circuit connection method is as follows: Figure 3 shown.
[0033] 2. Apply standard ramp stress, that is, linearly increase the external programming voltage. For the 1.8V device with a gate oxide layer thickness of 3.2nm used in this embodiment, apply a standard ramp voltage of Vramp=0-7V, such as Figure 4 shown.
[0034] 3. The gate current-gate voltage characteristic curve after the MOS antifuse is broken down is tested at room temperature. For the 1.8V device with a gate oxide layer thickness of 3.2nm in the embodiment, the gate current-gate voltage characteristic curve results of different samples are as follows: Figure 5 As shown. Select 5 test points, such as 1V, 2V, 3V, 4V, and 5V, and the test results of the three test curves selected by the present invention are shown in Table 1. The measured gate current results are stored and used as the chip ID. The chip gate current results obtained by the test are matched one by one with the chip number, uploaded to the database, and used as the chip identifier ID.
[0035] 4. Simulate user testing, test the IV characteristic curve of the sample under different environments, and compare it with the data in the database. If the current data of each characteristic point is consistent (a certain test error can be allowed, such as 10%), it proves that the chip is authentic, otherwise it is a counterfeit.
[0036] The above protection mechanism can effectively prevent the imitation and piracy of CMOS integrated circuit chips.
[0037]
[0038] Table 1 Test point currents for different antifuses.
Claims
1. A PUF tag generation method based on the breakdown characteristics of a MOS type anti-fuse, characterized in that: The steps include: a. Using a gradually increasing voltage to perform a breakdown operation on the MOS type anti-fuse unit; b. Apply voltage to the MOS anti-fuse unit after breakdown to measure, and record the gate current-gate voltage characteristic value as the characteristic information of the MOS anti-fuse unit. The MOS anti-fuse unit becomes a PUF tag.
2. The method for generating a PUF tag based on the breakdown characteristics of a MOS type anti-fuse according to claim 1, characterized in that: The step a is: A linearly increasing standard ramp voltage is used to perform a breakdown operation on the MOS type anti-fuse unit.
3. The method for generating a PUF tag based on the breakdown characteristics of a MOS type anti-fuse according to claim 1, characterized in that: In the step b, the gate current-gate voltage characteristic value is a preset number of gate current-gate voltage characteristic value points sampled on the gate current-gate voltage characteristic curve.
4. The method for generating a PUF tag based on the breakdown characteristics of a MOS anti-fuse according to claim 1, characterized in that: The step a comprises: a1. Before the chip is taped out as a commodity, a preset number of MOS anti-fuse units are added to the circuit, and the MOS anti-fuse units serve as PUF tags; a2. Use a gradually increasing voltage to perform a breakdown operation on the MOS anti-fuse unit.
5. A PUF verification system based on the breakdown characteristics of a MOS-type antifuse, characterized in that: Includes the following parts: A PUF tag, wherein the PUF tag is obtained by breaking down a MOS anti-fuse unit with a gradually increasing voltage; A database stores characteristic information of a PUF tag attached to a commodity, wherein the characteristic information is a gate current-gate voltage characteristic value of the PUF tag.
6. The PUF verification system based on the breakdown characteristics of the MOS anti-fuse according to claim 5, characterized in that: The device also includes a detection device, which includes an adjustable voltage output unit and a current measurement unit.
7. The PUF verification system based on the breakdown characteristics of the MOS type anti-fuse according to claim 5, characterized in that: The database also stores a commodity ID corresponding to the PUF tag.
8. The PUF verification system based on the breakdown characteristics of the MOS anti-fuse according to claim 7, characterized in that: The database also stores distribution channel information corresponding to the commodity ID.