Accelerator power consumption optimization method, system, device and storage medium based on hybrid regulation strategy

Abstract

This invention discloses an accelerator power consumption optimization method, system, device, and storage medium based on a hybrid adjustment strategy. The method includes: a bank manager collecting usage status information of each bank module in the accelerator; the accelerator determining whether the bank status has been updated via a state machine; when the bank status is updated, the bank manager sending the status information to a microcontroller via a low-speed transmission protocol; the microcontroller receiving the bank status information and controlling the accelerator power module and clock module according to the status information using an adjustment strategy to adjust the accelerator power consumption to the optimal mode; and the microcontroller acquiring on-board status information and adjusting the fan speed accordingly to achieve optimal overall board power consumption configuration. Applying the real-time accelerator power consumption adjustment method provided in this application ensures that the accelerator always operates in an optimal state, saving data center costs.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to an accelerator power consumption optimization method, system, device, and storage medium based on a hybrid adjustment strategy. Background Technology

[0002] FPGAs are widely used in data centers due to their performance advantages in low latency, high parallelism, and low power consumption. As early as 2018, Microsoft announced hardware specifically designed for artificial intelligence computing based on Intel A10 / S10 FPGA chips, offloading the file ranking operations of its Bing search engine (originally over 30,000 lines of C++ code) to FPGAs for hardware acceleration. With the same system latency, the throughput increased by nearly double after using FPGA hardware acceleration; for the same throughput requirements, system latency decreased by 29% after using FPGA. Furthermore, the additional power consumption of each FPGA is less than 25W, an increase of less than 10% compared to the original system, and the overall cost increase is less than 30%. Amazon AWS launched its FPGA cloud service EC2 F1 in 2016. Each F1 instance can be configured with eight FPGAs in its compute pool, applicable to various application scenarios such as data analysis, video processing, security, and machine learning, providing users with flexible acceleration solutions to meet the needs of different workloads. IBM and Xilinx jointly announced a strategic collaboration to utilize Xilinx FPGA acceleration workload processing technology on IBM POWER systems. The two parties are jointly developing open acceleration infrastructure, software, and middleware to meet the needs of emerging applications such as machine learning, network function virtualization (NFV), genomic analysis, high-performance computing (HPC), and big data analytics. IBM Systems developers are using Xilinx FPGA accelerators to build solution protocol stacks for POWER-based server, storage, and middleware systems. To date, FPGA applications in data centers cover several key areas. In machine learning, they are used to accelerate model training and inference; in network function virtualization, they are used to implement high-speed network packet processing and firewall functions; and in data storage and retrieval, they are used to accelerate data encryption, decryption, and index building. FPGAs have gradually become one of the important technologies for improving performance, reducing energy consumption, and enhancing flexibility in data centers.

[0003] However, with the development of FPGA chip technology, although FPGA chips have more and more logic resources and higher and higher performance, their power consumption is also increasing. Taking Xilinx FPGA chips as an example, the Spartan-7 series chips consume tens of watts, the Artix-7 series chips may consume close to 30 watts, the Kintex-7 series chips consume roughly tens of watts, the UltraScale series chips consume tens to hundreds of watts, and the latest adaptive computing acceleration platform products consume hundreds of watts or even more. At the same time, as coprocessors in data centers, FPGA accelerators may be idle most of the time, wasting more energy. Therefore, optimizing the power consumption of FPGAs while ensuring performance has become a hot research topic in academia and industry. CTChow et al. proposed a dynamic voltage regulation method based on logic delay measurement circuit to reduce the operating power consumption of FPGAs. For a given task, the minimum operating power supply voltage is derived through experiments, and the voltage is adjusted during operation to make it run at this critical point. Under different operating tasks, the power supply can achieve power savings of 4% to 54%. However, this scheme has only been verified as an FPGA energy saving concept and has not realized an implementation strategy for optimal energy consumption. Meanwhile, this solution uses a timed polling method to obtain the internal voltage, which lacks real-time capability. Jose Luis Nunez-Yanez proposed an FPGA voltage regulation method with adaptive voltage scaling technology. By adding an in-situ detector to the outside of the FPGA chip and instantiating the corresponding monitoring and management unit in the FPGA, the device can automatically adjust its voltage and frequency in a closed-loop configuration based on workload, process, and operating conditions. Its test results show that energy consumption is reduced by more than 85% compared to operating at the rated voltage at the same frequency. However, this solution uses an extended substrate to implement the in-situ detector, and the design of the FPGA monitoring and management unit consumes a lot of logic resources. Xilinx has built an XADC module into its FPGA chip, which can read the temperature and voltage information inside the FPGA through the DRP interface. However, its use requires instantiating IP cores such as XADC and DSP48E2, resulting in a waste of computing resources. In addition, this solution can only obtain the temperature information of the FPGA chip itself and cannot obtain the status information of the entire accelerator board.

[0004] In summary, although considerable research has been conducted on power management and optimization for FPGAs, this work suffers from two shortcomings: first, power consumption information is collected based on the FPGA itself, resulting in a waste of FPGA computing resources; second, power control is implemented based on major power consumption influencing factors such as voltage, leading to coarse-grained adjustment and failing to achieve fine-grained power regulation while ensuring performance. Research on specific implementation schemes for fine-grained power regulation and optimization using FPGA accelerators in the data center field is still limited. Especially for data center applications, designing accelerator power optimization schemes based on hybrid regulation strategies to reduce energy consumption is of great practical significance. Therefore, this invention designs an out-of-band power regulation method based on a microcontroller to achieve fine-grained power regulation of FPGA accelerators. Summary of the Invention

[0005] The main objective of this invention is to overcome the shortcomings and deficiencies of the prior art and provide an accelerator power consumption optimization method, system, device and storage medium based on a hybrid adjustment strategy. This invention can enable FPGA accelerator power consumption to always operate in the optimal state, thereby solving the problem of high ineffective power consumption and large energy waste in current data center FPGA accelerators.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides an accelerator power consumption optimization method based on a hybrid regulation strategy, comprising the following steps:

[0008] The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator uses a state machine to determine whether the bank status has been updated; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol.

[0009] The microcontroller receives bank status information and controls the accelerator power module and clock module according to the status information through power optimization strategy to adjust the accelerator power consumption to the optimal mode; the microcontroller obtains the status information on the board and adjusts the fan speed according to the status information to achieve the optimal configuration of the overall board power consumption.

[0010] The accelerator-side bank manager is built using an FPGA, and the accelerator-side state control system consists of a microcontroller, a clock control module, and a power control module.

[0011] As a preferred technical solution, the bank manager includes a low-speed protocol transmission module, a frame assembler, a state machine manager, and multiple state receivers; wherein, the low-speed protocol transmission module is used to send data from the FPGA to the microcontroller; the frame assembler is used to assemble data packets, including a data protocol frame header, frame trailer, checksum, and data; the state machine manager is used for bank state transitions; and the state receivers are used to collect the usage status of each bank module of the accelerator, the bank module including an optical port module, a DDR module, and an IO module.

[0012] As a preferred technical solution, the accelerator determines whether the bank state has been updated through a state machine, specifically:

[0013] Obtain the return status information from each monitoring module;

[0014] When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the framing module; when the state does not change, no transition occurs, and the manager waits for feedback from the accelerator state information.

[0015] The status information is framed and encapsulated according to a custom data frame format and sent to the accelerator's microcontroller via the sending module.

[0016] As a preferred technical solution, the custom data frame format is specifically as follows:

[0017] A data frame includes a data frame header, bank number, bank status, checksum, and data frame trailer;

[0018] The data frame header occupies two bytes, the bank number occupies N*2 bytes, the bank status occupies N*2 bytes, the checksum is the valid CRC value of the data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

[0019] As a preferred technical solution, after the microcontroller at the accelerator end obtains the status information reported by the accelerator via a low-speed bus, it further includes:

[0020] The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC check algorithm.

[0021] When the microcontroller at the accelerator end receives the correct information, it will look up the preset strategy stored in the microcontroller based on the received information and the bank number in the information, and complete the accelerator state adjustment so that the accelerator power consumption reaches the optimal state.

[0022] The preset strategy is as follows: a power optimization strategy is set in advance according to the bank function, and the strategy is stored in the accelerator's readable memory. When power optimization adjustment is required, the voltage and clock states are adjusted according to the optimization strategy.

[0023] As a preferred technical solution, the power consumption optimization strategy is as follows:

[0024] The clock and voltage of each FPGA bank are segmented. For resources that are not frequently used and are in an idle state, the power is turned off; for resources that are frequently used and are in an idle state, the operating clock and voltage are reduced to keep them in standby or low-power mode; and for resources that are frequently used and in operation, they are kept at full load to ensure operating efficiency.

[0025] As a preferred technical solution, the bank's operating state is adjusted according to a power consumption optimization strategy, specifically as follows:

[0026] When the bank operating clock needs to be adjusted, the clock configuration file in the readable memory must first be found based on the clock key-value pair, and then the configuration file is updated to the clock controller; when the bank operating clock does not need to be adjusted, the bank voltage state is adjusted according to the power consumption optimization strategy.

[0027] Secondly, the present invention provides an accelerator power consumption optimization system based on a hybrid regulation strategy, comprising:

[0028] Accelerators are used to speed up computation.

[0029] A processor, used to implement the steps of the accelerator power consumption optimization method based on a hybrid regulation strategy when executing the computer program.

[0030] Thirdly, the present invention provides an electronic device, characterized in that the electronic device comprises:

[0031] At least one processor; and,

[0032] A memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores computer program instructions that can be executed by the at least one processor to enable the at least one processor to perform the steps of the accelerator power consumption optimization method based on the hybrid regulation strategy.

[0034] Fourthly, the present invention provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the steps of the accelerator power consumption optimization method based on a hybrid regulation strategy.

[0035] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0036] 1. This invention adopts an out-of-band management mode. Accelerator status monitoring and control are performed through the onboard microcontroller of the accelerator. The FPGA only needs a small amount of logic resources to monitor the bank usage status. While ensuring real-time performance, it avoids the waste of logic resources and can provide more programmable resources to the user layer.

[0037] 2. This invention achieves fine-grained accelerator power consumption control. First, based on the function settings of the bank, a multi-level optimization strategy based on clock and voltage is set. Then, clock and voltage adjustment combinations are implemented for different application states, so as to achieve fine-grained power consumption optimization and control while ensuring performance.

[0038] 3. The power consumption optimization method proposed in this invention is fully implemented autonomously at the accelerator end, without the involvement of the host. When deployed in the data center, no environmental configuration or system compatibility is required, which increases the universality of use.

[0039] 4. This invention automatically adjusts the power consumption status in real time according to the accelerator's operating status, thereby reducing the energy consumption and operation and maintenance costs of the data center. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a design diagram of the accelerator in this embodiment of the present invention.

[0042] Figure 2 This is a design topology diagram of the monitoring and management system in an embodiment of the present invention.

[0043] Figure 3 This is a block diagram of the accelerator FPGA-side bank manager design in an embodiment of the present invention.

[0044] Figure 4 This is a flowchart of the accelerator power consumption optimization method based on a hybrid adjustment strategy in an embodiment of the present invention.

[0045] Figure 5 This is a block diagram of an accelerator power consumption optimization system based on a hybrid regulation strategy according to an embodiment of the present invention.

[0046] Figure 6 This is a structural diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0048] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0049] like Figure 1 The diagram shown is the accelerator design diagram of this invention. The accelerator's external interfaces are PCIe and optical ports for high-speed data transmission. The PCIe interface provides 3V3 power to the MCU, ensuring that the MCU can still monitor the board status even without external AUX power. The core computing component of the accelerator is an FPGA. To reserve more resources for user use, this invention uses only a small amount of resources to design the FPGA status monitoring module (bank manager), avoiding unnecessary resource waste. The accelerator includes multiple DDR memory modules for data caching. The power module includes an AUX 12V output and multiple cascaded DC circuits to meet the power supply requirements of 12V, 5V, 3V3, 1V8, 0V9, and 0V6. The control module uses a microcontroller as its core component, along with sensors, fans, memory, and a frequency multiplier (clock chip), to meet the power consumption management and control requirements of the accelerator.

[0050] like Figure 2The diagram shows the design topology of the monitoring and management system. In this system, each FPGA module in the accelerator, such as optical ports, DDR, I / O, and FPGA (RSVD), is connected to the bank manager within the FPGA. The bank manager sends FPGA bank status information to the microcontroller in the accelerator via low-speed signals. The microcontroller is connected to the clock control module and the power control module. The clock control module includes non-volatile memory and a frequency multiplier. The non-volatile memory stores the frequency multiplier's configuration file according to a preset strategy. The frequency multiplier is connected to each functional module of the FPGA, providing an operating clock for each module and facilitating fine-grained control. The power control module can output multiple voltages to provide voltages to each functional module of the FPGA, enabling fine-grained power control. This achieves closed-loop control of the accelerator power optimization monitoring and management system.

[0051] like Figure 3 The diagram shows the architecture block diagram of the accelerator FPGA-side bank manager. To save FPGA logic resources, the bank manager adopts a simplified design, only responsible for collecting state information, while complex processing is handled by the out-of-band microcontroller. The bank manager consists of four main parts: a low-speed protocol transmission module, a framer, a state machine manager, and a state receiver. The low-speed protocol transmission module reports state information data to the microcontroller via protocols such as SPI and I2C. The framer is responsible for assembling the collected data into packets according to the protocol and sending them to the low-speed protocol transmission module. The state machine manager is responsible for recording and transitioning the state of each bank functional module, and the state receiver receives the state information from each functional module.

[0052] like Figure 4The diagram shows the workflow of an accelerator power optimization system based on a hybrid control strategy. The process is divided into two parts: the accelerator FPGA side and the accelerator microcontroller side. The FPGA side workflow is as follows: The FPGA bank manager is in an idle state, waiting for bank status update signals. If a status update occurs, it sends a command to the bank manager's framer. The framer packages the status information into data frames according to a preset protocol, and simultaneously, the bank manager's state machine completes the state transition. Then, the low-speed transmission protocol module sends the data packaged by the framer to the microcontroller side. The microcontroller side workflow is as follows: The microcontroller waits for information reported by the bank manager in interrupt mode. If information is received, it checks the correctness of the information. If the check is incorrect, it returns to the previous process to continue waiting for information. If the information is correct, it checks whether the bank status has changed based on the bank status information contained in the information. If the bank status has not changed, it returns to continue waiting for information. If the bank status has changed, it checks the preset power optimization strategy based on the bank number and bank status in the information. If the optimization strategy includes clock updates, the clock configuration file stored in the readable storage needs to be read first, then the file is updated to the clock controller, and then the power module is adjusted; otherwise, the power module is adjusted according to the preset strategy to complete the power consumption optimization adjustment.

[0053] In one specific embodiment, the accelerator power consumption optimization method based on a hybrid regulation strategy of the present invention specifically includes the following steps:

[0054] S1. Design a bank manager on the accelerator FPGA chip side, including a low-speed protocol transmission module, a framer, a state machine manager, and multiple state receivers; among them, the low-speed protocol transmission module is used to send data from the FPGA side to the microcontroller side; the framer is used to assemble data packets, including data protocol frame header, frame trailer, checksum, data, etc.; the state machine manager is used for bank state transitions; the state receivers are used to collect the usage status of each bank module of the accelerator, including optical port module, DDR module, IO module, etc.

[0055] S2. The bank manager collects the operating status of the accelerator bank in real time. The accelerator uses a state machine to determine whether the bank status has been updated. When the bank status is updated, the data is packetized by the framer and sent to the microcontroller module through the bank manager's low-speed protocol transmission module.

[0056] Furthermore, the accelerator determines whether the bank state has been updated through a state machine, specifically:

[0057] Obtain the return status information from each monitoring module;

[0058] When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the framing module; when the state does not change, no transition occurs, and the manager waits for feedback from the accelerator state information.

[0059] The status information is framed and encapsulated according to a custom data frame format and sent to the accelerator's microcontroller via the sending module.

[0060] Furthermore, the custom data frame format is specifically as follows:

[0061] A data frame includes a data frame header, bank number, bank status, checksum, and data frame trailer;

[0062] The data frame header occupies two bytes, the bank number occupies N*2 bytes, the bank status occupies N*2 bytes, the checksum is the valid CRC value of the data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

[0063] Furthermore, after the microcontroller at the accelerator end obtains the status information reported by the accelerator via a low-speed bus, it also includes:

[0064] The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC check algorithm.

[0065] When the microcontroller at the accelerator end receives the correct information, it will look up the preset strategy stored in the microcontroller based on the received information and the bank number in the information, and complete the accelerator state adjustment so that the accelerator power consumption reaches the optimal state.

[0066] The preset strategy is as follows: a power optimization strategy is set in advance according to the bank function, and the strategy is stored in the accelerator's readable memory. When power optimization adjustment is required, the voltage and clock states are adjusted according to the optimization strategy.

[0067] S3. The microcontroller on the accelerator side responds to data from the FPGA side in interrupt mode. First, it checks the correctness of the data; if the data verification is correct, execution continues; if the data verification fails, the data packet is discarded.

[0068] S4. The microcontroller determines whether the bank state has changed based on the information. If the bank state has changed, it continues execution; if the state has not changed, it returns to step S3.

[0069] S5. The microcontroller calls the preset power optimization strategy in the microcontroller according to the bank number and its corresponding bank status in the data packet. The power optimization strategy is as follows: the clock and voltage of each bank of the FPGA are segmented. For resources that are not frequently used and are in an idle state, the power is turned off; for resources that are frequently used and are in an idle state, the running clock and voltage are reduced to maintain standby or low power mode; for resources that are frequently used and are in operation, they are kept at full load to ensure operating efficiency.

[0070] S6. Adjust the bank's operating state according to the power optimization strategy in step 5. When it is necessary to adjust the bank's operating clock, first find the clock configuration file in the readable memory according to the clock key pair, and then update the configuration file to the clock controller. When it is not necessary to adjust the bank's operating clock, adjust the bank's voltage state according to the power optimization strategy.

[0071] S7. During the execution of steps S1-S6, the microcontroller performs accelerator temperature and power consumption reading operations in parallel, and adjusts the accelerator fan speed in real time according to the power consumption and temperature information, so as to keep the power consumption of the entire accelerator in an optimal state.

[0072] Based on the same idea as the accelerator power consumption optimization method based on a hybrid regulation strategy in the above embodiments, the present invention also provides an accelerator power consumption optimization system based on a hybrid regulation strategy, which can be used to execute the above-described accelerator power consumption optimization method based on a hybrid regulation strategy. For ease of explanation, the structural schematic diagram of the embodiment of the accelerator power consumption optimization system based on a hybrid regulation strategy only shows the parts related to the embodiments of the present invention. Those skilled in the art will understand that the illustrated structure does not constitute a limitation on the device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0073] Please see Figure 5 In another embodiment of this application, an accelerator power consumption optimization system 100 based on a hybrid adjustment strategy is provided. The system includes an accelerator 101 for computing acceleration.

[0074] The processor 102 is configured to implement the steps of the accelerator power consumption optimization method based on the hybrid regulation strategy when executing the computer program.

[0075] It should be noted that the accelerator power consumption optimization system based on the hybrid regulation strategy of the present invention corresponds one-to-one with the accelerator power consumption optimization method based on the hybrid regulation strategy of the present invention. The technical features and beneficial effects described in the embodiments of the accelerator power consumption optimization method based on the hybrid regulation strategy described above are applicable to the embodiments of accelerator power consumption optimization based on the hybrid regulation strategy. For details, please refer to the description in the embodiments of the method of the present invention, which will not be repeated here.

[0076] Furthermore, in the implementation of the accelerator power optimization system based on the hybrid regulation strategy described above, the logical division of each program module is merely illustrative. In practical applications, the above functions can be assigned to different program modules as needed, for example, for the sake of corresponding hardware configuration requirements or the convenience of software implementation. That is, the internal structure of the accelerator power optimization system based on the hybrid regulation strategy can be divided into different program modules to complete all or part of the functions described above.

[0077] Please see Figure 6 In one embodiment, an electronic device is provided that implements an accelerator power consumption optimization method based on a hybrid regulation strategy. The electronic device 200 may include a first processor 201, a first memory 202 and a bus, and may also include a computer program stored in the first memory 202 and executable on the first processor 201, such as an accelerator power consumption optimization program 203 based on a hybrid regulation strategy.

[0078] The first memory 202 includes at least one type of readable storage medium, including flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the first memory 202 can be an internal storage unit of the electronic device 200, such as the portable hard drive of the electronic device 200. In other embodiments, the first memory 202 can also be an external storage device of the electronic device 200, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 200. Furthermore, the first memory 202 can include both internal storage units and external storage devices of the electronic device 200. The first memory 202 can be used not only to store application software and various types of data installed on the electronic device 200, such as the code of the accelerator power optimization program 203 based on a hybrid regulation strategy, but also to temporarily store data that has been output or will be output.

[0079] In some embodiments, the first processor 201 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The first processor 201 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the first memory 202 and calls data stored in the first memory 202 to perform various functions of the electronic device 200 and process data.

[0080] Figure 6 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 6 The structure shown does not constitute a limitation on the electronic device 200, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0081] The accelerator power optimization program 203 based on a hybrid regulation strategy stored in the first memory 202 of the electronic device 200 is a combination of multiple instructions. When run in the first processor 201, it can achieve the following:

[0082] The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator uses a state machine to determine whether the bank status has been updated; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol.

[0083] The microcontroller receives bank status information and controls the accelerator power module and clock module according to the status information through power optimization strategy to adjust the accelerator power consumption to the optimal mode; the microcontroller obtains the status information on the board and adjusts the fan speed according to the status information to achieve the optimal configuration of the overall board power consumption.

[0084] The accelerator-side bank manager is built using an FPGA, and the accelerator-side state control system consists of a microcontroller, a clock control module, and a power control module.

[0085] Furthermore, if the modules / units integrated in the electronic device 200 are implemented as software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium. The computer-readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0086] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. An accelerator power consumption optimization method based on a hybrid regulation strategy, characterized in that, Includes the following steps: The bank manager at the accelerator end collects the usage status information of each bank module of the accelerator; the accelerator uses a state machine to determine whether the bank status has been updated; when the bank status is updated, the bank manager sends the status information to the microcontroller through a low-speed transmission protocol. The microcontroller receives bank status information and controls the accelerator power module and clock module according to the status information using a power optimization strategy to adjust the accelerator power consumption to the optimal mode. Specifically, the microcontroller adjusts the bank operating state according to the power optimization strategy: when the bank operating clock needs adjustment, it first locates the clock configuration file in the readable memory based on the clock key pair, and then updates the configuration file to the clock control module; when the bank operating clock does not need adjustment, it adjusts the bank voltage state according to the power optimization strategy. The microcontroller acquires on-board status information and adjusts the fan speed according to the on-board status information to achieve optimal configuration of the overall board power consumption. The power optimization strategy is as follows: the clock and voltage of each FPGA bank are segmented; resources that are not frequently used and are idle are powered off; resources that are frequently used and are idle have their operating clock and voltage reduced to maintain standby or low-power mode; and resources that are frequently used and in operation are kept at full load to ensure operating efficiency. The accelerator-side bank manager is built using an FPGA, and the accelerator-side state control system consists of a microcontroller, a clock control module, and a power control module.

2. The accelerator power consumption optimization method based on a hybrid regulation strategy according to claim 1, characterized in that, The bank manager includes a low-speed protocol transmission module, a frame assembler, a state machine manager, and multiple state receivers. The low-speed protocol transmission module is used to send data from the FPGA to the microcontroller. The frame assembler is used to assemble data packets, including a data protocol frame header, frame trailer, checksum, and data. The state machine manager is used for bank state transitions. The state receivers are used to collect the usage status of each bank module of the accelerator. The bank modules include optical port modules, DDR modules, and IO modules.

3. The accelerator power consumption optimization method based on a hybrid regulation strategy according to claim 2, characterized in that, The accelerator determines whether the bank state has been updated through a state machine, specifically: Obtain the return status information from each monitoring module; When the state changes, the state machine manager performs the corresponding state transition and sends the state information to the framing module. If the state has not changed, no transition will occur, and the system will wait for accelerator state information feedback. The status information is framed and encapsulated according to a custom data frame format and sent to the accelerator's microcontroller via the sending module.

4. The accelerator power consumption optimization method based on a hybrid regulation strategy according to claim 3, characterized in that, The custom data frame format is specifically as follows: A data frame includes a data frame header, bank number, bank status, checksum, and data frame trailer; The data frame header occupies two bytes, the bank number occupies N*2 bytes, the bank status occupies N*2 bytes, the checksum is the valid CRC value of the data excluding the frame header and frame tail, which occupies two bytes, the data frame tail occupies two bytes, and N is the number of banks used.

5. The accelerator power consumption optimization method based on a hybrid regulation strategy according to claim 4, characterized in that, After the microcontroller at the accelerator end obtains the status information reported by the accelerator via a low-speed bus, it also includes: The microcontroller at the accelerator end verifies the received information through a built-in algorithm to determine the correctness of the information; the built-in algorithm is a CRC check algorithm. When the microcontroller at the accelerator end receives the correct information, it will look up the preset strategy stored in the microcontroller based on the bank number in the information and complete the accelerator state adjustment so that the accelerator power consumption reaches the optimal state. The preset strategy is as follows: a power optimization strategy is set in advance according to the bank function, and the strategy is stored in the accelerator's readable memory. When power optimization adjustment is required, the voltage and clock states are adjusted according to the optimization strategy.

6. An accelerator power consumption optimization system based on a hybrid regulation strategy, characterized in that, include: Accelerators are used to speed up computation. A processor for executing a computer program to implement the steps of the accelerator power consumption optimization method based on a hybrid regulation strategy as described in any one of claims 1-5.

7. An electronic device, characterized in that, The electronic device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores computer program instructions that can be executed by the at least one processor to enable the at least one processor to perform the steps of the accelerator power consumption optimization method based on a hybrid regulation strategy as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the accelerator power consumption optimization method based on a hybrid regulation strategy as described in any one of claims 1-5.

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