Gate drive circuit and display panel

Abstract

The present application discloses a gate drive circuit and display panel, wherein the gate drive circuit includes: a plurality of cascaded gate drive units, each of which includes at least: a first cascade unit connected to the gate drive unit of the previous level; a first output unit connected to the first cascade unit, for controlling the output of a scan signal according to a cascade signal of the first cascade unit; the scan signal includes a turn-on voltage and a turn-off voltage; and an overvoltage output unit connected to the first cascade unit, for outputting an overvoltage scan signal according to the cascade signal of the first cascade unit after the first output unit outputs the turn-on voltage; wherein the overvoltage scan signal is greater than the turn-off voltage of the scan signal. The above circuit shortens the blanking time and is suitable for high refresh rate panels.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate drive circuit and a display panel. Background Art

[0002] As display technology matures, high refresh rate, high-frequency dimming and ultra-narrow bezel technologies have emerged one after another. These are all technological upgrades centered around GOA (gate on array) circuits.

[0003] Similar to other display devices, OLEDs (Organic Light Emitting Displays) operate on a row refresh logic. That is, within a single frame, the driver chip sequentially outputs data signals to each row of the panel. This requires that data signals be input when the switching transistor connected to one end of the storage capacitor in the pixel circuit for that row is fully turned on. Simultaneously, data for the next row is input when the switching transistor for that row is fully turned off and the corresponding switching transistor for the pixel circuit in the next row, following the refresh direction, is turned on.

[0004] Obviously, due to the parasitic capacitance between the scanning signal lines and the gate and source / drain electrodes of the switching transistors in the panel display area, a certain recovery charging time is required for the switching transistors to reach the threshold voltage for full shutdown. Therefore, there must be a gap between the two data signal transmissions on the same data line. In other words, there must be a certain blanking time (H-Blanking) between the data signal transmissions of each two rows. Otherwise, mischarging may occur. That is, the data signal that should be charged into the n+1th row will be charged into the nth and n+1th rows because the switching transistor in the nth row is not fully closed, thus affecting the display effect. Especially when facing high refresh rate or high resolution, especially when there are many rows in the scanning direction, the charging / switching time of a frame or a row needs to be further compressed, and the demand for low H-Blanking is even greater. Summary of the Invention

[0005] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel that shorten the blank time and are suitable for high refresh panels.

[0006] To solve the above problems, the present application provides a gate drive circuit in a first aspect, wherein the gate drive circuit includes: a plurality of cascaded gate drive units, each of the gate drive units includes at least: a first cascade unit, connected to the gate drive unit of the previous level; a first output unit, connected to the first cascade unit, for controlling the output of a scan signal according to the cascade signal of the first cascade unit; the scan signal includes a start-up voltage and a cut-off voltage; an overvoltage output unit, connected to the first cascade unit, for outputting an overvoltage scan signal according to the cascade signal of the first cascade unit after the first output unit outputs the start-up voltage; wherein the overvoltage scan signal is greater than the cut-off voltage of the scan signal.

[0007] The first output unit includes a first transistor; the gate of the first transistor is connected to the output end of the first cascade unit, and the input end of the first transistor is connected to the first jump signal line; wherein the first jump signal line transmits a high / low level jump signal.

[0008] The first output unit further includes a first capacitor, a first plate of which is connected to the gate of the first transistor, the output end of the first cascade unit, and the input end of the overvoltage output unit, for storing the gate voltage charged to the first transistor.

[0009] Wherein, the overvoltage output unit includes: a bootstrap capacitor; a first control unit, arranged between the first plate of the bootstrap capacitor and the first cascade unit, for controlling the first cascade unit to charge the first plate of the bootstrap capacitor with a first voltage; a second cascade unit, the control end of which is connected to the gate drive unit of the next level, the input end of which is connected to the first signal line, and the output end of which is connected to the first plate of the bootstrap capacitor, for charging the first plate of the bootstrap capacitor with a second voltage; wherein, the second voltage is greater than the first voltage.

[0010] The overvoltage output unit includes: an overvoltage output control unit connected to the second plate of the bootstrap capacitor, and configured to control the output of the overvoltage scanning signal.

[0011] In which, the overvoltage output unit also includes: a third cascade unit, the control end of the third cascade unit is connected to the gate drive unit of the next level, the input end is connected to the first signal line, and the output end is connected to the second plate of the bootstrap capacitor, for charging the second voltage to the second plate of the bootstrap capacitor.

[0012] The third cascade unit and the overvoltage output control unit include a group of transistors with opposite driving characteristics; the third cascade unit and the second cascade unit include a group of transistors with opposite driving characteristics; the third cascade unit includes an N-type transistor.

[0013] The gate driving unit further includes: a second output unit connected to the first signal line and configured to output a cut-off voltage of the scanning signal.

[0014] Among them, the second output unit includes a second transistor and a first diode; the gate of the second transistor is connected to the first plate of the bootstrap capacitor, and the input end is connected to the first signal line, and is used to control the output of the cut-off voltage according to the voltage signal on the first plate of the bootstrap capacitor; the positive electrode of the first diode is connected to the output end of the second transistor, and the negative electrode is connected to the output end of the gate drive unit, and is used to control the output of the cut-off voltage.

[0015] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0016] The beneficial effect of the present application is that an overvoltage scan signal is provided after the scan pulse through the gate drive circuit, so that the driving transistor in the display panel can quickly return to the off state after the data voltage charging is completed, reducing the time required for the driving transistor to turn off, thereby achieving the purpose of shortening the blanking time H-blanking and avoiding display abnormalities caused by incorrect charging or erroneous charging. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 A schematic structural diagram of an embodiment of a gate drive circuit provided in this application;

[0019] Figure 2 This is a schematic structural diagram of a first specific embodiment of a gate driving unit provided in this application;

[0020] Figure 3 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in this application;

[0021] Figure 4 A schematic structural diagram of a third specific embodiment of a gate driving unit provided in this application;

[0022] Figure 5 This is a schematic structural diagram of a fourth specific embodiment of a gate driving unit provided in this application;

[0023] Figure 6 This is a schematic structural diagram of a fifth specific embodiment of a gate driving unit provided in this application;

[0024] Figure 7 A schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application;

[0025] Figure 8 A driving timing diagram of a specific embodiment of the gate driving unit provided in this application;

[0026] Figure 9 A circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application;

[0027] Figure 10 A circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application;

[0028] Figure 11 A circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application;

[0029] Figure 12 A circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application;

[0030] Figure 13 A circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in this application;

[0031] Figure 14 A schematic diagram of the circuit structure of another specific embodiment of the gate driving unit provided in this application;

[0032] Figure 15 This is a schematic structural diagram of an embodiment of a display panel provided in this application.

[0033] Explanation of symbols:

[0034] A first cascade unit 11; a first output unit 12; an overvoltage output unit 13; a first control unit 131; a second cascade unit 132; an overvoltage output control unit 133; a third cascade unit 134; a second output unit 14; an N-th gate driving unit GOA(n); a first signal line VGH; a first jump signal line CK; a second jump signal line XCK; an N-th level scan signal Pscan(n); an N-1-th level scan signal / previous level scan signal Pscan(n-1); an N+1-th level scan signal / next level scan signal Pscan(n+1); a first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a fifth transistor T5; a sixth transistor T6; a seventh transistor T7; a first capacitor C1; a bootstrap capacitor C2; a first diode D1; a display panel 100; a display area 101; and a non-display area 102. DETAILED DESCRIPTION

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0037] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0038] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0039] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0040] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0041] The charging time t across the capacitor voltage = ; t is the charging time; R is the equivalent resistance; C is the equivalent capacitance; V is the charging voltage; Vc is the charging saturation voltage. It can be seen that when The closer t is to 1, the smaller the t value, and the shorter the charging time. Specifically, the higher the charging voltage V, the shorter the charging time and the shorter the H-blanking. However, in traditional GOA circuits, the shutdown recovery charging voltage comes from a high-voltage source. The high-voltage voltage provided by ICs like TDDI (Touch and Display Driver Integration) typically has a low upper limit. To ensure that the driver transistor quickly returns to the off state after the data voltage is charged, an overvoltage charge is applied to the driver transistor, thereby shortening H-blanking.

[0042] The present application provides a gate drive circuit, which includes: a plurality of gate drive units connected in cascade. Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by this application. Figure 1 As shown, each gate driving unit GOA(n) at least includes: a first cascade unit 11 , a first output unit 12 and an overvoltage output unit 13 .

[0043] Specifically, the gate drive unit of this stage is the N-th stage gate drive unit GOA(n) as an example for explanation, where n can be a positive integer. Among them, the previous stage gate drive unit GOA(n-1) is also called the N-1-th stage gate drive unit, and the next stage gate drive unit GOA(n+1) is also called the N+1-th stage gate drive unit. It should be noted that the scan signal output by the N-th stage gate drive unit GOA(n) is the N-th stage scan signal Pscan(n), and the previous stage scan signal Pscan(n-1) is the scan signal output by the previous stage gate drive unit GOA(n-1), and therefore, it is also called the N-1-th stage scan signal, and the next stage scan signal is also called the N+1-th stage scan signal.

[0044] The first cascade unit 11 is connected to the output end of the previous-stage gate driver unit GOA(n-1) and is used to receive the scan signal Pscan(n-1) output by the previous-stage gate driver unit GOA(n-1). Specifically, the input end of the first cascade unit 11 is connected to the output end of the previous-stage gate driver unit GOA(n-1), and the output end is connected to the control end of the first output unit 12. The control end is connected to a jump signal line and is used to transmit the scan signal Pscan(n-1) of the previous stage to the control end of the first output unit 12 to control the on / off of the first output unit 12, thereby controlling the first output unit 12 to output the scan signal Pscan(n).

[0045] The control end of the first output unit 12 is connected to the output end of the first cascade unit 11. The input end of the first output unit 12 is connected to a jump signal line, and is used to control the output of the scan signal Pscan(n) according to the cascade signal transmitted by the first cascade unit 11. The cascade signal is the previous level scan signal Pscan(n-1). The scan signal Pscan(n) includes a start voltage and a cutoff voltage.

[0046] The overvoltage output unit 13 is connected to the first cascade unit 11 and is configured to output an overvoltage scanning signal according to the cascade signal of the first cascade unit 11 after the first output unit outputs the turn-on voltage.

[0047] The cutoff voltage of the scan signal refers to the voltage that causes the transistor to cut off (shut off). The scan signal includes a turn-on voltage and a cutoff voltage. The turn-on voltage, transmitted to the transistor's gate, turns on the transistor's source and drain. The cutoff voltage, transmitted to the transistor's gate, turns off the transistor's source and drain. Specifically, when the transistor is a P-type transistor, the transistor turns on at a low potential voltage and turns off at a high potential voltage. In this case, the overvoltage scan signal is a higher voltage than the high potential voltage. When the transistor is an N-type transistor, the transistor turns on at a high potential voltage and turns off at a low potential voltage. In this case, the overvoltage scan signal is a lower voltage than the low potential voltage. The overvoltage scan signal being greater than the cutoff voltage of the scan signal means that the absolute value of the overvoltage scan signal is greater than the absolute value of the cutoff voltage of the scan signal. The low potential voltage is typically negative. In other words, the overvoltage scan signal is higher than the voltage of the high potential scan signal or lower than the voltage of the low potential scan signal. When the transistor is cut off / off at a low potential, the voltage of the overvoltage scan signal is lower than the voltage of the low potential scan signal; when the transistor is cut off / off at a high potential, the voltage of the overvoltage scan signal is higher than the voltage of the high potential scan signal.

[0048] In this embodiment, the overvoltage output unit 13 outputs the overvoltage scan signal after the first output unit 12 outputs the turn-on voltage, so that the overvoltage scan signal is greater than the cut-off voltage of the scan signal, thereby accelerating the turn-off of the transistor transmitted to the surface and shortening the blank time.

[0049] In some embodiments, the transistors in the plane are P-type transistors, and the scanning signal is a low-potential pulse signal with a normal high potential. The transistor is turned on during the low-potential pulse and turned off during the high potential. In other embodiments, the transistors can also be N-type transistors, and the scanning signal is a high-potential pulse signal with a normal low potential. It should be noted that high potential and low potential are relative and are not limited to positive or negative values.

[0050] The following description is made by taking a P-type transistor as an example. In other embodiments, an N-type transistor may be used, and the corresponding timings of the signals are opposite.

[0051] For further information, please refer to Figure 2 , Figure 2 This is a schematic structural diagram of the first specific embodiment of the gate drive unit provided in this application. Figure 2 As shown, specifically, the first output unit 12 includes a first transistor T1, the gate of the first transistor T1 is connected to the output end of the first cascade unit 11, and the input end of the first transistor T1 is connected to the first jump signal line CK. The first jump signal line CK transmits high / low level jump pulses. Specifically, the first jump signal line CK outputs a high potential voltage during the sampling phase and outputs a low potential voltage during the output phase. The high potential voltage is the cut-off voltage of the scanning signal, and the low potential voltage is the start-up voltage of the scanning signal.

[0052] The first output unit 12 also includes a first capacitor C1. The first plate of the first capacitor C1 is connected to the gate of the first transistor T1 and is used to store the gate voltage charged to the first transistor T1, so that the first transistor T1 remains in an on state during both the sampling phase and the output phase. Specifically, the first plate of the first capacitor C1 is also connected to the output end of the first cascade unit 11 and the input end of the overvoltage output unit 13. The second plate of the first capacitor C1 is connected to the low-potential signal line VGL. In other embodiments, the second plate of the first capacitor C1 can also be connected to a ground line or a high-potential signal line, which is not limited here.

[0053] See further Figure 3 , Figure 3 This is a schematic diagram of the structure of the second specific embodiment of the gate drive unit provided in this application. Figure 3 As shown, the overvoltage output unit 13 includes: a bootstrap capacitor C2 , a first control unit 131 and a second cascade unit 132 .

[0054] The first plate of the bootstrap capacitor C2 is connected to the output end of the first cascade unit 11 through the first control unit 131, and the second plate of the bootstrap capacitor C2 is connected to the output end of the gate drive unit GOA(n). By increasing the voltage on the first plate of the bootstrap capacitor C2, the voltage on the second plate of the bootstrap capacitor C2 is coupled to the overvoltage scanning signal and output, so that the overvoltage output unit 13 outputs the overvoltage scanning signal.

[0055] The first control unit 131 is disposed between the first plate of the bootstrap capacitor C2 and the first cascade unit 11 , and is configured to control the first cascade unit 11 to charge the first plate of the bootstrap capacitor C2 with the first voltage V1 .

[0056] The second cascade unit 132 is connected to the first plate of the bootstrap capacitor C2 and is configured to charge the first plate of the bootstrap capacitor C2 with a second voltage V2. The second voltage V2 is greater than the first voltage V1. Specifically, during the output phase, the first control unit 131 controls the first plate of the bootstrap capacitor C2 to charge the first voltage V1. During the overvoltage phase following the output phase, the second cascade unit 132 charges the first plate of the bootstrap capacitor C2 with the second voltage V2, thereby coupling the second plate of the bootstrap capacitor C2 to the voltage corresponding to the overvoltage scan signal.

[0057] In one embodiment, the control terminal of the second cascade unit 132 is connected to the output terminal of the next-stage gate driver unit GOA(n+1), the input terminal is connected to the first signal line VGH, and the output terminal is connected to the first plate of the bootstrap capacitor C2. This is used to control the second cascade unit 132 to charge the second voltage V2 into the first plate of the bootstrap capacitor C2 according to the scan signal Pscan(n+1) output by the next-stage gate driver unit GOA(n+1) during the overvoltage phase. In this embodiment, the first signal line VGH is a high-potential signal line for transmitting a high-potential voltage. In other embodiments, the first signal line VGH may also transmit other constant voltages, which is not limited here.

[0058] For further information, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the third specific embodiment of the gate drive unit provided in this application. In a further embodiment, the overvoltage output unit 13 further includes an overvoltage output control unit 133. The overvoltage output control unit 133 is disposed between the second plate of the bootstrap capacitor C2 and the output terminal of the gate drive unit GOA(n) and is used to control the output of the overvoltage output unit 13. Specifically, the overvoltage output unit 13 is turned on during the overvoltage phase and turned off during other phases.

[0059] In a preferred embodiment, the control terminal of the overvoltage output control unit 133 and the control terminal of the second cascade unit 132 are connected to the same control signal line, that is, both are connected to the output terminal of the next-stage gate drive unit GOA(n+1). The output of the overvoltage output unit 13 is controlled according to the next-stage scan signal Pscan(n+1). Specifically, the overvoltage output control unit 133 turns on when the next-stage scan signal Pscan(n+1) outputs a low-voltage pulse, thereby outputting the overvoltage scan signal during the overvoltage phase (i.e., after the output phase). In other embodiments, the control terminal of the overvoltage output control unit 133 may also be controlled by other control signal lines, which are not limited here. In this specific embodiment, the transistors in the overvoltage output control unit 133 are P-type transistors.

[0060] The transistors in the second cascade unit 132 are also P-type transistors.

[0061] The specific driving stage in the above embodiment includes a sampling stage, an output stage and an overvoltage stage. In the sampling stage, the first cascade unit 11 controls the first output unit 12 to output a high potential voltage. In the output stage, the first cascade unit 11 controls the first output unit 12 to output a low potential voltage. In the output stage, the first control unit 131 transmits the cascade signal stored on the first capacitor C1 to the first plate of the bootstrap capacitor C2. At this time, the cascade signal is a low potential voltage, and the first voltage V1 stored on the first plate of the bootstrap capacitor C2 is a low potential voltage. In the overvoltage stage, the second cascade unit 132 charges the first plate of the bootstrap capacitor C2 with a second voltage V2, and the second voltage V2 is a high potential voltage. At the same time, the overvoltage output control unit 133 transmits the voltage on the second plate of the bootstrap capacitor C2 to the output end.

[0062] For further information, please refer to Figure 5 , Figure 5 This is a schematic structural diagram of the fourth specific embodiment of the gate drive unit provided in this application. Figure 5As shown, the overvoltage output unit 13 further includes a third cascade unit 134. The control terminal of the third cascade unit 134 is connected to the output terminal of the next-stage gate driver unit GOA(n+1), the input terminal is connected to the first signal line VGH, and the output terminal is connected to the second plate of the bootstrap capacitor C2. The third cascade unit 134 is configured to charge the second plate of the bootstrap capacitor C2 with a second voltage V2 during the output phase. The second voltage V2 is a high-potential voltage, that is, a starting voltage is charged to the second plate of the bootstrap capacitor C2 so that it is coupled to the overvoltage voltage during the overvoltage phase. In other embodiments, during the sampling phase, the overvoltage output control unit 133 may charge the second plate of the bootstrap capacitor C2 with a high-potential voltage, and preferably, the first control unit 131 may simultaneously charge the first plate of the bootstrap capacitor C2 with a low-potential voltage. That is, during the sampling phase, the first control unit 131 and the overvoltage output control unit 133 are turned on, thereby charging voltages to the first and second plates of the bootstrap capacitor C2, respectively. In the output phase, the first control unit 131 and the overvoltage output control unit 133 are turned off, so that the first plate and the second plate of the bootstrap capacitor C2 are suspended, thereby maintaining the voltage stored on the bootstrap capacitor C2.

[0063] The transistors in the third cascade unit 134, the second cascade unit 132, and the overvoltage output control unit 133 are a group of transistors with opposite driving characteristics. Specifically, the transistors in the third cascade unit 134 are N-type transistors, and the transistors in the second cascade unit 132 and the overvoltage output control unit 133 are P-type transistors.

[0064] Furthermore, the gate drive unit further includes a second output unit 14, which is provided between the first signal line and the output terminal of the gate drive unit GOA(n) and is used to output a high potential voltage (i.e., a cut-off voltage) after the overvoltage stage to keep the transistors in the plane in the cut-off state. Figure 6 , Figure 6 This is a schematic structural diagram of the fifth specific embodiment of the gate drive unit provided in this application. Figure 6 As shown, the second output unit 14 includes a second transistor T2 and a first diode D1.

[0065] The gate of the second transistor T2 is connected to the first plate of the bootstrap capacitor C2, the input end is connected to the first signal line VGH, and the output end is connected to the output end of the gate drive unit GOA(n). It is used to control the conduction of the second transistor T2 according to the voltage signal on the first plate of the bootstrap capacitor C2, and further control its output cut-off voltage (high potential voltage).

[0066] The anode of the first diode D1 is connected to the output end of the second transistor T2 , and the cathode is connected to the output end of the gate driving unit GOA(n) for controlling its output cut-off voltage.

[0067] Specifically, the second transistor T2 is turned on during the overvoltage stage and the stage after the overvoltage stage to output a high potential voltage. It should be noted that during the overvoltage stage, since the voltage output by the overvoltage output unit 13 is greater than the high potential voltage output by the second transistor T2, the first diode D1 has a cutoff effect.

[0068] In a specific embodiment, the control terminal of the first cascade unit 11 is connected to the second jump signal line XCK. The second jump signal line XCK and the first jump signal line CK are a set of high / low level jump signals with the same frequency and opposite phases.

[0069] This application provides a circuit structure of a gate drive unit. Please refer to Figure 7 , Figure 7 This is a schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application. Figure 7 shown.

[0070] The first output unit 12 includes a first transistor T1 and a first capacitor C1. The second output unit 14 includes a second transistor T2 and a first diode D1. The first cascade unit 11 includes a third transistor T3. The first control unit 131 includes a fourth transistor T4. The second cascade unit 132 includes a fifth transistor T5. The overvoltage output control unit 133 includes a sixth transistor T6. The third cascade unit 134 includes a seventh transistor T7.

[0071] The second transistor T2 and the seventh transistor T7 are N-type transistors, and the remaining transistors are P-type transistors.

[0072] This application also provides a driving timing diagram of a specific embodiment of a gate driving unit. Figure 8 , Figure 8 This is a driving timing diagram of a specific embodiment of the gate drive unit provided in this application. The driving phase includes a sampling phase (first phase), an output phase (second phase), an overvoltage phase (third phase), and a holding phase (fourth and fifth phases). For further details, please refer to Figures 9 to 13 . Figure 9 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 10 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 11 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 12 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 13 This is a circuit diagram of the fifth driving stage of a specific embodiment of the gate driving unit provided in this application.

[0073] During the sampling phase, the previous scan signal Pscan(n-1) transmits a low-level signal, the next scan signal Pscan(n+1) transmits a high-level signal, the first jump signal line CK transmits a high-level signal, the second jump signal line XCK transmits a low-level signal, and the first signal line VGH transmits a high-level signal. The third transistor T3 is turned on, the fourth transistor T4 is turned off, and the previous scan signal Pscan(n-1) transmits a low-level signal to the gate of the first transistor T1 and the first plate of the first capacitor C1 through the third transistor T3. The first transistor T1 is turned on, and the first jump signal line CK outputs a high-level signal to the output terminal of the gate driver unit GOA(n) through the first transistor T1. At the same time, the high-potential signal of the next-stage scan signal Pscan(n+1) controls the seventh transistor T7 to turn on, charging the second plate of the bootstrap capacitor C2 with a high-potential signal. The first plate of the bootstrap capacitor C2 stores a high-potential signal in the previous stage and transmits the high-potential signal to the gate of the second transistor T2. The second transistor T2 is turned on, and the first signal line VGH outputs a high-potential signal to the output terminal of the gate driver unit GOA(n) through the second transistor T2 and the first diode D1. It should be noted that whether a high potential is stored on the first plate of the bootstrap capacitor C2, the output terminal of the gate driver unit GOA(n) outputs a high-potential signal. For details, please refer to Figure 9 , Figure 9 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0074] During the output phase, the previous-stage scan signal Pscan(n-1) transmits a high-potential signal, the next-stage scan signal Pscan(n+1) transmits a high-potential signal, the first jump signal line CK transmits a low-potential signal, the second jump signal line XCK transmits a high-potential signal, and the first signal line VGH transmits a high-potential signal. The gate of the first transistor T1 remains conductive due to the action of the first capacitor C1. The first jump signal line CK outputs a low-potential signal to the output terminal of the gate drive unit GOA(n) through the first transistor T1. The third transistor T3 is turned off, and the fourth transistor T4 is turned on. The low-potential signal stored in the first capacitor C1 in the previous phase is transmitted to the first plate of the bootstrap capacitor C2 through the fourth transistor T4. At the same time, the high-potential signal of the next-stage scan signal Pscan(n+1) controls the seventh transistor T7 to turn on, charging the second plate of the bootstrap capacitor C2 with a high-potential signal. At this time, the potential difference between the first and second plates of the bootstrap capacitor C2 is Pscan(n-1)L-VGH. For details, please refer to Figure 10 , Figure 10 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0075] During the overvoltage phase, the previous-stage scan signal Pscan(n-1) transmits a high-potential signal, the next-stage scan signal Pscan(n+1) transmits a low-potential signal, the first jump signal line CK transmits a high-potential signal, the second jump signal line XCK transmits a low-potential signal, and the first signal line VGH transmits a high-potential signal. The third transistor T3 is turned on, the fourth transistor T4 is turned off, and the high-potential signal of the previous-stage scan signal Pscan(n-1) is transmitted to the gate of the first transistor T1 and the first plate of the first capacitor C1 through the third transistor T3. The first transistor T1 is turned off. At the same time, the low-potential signal of the next-stage scan signal Pscan(n+1) controls the seventh transistor T7 to be turned off, controls the fifth transistor T5 and the sixth transistor T6 to be turned on, and the first signal line VGH charges the high-potential signal to the first plate of the bootstrap capacitor C2 through the fifth transistor T5. According to the KVL law, the voltage on the second plate of the bootstrap capacitor C2 is coupled to VGH - Pscan(n-1)L + VGL = 2VGH - Pscan(n-1)L > VGH. At this point, Pscan(n-1)L represents the low-potential signal (low-potential voltage) of the previous-stage scan signal Pscan(n-1), which is a negative value. Furthermore, Pscan(n-1)L represents the low-potential pulse transmitted on the first jump signal line CK, which is also Vck(L). The voltage on the second plate of the bootstrap capacitor C2 is transmitted to the output terminal of the gate driver unit GOA(n) via the sixth transistor T6, thereby outputting an overvoltage scan signal higher than the high-potential scan signal to the output terminal of the gate driver unit GOA(n). Simultaneously, the high-potential signal on the first plate of the bootstrap capacitor C2 is transmitted to the gate of the second transistor T2, turning on the second transistor T2. At this point, the voltage of the overvoltage scan signal output from the second plate of the bootstrap capacitor C2 is greater than the anode of the first diode D1, turning off the first diode D1. For details, please refer to [Note: The following sentences appear to be unrelated and should likely be omitted.] Figure 11 , Figure 11 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0076] During the first hold phase of the hold phase, the previous scan signal Pscan(n-1) transmits a high-voltage signal, the next scan signal Pscan(n+1) transmits a high-voltage signal, the first jump signal line CK transmits a low-voltage signal, the second jump signal line XCK transmits a high-voltage signal, and the first signal line VGH transmits a high-voltage signal. The third transistor T3 is turned off, the fourth transistor T4 is turned on, and the high-voltage signal stored on the first plate of the first capacitor C1 is transmitted to the first plate of the bootstrap capacitor C2 via the fourth transistor T4 and then to the gate of the second transistor T2, controlling the conduction of the second transistor T2. The first signal line VGH outputs a high-voltage scan signal to the output terminal of the gate drive unit GOA(n) via the second transistor T2. The high-voltage signal of the next scan signal Pscan(n+1) controls the conduction of the seventh transistor T7 and the turn-off of the fifth and sixth transistors T5 and T6. The first signal line VGH charges the second plate of the bootstrap capacitor C2 with a high-voltage signal via the seventh transistor T7, enabling the bootstrap capacitor C2 to maintain its storage function. For details, please refer to [ 15 ] Figure 12 , Figure 12 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0077] During the second hold phase of the hold stage, the previous scan signal Pscan(n-1) transmits a high-potential signal, the next scan signal Pscan(n+1) transmits a high-potential signal, the first jump signal line CK transmits a high-potential signal, the second jump signal line XCK transmits a low-potential signal, and the first signal line VGH transmits a high-potential signal. The high-potential signal of the next scan signal Pscan(n+1) controls the seventh transistor T7 to turn on, and the fifth transistor T5 and the sixth transistor T6 to turn off. The first signal line VGH charges the second plate of the bootstrap capacitor C2 with a high-potential signal through the seventh transistor T7, enabling the bootstrap capacitor C2 to maintain its storage function. This allows the high-potential signal stored on the first plate of the bootstrap capacitor C2 to be maintained and then transmitted to the gate of the second transistor T2, controlling the second transistor T2 to remain on. The first signal line VGH outputs a high-potential scan signal to the output terminal of the gate drive unit GOA(n) through the second transistor T2. For details, please refer to [ 15 ] for details. Figure 13 , Figure 13 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0078] Before the current frame is completely refreshed, the gate drive unit will continue to work alternately according to the first hold phase h1 and the second hold phase h2 according to the signals on the first jump signal line CK and the second jump signal line XCK, and the scanning signal Pscan(n) will continue to output the high potential signal Vgh, thereby achieving the design purpose.

[0079] This application also provides another circuit structure of the gate drive unit, please refer to Figure 14 , Figure 14 This is a circuit diagram of another specific embodiment of the gate drive unit provided in this application. Figure 14 As shown, each gate driving unit further includes a third capacitor C3 and an eighth transistor T8 , and the first plate of the third capacitor C3 is connected to the output end of the first cascade unit 11 (third transistor T3 ) and the input end of the overvoltage output unit 13 (fourth transistor T4 ).

[0080] It should be noted that the third capacitor C3 improves the stability of the first capacitor C1. During the output phase (second phase), if only one first capacitor C1 were present, it would both drive the first transistor T1 and charge the bootstrap capacitor C2. This could cause voltage jumps on the first capacitor C1, and consequently, on the gate voltage of the first transistor T1. Furthermore, the provision of the third capacitor C3 significantly reduces the charging path of the bootstrap capacitor C2, increases driving force, and improves response efficiency.

[0081] The eighth transistor T8 has an input connected to the first signal line VGH, an output connected to the second plate of the bootstrap capacitor C2, and a control terminal connected to the first transition signal line CK. The eighth transistor T8 is conductive during the second phase (output phase) and the fourth phase (first hold phase). The eighth transistor T8 serves as a backup transistor for the seventh transistor T7. For image quality reasons, the gate driver unit GOA(n) is often "precharged," a common practice in LCD display panels. During this time, the rising and falling edges of the waveforms on the second transition signal line XCK and the first transition signal line CK do not completely coincide. This means that when the Nth-stage gate driver unit GOA(n) is at a low voltage, the N+1th-stage gate driver unit GOA(n+1) may also be at a low voltage. During this time, the seventh transistor T7 may be weakly conductive or have a slow response rate. Therefore, when the Nth-stage gate driver unit GOA(n) is outputting, an additional eighth transistor T8 branch is added as a backup charging path for output stability.

[0082] It should be noted that, in an ideal (standard) cycle, the eighth transistor T8 can be omitted.

[0083] This application also provides a display panel. Figure 15 , Figure 15 This is a schematic diagram of the structure of an embodiment of a display panel provided by this application. Figure 15As shown, the display panel 100 includes a display area 101 and a non-display area 102. The non-display area 102 on one side or opposite sides of the display panel 100 is provided with a gate drive circuit as described in any of the above embodiments. The gate drive circuit includes a plurality of cascaded gate drive units. The gate drive circuit transmits a scan signal Pscan(n) to each row of pixel units in the display area 101 in sequence. The scan signal Pscan(n) includes a high-potential scan signal, a low-potential scan signal, and an overvoltage scan signal. In this specific embodiment, the overvoltage scan signal is higher than the high-potential scan signal.

[0084] In the above embodiment, all transistors in the gate drive circuit are P-type transistors. In other embodiments, they may all be N-type transistors, which is not limited here.

[0085] The present application uses the above-mentioned gate drive circuit to provide an overvoltage scan signal after the scan pulse (a low-voltage signal used to turn on the transistor), so that the driving transistor in the display panel can quickly return to the off state after the data voltage charging is completed, reducing the time required to turn off the driving transistor, thereby achieving the purpose of shortening the blanking time H-blanking and avoiding display abnormalities caused by incorrect charging or erroneous charging.

[0086] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of the gate drive units comprising at least: A first cascade unit connected to the gate driving unit of the previous stage; a first output unit connected to the first cascade unit, configured to control an output scan signal according to a cascade signal of the first cascade unit; the scan signal includes a start voltage and a cut-off voltage; an overvoltage output unit connected to the first cascade unit, configured to output an overvoltage scanning signal according to the cascade signal of the first cascade unit after the first output unit outputs the turn-on voltage; wherein the overvoltage scanning signal is greater than the cut-off voltage of the scanning signal; specifically, the overvoltage output unit includes a bootstrap capacitor, a first control unit, and a second cascade unit, wherein the first plate of the bootstrap capacitor is connected to the first control unit and the output end of the first cascade unit, and the second plate of the bootstrap capacitor is connected to the output end of the gate drive unit; the first control unit is arranged between the first plate of the bootstrap capacitor and the first cascade unit, and is configured to control the first cascade unit to charge a first voltage into the first plate of the bootstrap capacitor; the control end of the second cascade unit is connected to the gate drive unit of the next stage, the input end is connected to the first signal line, and the output end is connected to the first plate of the bootstrap capacitor, and is configured to charge a second voltage into the first plate of the bootstrap capacitor during the overvoltage stage; wherein the second voltage is greater than the first voltage, so as to increase the voltage on the first plate of the bootstrap capacitor, thereby causing the voltage on the second plate of the bootstrap capacitor to output the overvoltage scanning signal.

2. The gate drive circuit according to claim 1, wherein: The first output unit includes a first transistor; The gate of the first transistor is connected to the output end of the first cascade unit, the input end of the first transistor is connected to the first jump signal line, and the output end of the first transistor is connected to the output end of the gate driving unit; wherein, the first jump signal line transmits a high / low level jump signal.

3. The gate drive circuit according to claim 2, wherein: The first output unit also includes a first capacitor, the first plate of the first capacitor is connected to the gate of the first transistor, the output end of the first cascade unit and the input end of the overvoltage output unit, and is used to store the gate voltage charged to the first transistor, and the second plate of the first capacitor is connected to a fixed potential signal line.

4. The gate drive circuit according to claim 1, wherein: The overvoltage output unit includes: An overvoltage output control unit is connected to the second electrode plate of the bootstrap capacitor and is used to control the output of the overvoltage scanning signal.

5. The gate driving circuit according to claim 4, wherein: The overvoltage output unit further includes: A third cascade unit, wherein the control end of the third cascade unit is connected to the gate drive unit of the next stage, the input end is connected to the first signal line, and the output end is connected to the second plate of the bootstrap capacitor, and is used to charge the second voltage to the second plate of the bootstrap capacitor.

6. The gate driving circuit according to claim 5, wherein: The third cascade unit and the overvoltage output control unit include a group of transistors with opposite driving characteristics; The third cascade unit and the second cascade unit include a group of transistors with opposite driving characteristics; Wherein, the third cascade unit includes an N-type transistor.

7. The gate driving circuit according to claim 1, wherein: The gate driving unit further includes: The second output unit is connected to the first signal line and is used to output a cut-off voltage of the scanning signal.

8. The gate driving circuit according to claim 7, wherein: The second output unit includes a second transistor and a first diode; The gate of the second transistor is connected to the first plate of the bootstrap capacitor, and the input end is connected to the first signal line, and is used to control the output of the cut-off voltage according to the voltage signal on the first plate of the bootstrap capacitor; The anode of the first diode is connected to the output end of the second transistor, and the cathode is connected to the output end of the gate driving unit, and is used to control the output of the cut-off voltage.

9. A display panel, characterized in that: The display panel includes the gate driving circuit according to any one of claims 1 to 8.

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