Display panel and display device
By setting different data writing transistor channel area width and length ratios for subpixels of different luminous colors in the display panel, the problem of difficult to improve display quality and reliability simultaneously is solved, and higher brightness uniformity and lower leakage flow are achieved.
Patent Information
- Application Number
- CN202510104072.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-16
Smart Images
Figure CN120014983A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art
[0002] With the continuous development of display technology, organic light-emitting diode (OLED) display devices have been widely used in many fields such as flat panel display, flexible display, vehicle display and solid-state lighting due to their advantages such as wide color gamut, high contrast, energy saving and foldability. The OLED display panel includes a substrate and a plurality of sub-pixels arranged on the substrate, and the plurality of sub-pixels can display images.
[0003] However, the prior art has the problem that it is difficult to improve both display quality and reliability at the same time. Summary of the invention
[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to solve the problem in the prior art that it is difficult to improve both display quality and reliability at the same time.
[0005] In a first aspect, an embodiment of the present application provides a display panel, including a plurality of sub-pixels, wherein the sub-pixels include an electrically connected pixel circuit and a light-emitting element, and the pixel circuit includes:
[0006] A driving module, wherein the driving module and the light emitting element are electrically connected between the first power line and the second power line in sequence, and the driving module is configured to provide a driving current to the light emitting element;
[0007] A data writing module, comprising a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to a data signal line, a second electrode of the data writing transistor is electrically connected to a first end of the driving module, and the data writing module is configured to write a data signal to the first end of the driving module during a data writing phase;
[0008] The plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel, and the light-emitting color of the first sub-pixel is different from the light-emitting color of the second sub-pixel;
[0009] The width-to-length ratio of the channel region of the data writing transistor in the first sub-pixel is E1, and the width-to-length ratio of the channel region of the data writing transistor in the second sub-pixel is E2; wherein E1 is different from E2.
[0010] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.
[0011] In an embodiment of the present application, in a display panel, a plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel, the luminous color of the first sub-pixel is different from the luminous color of the second sub-pixel; the width-to-length ratio of the channel region of the data write transistor in the first sub-pixel is E1, and the width-to-length ratio of the channel region of the data write transistor in the second sub-pixel is E2; wherein E1 and E2 are set differently. That is, for the first sub-pixel and the second sub-pixel of different luminous colors, the channel region of the data write transistor is set to have a different width-to-length ratio to adapt to the different data signal voltages required by the first sub-pixel and the second sub-pixel of different luminous colors, including but not limited to, at least under 255 grayscale, the voltage of the data signal line in the first sub-pixel is less than the voltage of the data signal line in the second sub-pixel, and E1>E2 is set. 1) In the first aspect, a larger width-to-length ratio (larger E1) is set for the sub-pixel with a small driving voltage (the voltage of the data signal line is small) to increase the current in the corresponding data write transistor, so that the charging current of the voltage of the data signal line to charge the first node N1 (for example, the gate of the driving transistor) increases, thereby improving the brightness of the sub-pixel with a small driving voltage, and the display uniformity of the display panel is improved (for example, the brightness uniformity is improved), the power consumption of the driving chip is reduced, and the display quality is improved. 2) Secondly, a smaller aspect ratio (smaller E2) is set for sub-pixels with high driving voltage (high voltage on data signal lines) to reduce leakage of sub-pixels with high driving voltage to other unopened pixel circuits, thus avoiding or improving display anomalies such as four-split screen or black rings, and improving reliability. Through these two differentiated settings, both display quality and reliability are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0013] Figure 1 A first schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0014] Figure 2 A second schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0015] Figure 3 A third schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0016] Figure 4 A fourth schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0017] Figure 5 A fifth schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0018] Figure 6 A schematic diagram of a display device provided in some embodiments of the present application.
[0019] Reference numerals:
[0020] Display panel 100; sub-pixel 10P; pixel circuit 101; light emitting element 102; data writing module 10; driving module 20; threshold compensation module 30; light emitting control module 40; first light emitting control module 401; second light emitting control module 402; storage module 50; first reset module 60; second reset module 70; bias adjustment module 80;
[0021] a first power line PVDD; a second power line PVEE; a data signal line DATA; a first reset scan signal line SP1; a compensation scan signal line SP2; a first initialization signal line VREF1; a second initialization signal line VREF2; a second reset scan signal line SPX; a first bias scan signal line SPY; a first light emission control scan signal line EMIT1; a second light emission control scan signal line EMIT2; a bias signal line DVH;
[0022] A first light-emitting control transistor M1; a data writing transistor M2; a driving transistor M3; a compensation transistor M4; a first reset transistor M5; a second light-emitting control transistor M6; a second reset transistor M7; a bias transistor M8; a storage capacitor Cst; a first node N1; a second node N2; a third node N3; a fourth node N4; a first sub-pixel 10P1; a second sub-pixel 10P2; a first light-emitting element 102a; a second light-emitting element 102b; a first pixel circuit 101a; and a second pixel circuit 101b. DETAILED DESCRIPTION
[0023] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.
[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0025] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.
[0026] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be construed as being one in number.
[0027] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.
[0028] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.
[0029] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.
[0030] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.
[0031] As described in the background technology section, there is a problem in the prior art that it is difficult to improve both display quality and reliability at the same time. The inventor found that the reason for the above phenomenon is that in the pixel circuit, the data signal is written into the pixel circuit through the data writing transistor of the data writing module. When the width-to-length ratio (W / L value) of the data writing transistor is too large, the data signal in part of the screen (for example, a black screen) cannot be turned off by the data writing transistor, and the current in the turned-on pixel circuit will leak into other unturned pixel circuits, resulting in display anomalies such as a four-split screen or a black ring, leading to reliability problems; when the width-to-length ratio (W / L value) of the data writing transistor is too small, the charging current of the data signal to the first node N1 (for example, the gate of the driving transistor) will be reduced, the display uniformity of the display panel will decrease (for example, the brightness uniformity will decrease), and the power consumption of the driving chip will increase, resulting in a decrease in the display quality of the display panel, that is, the problem that it is difficult to improve both display quality and reliability at the same time has occurred.
[0032] Based on the above technical problems, the inventors have found that in a display panel, multiple sub-pixels include at least a first sub-pixel and a second sub-pixel, and the luminous color of the first sub-pixel is different from the luminous color of the second sub-pixel; the width-to-length ratio of the channel region of the data write transistor in the first sub-pixel is E1, and the width-to-length ratio of the channel region of the data write transistor in the second sub-pixel is E2; wherein, E1 and E2 are set differently. That is, for the first sub-pixel and the second sub-pixel of different luminous colors, the channel region of the data write transistor is set to have a different width-to-length ratio to adapt to the different data signal voltages required by the first sub-pixel and the second sub-pixel of different luminous colors, including but not limited to, at least under 255 grayscale, the voltage of the data signal line in the first sub-pixel is less than the voltage of the data signal line in the second sub-pixel, and E1>E2 is set. 1) In the first aspect, a larger width-to-length ratio (larger E1) is set for the sub-pixel with a small driving voltage (the voltage of the data signal line is small) to increase the current in the corresponding data write transistor, so that the charging current of the voltage of the data signal line to charge the first node N1 (for example, the gate of the driving transistor) increases, thereby improving the brightness of the sub-pixel with a small driving voltage, and the display uniformity of the display panel is improved (for example, the brightness uniformity is improved), the power consumption of the driving chip is reduced, and the display quality is improved. 2) Secondly, a smaller aspect ratio (smaller E2) is set for sub-pixels with high driving voltage (high voltage on data signal lines) to reduce leakage of sub-pixels with high driving voltage to other unopened pixel circuits, thus avoiding or improving display anomalies such as four-split screen or black rings, and improving reliability. Through these two differentiated settings, both display quality and reliability are improved.
[0033] See also Figures 1 to 5 . Figure 1 A first schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application. Figure 2 A second schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application. Figure 3 A third schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application. Figure 4 A fourth schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application. Figure 5 A fifth schematic diagram of a pixel circuit of a display panel provided in some embodiments of the present application.
[0034] It should be noted that Figure 1 and Figure 3 Schematic diagram of a pixel circuit of a first sub-pixel (first pixel circuit 101a), Figure 2 and Figure 4 The pixel circuit of the second sub-pixel (the second pixel circuit 101b) is shown. Figure 1 , Figure 3 It is shown that the first pixel circuit 101a further includes a bias adjustment module 80. Figure 2 , Figure 4 The second pixel circuit 101b further includes a bias adjustment module 80. Figures 1 to 4 , Figure 5 1 and 2. It is illustrated that in the first pixel circuit 101a, the first reset transistor M5 includes a first sub-reset transistor M5_1 and a second sub-reset transistor M5_2, and the compensation transistor M4 includes a first sub-compensation transistor M4_1 and a second sub-compensation transistor M4_2.
[0035] The present application provides a display panel 100, which includes a plurality of sub-pixels 10P. The sub-pixels 10P include an electrically connected pixel circuit 101 and a light-emitting element 102. The pixel circuit 101 includes a driving module 20 and a data writing module 10. The driving module 20 and the light-emitting element 102 are electrically connected between a first power line PVDD and a second power line PVEE in sequence. The driving module 20 is configured to provide a driving current to the light-emitting element 102. The data writing module 10 includes a data writing transistor M2. The first electrode of the data writing transistor M2 is electrically connected to a data signal line DATA. The second electrode of the data writing transistor M2 is electrically connected to a first end of the driving module 20. The data writing module 10 is configured to write a data signal to the first end of the driving module 20 during a data writing phase. The plurality of sub-pixels 10P include at least a first sub-pixel 10P1 and a second sub-pixel 10P2. The light-emitting color of the first sub-pixel 10P1 is different from the light-emitting color of the second sub-pixel 10P2. The width-to-length ratio of the channel region of the data writing transistor M2 in the first sub-pixel 10P1 is E1, and the width-to-length ratio of the channel region of the data writing transistor M2 in the second sub-pixel 10P2 is E2; wherein E1 is different from E2.
[0036] For example, Figure 1 and Figure 2 As shown, or as Figure 3 and Figure 4 As shown, the display panel 100 includes a plurality of sub-pixels 10P, and the plurality of sub-pixels 10P include a first sub-pixel 10P1 and a second sub-pixel 10P2; the luminous color of the first sub-pixel 10P1 is different from the luminous color of the second sub-pixel 10P2. For example, the luminous color of the first sub-pixel 10P1 is blue, and the luminous color of the second sub-pixel 10P2 is red. For example, the luminous color of the first sub-pixel 10P1 is blue, and the luminous color of the second sub-pixel 10P2 is green.
[0037] For example, Figure 1 and Figure 3 As shown, the first sub-pixel 10P1 includes a first pixel circuit 101a and a first light-emitting element 102a; Figure 2 and Figure 4 As shown, the second subpixel 10P2 includes a second pixel circuit 101b and a second light-emitting element 102b. For example, the first light-emitting element 102a is a blue light-emitting device, and the second light-emitting element 102b is a red light-emitting device. For example, the first light-emitting element 102a is a blue light-emitting device, and the second light-emitting element 102b is a green light-emitting device.
[0038] For example, the driving module 20 and the light emitting element 102 are electrically connected between the first power line PVDD and the second power line PVEE in sequence, and the driving module 20 is configured to provide a driving current to the light emitting element 102. That is, the first power line PVDD, the driving module 20, the light emitting element 102, and the second power line PVEE are electrically connected in sequence.
[0039] Illustratively, the first power line PVDD provides a first power signal or a first power voltage, and the second power line PVEE provides a second power signal or a second power voltage.
[0040] For example, the light emitting element 102 includes an anode and a cathode, the first power line PVDD can provide an electrical signal to one of the anode and the cathode, and the second power line PVEE can provide an electrical signal to the other of the anode and the cathode. In this application, the first power line PVDD provides an electrical signal to the anode, and the second power line PVEE provides an electrical signal to the cathode.
[0041] For example, Figure 1 and Figure 3 As shown, in the first pixel circuit 101a, the data writing transistor M2 included in the data writing module 10 is a first data writing transistor M2a, a first electrode of the first data writing transistor M2a is electrically connected to the first data signal line DATA1, and a second electrode of the first data writing transistor M2a is electrically connected to the first end of the driving module 20.
[0042] For example, Figure 2 and Figure 4 As shown, in the second pixel circuit 101b, the data writing transistor M2 included in the data writing module 10 is a second data writing transistor M2b, a first electrode of the second data writing transistor M2b is electrically connected to the second data signal line DATA2, and a second electrode of the second data writing transistor M2b is electrically connected to the first end of the driving module 20.
[0043] For example, Figure 1 and Figure 3 As shown, the width-to-length ratio of the channel region of the data writing transistor M2 in the first sub-pixel 10P1 is E1, that is, the width-to-length ratio of the first data writing transistor M2a is E1.
[0044] For example, Figure 2 and Figure 4 As shown, the width-to-length ratio of the channel region of the data writing transistor M2 in the second sub-pixel 10P2 is E2, that is, the width-to-length ratio of the second data writing transistor M2b is E2.
[0045] For example, compare Figure 1 and Figure 2 , or compare Figure 3 and Figure 4 , E1 is different from E2, that is, the width-to-length ratio of the first data writing transistor M2a and the width-to-length ratio of the second data writing transistor M2b is different.
[0046] For example, the data signal line DATA provides a data signal. The first data signal line DATA1 provides a first data signal to the first data write transistor M2a, and the second data signal line DATA2 provides a second data signal to the second data write transistor M2b.
[0047] For example, the luminous color of the first sub-pixel 10P1 is different from the luminous color of the second sub-pixel 10P2, so that at least partially the same grayscale, the voltage in the first data signal line DATA1 is different from the voltage in the second data signal line DATA2, that is, at at least partially the same grayscale, the driving voltages of the first light-emitting element 102a and the second light-emitting element 102b are different, the driving voltages of the first sub-pixel 10P1 and the second sub-pixel 10P2 are different, and E1 and E2 are set differently, so that the width-to-length ratio of the data write transistor M2 matches the driving voltage of the corresponding light-emitting element 102, so that different sub-pixels 10P can achieve the best display effect.
[0048] In an embodiment of the present application, in the display panel 100, a plurality of sub-pixels 10P include at least a first sub-pixel 10P1 and a second sub-pixel 10P2, the luminous color of the first sub-pixel 10P1 is different from the luminous color of the second sub-pixel 10P2; the width-to-length ratio of the channel region of the data write transistor M2 in the first sub-pixel 10P1 is E1, and the width-to-length ratio of the channel region of the data write transistor M2 in the second sub-pixel 10P2 is E2; wherein, E1 and E2 are set differently. That is, for the first sub-pixel 10P1 and the second sub-pixel 10P2 of different luminous colors, the channel region of the data write transistor M2 is set to have different width-to-length ratios to adapt to the different data signal voltages required by the first sub-pixel 10P1 and the second sub-pixel 10P2 of different luminous colors, including but not limited to, at least under 255 grayscale, the voltage of the data signal line DATA in the first sub-pixel 10P1 is less than the voltage of the data signal line DATA in the second sub-pixel 10P2, and E1>E2 is set. 1) In the first aspect, a larger width-to-length ratio (larger E1) is set for the sub-pixel 10P with a small driving voltage (the voltage of the data signal line DATA is small) to increase the current in the corresponding data write transistor M2, so that the charging current of the voltage of the data signal line DATA to charge the first node N1 (for example, the gate of the driving transistor) increases, thereby increasing the brightness of the sub-pixel 10P with a small driving voltage, and the display uniformity of the display panel 100 is improved (for example, the brightness uniformity is improved), the power consumption of the driving chip is reduced, and the display quality is improved. 2) Secondly, a smaller aspect ratio (smaller E2) is set for the sub-pixel 10P with a large driving voltage (the voltage of the data signal line DATA is large), reducing the leakage of the sub-pixel 10P with a large driving voltage to other unopened pixel circuits 101, avoiding or improving display anomalies such as four-split screen or black ring, and improving reliability. Through these two differentiated settings, the display quality and reliability are improved at the same time.
[0049] In some embodiments, at least at grayscale 255, the voltage of the data signal line DATA in the first subpixel 10P1 is less than the voltage of the data signal line DATA in the second subpixel 10P2, E1>E2.
[0050] For example, at least at grayscale 255, the voltage of the data signal line DATA in the first subpixel 10P1 is less than the voltage of the data signal line DATA in the second subpixel 10P2, that is, at least at grayscale 255, the voltage in the first data signal line DATA1 is less than the voltage in the second data signal line DATA2, and the width-to-length ratio of the first data write transistor M2a is greater than the width-to-length ratio of the second data write transistor M2b.
[0051] For example, in at least some grayscales, at the same grayscale, the voltage of the data signal line DATA in the first sub-pixel 10P1 is lower than the voltage of the data signal line DATA in the second sub-pixel 10P2.
[0052] For example, for the first sub-pixel 10P1 and the first light-emitting element 102a, a larger width-to-length ratio (E1 is larger) is set for the sub-pixel 10P with a small driving voltage (the voltage of the data signal line DATA is small) to increase the current in the corresponding data write transistor M2, so that the charging current of the voltage of the data signal line DATA to charge the first node N1 (for example, the gate of the driving transistor) increases, thereby increasing the brightness of the sub-pixel 10P with a small driving voltage, improving the display uniformity of the display panel 100 (for example, the brightness uniformity is improved), reducing the power consumption of the driving chip, and improving the display quality.
[0053] For example, for the second sub-pixel 10P2 and the second light-emitting element 102b, a smaller aspect ratio (smaller E2) is set for the sub-pixel 10P with a large driving voltage (the voltage of the data signal line DATA is large), reducing the leakage of the sub-pixel 10P with a large driving voltage to other unopened pixel circuits 101, avoiding or improving display anomalies such as a four-split screen or a black ring, and improving reliability. Through these two differentiated settings, the display quality and reliability are improved at the same time.
[0054] In some embodiments, the display panel 100 satisfies the following formula:
[0055] (Vdata2-PVDD) / (Vdata1-PVDD) / 5.8<(W1 / L1) / (W2 / L2) / 15
[0056] Among them, Vdata2 represents the voltage of the data signal line DATA in the second sub-pixel 10P2, Vdata1 represents the voltage of the data signal line DATA in the first sub-pixel 10P1, PVDD represents the voltage of the first power line PVDD, W2 represents the width of the channel region of the data write transistor M2 in the second sub-pixel 10P2, L2 represents the length of the channel region of the data write transistor M2 in the second sub-pixel 10P2, W1 represents the width of the channel region of the data write transistor M2 in the first sub-pixel 10P1, and L1 represents the length of the channel region of the data write transistor M2 in the first sub-pixel 10P1.
[0057] By way of example, Vdata2 represents the voltage of the second data signal line DATA2, Vdata1 represents the voltage of the first data signal line DATA1, PVDD represents the voltage of the first power line PVDD, W2 represents the width of the channel region of the second data write transistor M2b, L2 represents the length of the channel region of the second data write transistor M2b, W1 represents the width of the channel region of the first data write transistor M2a, and L1 represents the length of the channel region of the first data write transistor M2a.
[0058] For example, in the compensation phase, the data writing transistor M2 operates in the linear region, and the linear region current formula Ids=1 / 2* μ Cox*W / L*[2(Vgs-Vth)Vds-Vds^2], substitute the working state of M2 tube at this time, compensation current Ids=1 / 2* μ Cox*W / L*[2(VGL-PVDD-Vth)(Vdata-PVDD)-(Vdata-PVDD)^2].
[0059] Ids represents the current in the channel region of the transistor, μ represents the carrier mobility, Cox represents the channel capacitance per unit area of the transistor, W / L represents the width-to-length ratio of the channel, W represents the width of the channel region, L represents the length of the channel region, Vth represents the threshold voltage of the data write transistor M2, Vgs represents the voltage difference between the gate and the source, Vds represents the voltage difference between the drain and the source, VGL represents the gate voltage (low potential voltage) of the data write transistor M2 when the data write transistor M2 is turned off, and Vdata represents the voltage of the data signal.
[0060] Since the voltage of VGL is very low, the formula can be simplified to: Ids=μCox*W / L*(VGL-PVDD-Vth)(Vdata-PVDD).
[0061] According to the current ratio of the red sub-pixel to the blue sub-pixel, or the current ratio of the green sub-pixel to the blue sub-pixel, Ids2 / 5.8<Ids1 / 15, Ids2 represents the current in the channel region of the data write transistor M2 (the second data write transistor M2b) in the second sub-pixel 10P2, and Ids1 represents the current in the channel region of the data write transistor M2 (the first data write transistor M2a) in the first sub-pixel 10P1. 5.8 and 1.5 are values verified by the inventor. Considering factors such as the driving voltage of the red sub-pixel and the green sub-pixel and the light-emitting element in the blue sub-pixel, the brightness of different pictures of the display panel at 255 grayscale, and the color coordinates of different pictures of the display panel at 255 grayscale, the inventor verified and found that the display panel is required to satisfy the formula Ids*2 / 5.8<Ids*1 / 15, so that the width-to-length ratio of the data write transistor M2 matches the current in the light-emitting element 102.
[0062] The formula Ids2 / 5.8<Ids1 / 15, that is: (Vdata2-PVDD) / (Vdata1-PVDD) / 5.8<(W1 / L1) / (W2 / L2) / 15.
[0063] In some embodiments, E1>E2; the first sub-pixel 10P1 is a blue sub-pixel; and the second sub-pixel 10P2 is any one of a red sub-pixel and a green sub-pixel.
[0064] By way of example, in some embodiments, the display panel 100 includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and at least at grayscale 255, the driving voltage of the blue light-emitting element differs too much from the driving voltage of the red light-emitting element, and the driving voltage of the blue light-emitting element differs too much from the driving voltage of the green light-emitting element; or, in other words, at least at grayscale 255, the voltage of the data signal line DATA in the blue sub-pixel differs too much from the voltage of the data signal line DATA in the red sub-pixel, and the voltage of the data signal line DATA in the blue sub-pixel differs too much from the voltage of the data signal line DATA in the green sub-pixel; and the driving voltage of the blue light-emitting element is lower than the driving voltage of the red light-emitting element, and the driving voltage of the blue light-emitting element is lower than the driving voltage of the green light-emitting element. At this time, the width-to-length ratio of the data write transistor M2 in the blue sub-pixel is set to be greater than the width-to-length of the data write transistor M2 in the red sub-pixel, and / or the width-to-length ratio of the data write transistor M2 in the blue sub-pixel is greater than the width-to-length of the data write transistor M2 in the green sub-pixel.
[0065] For example, in some embodiments, the display panel sets the width-to-length ratio of the data write transistor M2 in the blue sub-pixel to be greater than the width-to-length ratio of the data write transistor M2 in the red sub-pixel. In some embodiments, the display panel sets the width-to-length ratio of the data write transistor M2 in the blue sub-pixel to be greater than the width-to-length ratio of the data write transistor M2 in the green sub-pixel. In some embodiments, the display panel sets the width-to-length ratio of the data write transistor M2 in the blue sub-pixel to be greater than the width-to-length ratio of the data write transistor M2 in the red sub-pixel, and at the same time, the display panel also sets the width-to-length ratio of the data write transistor M2 in the blue sub-pixel to be greater than the width-to-length ratio of the data write transistor M2 in the green sub-pixel.
[0066] For example, in some embodiments, the display panel is configured to set the width-to-length ratio of the data write transistor M2 in the red sub-pixel to be equal to the width-to-length ratio of the data write transistor M2 in the green sub-pixel, but is not limited thereto. For example, in some embodiments, the display panel is configured to set the width-to-length ratio of the data write transistor M2 in the red sub-pixel to be not equal to the width-to-length ratio of the data write transistor M2 in the green sub-pixel.
[0067] For example, in some embodiments, the display panel 100 may further include other sub-pixels besides the blue sub-pixel, the red sub-pixel, and the green sub-pixel. For example, the display panel 100 may further include a white sub-pixel.
[0068] In some embodiments, E1 is greater than or equal to 1.8:8; and / or, E2 is less than or equal to 3.2:3.4.
[0069] For example, it has been verified by the inventor that E1>E2, when the first sub-pixel 10P1 is a blue sub-pixel and the second sub-pixel 10P2 is either a red sub-pixel or a green sub-pixel, E1 is greater than or equal to 1.8:8, and / or E2 is less than or equal to 3.2:3.4. At this time, the display quality and reliability can be improved at the same time.
[0070] In some embodiments, Figure 1 and Figure 2 As shown, the driving module 20 includes a driving transistor M3, and the pixel circuit 101 also includes a threshold compensation module 30 and a light emitting control module 40. The threshold compensation module 30 is electrically connected between the second electrode of the driving transistor M3 and the gate of the driving transistor M3, and the threshold compensation module 30 is configured to compensate for the threshold voltage of the driving transistor M3. The light emitting control module 40 is connected in series between the first power line PVDD and the light emitting element 102, and the light emitting control module 40 is configured to control the light emitting element 102 to emit light.
[0071] In some embodiments, Figure 1 and Figure 2 As shown, the pixel circuit 101 further includes a storage module 50, a first reset module 60 and a second reset module 70. The storage module 50 is electrically connected between the first power line PVDD and the gate of the driving transistor M3, and the storage module 50 is configured to stabilize the voltage of the gate of the driving transistor M3 during the light-emitting stage; the first reset module 60 is configured to at least provide a first initialization voltage signal to the gate of the driving transistor M3; the second reset module 70 is configured to provide a second initialization voltage signal to the first electrode of the light-emitting element 102; the light-emitting control module 40 includes a first light-emitting control module 401 and a second light-emitting control module 402, the first light-emitting control module 401 is electrically connected between the first power line PVDD and the first electrode of the driving transistor M3, and the second light-emitting control module 402 is electrically connected between the second electrode of the driving transistor M3 and the first electrode of the light-emitting element 102.
[0072] For example, in some embodiments, the pixel circuit 101 may include one of the first reset module 60 and the second reset module 70. In some embodiments, the pixel circuit 101 may include both the first reset module 60 and the second reset module 70. In some embodiments, the pixel circuit 101 may not include the first reset module 60 and the second reset module 70.
[0073] For example, in some embodiments, the light control module 40 includes a first light control module 401 and a second light control module 402. In some embodiments, the light control module 40 includes one of the first light control module 401 and the second light control module 402.
[0074] In some embodiments, Figure 3 and Figure 4 As shown, the pixel circuit 101 further includes a bias adjustment module 80. The bias adjustment module 80 is electrically connected between the adjustment signal line DVH and the first electrode of the driving transistor M3, and the bias adjustment module 80 is configured to provide a bias adjustment signal to the driving transistor M3.
[0075] For example, in some implementations, a voltage value of the bias adjustment signal is greater than a voltage value of the first power line PVDD.
[0076] In some embodiments, Figures 1 to 4 As shown, the threshold compensation module 30 includes a compensation transistor M4, the storage module 50 includes a storage capacitor Cst, the first reset module 60 includes a first reset transistor M5, the second reset module 70 includes a second reset transistor M7, the first light-emitting control module 401 includes a first light-emitting control transistor M1, the second light-emitting control module 402 includes a second light-emitting control transistor M6, and the bias adjustment module 80 includes a bias transistor M8.
[0077] The gate of the first reset transistor M5 is electrically connected to the first reset scanning signal line SP1, the first electrode of the first reset transistor M5 is electrically connected to the first initialization signal line VREF1, the second electrode of the first reset transistor M5 is electrically connected to the first node N1, and the first node N1 is electrically connected to the gate of the driving transistor M3.
[0078] A gate of the second reset transistor M7 is electrically connected to the second reset scanning signal line SPX, a first electrode of the second reset transistor M7 is electrically connected to the second initialization signal line VREF2 , and a second electrode of the second reset transistor M7 is electrically connected to the first electrode of the light emitting element 102 .
[0079] A first plate of the storage capacitor Cst is electrically connected to the first power line PVDD, and a second plate of the storage capacitor Cst is electrically connected to the first node N1.
[0080] A gate of the compensation transistor M4 is electrically connected to the compensation scanning signal line SP2 , a first electrode of the compensation transistor M4 is electrically connected to the first node N1 , and a second electrode of the compensation transistor M4 is electrically connected to the second electrode of the driving transistor M3 .
[0081] A gate of the first light emission control transistor M1 is electrically connected to the first light emission control scanning signal line EMIT1 , a first electrode of the first light emission control transistor M1 is electrically connected to the first power line PVDD, and a second electrode of the first light emission control transistor M1 is electrically connected to a first electrode of the driving transistor M3 .
[0082] The gate of the second light emitting control transistor M6 is electrically connected to the second light emitting control scanning signal line EMIT2 , the first electrode of the second light emitting control transistor M6 is electrically connected to the second electrode of the driving transistor M3 , and the second electrode of the second light emitting control transistor M6 is electrically connected to the first electrode of the light emitting element 102 .
[0083] A gate of the bias transistor M8 is electrically connected to the first bias scanning signal line SPY, a first electrode of the bias transistor M8 is electrically connected to the first electrode of the driving transistor M3, and a second electrode of the bias transistor M8 is electrically connected to the bias signal line DVH.
[0084] It should be noted that if Figures 1 to 4 As shown, when the transistor is a thin film transistor or a field effect transistor, the transistor includes a gate, a source and a drain, with the upper portion in the schematic diagram being the first electrode of the transistor and the lower portion being the second electrode of the transistor, or the left portion in the schematic diagram being the first electrode of the transistor and the right portion being the second electrode of the transistor, the first electrode of the transistor being one of the source and the drain of the transistor, and the second electrode of the transistor being the other of the source and the drain of the transistor, and depending on the setting of the high and low levels in a specific circuit and the type and characteristics of the transistor, the source and drain of each transistor can be fully or partially interchangeable, which is easily implemented by those skilled in the art according to specific application scenarios and will not be elaborated herein.
[0085] By way of example, the first reset scan signal line SP1 provides a first reset scan signal, the first initialization signal line VREF1 provides a first initialization signal, the second reset scan signal line SPX provides a second reset scan signal, the second initialization signal line VREF2 provides a second initialization signal, the first light-emitting control scan signal line EMIT1 provides a first light-emitting control scan signal, the second light-emitting control scan signal line EMIT2 provides a second light-emitting control scan signal, the first bias scan signal line SPY provides a first bias scan signal, and the bias signal line DVH provides a bias signal.
[0086] For example, in some embodiments, the electrical signals in the first reset scan signal line SP1 and the second reset scan signal line SPX may be the same. In some embodiments, the electrical signals in the first reset scan signal line SP1 and the second reset scan signal line SPX may be different.
[0087] For example, in some embodiments, the electrical signals in the first light emission control scan signal line EMIT1 and the second light emission control scan signal line EMIT2 may be the same. In some embodiments, the electrical signals in the first light emission control scan signal line EMIT1 and the second light emission control scan signal line EMIT2 may be different.
[0088] For example, the first electrode of the light emitting element 102 may be one of an anode and a cathode. In the present application, the first electrode of the light emitting element 102 is taken as an anode for illustration.
[0089] For example, Figures 1 to 4 As shown, a first node N1, a second node N2, a third node N3 and a fourth node N4 are illustrated, the first node N1 is electrically connected to the gate of the driving transistor M3, the second node N2 is electrically connected to the first electrode of the driving transistor M3, the third node N3 is electrically connected to the second electrode of the driving transistor M3, and the fourth node N4 is electrically connected between the first electrode of the light emitting element 102 and the second electrode of the second light emitting control transistor M6.
[0090] For example, a gate of the data writing transistor M2 is electrically connected to the data control scanning signal line SP3 , a first electrode of the data writing transistor M2 is electrically connected to the data signal line DATA, and a second electrode of the data writing transistor M2 is electrically connected to a first electrode of the driving transistor M3 .
[0091] For example, in some embodiments, Figure 1 and Figure 2 In some embodiments, the pixel circuit 101 does not include the bias transistor M8. Figure 3 and Figure 4 In FIG. 1 , the pixel circuit 101 includes a bias transistor M8 .
[0092] For example, Figure 5 As shown, in some embodiments, in the first pixel circuit 101a, the gate of the first reset transistor M5 includes a first gate portion and a second gate portion, forming two small sub-transistors. For example, the first reset transistor M5 includes a first sub-reset transistor M5_1 and a second sub-reset transistor M5_2 connected in series.
[0093] For example, Figure 5As shown, in some embodiments, in the first pixel circuit 101a, the gate of the compensation transistor M4 includes a first gate portion and a second gate portion, forming two small sub-transistors. For example, the compensation transistor M4 includes a first sub-compensation transistor M4_1 and a second sub-compensation transistor M4_2 connected in series.
[0094] It should be noted that, in some embodiments, in the second pixel circuit 101b, the first reset transistor M5 may include a first sub-reset transistor M5_1 and a second sub-reset transistor M5_2, and / or the compensation transistor M4 may include a first sub-compensation transistor M4_1 and a second sub-compensation transistor M4_2.
[0095] Examples, such as Figure 1 and Figure 2 As shown, the working process of the pixel circuit 101 generally includes an initialization phase, a data writing and compensation phase, and a light emitting phase.
[0096] In the initialization stage, the first reset module 60 is turned on under the control of the signal of the first reset scan signal line SP1, and writes the signal of the first initialization signal line VREF1 into the first node N1 to initialize the first node N1. The second reset module 70 is turned on under the control of the signal of the second reset scan signal line SPX, and writes the signal of the second initialization signal line VREF2 into the first electrode of the light emitting element 102 to initialize the first electrode of the light emitting element 102.
[0097] During the data writing and compensation stage, the data writing module 10 is turned on under the control of the data control scanning signal line SP3, and the signal of the data signal line DATA is written into the first node N1 (data writing stage). At the same time, the threshold compensation module 30 is turned on under the control of the compensation scanning signal line SP2, and the threshold voltage of the driving transistor M3 is compensated to the first node N1 (compensation stage).
[0098] In the light-emitting stage, the light-emitting control module 40 is turned on under the control of the light-emitting control scanning signal (the signal of the first light-emitting control scanning signal line EMIT1 and / or the signal of the second light-emitting control scanning signal line EMIT2), and controls the driving current generated by the driving transistor M3 to flow into the light-emitting element 102 to drive the light-emitting element 102 to emit light.
[0099] It should be noted that in Figure 1 and Figure 2 In the example, the working process of the pixel circuit 101 is not limited to the initialization phase, data writing and compensation phase and light emitting phase described above. For example, in the initialization phase, the first reset module 60 and the second reset module 70 are performed successively; for example, the data writing and compensation phase is divided into a data writing phase and a compensation phase successively.
[0100] For example, compared to Figure 1 and Figure 2 ,like Figure 3 and Figure 4 As shown, the pixel circuit 101 further includes a bias adjustment module 80 . Figure 3 and Figure 4 The other structures except the bias adjustment module 80 can be arranged according to Figure 1 and Figure 2 The corresponding structure in the pixel driving circuit shown is set, and the embodiment of the present invention is not repeated here. The bias adjustment module 80 is used to adjust the bias state of the driving transistor M3.
[0101] Examples, such as Figure 3 and Figure 4 As shown, the pixel circuit 101 further includes a bias adjustment module 80. In some embodiments, within one frame scanning time, the bias adjustment module 80 is turned on twice, the first bias adjustment stage is set before the initialization stage, the potential of the first node N1 is negative in the first bias adjustment stage, and the voltage difference between the first node N1 and the third node N3 is large in this stage; the second bias adjustment stage is set after the data writing stage, the potential of the first node N1 is the voltage of the written data signal in the second bias adjustment stage, and the voltage difference between the first node N1 and the third node N3 is relatively small. Although the voltage difference between the first node N1 and the third node N3 is different in the first bias adjustment stage and the second bias adjustment stage, the provided bias adjustment module 80 can be used to transmit the signal of the bias signal line DVH to the second node N2, so as to control the charge of the second node N2 to be lower than the potential of the third node N3, so as to adjust the bias state of the driving transistor M3; to improve the threshold drift problem of the driving transistor M3 caused by the hysteresis effect, and to be applied in the display panel 100 to improve the influence of the driving transistor M3 on the display effect due to the hysteresis effect.
[0102] For example, Figure 3 and Figure 4 As shown, the working process of the bias adjustment module 80 is not limited to the first bias adjustment stage and the second bias adjustment stage described above, for example, there is only one of the first bias adjustment stage and the second bias adjustment stage.
[0103] See also Figure 6 , Figure 6 A schematic diagram of a display device provided in some embodiments of the present application.
[0104] On the second aspect, based on the same application concept, the present application also provides a display device 200, the display device 200 includes any one of the display panels 100 described above, or the display device 200 includes a display panel 100 that combines any several of the features described above.
[0105] For example, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 100 and will not be described in detail below.
[0106] For example, the display device 200 provided in the embodiment of the present application can be a mobile phone, or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiment of the present application does not make any special limitations on this.
[0107] The display device 200 provided in the embodiment of the present application can be Figure 6 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of the present application do not specifically limit this.
[0108] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0109] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A display panel, characterized in that: The invention comprises a plurality of sub-pixels, wherein the sub-pixels include a pixel circuit and a light-emitting element which are electrically connected, and the pixel circuit includes: A driving module, wherein the driving module and the light emitting element are electrically connected between the first power line and the second power line in sequence, and the driving module is configured to provide a driving current to the light emitting element; A data writing module, comprising a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to a data signal line, a second electrode of the data writing transistor is electrically connected to a first end of the driving module, and the data writing module is configured to write a data signal to the first end of the driving module during a data writing phase; The plurality of sub-pixels include at least a first sub-pixel and a second sub-pixel, and the luminous color of the first sub-pixel is different from the luminous color of the second sub-pixel; The width-to-length ratio of the channel region of the data writing transistor in the first sub-pixel is E1, and the width-to-length ratio of the channel region of the data writing transistor in the second sub-pixel is E2; wherein E1 is different from E2.
2. The display panel according to claim 1, characterized in that: At least at grayscale 255, the voltage of the data signal line in the first sub-pixel is lower than the voltage of the data signal line in the second sub-pixel, E1>E2.
3. The display panel according to claim 2, characterized in that: Satisfies the following formula: (Vdata2-PVDD) / (Vdata1-PVDD) / 5.8<(W1 / L1) / (W2 / L2) / 15 Among them, Vdata2 represents the voltage of the data signal line in the second sub-pixel, Vdata1 represents the voltage of the data signal line in the first sub-pixel, PVDD represents the voltage of the first power line, W2 represents the width of the channel region of the data write transistor in the second sub-pixel, L2 represents the length of the channel region of the data write transistor in the second sub-pixel, W1 represents the width of the channel region of the data write transistor in the first sub-pixel, and L1 represents the length of the channel region of the data write transistor in the first sub-pixel.
4. The display panel according to claim 1, characterized in that: E1>E2; The first sub-pixel is a blue sub-pixel; The second sub-pixel is any one of a red sub-pixel and a green sub-pixel.
5. The display panel according to claim 4, characterized in that: E1 is greater than or equal to 1.8:8; and / or, E2 is less than or equal to 3.2:3.
4.
6. The display panel according to claim 1, characterized in that: The driving module includes a driving transistor, and the pixel circuit further includes: a threshold compensation module, electrically connected between the second electrode of the driving transistor and the gate of the driving transistor, the threshold compensation module being configured to compensate for a threshold voltage of the driving transistor; The light emitting control module is connected in series between the first power line and the light emitting element, and the light emitting control module is configured to control the light emitting element to emit light.
7. The display panel according to claim 6, characterized in that: The pixel circuit further includes: a storage module, electrically connected between the first power line and the gate of the driving transistor, the storage module being configured to stabilize the voltage of the gate of the driving transistor in a light emitting stage; A first reset module, configured to provide at least a first initialization voltage signal to the gate of the driving transistor; A second reset module is configured to provide a second initialization voltage signal to the first electrode of the light emitting element; The light-emitting control module includes a first light-emitting control module and a second light-emitting control module, wherein the first light-emitting control module is electrically connected between the first power line and the first electrode of the driving transistor, and the second light-emitting control module is electrically connected between the second electrode of the driving transistor and the first electrode of the light-emitting element.
8. The display panel according to claim 7, characterized in that: The pixel circuit further includes: A bias adjustment module is electrically connected between the adjustment signal line and the first electrode of the driving transistor, and the bias adjustment module is configured to provide a bias adjustment signal to the driving transistor.
9. The display panel according to claim 8, characterized in that: The threshold compensation module includes a compensation transistor, the storage module includes a storage capacitor, the first reset module includes a first reset transistor, the second reset module includes a second reset transistor, the first light emission control module includes a first light emission control transistor, the second light emission control module includes a second light emission control transistor, and the bias adjustment module includes a bias transistor; The gate of the first reset transistor is electrically connected to the first reset scanning signal line, the first electrode of the first reset transistor is electrically connected to the first initialization signal line, the second electrode of the first reset transistor is electrically connected to the first node, and the first node is electrically connected to the gate of the driving transistor; The gate of the second reset transistor is electrically connected to the second reset scanning signal line, the first electrode of the second reset transistor is electrically connected to the second initialization signal line, and the second electrode of the second reset transistor is electrically connected to the first electrode of the light emitting element; The first plate of the storage capacitor is electrically connected to the first power line, and the second plate of the storage capacitor is electrically connected to the first node; The gate of the compensation transistor is electrically connected to the compensation scanning signal line, the first electrode of the compensation transistor is electrically connected to the first node, and the second electrode of the compensation transistor is electrically connected to the second electrode of the driving transistor; The gate of the first light emission control transistor is electrically connected to the first light emission control scanning signal line, the first electrode of the first light emission control transistor is electrically connected to the first power supply line, and the second electrode of the first light emission control transistor is electrically connected to the first electrode of the driving transistor; The gate of the second light emission control transistor is electrically connected to the second light emission control scanning signal line, the first electrode of the second light emission control transistor is electrically connected to the second electrode of the driving transistor, and the second electrode of the second light emission control transistor is electrically connected to the first electrode of the light emitting element; A gate of the bias transistor is electrically connected to a first bias scanning signal line, a first electrode of the bias transistor is electrically connected to a first electrode of the driving transistor, and a second electrode of the bias transistor is electrically connected to a bias signal line.
10. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 9.