Satellite-borne circuit packet fusion switching device based on time slot processing

Abstract

The invention provides a spaceborne circuit packet fusion switching device based on time slot processing, and relates to the field of satellite communication. The device comprises a low-speed access processing module, a medium-speed access processing module, a high-speed access processing module, a load equipment access processing module, a time slot separation module, a fusion switching module, a time slot shaping module and a configuration management module, receives an uplink TDMA time slot frame, converts the uplink TDMA time slot frame into an internal communication frame, analyzes and separates a circuit time slot and a grouping time slot, and transmits the internal communication frame to the load equipment access processing module. The method comprises the following steps: firstly, grouping time slots into grouping frames according to conversion, bearing grouping frames and circuit time slots into a unified internal communication grouping frame, carrying out data exchange according to a frame header forwarding field of the internal communication grouping frame, and bearing the exchanged circuit time slots and grouping frames into a downlink VTDM time slot frame in a time slot shaping manner. The method has the advantages of being high in integration degree, high in expandability, capable of supporting multiple service types, supporting multiple protocol specifications and the like, and meets the requirement for grouping, fusing and switching of circuits in any proportion.

Description

Technical Field

[0001] The invention relates to a satellite-borne circuit grouping fusion switching device based on time slot processing, belonging to the field of satellite communication. Background Art

[0002] At present, the switching method adopted by the satellite communication system depends on the service type, service volume, network structure and application background of the system. Existing switching technologies include circuit switching, packet switching, or a combination of circuit and packet switching. The switching system plays a decisive role in ensuring the QoS of user services, affecting not only the delay and jitter of real-time services, but also the loss rate of burst services such as data. On the premise of supporting current broadband and mobile packet services, the next-generation satellite Internet system also needs to support the guaranteed communication of special equipment using the traditional DVB satellite communication system under strong interference and high bit error rate conditions. However, the use of packet switching forwarded by the key field of the frame header will result in a large number of packet loss rates, making the system unavailable. Therefore, the next-generation satellite Internet system needs to support both circuit and packet switching. However, there is no such solution in the prior art. Summary of the invention

[0003] The purpose of the present invention is to solve the problems in the above background technology and provide a satellite circuit grouping fusion switching device based on time slot processing. The present invention supports real-time switching and distribution processing of time slot services with different rates such as low, medium and high, and has the characteristics of high degree of integration and strong scalability.

[0004] The object of the present invention is achieved in that: A satellite-borne circuit grouping fusion switching device based on time slot processing, comprising a medium-speed access processing module 2, a high-speed access processing module 3, a payload equipment access processing module 4, a configuration management module 8, and also comprising a low-speed access processing module 1, a time slot separation module 5, a fusion switching module 6 and a time slot shaping module 7; The low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively send the low-speed interface frame, the medium-speed interface frame, the high-speed interface frame, and the load device interface frame to the time slot separation module 5; The time slot separation module 5 parses and separates the circuit time slot and the packet time slot, adds an internal communication header to the processed circuit time slot and sends it to the fusion switching module 6, or adds an internal communication header to the packet frame and sends it to the fusion switching module 6; The fusion switching module 6 sends the processed circuit time slots and packet frames to the time slot shaping module 7; The time slot shaping module 7 sends the downlink VTDM time slot frame or the load device time slot frame to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively; The configuration management module 8 performs configuration management on the low-speed access processing module 1 , the medium-speed access processing module 2 , the high-speed access processing module 3 , the load device access processing module 4 , the time slot separation module 5 , the fusion switching module 6 and the time slot shaping module 7 .

[0005] Further, the low-speed access processing module 1 receives the low-speed interface frame carrying the low-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and low-speed interface frame processing, and sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5; The medium-speed access processing module 2 receives the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and medium-speed interface frame processing, and sends the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module 5; The high-speed access processing module 3 receives the high-speed interface frame carrying the high-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and high-speed interface frame processing, and then sends the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module 5; The load device access processing module 4 receives the load device interface frame carrying the load device time slot frame in the uplink, completes decoding, verification and load device interface frame processing, and then sends the load device interface frame carrying the load device time slot frame to the time slot separation module 5; After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module 1, the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module 2, the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module 3, and the load device interface frame carrying the load device time slot frame sent by the load device access processing module 4, the time slot separation module 5 parses the low-speed uplink TDMA time slot frame, the medium-speed uplink TDMA time slot frame, the high-speed uplink TDMA time slot frame and the load device time slot frame from the corresponding interface frame under the unified control of the configuration management module 8 and separates the circuit time slot and the packet time slot; for the circuit time slot, splicing, splitting or copying is performed according to the resource configuration of the configuration management module 8, and the processed circuit time slot is added with an internal communication header and sent to the fusion switching module 6; for the packet time slot, according to the splicing rule of the packet frame, splicing is performed on different packet time slots to form a complete packet frame, and the packet frame is added with an internal communication header and sent to the fusion switching module 6; The fusion switching module 6 performs fast forwarding switching processing according to the forwarding identification key field in the internal communication header of the circuit time slot and the frame type, address, identification, and priority key fields in the internal communication header of the packet frame, and sends the processed circuit time slot and packet frame to the time slot shaping module 7; After receiving the circuit time slot and packet frame sent by the fusion switching module 6, the time slot shaping module 7 performs subsequent processing respectively. For the circuit time slot, according to the control rule of the configuration management module 8, the circuit time slot is transferred to different downstream VTDM time slot frames or load device time slot frames after removing the internal communication header; for the packet frame, the internal communication header is removed according to the cache status of the logical queue, and the packet frame is deframed according to the downstream time slot length, and after the packet time slot is formed, it is loaded into different downstream VTDM time slot frames or load device time slot frames; then, the time slot shaping module 7 sends the downstream VTDM time slot frame or the load device time slot frame to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively; The low-speed access processing module 1 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, forms a low-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the low-speed interface frame out; the medium-speed access processing module 2 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, forms a medium-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the medium-speed interface frame out; the high-speed access processing module 3 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, forms a high-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the high-speed interface frame out; the load device access processing module 4 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, forms a load device interface frame carrying the load device time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the load device interface frame out; The configuration management module 8 completes the configuration management function of the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, the load device access processing module 4, the time slot separation module 5, the fusion switching module 6 and the time slot shaping module 7.

[0006] Furthermore, the low-speed access processing module 1 includes an interface receiving processing submodule 1-1, a decoding processing submodule 1-2, a frame format processing submodule 1-3, a time management submodule 1-4, a time slot selection submodule 1-5, an encoding processing submodule 1-6, and an interface sending processing submodule 1-7; After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, the interface receiving processing submodule 1-1 performs low-speed interface frame verification processing to ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding processing submodule 1-2; After receiving the low-speed interface frame, the decoding processing submodule 1-2 decodes the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, and sends the decoded low-speed interface frame to the frame format processing submodule 1-3; The frame format processing submodule 1-3 performs synchronization and alignment operations on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame under the unified clock control provided by the time management submodule 1-4, and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5; The time management submodule 1-4 provides unified clock control for the decoding processing submodule 1-2, the frame format processing submodule 1-3, the time slot selection submodule 1-5, and the encoding processing submodule 1-6; The time slot selection submodule 1-5 receives the low-speed interface frame carrying the downlink VTDM time slot frame from the time slot shaping module 7, synchronizes, aligns, and selects the time slot of the low-speed interface frame carrying the downlink VTDM time slot frame under the unified clock control provided by the time management submodule 1-4, and then sends the low-speed interface frame carrying the downlink VTDM time slot frame to the encoding processing submodule 1-6; After the encoding processing submodule 1-6 completes the encoding processing of the low-speed interface frame carrying the downlink VTDM time slot frame, it sends the low-speed interface frame to the interface transmission processing submodule 1-7; The interface transmission processing submodule 1-7 adds a check value to the low-speed interface frame carrying the downstream VTDM time slot frame and then sends it out.

[0007] Further, the time slot separation module 5 includes a first input scheduling submodule 5-1, a time slot writing submodule 5-2, a storage management submodule 5-3, a time slot reading submodule 5-4, a circuit framing submodule 5-5, a circuit sending submodule 5-6, a packet framing submodule 5-7, and a packet sending submodule 5-8; The first input scheduling submodule 5-1 adopts polling or weighted polling to perform input scheduling processing on the low-speed interface frames carrying low-speed uplink TDMA time slot frames sent by the low-speed access processing module 1, the medium-speed interface frames carrying medium-speed uplink TDMA time slot frames sent by the medium-speed access processing module 2, the high-speed interface frames carrying high-speed uplink TDMA time slot frames sent by the high-speed access processing module 3, and the load device interface frames carrying load device time slot frames sent by the load device access processing module 4, and sends the low-speed interface frames, medium-speed interface frames, high-speed interface frames, and load device interface frames that have completed the input scheduling processing to the time slot writing submodule 5-2; The time slot writing submodule 5-2 writes the received different interface frames into the storage management submodule 5-3 respectively; The storage management submodule 5-3 performs address space management and data scheduling management on the written interface frame; The time slot reading submodule 5-4 periodically reads the interface frame from the storage management submodule 5-3, parses and separates the circuit time slot and the packet time slot from the interface frame, and sends the circuit time slot to the circuit framing submodule 5-5 and the packet time slot to the packet framing submodule 5-7 respectively; The circuit framing submodule 5-5 splices, splits or copies the received circuit time slots according to the resource configuration of the configuration management module 8, and then sends them to the circuit sending submodule 5-6; The circuit sending submodule 5-6 adds an internal communication header to the received circuit time slot and sends it to the fusion switching module 6; The packet framing submodule 5-7 performs framing processing on different packet time slots according to the framing rules of the packet frames, forms a complete packet frame, and sends the packet frame to the packet sending submodule 5-8; The packet sending submodule 5 - 8 adds an internal communication header to the received packet frame and sends it to the fusion switching module 6 .

[0008] Further, the fusion switching module 6 includes an input scheduling submodule 6-1, a flow classification submodule 6-2, a table lookup configuration submodule 6-3, a packet processing submodule 6-4, a circuit processing submodule 6-5, and a first output scheduling submodule 6-6; The input scheduling submodule 6-1 receives the circuit time slot containing the internal communication header and the packet frame containing the internal communication header, and after completing the input scheduling, sends the circuit time slot to the circuit processing submodule 6-5 and sends the packet frame to the flow classification submodule 6-2; The flow classification submodule 6-2 extracts the identification, address, and priority information in the internal communication header of the packet frame in combination with the table entry information in the table lookup configuration submodule 6-3, fills the egress port information of the packet frame into the internal communication header of the packet frame, and sends the packet frame to the packet processing submodule 6-4; The table lookup configuration submodule 6-3 provides various table entries for packet forwarding for the flow classification submodule 6-2; The packet processing submodule 6-4 receives the packet frame from the flow classification submodule 6-2, and sends it to the first output scheduling submodule 6-6 after completing the packet processing; The circuit processing submodule 6-5 directly performs circuit switching processing according to the forwarding information in the communication header inside the circuit time slot, and sends the processed circuit time slot to the first output scheduling submodule 6-6; The first output scheduling submodule 6 - 6 sends the packet frames and circuit time slots to the time slot shaping module 7 respectively through polling scheduling.

[0009] Further, the time slot shaping module 7 includes a circuit receiving submodule 7-1, a packet receiving submodule 7-2, a second input scheduling submodule 7-3, a time slot filling submodule 7-4, a cache management module 7-5, and a second output scheduling submodule 7-6; The circuit receiving submodule 7-1 receives the switched circuit time slots from the fusion switching module 6, completes the circuit time slot buffering and shaping processing, and then sends it to the second input scheduling submodule 7-3; The packet receiving submodule 7-2 receives the switched packet frame from the fusion switching module 6, completes the packet frame buffering and verification processing, and then sends the packet frame to the second input scheduling submodule 7-3; After receiving the circuit time slot and the packet frame, the second input scheduling submodule 7-3 processes them respectively. For the circuit time slot, according to the control rule of the configuration management module 8, the circuit time slot is sent to the time slot filling submodule 7-4 after removing the internal communication header; for the packet frame, the internal communication is removed according to the cache status of the logical queue, and the packet frame is unpacked according to the downlink time slot length, and the packet time slot is formed and sent to the time slot filling submodule 7-4; The time slot filling submodule 7-4 loads the received packet time slot and circuit time slot into the downlink VTDM time slot frame or the load device time slot frame, and sends it to the buffer management module 7-5; The buffer management module 7-5 performs address space management and data scheduling management on the downlink VTDM time slot frame or the load device time slot frame; The second output scheduling submodule 7-6 schedules the downlink VTDM time slot frame or the load device time slot frame of the cache management module 7-5 in real time, and sends it to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively.

[0010] Compared with the background technology, the present invention has the following advantages: 1. The present invention supports the access of interface data of different rates such as low, medium and high, and has the characteristics of high degree of integration and strong scalability.

[0011] 2. The present invention can support the fusion exchange of circuit services and packet services in any proportion, meeting the fusion processing requirements of circuit services and packet services.

[0012] 3. The present invention can support priority-based QoS scheduling of packet services and support resource reservation-based circuit service guaranteed scheduling.

[0013] 4. The present invention is particularly suitable for satellite-borne switching systems with multiple business types and multiple rate requirements, and can be used to implement satellite-borne circuit grouping fusion payload equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1The present invention is an electrical principle block diagram of a satellite-borne circuit grouping fusion switching device based on time slot processing in an embodiment of the present invention.

[0015] Figure 2 yes Figure 1 Electrical block diagram of the medium and low speed access processing module.

[0016] Figure 3 yes Figure 1 Electrical block diagram of the time slot separation module.

[0017] Figure 4 yes Figure 1 Electrical block diagram of the fusion switching module.

[0018] Figure 5 yes Figure 1 Electrical block diagram of the mid-slot shaping module. DETAILED DESCRIPTION

[0019] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0020] Reference Figure 1 A satellite-borne circuit grouping fusion switching device based on time slot processing includes a low-speed access processing module 1, a medium-speed access processing module 2, a high-speed access processing module 3, a payload device access processing module 4, a time slot separation module 5, a fusion switching module 6, a time slot shaping module 7 and a configuration management module 8. The medium-speed access processing module 2, the high-speed access processing module 3 and the payload device access processing module 4 are the same as the low-speed access processing module 1 in terms of sub-module composition and connection relationship between modules, and the difference lies in the differences in the cache capacity, information processing capacity and other aspects of each sub-module. Figure 1 This is an electrical schematic diagram of a satellite-borne circuit grouping fusion switching device based on time slot processing, and the embodiment is according to Figure 1 Connect the lines.

[0021] Among them, the function of the low-speed access processing module 1 is to receive the low-speed interface frame carrying the low-speed uplink TDMA time slot frame in the uplink, complete the decoding, verification and low-speed interface frame processing, and then send the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5. In addition, the low-speed access processing module 1 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, completes the verification, synchronization, encoding and interface subframe processing operations to form a low-speed interface frame carrying the downlink VTDM time slot frame, and sends the low-speed interface frame out.

[0022] The function of the medium-speed access processing module 2 is to receive the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame in the uplink, complete the decoding, verification and medium-speed interface frame processing, and then send the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module 5. In addition, the medium-speed access processing module 2 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, completes the verification, synchronization, encoding and interface subframe processing operations to form a medium-speed interface frame carrying the downlink VTDM time slot frame, and sends the medium-speed interface frame out.

[0023] The function of the high-speed access processing module 3 is to receive the high-speed interface frame carrying the high-speed uplink TDMA time slot frame in the uplink, complete decoding, verification and high-speed interface frame processing, and then send the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module 5. In addition, the high-speed access processing module 3 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, completes the verification, synchronization, encoding and interface subframe processing operations to form a high-speed interface frame carrying the downlink VTDM time slot frame, and sends the high-speed interface frame out.

[0024] The function of the load device access processing module 4 is to receive the load device interface frame carrying the load device time slot frame in the uplink, complete decoding, verification and load device interface frame processing, and then send the load device interface frame carrying the load device time slot frame to the time slot separation module 5. In addition, the load device access processing module 4 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, completes verification, synchronization, encoding and interface subframe processing operations to form a load device interface frame carrying the load device time slot frame, and sends the load device interface frame out.

[0025] The function of the time slot separation module 5 is to receive the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module 1, the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module 2, the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module 3, and the load device interface frame carrying the load device time slot frame sent by the load device access processing module 4, and then, under the unified control of the configuration management module 8, parse the low-speed uplink TDMA time slot frame, the medium-speed uplink TDMA time slot frame, the high-speed uplink TDMA time slot frame and the load device time slot frame from the corresponding interface frame and separate the circuit time slot and the packet time slot. Specifically, for circuit time slots, they need to be spliced, split or copied according to the resource configuration of the configuration management module 8, and the processed circuit time slots need to be added with an internal communication header and sent to the fusion switching module 6; for packet time slots, they need to be spliced ​​according to the splicing rules of the packet frames, and different packet time slots need to be spliced ​​to form complete packet frames, and the packet frames need to be added with an internal communication header and sent to the fusion switching module 6.

[0026] The function of the fusion switching module 6 is to perform fast forwarding switching processing based on key fields such as the forwarding identifier in the internal communication header of the circuit time slot and key fields such as the frame type, address, identifier, priority, etc. in the internal communication header of the packet frame, and send the processed circuit time slot and packet frame to the time slot shaping module 7.

[0027] After receiving the circuit time slot and packet frame sent by the fusion switching module 6, the time slot shaping module 7 performs subsequent processing respectively. Specifically, for the circuit time slot, according to the control rules of the configuration management module 8, the circuit time slot is transferred to different downstream VTDM time slot frames or load device time slot frames after removing the internal communication header; for the packet frame, the internal communication header is removed according to the cache status of the logical queue, and the packet frame is deframed according to the downstream time slot length, and after the packet time slot is formed, it is loaded into different downstream VTDM time slot frames or load device time slot frames. Afterwards, the time slot shaping module 7 sends the downstream VTDM time slot frame or load device time slot frame to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively.

[0028] The function of the configuration management module 8 is to complete the configuration management function of the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, the load device access processing module 4, the time slot separation module 5, the fusion switching module 6 and the time slot shaping module 7.

[0029] like Figure 2 As shown, the low-speed access processing module 1 is composed of an interface receiving processing submodule 1-1, a decoding processing submodule 1-2, a frame format processing submodule 1-3, a time management submodule 1-4, a time slot selection submodule 1-5, a coding processing submodule 1-6, and an interface sending processing submodule 1-7. Figure 2 Connect the lines.

[0030] The function of the interface receiving and processing submodule 1-1 is to perform low-speed interface frame verification processing after receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and send the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding and processing submodule 1-2.

[0031] The function of the decoding processing submodule 1-2 is to decode the low-speed interface frame carrying the low-speed uplink TDMA time slot frame using a decoding algorithm after receiving the low-speed interface frame, and send the decoded low-speed interface frame to the frame format processing submodule 1-3.

[0032] The function of the frame format processing submodule 1-3 is to synchronize and align the low-speed interface frame carrying the low-speed uplink TDMA time slot frame under the unified clock control provided by the time management submodule 1-4, and then send the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5 for subsequent processing.

[0033] The function of the time management submodule 1-4 is to provide unified clock control for the decoding processing submodule 1-2, the frame format processing submodule 1-3, the time slot selection submodule 1-5, and the encoding processing submodule 1-6.

[0034] The function of the time slot selection submodule 1-5 is to receive the low-speed interface frame carrying the downstream VTDM time slot frame from the time slot shaping module 7, and after synchronizing, aligning, selecting time slots and other operations on the low-speed interface frame carrying the downstream VTDM time slot frame under the unified clock control provided by the time management submodule 1-4, send the low-speed interface frame carrying the downstream VTDM time slot frame to the encoding processing submodule 1-6.

[0035] The function of the encoding processing submodule 1-6 is to complete the encoding processing of the low-speed interface frame carrying the downlink VTDM time slot frame and then send the low-speed interface frame to the interface sending processing submodule 1-7.

[0036] The function of the interface transmission processing submodule 1-7 is to add a check value to the low-speed interface frame carrying the downstream VTDM time slot frame and then send it out.

[0037] like Figure 3 As shown, the time slot separation module 5 is composed of a first input scheduling submodule 5-1, a time slot writing submodule 5-2, a storage management submodule 5-3, a time slot reading submodule 5-4, a circuit framing submodule 5-5, a circuit sending submodule 5-6, a packet framing submodule 5-7, and a packet sending submodule 5-8. Figure 3 Connect the lines.

[0038] The function of the first input scheduling submodule 5-1 is to use polling or weighted polling to perform input scheduling processing on the low-speed interface frames carrying low-speed uplink TDMA time slot frames sent by the low-speed access processing module 1, the medium-speed interface frames carrying medium-speed uplink TDMA time slot frames sent by the medium-speed access processing module 2, the high-speed interface frames carrying high-speed uplink TDMA time slot frames sent by the high-speed access processing module 3, and the load device interface frames carrying load device time slot frames sent by the load device access processing module 4, and send the low-speed interface frames, medium-speed interface frames, high-speed interface frames, and load device interface frames that have completed the input scheduling processing to the time slot writing submodule 5-2.

[0039] The function of the time slot writing submodule 5-2 is to write different received interface frames into the storage management submodule 5-3 respectively according to the scheduling strategy.

[0040] The function of the storage management submodule 5 - 3 is to perform address space management and data scheduling management on the written interface frame to meet the processing requirements of subsequent interface frames.

[0041] The function of the time slot reading submodule 5-4 is to periodically read the interface frame from the storage management submodule 5-3, parse and separate the circuit time slot and the packet time slot from the interface frame, and send the circuit time slot to the circuit framing submodule 5-5 and the packet time slot to the packet framing submodule 5-7 respectively.

[0042] The function of the circuit framing submodule 5 - 5 is to splice, split or copy the received circuit time slots according to the resource configuration of the configuration management module 8 and then send them to the circuit sending submodule 5 - 6 .

[0043] The function of the circuit sending submodule 5 - 6 is to add an internal communication header to the received circuit time slot and then send it to the fusion switching module 6 .

[0044] The function of the packet framing submodule 5-7 is to assemble the received packet time slots into complete packet frames according to the framing rules of the packet frames for different packet time slots, and then send the packet frames to the packet sending submodule 5-8.

[0045] The function of the packet sending submodule 5 - 8 is to add an internal communication header to the received packet frame and then send it to the fusion switching module 6 .

[0046] like Figure 4 As shown, the fusion switching module 6 is composed of an input scheduling submodule 6-1, a flow classification submodule 6-2, a table lookup configuration submodule 6-3, a packet processing submodule 6-4, a circuit processing submodule 6-5, and a first output scheduling submodule 6-6. Figure 4 Connect the lines.

[0047] The function of the input scheduling submodule 6-1 is to receive the circuit time slot containing the internal communication header and the packet frame containing the internal communication header. After completing the input scheduling, the circuit time slot is sent to the circuit processing submodule 6-5 and the packet frame is sent to the flow classification submodule 6-2.

[0048] The function of the flow classification submodule 6-2 is to combine the table entry information in the table lookup configuration submodule 6-3, extract the forwarding information such as identification, address, priority, etc. in the internal communication header of the packet frame, fill in the output port information of the packet frame into the internal communication header of the packet frame, and send the packet frame to the packet processing submodule 6-4.

[0049] The function of the table lookup configuration submodule 6-3 is to provide various table entries for packet forwarding for the flow classification submodule 6-2.

[0050] The function of the packet processing submodule 6-4 is to receive the packet frames from the flow classification submodule 6-2, and send them to the first output scheduling submodule 6-6 after completing the packet processing.

[0051] The function of the circuit processing submodule 6-5 is to directly perform circuit switching processing according to the forwarding information in the communication header inside the circuit time slot, and send the processed circuit time slot to the first output scheduling submodule 6-6.

[0052] The function of the first output scheduling submodule 6 - 6 is to send the packet frames and circuit time slots to the time slot shaping module 7 respectively through polling scheduling.

[0053] like Figure 5 As shown, the time slot shaping module 7 is composed of a circuit receiving submodule 7-1, a packet receiving submodule 7-2, a second input scheduling submodule 7-3, a time slot filling submodule 7-4, a cache management module 7-5, and a second output scheduling submodule 7-6. Figure 5 Connect the lines.

[0054] The function of the circuit receiving submodule 7-1 is to receive the switched circuit time slots from the fusion switching module 6, and send them to the second input scheduling submodule 7-3 after completing the circuit time slot buffering, shaping and other processes.

[0055] The function of the packet receiving submodule 7-2 is to receive the switched packet frames from the fusion switching module 6, complete the packet frame buffering, verification and other processing, and then send the packet frames to the second input scheduling submodule 7-3.

[0056] The function of the second input scheduling submodule 7-3 is to process the circuit time slot and the packet frame respectively after receiving them. Specifically, for the circuit time slot, according to the control rules of the configuration management module 8, the circuit time slot is sent to the time slot filling submodule 7-4 after removing the internal communication header; for the packet frame, the internal communication is removed according to the cache status of the logical queue, and the packet frame is unpacked according to the downlink time slot length, and the packet time slot is formed and sent to the time slot filling submodule 7-4.

[0057] The function of the time slot filling submodule 7-4 is to load the received packet time slot and circuit time slot into the downlink VTDM time slot frame or the load device time slot frame, and send it to the buffer management module 7-5.

[0058] The function of the buffer management module 7-5 is to perform address space management and data scheduling management on the downlink VTDM time slot frame or the load device time slot frame.

[0059] The function of the second output scheduling submodule 7-6 is to schedule the downlink VTDM time slot frame or load device time slot frame of the cache management module 7-5 in real time, and send it to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the load device access processing module 4 respectively.

[0060] The brief working principle of this device is as follows: Receive the uplink TDMA time slot frame, complete decoding, verification and interface processing, convert it into an internal communication frame, parse and separate the circuit time slot and packet time slot carried by the uplink TDMA time slot frame, and then convert the packet time slot into a packet frame. Under the control of clock synchronization, both the packet frame and the circuit time slot are carried in a unified internal communication packet frame, and data is exchanged according to the frame header forwarding field of the internal communication packet frame. The exchanged circuit time slot and packet frame are carried in the downlink VTDM time slot frame through time slot shaping according to the configuration rules.

[0061] In the device, according to the beam properties and beam quantity of the satellite system, the number of modules of the low-speed access processing module 1, the medium-speed access processing module 2 and the high-speed access processing module 3 can be configured in any proportion. Considering the power consumption and weight of the onboard payload, the number of modules also needs to be limited. At the same time, the number of modules of the payload equipment access processing module 4 is generally 1, and modules can be added as appropriate according to the design requirements of the satellite payload.

[0062] For circuit services in satellite communication systems, the total number of bits in the uplink TDMA time slot and the downlink VTDM time slot is generally the same, but the uplink TDMA time slot and the downlink VTDM time slot are inconsistent in terms of single time slot length, number of time slots, etc. Therefore, the time slot separation module 5 needs to splice, split and copy the uplink TDMA time slot according to the downlink VTDM time slot resource configuration.

[0063] The fusion switching module 6 can support fusion switching of circuit time slots and packet time slots in any proportion. In extreme cases, it can support full circuit time slot switching and full packet time slot switching.

[0064] Finally, it should be noted that the above is only a preferred example of the present invention. Although the present invention has been described in detail with reference to the above embodiments, it is still possible for those skilled in the art to modify the technical solutions of the aforementioned embodiments or to make equivalent substitutions for other parts of the technical features. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A satellite circuit group fusion switching device based on time slot processing, comprising a medium-speed access processing module (2), a high-speed access processing module (3), a payload equipment access processing module (4), and a configuration management module (8), characterized in that: It also includes a low-speed access processing module (1), a time slot separation module (5), a fusion switching module (6) and a time slot shaping module (7); The low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively send the low-speed interface frame, the medium-speed interface frame, the high-speed interface frame, and the load device interface frame to the time slot separation module (5); The time slot separation module (5) parses and separates the circuit time slot and the packet time slot, adds an internal communication header to the processed circuit time slot and sends it to the fusion switching module (6), or adds an internal communication header to the packet frame and sends it to the fusion switching module (6); The fusion switching module (6) sends the processed circuit time slots and packet frames to the time slot shaping module (7); The time slot shaping module (7) sends the downlink VTDM time slot frame or the load device time slot frame to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively; The configuration management module (8) performs configuration management on the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), the load device access processing module (4), the time slot separation module (5), the fusion switching module (6) and the time slot shaping module (7).

2. The onboard circuit grouping fusion switching device based on time slot processing according to claim 1 is characterized in that: The low-speed access processing module (1) receives the low-speed interface frame carrying the low-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and low-speed interface frame processing, and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module (5); The medium-speed access processing module (2) receives the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and medium-speed interface frame processing, and then sends the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module (5); The high-speed access processing module (3) receives the high-speed interface frame carrying the high-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and high-speed interface frame processing, and then sends the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module (5); The load device access processing module (4) receives the load device interface frame carrying the load device time slot frame in the uplink, completes decoding, verification and load device interface frame processing, and then sends the load device interface frame carrying the load device time slot frame to the time slot separation module (5); After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module (1), the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module (2), the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module (3), and the load device interface frame carrying the load device time slot frame sent by the load device access processing module (4), the time slot separation module (5) separates the low-speed uplink TDMA time slot frame, the medium-speed uplink TDMA time slot frame and the load device interface frame under the unified control of the configuration management module (8). The time slot frame, the high-speed uplink TDMA time slot frame and the load device time slot frame are parsed from the corresponding interface frame and separated into the circuit time slot and the packet time slot; for the circuit time slot, splicing, splitting or copying is performed according to the resource configuration of the configuration management module (8), and the processed circuit time slot is added with an internal communication header and sent to the fusion switching module (6); for the packet time slot, according to the splicing rule of the packet frame, splicing is performed on different packet time slots to form a complete packet frame, and the packet frame is added with an internal communication header and sent to the fusion switching module (6); The fusion switching module (6) performs fast forwarding switching processing according to the forwarding identification key field in the internal communication header of the circuit time slot and the frame type, address, identification, and priority key fields in the internal communication header of the packet frame, and sends the processed circuit time slot and packet frame to the time slot shaping module (7); After receiving the circuit time slot and packet frame sent by the fusion switching module (6), the time slot shaping module (7) performs subsequent processing respectively. For the circuit time slot, according to the control rule of the configuration management module (8), the internal communication header is removed and the circuit time slot is transferred to different downstream VTDM time slot frames or load device time slot frames; for the packet frame, the internal communication header is removed according to the cache state of the logical queue, and the packet frame is deframed according to the downstream time slot length, and after the packet time slot is formed, it is loaded into different downstream VTDM time slot frames or load device time slot frames; then, the time slot shaping module (7) sends the downstream VTDM time slot frame or the load device time slot frame to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively; The low-speed access processing module (1) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a low-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the low-speed interface frame out; the medium-speed access processing module (2) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a medium-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the medium-speed interface frame out; the high-speed access processing module (3) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a high-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the high-speed interface frame out; the load device access processing module (4) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a load device interface frame carrying the load device time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the load device interface frame out; The configuration management module (8) completes the configuration management function of the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), the load device access processing module (4), the time slot separation module (5), the fusion switching module (6) and the time slot shaping module (7).

3. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The low-speed access processing module (1) comprises an interface receiving processing submodule (1-1), a decoding processing submodule (1-2), a frame format processing submodule (1-3), a time management submodule (1-4), a time slot selection submodule (1-5), a coding processing submodule (1-6), and an interface sending processing submodule (1-7); After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, the interface receiving processing submodule (1-1) performs low-speed interface frame verification processing to ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding processing submodule (1-2); After receiving the low-speed interface frame, the decoding processing submodule (1-2) decodes the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, and sends the decoded low-speed interface frame to the frame format processing submodule (1-3); The frame format processing submodule (1-3) performs synchronization and alignment operations on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame under the control of the unified clock provided by the time management submodule (1-4), and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module (5); The time management submodule (1-4) provides unified clock control for the decoding processing submodule (1-2), the frame format processing submodule (1-3), the time slot selection submodule (1-5), and the encoding processing submodule (1-6); The time slot selection submodule (1-5) receives the low-speed interface frame carrying the downlink VTDM time slot frame from the time slot shaping module (7), performs synchronization, alignment, and time slot selection on the low-speed interface frame carrying the downlink VTDM time slot frame under the control of the unified clock provided by the time management submodule (1-4), and then sends the low-speed interface frame carrying the downlink VTDM time slot frame to the encoding processing submodule (1-6); After the encoding processing submodule (1-6) completes the encoding processing of the low-speed interface frame carrying the downlink VTDM time slot frame, the low-speed interface frame carrying the downlink VTDM time slot frame is sent to the interface sending processing submodule (1-7); The interface transmission processing submodule (1-7) adds a check value to the low-speed interface frame carrying the downlink VTDM time slot frame and then sends it out.

4. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The time slot separation module (5) comprises a first input scheduling submodule (5-1), a time slot writing submodule (5-2), a storage management submodule (5-3), a time slot reading submodule (5-4), a circuit framing submodule (5-5), a circuit sending submodule (5-6), a packet framing submodule (5-7), and a packet sending submodule (5-8); The first input scheduling submodule (5-1) adopts a polling or weighted polling method to perform input scheduling processing on the low-speed interface frames carrying low-speed uplink TDMA time slot frames sent by the low-speed access processing module (1), the medium-speed interface frames carrying medium-speed uplink TDMA time slot frames sent by the medium-speed access processing module (2), the high-speed interface frames carrying high-speed uplink TDMA time slot frames sent by the high-speed access processing module (3), and the load device interface frames carrying load device time slot frames sent by the load device access processing module (4), and sends the low-speed interface frames, medium-speed interface frames, high-speed interface frames, and load device interface frames that have completed the input scheduling processing to the time slot writing submodule (5-2); The time slot writing submodule (5-2) writes the received different interface frames into the storage management submodule (5-3) respectively; The storage management submodule (5-3) performs address space management and data scheduling management on the written interface frame; The time slot reading submodule (5-4) periodically reads the interface frame from the storage management submodule (5-3), parses and separates the circuit time slot and the packet time slot from the interface frame, and sends the circuit time slot to the circuit framing submodule (5-5) and the packet time slot to the packet framing submodule (5-7); The circuit framing submodule (5-5) performs splicing, splitting or duplication processing on the received circuit time slots according to the resource configuration of the configuration management module (8), and then sends them to the circuit sending submodule (5-6); The circuit sending submodule (5-6) adds an internal communication header to the received circuit time slot and sends it to the fusion switching module (6); The packet framing submodule (5-7) performs framing processing on different packet time slots according to the framing rules of the packet frames, forms a complete packet frame, and sends the packet frame to the packet sending submodule (5-8); The packet sending submodule (5-8) adds an internal communication header to the received packet frame and sends it to the fusion switching module (6).

5. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The fusion switching module (6) comprises an input scheduling submodule (6-1), a flow classification submodule (6-2), a table lookup configuration submodule (6-3), a packet processing submodule (6-4), a circuit processing submodule (6-5), and a first output scheduling submodule (6-6); The input scheduling submodule (6-1) receives the circuit time slot containing the internal communication header and the packet frame containing the internal communication header, and after completing the input scheduling, sends the circuit time slot to the circuit processing submodule (6-5) and sends the packet frame to the flow classification submodule (6-2); The flow classification submodule (6-2) extracts the identification, address, and priority information in the internal communication header of the packet frame in combination with the table entry information in the table lookup configuration submodule (6-3), fills the egress port information of the packet frame into the internal communication header of the packet frame, and sends the packet frame to the packet processing submodule (6-4); The table lookup configuration submodule (6-3) provides various table items of packet forwarding for the flow classification submodule (6-2); The packet processing submodule (6-4) receives the packet frame from the flow classification submodule (6-2), and sends it to the first output scheduling submodule (6-6) after completing the packet processing; The circuit processing submodule (6-5) directly performs circuit switching processing according to the forwarding information in the communication header inside the circuit time slot, and sends the processed circuit time slot to the first output scheduling submodule (6-6); The first output scheduling submodule (6-6) sends the packet frames and circuit time slots to the time slot shaping module (7) respectively through polling scheduling.

6. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The time slot shaping module (7) comprises a circuit receiving submodule (7-1), a packet receiving submodule (7-2), a second input scheduling submodule (7-3), a time slot filling submodule (7-4), a cache management module (7-5), and a second output scheduling submodule (7-6); The circuit receiving submodule (7-1) receives the switched circuit time slots from the fusion switching module (6), completes the circuit time slot buffering and shaping processing, and then sends it to the second input scheduling submodule (7-3); The packet receiving submodule (7-2) receives the switched packet frame from the fusion switching module (6), completes the packet frame buffering and verification processing, and then sends the packet frame to the second input scheduling submodule (7-3); The second input scheduling submodule (7-3) processes the circuit time slot and the packet frame respectively after receiving them. For the circuit time slot, according to the control rule of the configuration management module (8), the circuit time slot is sent to the time slot filling submodule (7-4) after removing the internal communication header; for the packet frame, the internal communication is removed according to the cache state of the logical queue, and the packet frame is unpacked according to the downlink time slot length, and the packet time slot is formed and sent to the time slot filling submodule (7-4); The time slot filling submodule (7-4) loads the received packet time slot and circuit time slot into the downlink VTDM time slot frame or the load device time slot frame, and sends it to the buffer management module (7-5); The buffer management module (7-5) performs address space management and data scheduling management on the downlink VTDM time slot frame or the load device time slot frame; The second output scheduling submodule (7-6) schedules the downlink VTDM time slot frame or the load device time slot frame of the cache management module (7-5) in real time, and sends it to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively.

Images