A spaceborne circuit packet fusion switching device based on time slot processing

Abstract

The present invention provides a spaceborne circuit packet fusion switching device based on time slot processing, which relates to the field of satellite communication. The device of the present invention includes a low-speed access processing module, a medium-speed access processing module, a high-speed access processing module, a payload device access processing module, a time slot separation module, a fusion switching module, a time slot shaping module, and a configuration management module. The device receives an uplink TDMA time slot frame, converts it into an internal communication frame, parses and separates circuit time slots and packet time slots, then converts the packet time slots into packet frames, and both the packet frames and the circuit time slots are carried into a unified internal communication packet frame, and data exchange is performed according to the frame header forwarding field of the internal communication packet frame. The exchanged circuit time slots and packet frames are carried into a downlink VTDM time slot frame through time slot shaping. The present invention has the characteristics of high integration level, strong scalability, support for multiple service types, support for multiple protocol specifications, etc., and supports circuit packet fusion switching requirements in any proportion.

Description

Technical Field

[0001] The present invention relates to an on - board circuit - packet fusion switching device based on time - slot processing, belonging to the field of satellite communication. Background Art

[0002] At present, the switching mode adopted by a satellite communication system depends on the service type, traffic volume, network structure and application background of the system. Existing switching technologies include circuit switching, packet switching, or a combination of circuit and packet switching. The switching mechanism plays a decisive role in ensuring the QoS of user services, affecting both the delay and jitter of real - time services and the packet loss rate of burst services such as data. The next - generation satellite Internet system, while supporting current broadband, mobile and other packet services, also needs to support the guaranteed communication of special equipment using the traditional DVB satellite communication system under strong interference and high bit - error rate conditions. However, using a packet - switching method that forwards based on frame - header key fields will result in a large packet loss rate, making the system unavailable. Therefore, the next - generation satellite Internet system needs to support both circuit and packet switching methods. However, there is no such solution in the existing technology. Summary of the Invention

[0003] The purpose of the present invention is to solve the problems in the above - mentioned background art and provide an on - board circuit - packet fusion switching device based on time - slot processing. The present invention supports real - time switching and distribution processing of time - slot services with different rates such as low, medium and high, and has the characteristics of high integration level and strong scalability.

[0004] The purpose of the present invention is achieved as follows:

[0005] An on - board circuit - packet fusion switching device based on time - slot processing includes a medium - speed access processing module 2, a high - speed access processing module 3, a payload equipment access processing module 4, a configuration management module 8, and also includes a low - speed access processing module 1, a time - slot separation module 5, a fusion switching module 6 and a time - slot shaping module 7;

[0006] The low - speed access processing module 1, the medium - speed access processing module 2, the high - speed access processing module 3, and the payload equipment access processing module 4 respectively send low - speed interface frames, medium - speed interface frames, high - speed interface frames, and payload equipment interface frames to the time - slot separation module 5;

[0007] The time - slot separation module 5 parses and separates circuit time - slots and packet time - slots, adds an internal communication header to the processed circuit time - slots and sends them to the fusion switching module 6, or adds an internal communication header to the packet frames and sends them to the fusion switching module 6;

[0008] The fusion switching module 6 sends the processed circuit time - slots and packet frames to the time - slot shaping module 7;

[0009] The time slot shaping module 7 sends the downlink VTDM time slot frame or the payload device time slot frame to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the payload device access processing module 4 respectively;

[0010] The configuration management module 8 performs configuration management on the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, the payload device access processing module 4, the time slot separation module 5, the fusion switching module 6, and the time slot shaping module 7.

[0011] Furthermore, the low-speed access processing module 1 receives an uplink low-speed interface frame carrying a low-speed uplink TDMA time slot frame. After completing decoding, verification, and low-speed interface frame processing, it sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5;

[0012] The medium-speed access processing module 2 receives an uplink medium-speed interface frame carrying a medium-speed uplink TDMA time slot frame. After completing decoding, verification, and medium-speed interface frame processing, it sends the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module 5;

[0013] The high-speed access processing module 3 receives an uplink high-speed interface frame carrying a high-speed uplink TDMA time slot frame. After completing decoding, verification, and high-speed interface frame processing, it sends the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module 5;

[0014] The payload device access processing module 4 receives an uplink payload device interface frame carrying a payload device time slot frame. After completing decoding, verification, and payload device interface frame processing, it sends the payload device interface frame carrying the payload device time slot frame to the time slot separation module 5;

[0015] After the time slot separation module 5 receives the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module 1, the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module 2, the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module 3, and the payload device interface frame carrying the payload device time slot frame sent by the payload device access processing module 4, under the unified control of the configuration management module 8, it parses and separates the circuit time slots and packet time slots from the corresponding interface frames for the low-speed uplink TDMA time slot frame, medium-speed uplink TDMA time slot frame, high-speed uplink TDMA time slot frame, and payload device time slot frame; for the circuit time slots, according to the resource configuration of the configuration management module 8, splicing, splitting, or copying processing is performed, and the processed circuit time slots are sent to the fusion switching module 6 after adding an internal communication header; for the packet time slots, according to the frame assembly rules of the packet frames, different packet time slots are respectively assembled into complete packet frames, and the packet frames are sent to the fusion switching module 6 after adding an internal communication header;

[0016] The fusion switching module 6 performs fast forwarding and switching processing according to the forwarding identification keyword field in the internal communication header of the circuit time slot and the frame type, address, identification, and priority keyword fields in the internal communication header of the packet frame, and sends the processed circuit time slots and packet frames to the time slot shaping module 7;

[0017] After the time slot shaping module 7 receives the circuit time slots and packet frames sent by the fusion switching module 6, subsequent processing is respectively performed. For the circuit time slots, according to the control rules of the configuration management module 8, after removing the internal communication header, the circuit time slots are respectively loaded into different downlink VTDM time slot frames or payload device time slot frames; for the packet frames, according to the cache status of the logical queue, the internal communication header is removed, and the packet frames are disassembled according to the downlink time slot length to form packet time slots and then respectively loaded into different downlink VTDM time slot frames or payload device time slot frames; then, the time slot shaping module 7 sends the downlink VTDM time slot frames or payload device time slot frames to the low-speed access processing module 1, medium-speed access processing module 2, high-speed access processing module 3, and payload device access processing module 4 respectively;

[0018] The low-speed access processing module 1 receives the downlink VTDM time slot frame sent by the time slot shaping module 7. After completing verification, synchronization, encoding, and interface sub-frame processing, it forms a low-speed interface frame carrying the downlink VTDM time slot frame and sends the low-speed interface frame out; the medium-speed access processing module 2 receives the downlink VTDM time slot frame sent by the time slot shaping module 7. After completing verification, synchronization, encoding, and interface sub-frame processing, it forms a medium-speed interface frame carrying the downlink VTDM time slot frame and sends the medium-speed interface frame out; the high-speed access processing module 3 receives the downlink VTDM time slot frame sent by the time slot shaping module 7. After completing verification, synchronization, encoding, and interface sub-frame processing, it forms a high-speed interface frame carrying the downlink VTDM time slot frame and sends the high-speed interface frame out; the payload device access processing module 4 receives the downlink VTDM time slot frame sent by the time slot shaping module 7. After completing verification, synchronization, encoding, and interface sub-frame processing, it forms a payload device interface frame carrying the payload device time slot frame and sends the payload device interface frame out;

[0019] The configuration management module 8 completes the configuration management functions for the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, the payload device access processing module 4, the time slot separation module 5, the fusion switching module 6, and the time slot shaping module 7.

[0020] Furthermore, the low-speed access processing module 1 includes an interface receiving and processing sub-module 1-1, a decoding processing sub-module 1-2, a frame format processing sub-module 1-3, a time management sub-module 1-4, a time slot selection sub-module 1-5, an encoding processing sub-module 1-6, and an interface sending and processing sub-module 1-7;

[0021] After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, the interface receiving and processing sub-module 1-1 performs low-speed interface frame verification processing to ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding processing sub-module 1-2;

[0022] After receiving the low-speed interface frame, the decoding processing sub-module 1-2 performs decoding processing on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, and sends the decoded low-speed interface frame to the frame format processing sub-module 1-3;

[0023] Under the control of the unified clock provided by the time management sub-module 1-4, the frame format processing sub-module 1-3 performs synchronization and alignment operations on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module 5;

[0024] The time management sub-module 1-4 provides unified clock control for the decoding processing sub-module 1-2, the frame format processing sub-module 1-3, the time slot selection sub-module 1-5, and the encoding processing sub-module 1-6;

[0025] The time slot selection sub-module 1-5 receives the low-speed interface frame carrying the downlink VTDM time slot frame from the time slot shaping module 7, synchronizes, aligns, and selects time slots for the low-speed interface frame carrying the downlink VTDM time slot frame under the unified clock control provided by the time management sub-module 1-4, and then sends the low-speed interface frame carrying the downlink VTDM time slot frame to the encoding processing sub-module 1-6;

[0026] After the encoding processing sub-module 1-6 completes the encoding processing of the low-speed interface frame carrying the downlink VTDM time slot frame, it sends the low-speed interface frame to the interface sending processing sub-module 1-7;

[0027] The interface sending processing sub-module 1-7 adds a check value to the low-speed interface frame carrying the downlink VTDM time slot frame and then sends it out.

[0028] Furthermore, the time slot separation module 5 includes a first input scheduling sub-module 5-1, a time slot writing sub-module 5-2, a storage management sub-module 5-3, a time slot reading sub-module 5-4, a circuit framing sub-module 5-5, a circuit sending sub-module 5-6, a packet framing sub-module 5-7, and a packet sending sub-module 5-8;

[0029] The first input scheduling sub-module 5-1 uses a polling or weighted polling method to perform input scheduling processing on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module 1, the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module 2, the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module 3, and the payload device interface frame carrying the payload device time slot frame sent by the payload device access processing module 4, and sends the completed low-speed interface frame, medium-speed interface frame, high-speed interface frame, and payload device interface frame to the time slot writing sub-module 5-2;

[0030] The time slot writing sub-module 5-2 writes the received different interface frames into the storage management sub-module 5-3 respectively;

[0031] The storage management sub-module 5-3 performs address space management and data scheduling management on the written interface frames;

[0032] The time slot reading sub-module 5-4 periodically reads interface frames from the storage management sub-module 5-3, parses and separates circuit time slots and packet time slots from the interface frames, and sends the circuit time slots to the circuit framing sub-module 5-5 and the packet time slots to the packet framing sub-module 5-7 respectively;

[0033] The circuit framing sub-module 5-5 splices, splits or duplicates the received circuit time slots according to the resource configuration of the configuration management module 8, and then sends them to the circuit sending sub-module 5-6;

[0034] The circuit sending sub-module 5-6 adds an internal communication header to the received circuit time slots and sends them to the fusion switching module 6;

[0035] The packet framing sub-module 5-7 frames the received packet time slots respectively according to the framing rules of the packet frame to form a complete packet frame, and sends the packet frame to the packet sending sub-module 5-8;

[0036] The packet sending sub-module 5-8 adds an internal communication header to the received packet frame and sends it to the fusion switching module 6.

[0037] Furthermore, the fusion switching module 6 includes an input scheduling sub-module 6-1, a flow classification sub-module 6-2, a table lookup configuration sub-module 6-3, a packet processing sub-module 6-4, a circuit processing sub-module 6-5, and a first output scheduling sub-module 6-6;

[0038] The input scheduling sub-module 6-1 receives the circuit time slots with internal communication headers and the packet frames with internal communication headers. After completing the input scheduling, it sends the circuit time slots to the circuit processing sub-module 6-5 and the packet frames to the flow classification sub-module 6-2;

[0039] The flow classification sub-module 6-2 combines the entry information in the table lookup configuration sub-module 6-3, extracts the identification, address, and priority information in the internal communication header of the packet frame, fills in the output port information of the packet frame into the internal communication header of the packet frame, and sends the packet frame to the packet processing sub-module 6-4;

[0040] The table lookup configuration sub-module 6-3 provides various entries for packet forwarding to the flow classification sub-module 6-2;

[0041] The packet processing sub-module 6-4 receives the packet frames from the flow classification sub-module 6-2, and after completing the packet processing, sends them to the first output scheduling sub-module 6-6;

[0042] The circuit processing sub-module 6-5 directly performs circuit switching processing according to the forwarding information in the internal communication header of the circuit time slots, and sends the processed circuit time slots to the first output scheduling sub-module 6-6;

[0043] The first output scheduling sub-module 6-6 sends the packet frames and circuit time slots to the time slot shaping module 7 respectively by means of round-robin scheduling.

[0044] Furthermore, the time slot shaping module 7 includes a circuit receiving sub-module 7-1, a packet receiving sub-module 7-2, a second input scheduling sub-module 7-3, a time slot filling sub-module 7-4, a cache management module 7-5, and a second output scheduling sub-module 7-6;

[0045] The circuit receiving sub-module 7-1 receives the circuit time slots that have completed switching from the fusion switching module 6, and after completing the caching and shaping processing of the circuit time slots, sends them to the second input scheduling sub-module 7-3;

[0046] The packet receiving sub-module 7-2 receives the packet frames that have completed switching from the fusion switching module 6, and after completing the caching and verification processing of the packet frames, sends the packet frames to the second input scheduling sub-module 7-3;

[0047] After receiving the circuit time slots and packet frames, the second input scheduling sub-module 7-3 processes them respectively. For the circuit time slots, according to the control rules of the configuration management module 8, after removing the internal communication header, the circuit time slots are sent to the time slot filling sub-module 7-4; for the packet frames, after removing the internal communication according to the caching status of the logical queue, and unpacking the packet frames according to the length of the downlink time slots to form packet time slots, which are then sent to the time slot filling sub-module 7-4;

[0048] The time slot filling sub-module 7-4 loads the received packet time slots and circuit time slots into the downlink VTDM time slot frame or the payload device time slot frame, and sends them to the cache management module 7-5;

[0049] The cache management module 7-5 performs address space management and data scheduling management on the downlink VTDM time slot frame or the payload device time slot frame;

[0050] The second output scheduling sub-module 7-6 schedules the downlink VTDM time slot frame or the payload device time slot frame of the cache management module 7-5 in real time, and sends them to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the payload device access processing module 4 respectively.

[0051] The present invention has the following advantages compared with the background technology:

[0052] 1. The present invention supports the access of data with different rate interfaces such as low, medium, and high, and has the characteristics of high integration level and strong scalability.

[0053] 2. The present invention can support the fusion switching of circuit services and packet services in any proportion, and meet the fusion processing requirements of circuit services and packet services.

[0054] 3. The present invention can support the Qos scheduling of packet services based on priorities, and support the guarantee scheduling of circuit services based on resource reservation.

[0055] 4. The present invention is particularly applicable to a spaceborne switching system with multiple service types and various rate requirements, and can be used to implement a spaceborne circuit packet fusion payload device. Description of the Drawings

[0056] Figure 1 It is the electrical principle block diagram of a spaceborne circuit packet fusion switching device based on time slot processing in an embodiment of the present invention.

[0057] Figure 2 is Figure 1 the electrical principle block diagram of the low and medium speed access processing module.

[0058] Figure 3 is Figure 1 the electrical principle block diagram of the medium time slot separation module.

[0059] Figure 4 is Figure 1 the electrical principle block diagram of the fusion switching module.

[0060] Figure 5 is Figure 1 the electrical principle block diagram of the time slot shaping module. Detailed Embodiment

[0061] The present invention will be further described below in conjunction with the drawings and specific embodiments.

[0062] Referring to Figure 1 , a spaceborne circuit packet fusion switching device based on time slot processing includes a low speed access processing module 1, a medium speed access processing module 2, a high speed access processing module 3, a payload device access processing module 4, a time slot separation module 5, a fusion switching module 6, a time slot shaping module 7, and a configuration management module 8. The composition and the connection relationship between modules of the sub-modules of the medium speed access processing module 2, the high speed access processing module 3, and the payload device access processing module 4 and the low speed access processing module 1 are the same, and the difference lies in the cache capacity, information processing capacity, etc. of each sub-module. Figure 1 It is the electrical schematic diagram of a spaceborne circuit packet fusion switching device based on time slot processing, and the embodiment is connected according to Figure 1 the connection lines.

[0063] Among them, the function of the low speed access processing module 1 is to receive the low speed interface frame carrying the low speed uplink TDMA time slot frame from the upstream, and after completing decoding, verification, and low speed interface frame processing, send the low speed interface frame carrying the low speed uplink TDMA time slot frame to the time slot separation module 5. In addition, the low speed access processing module 1 receives the downlink VTDM time slot frame sent by the time slot shaping module 7, and after completing operations such as verification, synchronization, encoding, and interface sub-frame processing, forms a low speed interface frame carrying the downlink VTDM time slot frame, and sends out this low speed interface frame.

[0064] The function of the medium-speed access processing module 2 is to receive, on the uplink, a medium-speed interface frame carrying a medium-speed uplink TDMA time slot frame. After completing decoding, verification, and medium-speed interface frame processing, it sends the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module 5. In addition, when the medium-speed access processing module 2 receives a downlink VTDM time slot frame sent by the time slot shaping module 7, it forms a medium-speed interface frame carrying the downlink VTDM time slot frame after completing operations such as verification, synchronization, encoding, and interface sub-frame processing, and sends out this medium-speed interface frame.

[0065] The function of the high-speed access processing module 3 is to receive, on the uplink, a high-speed interface frame carrying a high-speed uplink TDMA time slot frame. After completing decoding, verification, and high-speed interface frame processing, it sends the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module 5. In addition, when the high-speed access processing module 3 receives a downlink VTDM time slot frame sent by the time slot shaping module 7, it forms a high-speed interface frame carrying the downlink VTDM time slot frame after completing operations such as verification, synchronization, encoding, and interface sub-frame processing, and sends out this high-speed interface frame.

[0066] The function of the payload device access processing module 4 is to receive, on the uplink, a payload device interface frame carrying a payload device time slot frame. After completing decoding, verification, and payload device interface frame processing, it sends the payload device interface frame carrying the payload device time slot frame to the time slot separation module 5. In addition, when the payload device access processing module 4 receives a downlink VTDM time slot frame sent by the time slot shaping module 7, it forms a payload device interface frame carrying the payload device time slot frame after completing operations such as verification, synchronization, encoding, and interface sub-frame processing, and sends out this payload device interface frame.

[0067] The function of the time slot separation module 5 is to receive the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module 1, the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module 2, the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module 3, and the payload device interface frame carrying the payload device time slot frame sent by the payload device access processing module 4. Under the unified control of the configuration management module 8, it resolves and separates the circuit time slots and packet time slots from the corresponding interface frames for the low-speed uplink TDMA time slot frame, medium-speed uplink TDMA time slot frame, high-speed uplink TDMA time slot frame, and payload device time slot frame. Specifically, for the circuit time slots, splicing, splitting, or copying processing needs to be performed according to the resource configuration of the configuration management module 8, and the processed circuit time slots are sent to the fusion switching module 6 after adding an internal communication header; for the packet time slots, according to the frame assembly rules of the packet frames, the different packet time slots are respectively assembled into complete packet frames, and the packet frames are sent to the fusion switching module 6 after adding an internal communication header.

[0068] The function of the fusion switching module 6 is to perform fast forwarding and switching processing based on keyword fields such as the forwarding identifier in the internal communication header of the circuit time slot and keyword fields such as the frame type, address, identifier, and priority in the internal communication header of the packet frame, and send the processed circuit time slot and packet frame to the time slot shaping module 7.

[0069] After receiving the circuit time slot and packet frame sent by the fusion switching module 6, the time slot shaping module 7 performs subsequent processing respectively. Specifically, for the circuit time slot, according to the control rules of the configuration management module 8, after removing the internal communication header, the circuit time slot is respectively loaded into different downstream VTDM time slot frames or payload device time slot frames; for the packet frame, according to the cache status of the logical queue, the internal communication header is removed, and the packet frame is disassembled according to the downstream time slot length to form packet time slots, which are then respectively loaded into different downstream VTDM time slot frames or payload device time slot frames. Then, the time slot shaping module 7 sends the downstream VTDM time slot frame or payload device time slot frame to the low-speed access processing module 1, medium-speed access processing module 2, high-speed access processing module 3, and payload device access processing module 4 respectively.

[0070] The function of the configuration management module 8 is to complete the configuration management functions of the low-speed access processing module 1, medium-speed access processing module 2, high-speed access processing module 3, payload device access processing module 4, time slot separation module 5, fusion switching module 6, and time slot shaping module 7.

[0071] As Figure 2 shown, the low-speed access processing module 1 consists of an interface receiving and processing sub-module 1-1, a decoding processing sub-module 1-2, a frame format processing sub-module 1-3, a time management sub-module 1-4, a time slot selection sub-module 1-5, an encoding processing sub-module 1-6, and an interface sending and processing sub-module 1-7. The embodiment is in accordance with Figure 2 the connection line.

[0072] The function of the interface receiving and processing sub-module 1-1 is to perform low-speed interface frame verification processing after receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and send the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding processing sub-module 1-2.

[0073] The function of the decoding processing sub-module 1-2 is to perform decoding processing on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame using a decoding algorithm after receiving the low-speed interface frame, and send the decoded low-speed interface frame to the frame format processing sub-module 1-3.

[0074] The function of the frame format processing sub-module 1-3 is to perform operations such as synchronization and alignment on the low-speed interface frames carrying the low-speed uplink TDMA time slot frames under the unified clock control provided by the time management sub-module 1-4, and then send the low-speed interface frames carrying the low-speed uplink TDMA time slot frames to the time slot separation module 5 for subsequent processing.

[0075] The function of the time management sub-module 1-4 is to provide unified clock control for the decoding processing sub-module 1-2, the frame format processing sub-module 1-3, the time slot selection sub-module 1-5, and the encoding processing sub-module 1-6.

[0076] The function of the time slot selection sub-module 1-5 is to receive the low-speed interface frames carrying the downlink VTDM time slot frames from the time slot shaping module 7, perform operations such as synchronization, alignment, and time slot selection on the low-speed interface frames carrying the downlink VTDM time slot frames under the unified clock control provided by the time management sub-module 1-4, and then send the low-speed interface frames carrying the downlink VTDM time slot frames to the encoding processing sub-module 1-6.

[0077] The function of the encoding processing sub-module 1-6 is to complete the encoding processing of the low-speed interface frames carrying the downlink VTDM time slot frames, and then send the low-speed interface frames carrying the low-speed interface frames to the interface sending processing sub-module 1-7.

[0078] The function of the interface sending processing sub-module 1-7 is to add a check value to the low-speed interface frames carrying the downlink VTDM time slot frames and then send them out.

[0079] As Figure 3 shown, the time slot separation module 5 consists of a first input scheduling sub-module 5-1, a time slot writing sub-module 5-2, a storage management sub-module 5-3, a time slot reading sub-module 5-4, a circuit framing sub-module 5-5, a circuit sending sub-module 5-6, a packet framing sub-module 5-7, and a packet sending sub-module 5-8. The embodiments are in accordance with Figure 3 the connection lines.

[0080] The function of the first input scheduling sub-module 5-1 is to perform input scheduling processing on the low-speed interface frames carrying the low-speed uplink TDMA time slot frames sent by the low-speed access processing module 1, the medium-speed interface frames carrying the medium-speed uplink TDMA time slot frames sent by the medium-speed access processing module 2, the high-speed interface frames carrying the high-speed uplink TDMA time slot frames sent by the high-speed access processing module 3, and the payload device interface frames carrying the payload device time slot frames sent by the payload device access processing module 4 by means of polling or weighted polling, and send the completed low-speed interface frames, medium-speed interface frames, high-speed interface frames, and payload device interface frames to the time slot writing sub-module 5-2.

[0081] The function of the time slot writing sub-module 5-2 is to write the received different interface frames into the storage management sub-module 5-3 according to the scheduling strategy.

[0082] The function of the storage management sub-module 5-3 is to manage the address space and data scheduling of the written interface frames to meet the processing requirements of subsequent interface frames.

[0083] The function of the time slot reading sub-module 5-4 is to regularly read interface frames from the storage management sub-module 5-3, parse and separate the circuit time slots and packet time slots from the interface frames, and send the circuit time slots to the circuit framing sub-module 5-5 and the packet time slots to the packet framing sub-module 5-7 respectively.

[0084] The function of the circuit framing sub-module 5-5 is to splice, split or copy the received circuit time slots according to the resource configuration of the configuration management module 8 and then send them to the circuit sending sub-module 5-6.

[0085] The function of the circuit sending sub-module 5-6 is to add an internal communication header to the received circuit time slots and then send them to the fusion switching module 6.

[0086] The function of the packet framing sub-module 5-7 is to frame the received packet time slots respectively according to the framing rules of the packet frames to form complete packet frames, and send the packet frames to the packet sending sub-module 5-8.

[0087] The function of the packet sending sub-module 5-8 is to add an internal communication header to the received packet frames and then send them to the fusion switching module 6.

[0088] As Figure 4 shown, the fusion switching module 6 consists of an input scheduling sub-module 6-1, a flow classification sub-module 6-2, a table lookup configuration sub-module 6-3, a packet processing sub-module 6-4, a circuit processing sub-module 6-5, and a first output scheduling sub-module 6-6. The embodiment is connected according to Figure 4 the connection lines.

[0089] The function of the input scheduling sub-module 6-1 is to receive the circuit time slots with internal communication headers and the packet frames with internal communication headers. After completing the input scheduling, it sends the circuit time slots to the circuit processing sub-module 6-5 and the packet frames to the flow classification sub-module 6-2.

[0090] The function of the flow classification sub-module 6-2 is to combine the entry information in the table lookup configuration sub-module 6-3, extract the forwarding information such as identification, address, and priority in the internal communication header of the packet frame, fill in the output port information of the packet frame into the internal communication header of the packet frame, and send the packet frame to the packet processing sub-module 6-4.

[0091] The function of the table lookup configuration sub-module 6-3 is to provide various entries for packet forwarding to the flow classification sub-module 6-2.

[0092] The function of the packet processing sub-module 6-4 is to receive the packet frames from the flow classification sub-module 6-2, and after completing the packet processing, send them to the first output scheduling sub-module 6-6.

[0093] The function of the circuit processing sub-module 6-5 is to directly perform circuit switching processing according to the forwarding information in the internal communication header of the circuit time slot, and send the processed circuit time slot to the first output scheduling sub-module 6-6.

[0094] The function of the first output scheduling sub-module 6-6 is to send the packet frames and circuit time slots to the time slot shaping module 7 respectively through the polling scheduling method.

[0095] As Figure 5 shown, the time slot shaping module 7 consists of a circuit receiving sub-module 7-1, a packet receiving sub-module 7-2, a second input scheduling sub-module 7-3, a time slot filling sub-module 7-4, a buffer management module 7-5, and a second output scheduling sub-module 7-6. The embodiment is in accordance with Figure 5 the connection line.

[0096] The function of the circuit receiving sub-module 7-1 is to receive the circuit time slots that have completed switching from the fusion switching module 6, and after completing processing such as circuit time slot caching and shaping, send them to the second input scheduling sub-module 7-3.

[0097] The function of the packet receiving sub-module 7-2 is to receive the packet frames that have completed switching from the fusion switching module 6, and after completing processing such as packet frame caching and verification, send the packet frames to the second input scheduling sub-module 7-3.

[0098] The function of the second input scheduling sub-module 7-3 is to process the circuit time slots and packet frames respectively after receiving them. Specifically, for the circuit time slots, according to the control rules of the configuration management module 8, after removing the internal communication header, send the circuit time slots to the time slot filling sub-module 7-4; for the packet frames, according to the cache status of the logical queue, remove the internal communication, and unpack the packet frames according to the length of the downlink time slot to form packet time slots and send them to the time slot filling sub-module 7-4.

[0099] The function of the time slot filling sub-module 7-4 is to load the received packet time slots and circuit time slots into the downlink VTDM time slot frame or the payload device time slot frame, and send them to the buffer management module 7-5.

[0100] The function of the buffer management module 7-5 is to perform address space management and data scheduling management on the downlink VTDM time slot frame or the payload device time slot frame.

[0101] The function of the second output scheduling sub-module 7-6 is to schedule the downlink VTDM time slot frames or payload device time slot frames of the cache management module 7-5 in real time and send them to the low-speed access processing module 1, the medium-speed access processing module 2, the high-speed access processing module 3, and the payload device access processing module 4 respectively.

[0102] The brief working principle of this device is as follows:

[0103] Receive the uplink TDMA time slot frame. After completing decoding, verification, and interface processing, convert it into an internal communication frame, parse and separate the circuit time slot and packet time slot carried by the uplink TDMA time slot frame, then convert the packet time slot into a packet frame. Under the control of clock synchronization, carry both the packet frame and the circuit time slot into a unified internal communication packet frame, and perform data exchange according to the frame header forwarding field of the internal communication packet frame. The exchanged circuit time slot and packet frame are carried into the downlink VTDM time slot frame in the form of time slot shaping according to the configuration rules.

[0104] In this device, according to the beam properties and the number of beams equipped in the satellite system, the number of modules of the low-speed access processing module 1, the medium-speed access processing module 2, and the high-speed access processing module 3 can be configured in any proportion. Considering the limitations of on-board payload power consumption, weight, etc., the number of modules also needs to be limited to a certain extent. At the same time, the number of modules of the payload device access processing module 4 is generally 1, and the number of modules can also be increased as appropriate according to the design requirements of the satellite payload.

[0105] In the satellite communication system for circuit services, the total number of bits of the uplink TDMA time slot and the downlink VTDM time slot is generally the same, but the uplink TDMA time slot and the downlink VTDM time slot are inconsistent in terms of single time slot length, number of time slots, etc. Therefore, the time slot separation module 5 needs to perform processing such as splicing, splitting, and copying on the uplink TDMA time slot according to the downlink VTDM time slot resource configuration.

[0106] The fusion switching module 6 can support the fusion switching of circuit time slots and packet time slots in any proportion. In extreme cases, it can support full circuit time slot switching or full packet time slot switching.

[0107] Finally, it should be noted that the above are only the preferred examples of the present invention. Although the present invention has been described in detail with reference to the above embodiments, for those skilled in the art, they can still modify the technical solutions of the foregoing embodiments, or perform equivalent replacements on other technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A satellite circuit group fusion switching device based on time slot processing, comprising a medium-speed access processing module (2), a high-speed access processing module (3), a payload equipment access processing module (4), and a configuration management module (8), characterized in that: It also includes a low-speed access processing module (1), a time slot separation module (5), a fusion switching module (6) and a time slot shaping module (7); The low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively send the low-speed interface frame, the medium-speed interface frame, the high-speed interface frame, and the load device interface frame to the time slot separation module (5); The time slot separation module (5) parses and separates the circuit time slot and the packet time slot, adds an internal communication header to the processed circuit time slot and sends it to the fusion switching module (6), or adds an internal communication header to the packet frame and sends it to the fusion switching module (6); The fusion switching module (6) sends the processed circuit time slots and packet frames to the time slot shaping module (7); The time slot shaping module (7) sends the downlink VTDM time slot frame or the load device time slot frame to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively; The configuration management module (8) performs configuration management on the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), the load device access processing module (4), the time slot separation module (5), the fusion switching module (6) and the time slot shaping module (7).

2. The onboard circuit grouping fusion switching device based on time slot processing according to claim 1 is characterized in that: The low-speed access processing module (1) receives the low-speed interface frame carrying the low-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and low-speed interface frame processing, and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module (5); The medium-speed access processing module (2) receives the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and medium-speed interface frame processing, and then sends the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame to the time slot separation module (5); The high-speed access processing module (3) receives the high-speed interface frame carrying the high-speed uplink TDMA time slot frame in the uplink, completes decoding, verification and high-speed interface frame processing, and then sends the high-speed interface frame carrying the high-speed uplink TDMA time slot frame to the time slot separation module (5); The load device access processing module (4) receives the load device interface frame carrying the load device time slot frame in the uplink, completes decoding, verification and load device interface frame processing, and then sends the load device interface frame carrying the load device time slot frame to the time slot separation module (5); After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame sent by the low-speed access processing module (1), the medium-speed interface frame carrying the medium-speed uplink TDMA time slot frame sent by the medium-speed access processing module (2), the high-speed interface frame carrying the high-speed uplink TDMA time slot frame sent by the high-speed access processing module (3), and the load device interface frame carrying the load device time slot frame sent by the load device access processing module (4), the time slot separation module (5) separates the low-speed uplink TDMA time slot frame, the medium-speed uplink TDMA time slot frame and the load device interface frame under the unified control of the configuration management module (8). The time slot frame, the high-speed uplink TDMA time slot frame and the load device time slot frame are parsed from the corresponding interface frame and separated into the circuit time slot and the packet time slot; for the circuit time slot, splicing, splitting or copying is performed according to the resource configuration of the configuration management module (8), and the processed circuit time slot is added with an internal communication header and sent to the fusion switching module (6); for the packet time slot, according to the splicing rule of the packet frame, splicing is performed on different packet time slots to form a complete packet frame, and the packet frame is added with an internal communication header and sent to the fusion switching module (6); The fusion switching module (6) performs fast forwarding switching processing according to the forwarding identification key field in the internal communication header of the circuit time slot and the frame type, address, identification, and priority key fields in the internal communication header of the packet frame, and sends the processed circuit time slot and packet frame to the time slot shaping module (7); After receiving the circuit time slot and packet frame sent by the fusion switching module (6), the time slot shaping module (7) performs subsequent processing respectively. For the circuit time slot, according to the control rule of the configuration management module (8), the internal communication header is removed and the circuit time slot is transferred to different downstream VTDM time slot frames or load device time slot frames; for the packet frame, the internal communication header is removed according to the cache state of the logical queue, and the packet frame is deframed according to the downstream time slot length, and after the packet time slot is formed, it is loaded into different downstream VTDM time slot frames or load device time slot frames; then, the time slot shaping module (7) sends the downstream VTDM time slot frame or the load device time slot frame to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively; The low-speed access processing module (1) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a low-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the low-speed interface frame out; the medium-speed access processing module (2) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a medium-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the medium-speed interface frame out; the high-speed access processing module (3) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a high-speed interface frame carrying the downlink VTDM time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the high-speed interface frame out; the load device access processing module (4) receives the downlink VTDM time slot frame sent by the time slot shaping module (7), forms a load device interface frame carrying the load device time slot frame after completing the check, synchronization, coding and interface subframe processing, and sends the load device interface frame out; The configuration management module (8) completes the configuration management function of the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), the load device access processing module (4), the time slot separation module (5), the fusion switching module (6) and the time slot shaping module (7).

3. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The low-speed access processing module (1) comprises an interface receiving processing submodule (1-1), a decoding processing submodule (1-2), a frame format processing submodule (1-3), a time management submodule (1-4), a time slot selection submodule (1-5), a coding processing submodule (1-6), and an interface sending processing submodule (1-7); After receiving the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, the interface receiving processing submodule (1-1) performs low-speed interface frame verification processing to ensure that the low-speed interface frame meets the requirements of the low-speed interface protocol, and sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the decoding processing submodule (1-2); After receiving the low-speed interface frame, the decoding processing submodule (1-2) decodes the low-speed interface frame carrying the low-speed uplink TDMA time slot frame, and sends the decoded low-speed interface frame to the frame format processing submodule (1-3); The frame format processing submodule (1-3) performs synchronization and alignment operations on the low-speed interface frame carrying the low-speed uplink TDMA time slot frame under the control of the unified clock provided by the time management submodule (1-4), and then sends the low-speed interface frame carrying the low-speed uplink TDMA time slot frame to the time slot separation module (5); The time management submodule (1-4) provides unified clock control for the decoding processing submodule (1-2), the frame format processing submodule (1-3), the time slot selection submodule (1-5), and the encoding processing submodule (1-6); The time slot selection submodule (1-5) receives the low-speed interface frame carrying the downlink VTDM time slot frame from the time slot shaping module (7), performs synchronization, alignment, and time slot selection on the low-speed interface frame carrying the downlink VTDM time slot frame under the control of the unified clock provided by the time management submodule (1-4), and then sends the low-speed interface frame carrying the downlink VTDM time slot frame to the encoding processing submodule (1-6); After the encoding processing submodule (1-6) completes the encoding processing of the low-speed interface frame carrying the downlink VTDM time slot frame, the low-speed interface frame carrying the downlink VTDM time slot frame is sent to the interface sending processing submodule (1-7); The interface transmission processing submodule (1-7) adds a check value to the low-speed interface frame carrying the downlink VTDM time slot frame and then sends it out.

4. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The time slot separation module (5) comprises a first input scheduling submodule (5-1), a time slot writing submodule (5-2), a storage management submodule (5-3), a time slot reading submodule (5-4), a circuit framing submodule (5-5), a circuit sending submodule (5-6), a packet framing submodule (5-7), and a packet sending submodule (5-8); The first input scheduling submodule (5-1) adopts a polling or weighted polling method to perform input scheduling processing on the low-speed interface frames carrying low-speed uplink TDMA time slot frames sent by the low-speed access processing module (1), the medium-speed interface frames carrying medium-speed uplink TDMA time slot frames sent by the medium-speed access processing module (2), the high-speed interface frames carrying high-speed uplink TDMA time slot frames sent by the high-speed access processing module (3), and the load device interface frames carrying load device time slot frames sent by the load device access processing module (4), and sends the low-speed interface frames, medium-speed interface frames, high-speed interface frames, and load device interface frames that have completed the input scheduling processing to the time slot writing submodule (5-2); The time slot writing submodule (5-2) writes the received different interface frames into the storage management submodule (5-3) respectively; The storage management submodule (5-3) performs address space management and data scheduling management on the written interface frame; The time slot reading submodule (5-4) periodically reads the interface frame from the storage management submodule (5-3), parses and separates the circuit time slot and the packet time slot from the interface frame, and sends the circuit time slot to the circuit framing submodule (5-5) and the packet time slot to the packet framing submodule (5-7); The circuit framing submodule (5-5) performs splicing, splitting or duplication processing on the received circuit time slots according to the resource configuration of the configuration management module (8), and then sends them to the circuit sending submodule (5-6); The circuit sending submodule (5-6) adds an internal communication header to the received circuit time slot and sends it to the fusion switching module (6); The packet framing submodule (5-7) performs framing processing on different packet time slots according to the framing rules of the packet frames, forms a complete packet frame, and sends the packet frame to the packet sending submodule (5-8); The packet sending submodule (5-8) adds an internal communication header to the received packet frame and sends it to the fusion switching module (6).

5. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The fusion switching module (6) comprises an input scheduling submodule (6-1), a flow classification submodule (6-2), a table lookup configuration submodule (6-3), a packet processing submodule (6-4), a circuit processing submodule (6-5), and a first output scheduling submodule (6-6); The input scheduling submodule (6-1) receives the circuit time slot containing the internal communication header and the packet frame containing the internal communication header, and after completing the input scheduling, sends the circuit time slot to the circuit processing submodule (6-5) and sends the packet frame to the flow classification submodule (6-2); The flow classification submodule (6-2) extracts the identification, address, and priority information in the internal communication header of the packet frame in combination with the table entry information in the table lookup configuration submodule (6-3), fills the egress port information of the packet frame into the internal communication header of the packet frame, and sends the packet frame to the packet processing submodule (6-4); The table lookup configuration submodule (6-3) provides various table items of packet forwarding for the flow classification submodule (6-2); The packet processing submodule (6-4) receives the packet frame from the flow classification submodule (6-2), and sends it to the first output scheduling submodule (6-6) after completing the packet processing; The circuit processing submodule (6-5) directly performs circuit switching processing according to the forwarding information in the communication header inside the circuit time slot, and sends the processed circuit time slot to the first output scheduling submodule (6-6); The first output scheduling submodule (6-6) sends the packet frames and circuit time slots to the time slot shaping module (7) respectively through polling scheduling.

6. The onboard circuit grouping fusion switching device based on time slot processing according to claim 2 is characterized in that: The time slot shaping module (7) comprises a circuit receiving submodule (7-1), a packet receiving submodule (7-2), a second input scheduling submodule (7-3), a time slot filling submodule (7-4), a cache management module (7-5), and a second output scheduling submodule (7-6); The circuit receiving submodule (7-1) receives the switched circuit time slots from the fusion switching module (6), completes the circuit time slot buffering and shaping processing, and then sends it to the second input scheduling submodule (7-3); The packet receiving submodule (7-2) receives the switched packet frame from the fusion switching module (6), completes the packet frame buffering and verification processing, and then sends the packet frame to the second input scheduling submodule (7-3); The second input scheduling submodule (7-3) processes the circuit time slot and the packet frame respectively after receiving them. For the circuit time slot, according to the control rule of the configuration management module (8), the circuit time slot is sent to the time slot filling submodule (7-4) after removing the internal communication header; for the packet frame, the internal communication is removed according to the cache state of the logical queue, and the packet frame is unpacked according to the downlink time slot length, and the packet time slot is formed and sent to the time slot filling submodule (7-4); The time slot filling submodule (7-4) loads the received packet time slot and circuit time slot into the downlink VTDM time slot frame or the load device time slot frame, and sends it to the buffer management module (7-5); The buffer management module (7-5) performs address space management and data scheduling management on the downlink VTDM time slot frame or the load device time slot frame; The second output scheduling submodule (7-6) schedules the downlink VTDM time slot frame or the load device time slot frame of the cache management module (7-5) in real time, and sends it to the low-speed access processing module (1), the medium-speed access processing module (2), the high-speed access processing module (3), and the load device access processing module (4) respectively.

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