Time division multiplexing media independent interface and method supporting multi-rate multi-channel communication

Abstract

The invention discloses a time division multiplexing media independent interface and method supporting multi-rate and multi-channel communication, and the interface comprises a media access control layer module and a physical coding sub-layer module which support the multi-rate and multi-channel communication, the medium access control layer module and the physical coding sub-layer module share the same path of clock signals and channel mode configuration signals, and signals output to the physical coding sub-layer module by the medium access control layer module comprise transmission channel time slot signals, transmission data signals, transmission control signals and transmission data and control effective signals; signals output to the medium access control layer module by the physical coding sub-layer module comprise a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal and a receiving data and control effective signal. The invention aims to solve the problems of various interface types and interface signals in the existing medium independent interface technology, and realizes the compatibility of the multi-rate multi-channel Ethernet in a large rate range.

Description

Technical Field

[0001] The present invention relates to the field of network communication chips, and in particular to a time division multiplexing medium independent interface (TDMII) and method supporting multi-rate multi-channel communication. Background Art

[0002] In network communication chips, the bottom layer of the protocol stack usually includes the media access control layer (MAC), the physical coding sublayer (PCS) and the serial-to-parallel converter group (SERDES), such as Figure 1 As shown. Among them, the interface between MAC and PCS is called the media independent interface (MII), which is a logical interface for connecting the physical layer of different media types with the media access control layer of the same rate type; the interface between PCS and SERDES is called the physical medium attachment (PMA) interface, which is the physical medium adapter interface in the high-speed serial-to-parallel converter. At present, in order to enable network communication chips to be applied to more communication scenarios, there are usually two design requirements: one is to support multiple rates, that is, the SERDES channel can be configured to different rates according to the application scenario requirements. For example, the SERDES channel rates defined by the IEEE 802.3 Ethernet standard series include 10.3125Gbps, 25.78125Gbps, 53.125Gbps, etc.; the second is to support multiple channels, that is, to be able to realize flexible binding and network port splitting of different numbers of SERDES channels according to the application scenario requirements. For example, a single 200G network port defined by the IEEE 802.3 Ethernet standard series can be implemented by binding eight 25.78125Gbps SERDES channels, and this 200G network port can be reconfigured and split into two 100G network ports, each of which is implemented by binding four 25.78125Gbps SERDES channels. The above network port refers to a unit with data transmission and reception functions including MAC, PCS and SERDES.

[0003] In order for network communication chips to support multi-rate and multi-channel features, not only is it required that the underlying SERDES channel support configuration in multiple rate modes, but also that the PCS and MAC have the ability to support multi-rate and multi-channel. To this end, the existing technology usually simply encapsulates the PCS and MAC of multiple rates together, and connects them to the underlying SERDES channel that supports multiple rates through a multiplexer (MUX) and a demultiplexer (DEMUX). Figure 2As shown in the figure, it is assumed that the SERDES contains 8 channels in total, and its single channel rate can be configured to 10.3125Gbps and 25.78125Gbps. In order to support multi-rate multi-channel network port modes configured as 1×200G, 2×100G, 4×50G, 2×40G, 8×25G, 8×10G, etc., it is usually necessary to integrate the following IP logic modules: 1 200G MAC, 1 200G-R8 PCS, 2 100G MAC, 2 100G-R4 PCS, 4 50G MAC, 4 50G-R2PCS, 2 40G MAC, 2 40G-R4 PCS, 8 25G MAC, 8 25G-R1 PCS, 8 10G MAC, 8 10G-R1PCS. In this implementation structure, MACs of different rates and their corresponding PCS are connected using different MII interfaces. Specifically, the CDMII interface is used between the 200G MAC and the 200G-R8 PCS, the CGMII interface is used between the 100G MAC and the 100G-R4 PCS, the LGMII interface is used between the 50G MAC and the 50G-R2 PCS, the XLGMII interface is used between the 40G MAC and the 40G-R4 PCS, and the XGMII interface is used between the 10G MAC and the 10G-R1 PCS.

[0004] Figure 3 and Figure 4 Signal definition examples of CDMII interface and CGMII interface in the prior art are given respectively. Among them, *MII_TXD and *MII_TXC are respectively the data transmission signal and control transmission signal from *MAC to *PCS, *MII_TXCLK_ENA is the back pressure control signal from *PCS to *MAC, *MII_RXD and *MII_RXC are respectively the data reception signal and control reception signal from *PCS to *MAC, *MII_RXCLK_ENA is the valid signal for receiving data and control from *PCS to *MAC (the above symbol * represents CD or CG).

[0005] It can be seen that in order to support multi-rate and multi-channel communication of network communication chips, the existing MII interface technology has two disadvantages: (1) There are many types of interfaces. Figure 2 The implementation structure shown in the figure shows that the types of MII interfaces include CDMII, CGMII, LGMII, XLGMII, and XGMII. (2) There are many interface signals. For example, Figure 2In the implementation structure shown, the number of signals of CDMII and CGMII interfaces alone reaches 1158 (578+290×2=1158). As the underlying SERDES technology continues to develop towards higher speeds, network communication chip design will need to integrate more types of MII interfaces, and the number of signal lines will further increase, which is not only not conducive to the integration of multi-rate multi-channel MAC and PCS in the front-end design process of network communication chips, but also will cause difficulties in the layout and routing of multi-rate multi-channel MAC and PCS in the back-end design process of network communication chips. Summary of the invention

[0006] Technical problem to be solved by the present invention: In view of the above-mentioned problems in the prior art, a time-division multiplexed media-independent interface and method supporting multi-rate multi-channel communication is provided. The present invention aims to solve the problem of numerous interface types and interface signals in the existing media-independent interface technology, and achieve compatibility with multi-rate multi-channel Ethernet with a large rate range.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is: A time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication, comprising a medium access control layer module UMAC and a physical coding sublayer module UPCS supporting multi-rate multi-channel communication, wherein the medium access control layer module UMAC and the physical coding sublayer module UPCS share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0], and the signals output by the medium access control layer module UMAC to the physical coding sublayer module UPCS include a sending channel time slot signal TDMII_TXCHANSLOT[2:0], a sending data signal TDMII_TXCHANSLOT[2:0], and a sending channel time slot signal TDMII_TXCHANSLOT[2:0]. _TXDATA, transmit control signal TDMII_TXCTRL and transmit data and control valid signal TDMII_TXVALID[2:0]; the signals output by the physical coding sublayer module UPCS to the media access control layer module UMAC include the transmit enable signal TDMII_TXENABLE, the receive channel time slot signal TDMII_RXCHANSLOT[2:0], the receive data signal TDMII_RXDATA, the receive control signal TDMII_RXCTRL and the receive data and control valid signal TDMII_RXVALID[2:0].

[0008] Optionally, the channel mode configuration signal CFG_TDMII[23:0] supports a maximum of 8 channels, whose channel numbers are 0, 1, 2, 3, 4, 5, 6, and 7, respectively, and the mode of the i-th channel is controlled by the bit field CFG_TDMII[i*3+2: i*3] of the channel mode configuration signal CFG_TDMII, including: when the bit field CFG_TDMII[i*3+2: i*3]=3'b001, it indicates that the mode of the i-th channel is 10G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2: i*3]=3'b010, it indicates that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2: i*3]=3'b01 i*3]=3'b011, indicating that the mode of the i-th channel is 40G-R4, and the value range of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b100, indicating that the mode of the i-th channel is 50G-R2, and the value range of i is {0, 2, 4, 6}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b101, indicating that the mode of the i-th channel is 100G-R4, and the value range of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b110, indicating that the mode of the i-th channel is 200G-R8, and the value range of i is {0}, where 10G-R1 indicates that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 10.3125 Gbps; 25G-R1 indicates that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 25.78125 Gbps; 40G-R4 indicates that the network port has four SERDES channels bound to it at the bottom layer, and the rates of each SERDES channel are Configured as 10.3125Gbps; 50G-R2 means that the network port is bound to 2 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 means that the network port is bound to 4 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 means that the network port is bound to 8 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps.

[0009] Optionally, the valid signal TDMII_TXVALID[2:0] for sending data and control is used to control the effective bit width of the sending data signal TDMII_TXDATA and the sending control signal TDMII_TXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the valid signal TDMII_TXVALID[2:0] for sending data and control in each clock cycle determines the corresponding sending channel number in the current clock cycle. The sending channel mode of the network port in the current clock cycle is determined according to the sending channel number of the current clock cycle and the channel mode configuration signal CFG_TDMII[23:0]. The sending channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for sending data and control in the current clock cycle.

[0010] Optionally, the transmission channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control of the current clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (3) If the channel mode is 40G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}.}; (5) If the channel mode is 100G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for sending data and control is {3'b000}; (6) If the channel mode is 200G-R8, the value range of the valid signal TDMII_TXVALID[2:0] for sending data and control is {3'b000}; In each transmit channel mode, whether the specific value of the valid signal TDMII_TXVALID[2:0] for transmit data and control is 3'b000 or not depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If the transmit enable signal TDMII_TXENABLE=1 k clock cycles ago, the valid signal TDMII_TXVALID[2:0] for transmit data and control takes a non-3'b000 value in this clock cycle; otherwise, if the transmit enable signal TDMII_TXENABLE=0 k clock cycles ago, the valid signal TDMII_TXVALID[2:0] for transmit data and control takes a 3'b000 value in this clock cycle.

[0011] Optionally, the valid signal TDMII_RXVALID[2:0] for receiving data and control is used to control the effective bit width of the receiving data signal TDMII_RXDATA and the receiving control signal TDMII_RXCTRL. The effective bit width of the receiving direction of the time-division multiplexed medium-independent interface is controlled in a time-division multiplexing manner. The value of the valid signal TDMII_RXVALID[2:0] for receiving data and control in each clock cycle determines the corresponding receiving channel number in the current clock cycle. The receiving channel mode of the network port in the current clock cycle is determined according to the receiving channel number of the current clock cycle and the channel mode configuration signal CFG_TDMII[23:0]. The receiving channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control in the current clock cycle.

[0012] Optionally, the receiving channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control of the current clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; The value range of LID[2:0] is {3'b001}; (3) If the channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] and TDMII_RXVALID[2:0] is {3'b001}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (5) If the channel mode is 100G -R4, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b010}; (6) If the channel mode is 200G-R8, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b100}; In each receiving channel mode, whether the specific value of the valid signal TDMII_RXVALID[2:0] for receiving data and control is 3'b000 or not depends on whether the corresponding receiving channel of the physical coding sublayer module UPCS has data to transmit to the medium access control layer module UMAC in this clock cycle; if there is data to be transmitted, the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a non-3'b000 value in this clock cycle; otherwise, if there is no data to be transmitted, the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a 3'b000 value in this clock cycle.

[0013] In addition, the present invention also provides an application method of the aforementioned time-division multiplexed media-independent interface supporting multi-rate multi-channel communication, comprising forming a plurality of time-division multiplexed media-independent interfaces supporting multi-rate multi-channel communication into one of the following six homogeneous network port channel modes: (1) 8×10G-R1, indicating that the time-division multiplexed media-independent interface is sequentially split into 8 network ports with a channel mode of 10G-R1 for use, and the allocated channel numbers are {0, 1, 2, 3, 4, 5, 6, 7} respectively, and the value of its channel mode configuration signal CFG_TDMII is {8{3'b001}}; (2) 8×25G-R1, indicating that the time-division multiplexed media-independent interface is sequentially split into 8 network ports with a channel mode of 25G-R1 for use, and the allocated channel numbers are {0, 1, 2, 3, 4, 5, 6, 7} respectively. 1, 2, 3, 4, 5, 6, 7}, and the value of its channel mode configuration signal CFG_TDMII is {8{3'b010}}; (3) 2×40G-R4, indicating that the time-division multiplexed medium-independent interface is sequentially split into two network ports with a channel mode of 40G-R4, and the allocated channels are numbered {0, 4}, and the value of its channel mode configuration signal CFG_TDMII is {2{{3'b011}, 3{3'bzzz}}}; (4) 4×50G-R2, indicating that the time-division multiplexed medium-independent interface is sequentially split into four network ports with a channel mode of 50G-R2, and the allocated channels are numbered {0, 2, 4, 6}, and the value of its channel mode configuration signal CFG_TDMII is {4{{3'b100}, {3'bzzz}}}; (5) 2×100G-R4, indicating that the time-division multiplexed media-independent interface is sequentially split into two network ports with a channel mode of 100G-R4, and the assigned channel numbers are {0, 4} respectively. The value of the channel mode configuration signal CFG_TDMII is {2{{3'b101}, 3{3'bzzz}}}; (6) 1×200G-R8, indicating that the time-division multiplexed media-independent interface is used as a network port with a channel mode of 200G-R8, and the assigned channel number is {0}. The value of the channel mode configuration signal CFG_TDMII is {{3'b101}, 7{3'bzzz}}}, where {3'bzzz} indicates that each bit is a 3-bit signal with an arbitrary value.

[0014] Optionally, in the six homogeneous network port channel modes: (1) in the 8×10G-R1 homogeneous network port channel mode, the values ​​of the sending channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] in the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 2, 6, 1, 5, 3, 7} respectively, and each channel mode allocates 1 / 8 of the clock cycle to the 25G-R1 network port; (2) in the 8×25G-R1 homogeneous network port channel mode, the sending channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] are {0, 4, 2, 6, 1, 5, 3, 7} in the 1st scheduling cycle to the 8th scheduling cycle. The values ​​of TDMII_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 2, 6, 1, 5, 3, 7}, respectively. That is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1. (3) In the 2×40G-R4 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 0, 4, 0, 4, 0, 4}, respectively. That is, 4 / 8 of the clock cycle is allocated to each network port with a channel mode of 40G-R4. 8 clock cycles; (4) In the 4×50G-R2 homogeneous network port channel mode, the transmission channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 0, 4, 2, 6} in the 1st scheduling cycle to the 8th scheduling cycle, respectively, and 2 / 8 clock cycles are allocated to each network port with a channel mode of 50G-R2; (5) In the 2×100G-R4 homogeneous network port channel mode, the transmission channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHA The values ​​of NSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 0, 4, 0, 4, 0, 4}, respectively, allocating 4 / 8 of the clock cycle to each network port with a channel mode of 100G-R4. (6) In the 1×200G-R8 homogeneous network port channel mode, the values ​​of the transmitting channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 0, 0, 0, 0, 0, 0, 0}, respectively, allocating all 8 / 8 of the clock cycle to a single network port with a channel mode of 200G-R8.

[0015] In addition, the present invention also provides an application method of the aforementioned time-division multiplexed media-independent interface supporting multi-rate multi-channel communication, comprising forming a plurality of time-division multiplexed media-independent interfaces supporting multi-rate multi-channel communication into one of the following four heterogeneous network port channel modes: (1) 1×100G-R4+2×50G-R2, the time-division multiplexed media-independent interface is sequentially split into one network port with a channel mode of 100G-R4 and two network ports with a channel mode of 50G-R2, the assigned channel numbers are {0, 4, 6} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},3{3'bzzz},2{{3'b100},{3'bzzz}}}; (2) 4×25G-R1+1×40G-R4, the time-division multiplexed media-independent interface is sequentially split into 4 (3) 1×50G-R2+2×25G-R1+1×100G-R4, the time-division multiplexed media-independent interface is sequentially split into 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1 and 1 network port with a channel mode of 100G-R4, and the assigned channel numbers are {0, 1, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b100},{3'bzzz}}; (4) 1×50G-R2+2×25G-R1+1×100G-R4, the time-division multiplexed media-independent interface is sequentially split into 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1 and 1 network port with a channel mode of 100G-R4, and the assigned channel numbers are {0, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b100},{3'bzzz}}, 2{3'b010},{3'b101},3{3'bzzz}}; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the time-division multiplexed media-independent interface is sequentially split into 2 network ports with a channel mode of 10G-R1, 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1, and 1 network port with a channel mode of 50G-R2. The assigned channel numbers are {0, 1, 2, 4, 5, 6} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010},{3'b100},{3'bzzz}}, where {3'bzzz}}} indicates a 3-bit signal where each bit can take any value.

[0016] Optionally, in the four heterogeneous network port channel modes: (1) in the 1×100G-R4+2×50G-R2 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 0, 6, 0, 4, 0, 6} in the 1st scheduling cycle to the 8th scheduling cycle, respectively, and 4 / 8 of the clock cycle is allocated to a single network port with a channel mode of 100G-R4, and 2 / 8 of the clock cycle is allocated to each network port with a channel mode of 50G-R2; (2) in the 4×25G-R1+1 In the 1×40G-R4 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 4, 1, 4, 3, 4} in the 1st to 8th scheduling cycles, respectively. 1 / 8 of the clock cycle is allocated to each network port in the 25G-R1 channel mode, and 4 / 8 of the clock cycle is allocated to a single network port in the 40G-R4 channel mode. (3) In the 1×50G-R2+2×25G-R1+1×100G-R4 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 4, 1, 4, 3, 4} in the 1st to 8th scheduling cycles, respectively. The values ​​of TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] in the 1st to 8th scheduling cycles are {0, 4, 2, 4, 0, 4, 3, 4}, respectively, allocating 2 / 8 of the clock cycle to a network port with a single channel mode of 50G-R2, 1 / 8 of the clock cycle to each network port with a channel mode of 25G-R1, and 4 / 8 of the clock cycle to a network port with a single channel mode of 100G-R4; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2 heterogeneous network In port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 1, 4, 3, 6} in the 1st to 8th scheduling cycles, respectively. 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 10G-R1, 2 / 8 of the clock cycle is allocated to a single channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 2 / 8 of the clock cycle is allocated to a single channel mode of 50G-R2.

[0017] Compared with the prior art, the present invention mainly has the following advantages: the time-division multiplexing medium-independent interface of the present invention includes a medium access control layer module and a physical coding sublayer module supporting multi-rate multi-channel communication, the medium access control layer module and the physical coding sublayer module share the same clock signal and channel mode configuration signal, the signal output from the medium access control layer module to the physical coding sublayer module includes a sending channel time slot signal, a sending data signal, a sending control signal and a valid signal for sending data and control; the signal output from the physical coding sublayer module to the medium access control layer module includes a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal and a receiving data and control The effective signal of control, the time-division multiplexing media-independent interface of the present invention can solve the problem of numerous interface types and interface signals of the existing media-independent interface technology, considering that 200G, 100G, 50G, 40G, and 10G are the mainstream applications of the current Ethernet market, and single-channel 25.78125Gbps and 10.3125Gbps are its commonly used rate configurations. The present invention is mainly aimed at Ethernet in the single-channel rate range. The time-division multiplexing media-independent interface of the present invention can achieve compatibility with multi-rate multi-channel Ethernet with a large rate range of 200G, 100G, 50G, 40G, 10G, 25.78125Gbps and 10.3125Gbps. The present invention can be applied to the time-division multiplexing media-independent interface TDMII connection between the physical coding sublayer PCS and the media access control layer MAC of multi-rate multi-channel communication. Compared with the medium-independent interface MII technology of the prior art, the present invention can realize the communication between the multi-rate multi-channel PCS and the multi-rate multi-channel MAC in a channelized time-division multiplexing manner, thereby simplifying the connection signal between the multi-rate multi-channel PCS and the multi-rate multi-channel MAC, and solving the problem of numerous interface types and interface signals in the prior art medium-independent interface MII technology. The method of the present invention is not only conducive to the integration of the multi-rate multi-channel MAC and the multi-rate multi-channel PCS in the front-end design process of the network communication chip, but also conducive to the layout and wiring of the multi-rate multi-channel MAC and the multi-rate multi-channel PCS in the back-end design process of the network communication chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The diagram is a schematic diagram of the underlying structure of the protocol stack of a multi-rate multi-channel network communication chip in the prior art.

[0019] Figure 2 The figure is a schematic diagram of the communication principle of a multi-rate multi-channel network communication chip in the prior art.

[0020] Figure 3 The figure is a schematic diagram of signal definition of CDMII interface in the prior art.

[0021] Figure 4The figure is a schematic diagram of signal definition of a CGMII interface in the prior art.

[0022] Figure 5 FIG. 4 is a schematic diagram of TDMII signal definition in an embodiment of the present invention.

[0023] Figure 6 FIG. 4 is a schematic diagram of a mode configuration of TDMII in an embodiment of the present invention.

[0024] Figure 7 Schematic diagram of channel scheduling of the homogeneous channel mode of TDMII in an embodiment of the present invention.

[0025] Figure 8 Schematic diagram of channel scheduling of the heterogeneous channel mode of TDMII in an embodiment of the present invention.

[0026] Fig. 9 Schematic diagram of the effective bit width of TDMII in an embodiment of the present invention.

[0027] Fig.10 Schematic diagram of a typical timing sequence of TDMII in an embodiment of the present invention, wherein (a) is a data sending direction and (b) is a data receiving direction.

[0028] Fig.11 2 are application examples of TDMII in the embodiments of the present invention, wherein (a) is an example of the first application scenario, and (b) is an example of the second application scenario. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] like Figure 5As shown, this embodiment provides a time division multiplexing medium independent interface (TDMII) supporting multi-rate multi-channel communication, including a medium access control layer module UMAC and a physical coding sublayer module UPCS supporting multi-rate multi-channel communication, the medium access control layer module UMAC and the physical coding sublayer module UPCS share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0], and the signal output by the medium access control layer module UMAC to the physical coding sublayer module UPCS includes a sending channel time slot signal TDMII_TXCHANSLOT[2:0] and a sending data signal TDMII_TXDAT A. Send control signal TDMII_TXCTRL and valid signal TDMII_TXVALID[2:0] for sending data and control; the signals output by the physical coding sublayer module UPCS to the medium access control layer module UMAC include the send enable signal TDMII_TXENABLE, the receive channel time slot signal TDMII_RXCHANSLOT[2:0], the receive data signal TDMII_RXDATA, the receive control signal TDMII_RXCTRL and the valid signal TDMII_RXVALID[2:0] for receiving data and control, where [23:0] indicates 24-bit width and [2:0] indicates 3-bit width. The interface signals are described as follows: (1) TDMII interface clock signal (TDMII_CLK), 1 bit wide, input from the outside of the TDMII interface and drives the UMAC and UPCS to work. In order to ensure that each SERDES channel supports a maximum data transmission rate of 25.78125Gbps, the minimum operating frequency of TDMII_CLK is (25.78125*64 / 66) / (256 / 8)=0.78125GHz. (2) TDMII interface channel mode configuration signal (CFG_TDMII), 24 bits wide, input from the outside of the TDMII interface and determines the working mode of UMAC and UPCS. Channel mode configuration signal CFG_TDMII[23:0] is used to control the channel mode when UMAC and UPCS are working. The TDMII interface supports a maximum of 8 channels, and the channel numbers are 0, 1, 2, 3, 4, 5, 6, and 7. The mode of the i-th channel of the TDMII interface is controlled by the CFG_TDMII[i*3+2: i*3] bit field. (3) TDMII interface transmit channel time slot signal (TDMII_TXCHANSLOT), 3 bits wide, output from UMAC to UPCS. This signal is used to indicate the transmit channel to which the TDMII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0], and TDMII_TXENABLE signals correspond in each clock cycle.The valid value range of TDMII_TXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicates that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th channels of UMAC are sending data characters and control characters. (4) The TDMII interface sends the data signal (TDMII_TXDATA), which is 256 bits wide and is output from UMAC to UPCS. (5) The TDMII interface sends the control signal (TDMII_TXCTRL), which is 32 bits wide and is output from UMAC to UPCS. Each bit of the send control signal TDMII_TXCTRL[31:0] is used to indicate whether the 1-byte information corresponding to TDMII_TXDATA[255:0] is a data character or a control character. When TDMII_TXCTRL[m]=0, it indicates that data characters are transmitted on TDMII_TXDATA[m*8+7:m*8]; when TDMII_TXCTRL[m]=1, it indicates that control characters are transmitted on TDMII_TXDATA[m*8+7:m*8]. (6) The TDMII interface sends a valid signal (TDMII_TXVALID) for data and control, 3 bits wide, output from UMAC to UPCS. The valid value range of TDMII_TXVALID[2:0] is {3'b100, 3'b010, 3'b001, 3'b000}. When TDMII_TXVALID[2:0]=3'b100, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle; when TDMII_TXVALID[2:0]=3'b010, it means that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[2:0]=3'b001, it means that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[2:0]=3'b000, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are invalid in the current clock cycle. (7) TDMII interface transmit enable signal (TDMII_TXENABLE), 1 bit wide, output from UPCS to UMAC.When TDMII_TXENABLE=0, it means that UPCS cannot receive the data and control signals sent by UMAC in the kth clock cycle starting from this clock cycle; when TDMII_TXENABLE=1, it means that UPCS can receive the data and control signals sent by UMAC in the kth clock cycle starting from this clock cycle. If k=0, the TDMII_TXENABLE signal value indicates whether UPCS can receive the data and control signals sent by UMAC in this clock cycle. (8) TDMII interface receive channel time slot signal (TDMII_RXCHANSLOT), 3 bits wide, is output by UPCS to UMAC. This signal is used to indicate the receive channel corresponding to the TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0] and TDMII_RXVALID[2:0] signals in each clock cycle. The valid value range of TDMII_RXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicates that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th, and 7th channels of UMAC are receiving data characters and control characters. (9) TDMII interface receive data signal (TDMII_RXDATA), 256 bits wide, output from UPCS to UMAC. (10) TDMII interface receive control signal (TDMII_RXCTRL), 32 bits wide, output from UPCS to UMAC. Each bit of the receive control signal RDMII_TXCTRL[31:0] is used to indicate whether the 1-byte information corresponding to TDMII_RXDATA[255:0] is a data character or a control character. When RDMII_TXCTRL[n]=0, it indicates that data characters are transmitted on RDMII_TXDATA[n*8+7:n*8]; when RDMII_TXCTRL[n]=1, it indicates that control characters are transmitted on RDMII_TXDATA[n*8+7:n*8]. (11) The valid signal (TDMII_RXVALID) for receiving data and control of the TDMII interface is 3 bits wide and is output from UPCS to UMAC. The valid value range of TDMII_RXVALID[2:0] is 3'b100, 3'b010, 3'b001, 3'b000.When TDMII_RXVALID[2:0]=3'b100, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle; when TDMII_RXVALID[2:0]=3'b010, it means that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_RXVALID[2:0]=3'b001, it means that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_RXVALID[2:0]=3'b000, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are invalid in the current clock cycle.

[0031] The definitions between the medium access control layer module UMAC and the physical coding sublayer module UPCS include TDMII interface signals, TDMII interface modes, TDMII interface channel scheduling, and TDMII interface effective bit width.

[0032] 1) TDMII interface signal The TDMII interface is used to connect UMAC and UPCS, where UMAC and UPCS refer to MAC and PCS supporting multi-rate and multi-channel communications respectively. The specific implementation is by users using the TDMII interface, but the signal interaction between them must comply with the TDMII interface specification. The TDMII interface signals specifically include: (1) TDMII interface clock signal (TDMII_CLK), 1 bit wide, input from the outside of the TDMII interface and driving the UMAC and UPCS to work; (2) TDMII interface channel mode configuration signal (CFG_TDMII), 24 bits wide, input from the outside of the TDMII interface and determining the working mode of the UMAC and UPCS; (3) TDMII interface send channel time slot signal (TDMII_TXCHANSLOT), 3 bits wide, output from UMAC to UPCS; (4) TDMII interface send data signal (TDMII_TXDATA), 256 bits wide, output from UMAC to UPCS; (5) TDMII interface send control signal (TDMII_TXCTRL), 32 bits wide, output from UMAC to UPCS; (6) TDMII interface send data (7) TDMII interface send enable signal (TDMII_TXENABLE), 1 bit wide, output from UPCS to UMAC; (8) TDMII interface receive channel time slot signal (TDMII_RXCHANSLOT), 3 bits wide, output from UPCS to UMAC; (9) TDMII interface receive data signal (TDMII_RXDATA), 256 bits wide, output from UPCS to UMAC; (10) TDMII interface receive control signal (TDMII_RXCTRL), 32 bits wide, output from UPCS to UMAC; (11) TDMII interface receive data and control valid signal (TDMII_RXVALID), 3 bits wide, output from UPCS to UMAC.

[0033] In the data transmission direction from UMAC to UPCS, each bit of the transmission control signal TDMII_TXCTRL[31:0] is used to indicate whether the corresponding 1-byte information of the transmission data signal TDMII_TXDATA[255:0] is a data character or a control character. When TDMII_TXCTRL[m]=0, it means that the data character is transmitted on TDMII_TXDATA[m*8+7:m*8]; when TDMII_TXCTRL[m]=1, it means that the control character is transmitted on TDMII_TXDATA[m*8+7:m*8].

[0034] The transmit enable signal TDMII_TXENABLE is used to control the data transmission behavior of UMAC according to the back pressure of the real-time data receiving capability of UPCS. When TDMII_TXENABLE=0, it means that UPCS cannot receive the data and control signals sent by UMAC in the kth clock cycle starting from this clock cycle; when TDMII_TXENABLE=1, it means that UPCS can receive the data and control signals sent by UMAC in the kth clock cycle starting from this clock cycle. If the parameter k=0, the TDMII_TXENABLE signal value indicates whether UPCS can receive the data and control signals sent by UMAC in this clock cycle.

[0035] The valid signal TDMII_TXVALID[2:0] for sending data and control is used to indicate the validity of the TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] bit fields in each clock cycle. The valid value range of TDMII_TXVALID[2:0] is {3'b100, 3'b010, 3'b001, 3'b000}. When TDMII_TXVALID[2:0]=3'b100, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle; when TDMII_TXVALID[2:0]=3'b010, it means that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[2:0]=3'b001, it means that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[2:0]=3'b000, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are invalid in the current clock cycle.

[0036] The transmit channel time slot signal TDMII_TXCHANSLOT[2:0] is used to indicate the transmit channel corresponding to the TDMII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0] and TDMII_TXENABLE signals in each clock cycle. The TDMII interface supports up to 8 transmit channels. The valid value range of TDMII_TXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicates that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th and 7th channels of UMAC are sending data characters and control characters. In the data receiving direction from UPCS to UMAC, each bit of the receive control signal RDMII_RXCTRL[31:0] is used to indicate whether the 1-byte information corresponding to the receive data signal TDMII_RXDATA[255:0] is a data character or a control character. When RDMII_TXCTRL[n]=0, it means that the data character is transmitted on RDMII_TXDATA[n*8+7:n*8]; when RDMII_TXCTRL[n]=1, it means that the control character is transmitted on RDMII_TXDATA[n*8+7:n*8].

[0037] The valid signal TDMII_RXVALID[2:0] for receiving data and control is used to indicate the validity of the TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] bit fields in each clock cycle. The valid value range of TDMII_RXVALID[2:0] is 3'b100, 3'b010, 3'b001, 3'b000. When TDMII_RXVALID[2:0]=3'b100, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle; when TDMII_RXVALID[2:0]=3'b010, it means that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_RXVALID[2:0]=3'b001, it means that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the rest of the bits are invalid. When TDMII_RXVALID[2:0]=3'b000, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are invalid in the current clock cycle.

[0038] The receive channel time slot signal TDMII_RXCHANSLOT[2:0] is used to indicate the receive channel corresponding to the TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0] and TDMII_RXVALID[2:0] signals in each clock cycle. The TDMII interface supports up to 8 receive channels. The valid value range of TDMII_RXCHANSLOT[2:0] is {3'b000, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110, 3'b111}, which respectively indicates that the 0th, 1st, 2nd, 3rd, 4th, 5th, 6th and 7th channels of UMAC are receiving data characters and control characters.

[0039] 2) TDMII interface mode The channel mode configuration signal CFG_TDMII[23:0] is used to control the channel mode of UMAC and UPCS, including network port splitting mode, channel bonding mode, channel rate, etc. Since the TDMII interface supports up to 8 channels, the channel numbers are 0, 1, 2, 3, 4, 5, 6, and 7. The mode of the i-th channel of the TDMII interface is controlled by the CFG_TDMII[i*3+2: i*3] bit field.

[0040] like Figure 6 As shown, in this embodiment, the corresponding relationship between the configuration value of the channel mode configuration signal CFG_TDMII[i*3+2: i*3] (bits i*3 to i*3+2) and the mode of the i-th channel is as follows: when CFG_TDMII[i*3+2: i*3]=3'b001, it means that the mode of the i-th channel is 10G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*3+2: i*3]=3'b010, it means that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*3+2: i*3]=3'b010, it means that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; i*3]=3'b011, indicating that the mode of the i-th channel is 40G-R4, and the value range of i is {0, 4}; when CFG_TDMII[i*3+2 : i*3]=3'b100, indicating that the mode of the i-th channel is 50G-R2, and the value range of i is {0, 2, 4, 6}; when CFG_TDMII[i*3+2 : i*3]=3'b101, indicating that the mode of the i-th channel is 100G-R4, and the value range of i is {0, 4}; when CFG_TDMII[i*3+2 : i*3]=3'b110, indicating that the mode of the i-th channel is 200G-R8, and the value range of i is {0}. Figure 6 In the example, CFG_XXX_TDMI represents the 3-bit XXX of the channel mode configuration signal CFG_TDMII[23:0], including [2:0], [5:3], [8:6], etc., which correspond to the i*3 to i*3+2 bits in the previous text, as shown in the following example. Figure 6 In the above description of channel mode configuration, the specific meanings of various channel modes are as follows: 10G-R1 means that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 10.3125Gbps; 25G-R1 means that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 25.78125Gbps; 40G-R4 means that the network port has 4 SERDES channels bound to it at the bottom layer, and the rates of each SERDES channel are configured to 10. 3125Gbps; 50G-R2 means that the network port is bound to 2 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 means that the network port is bound to 4 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 means that the network port is bound to 8 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps. The TDMII interface supports both homogeneous network port channel mode and heterogeneous network port channel mode. Homogeneous network port channel mode means that the network port generated according to the channel mode configuration signal CFG_TDMII[23:0] has only one channel mode. Figure 7As shown in the figure, the TDMII interface supports a total of 6 homogeneous network port channel modes (homogeneous channel modes), including: (1) 8×10G-R1, that is, the TDMII interface is sequentially split into 8 network ports with a channel mode of 10G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the channel mode configuration signal value is CFG_TDMII[23:0] = {8{3'b001}}. (2) 8×25G-R1, that is, the TDMII interface is sequentially split into 8 network ports with a channel mode of 25G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the channel mode configuration signal value is CFG_TDMII[23:0] = {8{3'b010}}. (3) 2×40G-R4, that is, the TDMII interface is sequentially split into 2 network ports with a channel mode of 40G-R4, and the allocated channels are numbered {0, 4}, and the channel mode configuration signal value is CFG_TDMII[23:0]={2{{3'b011},3{3'bzzz}}}. (4) 4×50G-R2, that is, the TDMII interface is sequentially split into 4 network ports with a channel mode of 50G-R2, and the allocated channels are numbered {0, 2, 4, 6}, and the channel mode configuration signal value is CFG_TDMII[23:0]={4{{3'b100}, {3'bzzz}}}. (5) 2×100G-R4, that is, the TDMII interface is sequentially split into two network ports with a channel mode of 100G-R4, and the assigned channel numbers are {0, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={2{{3'b101},3{3'bzzz}}}. (6) 1×200G-R8, that is, the TDMII interface is used as a network port with a channel mode of 200G-R8, and the assigned channel number is {0}, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},7{3'bzzz}}}. The above {3'bzzz} indicates that each bit is a 3-bit signal with an arbitrary value.

[0041] Heterogeneous network port channel mode means that the network port generated according to the channel mode configuration signal CFG_TDMII[23:0] has at least two channel modes. Figure 8As shown, the TDMII interface can flexibly support multiple heterogeneous network port channel modes (heterogeneous channel modes), for example (but not limited to): (1) 1×100G-R4+2×50G-R2, that is, the TDMII interface is sequentially split into 1 network port with a channel mode of 100G-R4 and 2 network ports with a channel mode of 50G-R2, and the allocated channel numbers are {0, 4, 6} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101},3{3'bzzz}, 2{{3'b100},{3'bzzz}}}. (2) 4×25G-R1+1×40G-R4, that is, the TDMII interface is split into 4 network ports with channel mode of 25G-R1 and 1 network port with channel mode of 40G-R4 in sequence. The assigned channel numbers are {0, 1, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={4{3'b010},{3'b011},3{3'bzzz}}. (3) 1×50G-R2+2×25G-R1+1×100G-R4, that is, the TDMII interface is split into 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1, and 1 network port with a channel mode of 100G-R4. The assigned channel numbers are {0, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b100},{3'bzzz},2{3'b010},{3'b101},3{3'bzzz}}. (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, that is, the TDMII interface is sequentially split into 2 network ports with a channel mode of 10G-R1, 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1, and 1 network port with a channel mode of 50G-R2. The assigned channel numbers are {0, 1, 2, 4, 5, 6}, respectively, and the channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010}, {3'b100},{3'bzzz}}. The above {3'bzzz} indicates that each bit is a 3-bit signal with an arbitrary value. 3) TDMII interface channel scheduling The transmit channel time slot signal TDMII_TXCHANSLOT[2:0] is used to schedule the various transmit channels that send data characters and control characters from UMAC to UPCS. The receive channel time slot signal TDMII_RXCHANSLOT[2:0] is used to schedule the various receive channels that receive data characters and control characters from UPCS to UMAC. Both the scheduling of the transmit channel and the scheduling of the receive channel are based on a single clock cycle as the basic unit, using the time division multiplexing method. Each transmit channel shares the use of MII_TXDATA[255:0], TDMII_TXCTRL[31:0], TDMII_TXVALID[2:0] and TDMII_TXENABLE signals, and each receive channel shares the use of TDMII_RXDATA[255:0], TDMII_RXCTRL[31:0] and TDMII_RXVALID[2:0] signals. The scheduling of the transmit channel is the responsibility of UMAC, and the scheduling is usually started after the UMAC is reset. The scheduling of the receiving channel is in charge of UPCS, and the scheduling is usually started after UPCS is reset. When the channel scheduling is started, the consecutive clock cycles are cyclically numbered as follows: the 1st scheduling cycle, the 2nd scheduling cycle, the 3rd scheduling cycle, the 4th scheduling cycle, the 5th scheduling cycle, the 6th scheduling cycle, the 7th scheduling cycle, the 8th scheduling cycle, the 1st scheduling cycle, and the 2nd scheduling cycle. Channel scheduling is to assign channel numbers to the TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] signals from the 1st scheduling cycle to the 8th scheduling cycle.

[0042] like Fig. 9As shown in the figure, the TDMII interface supports a total of 6 homogeneous network port channel modes. In various homogeneous network port channel modes, the specific methods of channel scheduling are described as follows: (1) 8×10G-R1, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 1, 5, 3, 7} from the 1st scheduling cycle to the 8th scheduling cycle, that is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1. (2) 8×25G-R1, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 1, 5, 3, 7} from the 1st scheduling cycle to the 8th scheduling cycle, that is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1. (3) 2×40G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 0, 4, 0, 4, 0, 4} from the 1st scheduling cycle to the 8th scheduling cycle, that is, 4 / 8 of the clock cycle is allocated to each network port with a channel mode of 40G-R4. (4) 4×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 0, 4, 2, 6} from the 1st scheduling cycle to the 8th scheduling cycle, that is, 2 / 8 of the clock cycle is allocated to each network port with a channel mode of 50G-R2. (5) 2×100G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 0, 4, 0, 4, 0, 4} from the 1st scheduling cycle to the 8th scheduling cycle, that is, 4 / 8 clock cycles are allocated to each network port with a channel mode of 100G-R4. (6) 1×200G-R8, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 0, 0, 0, 0, 0, 0, 0} from the 1st scheduling cycle to the 8th scheduling cycle, that is, all 8 / 8 clock cycles are allocated to a single network port with a channel mode of 200G-R8.

[0043] The TDMII interface can flexibly support a variety of heterogeneous network port channel modes. In the above-mentioned heterogeneous channel modes, the specific methods of channel scheduling are described as follows: (1) 1×100G-R4+2×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 0, 6, 0, 4, 0, 6} from the 1st scheduling cycle to the 8th scheduling cycle, respectively. That is, 4 / 8 of the clock cycle is allocated to a single network port with a channel mode of 100G-R4, and 2 / 8 of the clock cycle is allocated to each network port with a channel mode of 50G-R2. (2) 4×25G-R1+1×40G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 4, 1, 4, 3, 4} in the 1st to 8th scheduling cycles, respectively. That is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 4 / 8 of the clock cycle is allocated to a single network port with a channel mode of 40G-R4. (3) 1×50G-R2+2×25G-R1+1×100G-R4, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 4, 0, 4, 3, 4} in the 1st to 8th scheduling cycles, respectively. That is, 2 / 8 of the clock cycle is allocated to the network port with a single channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 4 / 8 of the clock cycle is allocated to the network port with a single channel mode of 100G-R4. (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 1, 4, 3, 6} in the 1st to 8th scheduling cycles, respectively. That is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 10G-R1, 2 / 8 of the clock cycle is allocated to a single network port with a channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 2 / 8 of the clock cycle is allocated to a single network port with a channel mode of 50G-R2. 4) TDMII interface effective bit width The valid signal TDMII_TXVALID[2:0] for sending data and controlling the TDMII interface controls the valid bit width of the data signal (TDMII_TXDATA[255:0]) and the control signal (TDMII_TXCTRL[31:0]) in the sending direction. The valid signal TDMII_RXVALID[2:0] for receiving data and controlling the TDMII interface controls the valid bit width of the data signal (TDMII_RXDATA[255:0]) and the control signal (TDMII_RXCTRL[31:0]) in the receiving direction. The valid bit width of the sending direction and the receiving direction of the TDMII interface is controlled in a time division multiplexing manner. In the data and control sending direction, the value of TDMII_TXCHANSLOT[2:0] in each clock cycle determines the corresponding sending channel number in this clock cycle, and the sending channel mode of the network port in this clock cycle is determined according to the sending channel number of this clock cycle and the channel mode configuration signal CFG_TDMII[23:0]. In the data and control receiving direction, the value of TDMII_RXCHANSLOT[2:0] in each clock cycle determines the corresponding receiving channel number in this clock cycle, and the receiving channel mode of the network port in this clock cycle is determined according to the receiving channel number of this clock cycle and the channel mode configuration signal CFG_TDMII[23:0].

[0044] The transmit channel mode of this clock cycle determines the specific value range of TDMII_TXVALID[2:0] of this clock cycle. The value ranges under various channel modes are described as follows: (1) If the transmit channel mode is 10G-R1, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (2) If the transmit channel mode is 25G-R1, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (3) If the transmit channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (4) If the transmit channel mode is 50G-R2, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b001}. (5) If the transmit channel mode is 100G-R4, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b010}. (6) If the transmit channel mode is 200G-R8, the value range of TDMII_TXVALID[2:0] is {3'b000, 3'b100}. In each transmit channel mode, whether TDMII_TXVALID[2:0] is 3'b000 or not depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If TDMII_TXENABLE=1 k clock cycles ago, TDMII_TXVALID[2:0] takes a non-3'b000 value in this clock cycle. Otherwise, if TDMII_TXENABLE=0 k clock cycles ago, TDMII_TXVALID[2:0] takes a 3'b000 value in this clock cycle. The receive channel mode of this clock cycle determines the specific value range of TDMII_RXVALID[2:0] of this clock cycle. The value ranges under various channel modes are described as follows: (1) If the receive channel mode is 10G-R1, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (2) If the receive channel mode is 25G-R1, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (3) If the receive channel mode is 40G-R4, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (4) If the receiving channel mode is 50G-R2, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b001}. (5) If the receiving channel mode is 100G-R4, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b010}. (6) If the receiving channel mode is 200G-R8, the value range of TDMII_RXVALID[2:0] is {3'b000, 3'b100}. In each receiving channel mode, whether TDMII_RXVALID[2:0] takes a specific value of 3'b000 or not depends on whether the corresponding receiving channel of UPCS has data to transmit to UMAC in this clock cycle. If there is data to be transmitted, TDMII_RXVALID[2:0] takes a non-3'b000 value in this clock cycle. Otherwise, if there is no data to be transmitted, TDMII_RXVALID[2:0] takes the value 3'b000 in this clock cycle.

[0045] As a further extension of the time division multiplexing medium independent interface (TDMII) supporting multi-rate multi-channel communication in this embodiment: in order to be applicable to multi-rate multi-channel Ethernet with a larger rate range and more channel modes, the TDMII interface of the present invention can be expanded by appropriately increasing the data width of each signal. For example, in order to support 400G, 200G, 100G, 50G, 40G, 10G multi-channel, a single SERDES channel can be configured as 53.125Gbps, 25.78125Gbps and 10.3125Gbps multi-rate, and a maximum support Ethernet interface divided into 8 channels, the above TDMII interface signal can be expanded as follows: (1) The transmit data signal TDMII_TXDATA is expanded from 256 bits to 512 bits. (2) The transmit control signal TDMII_TXCTRL is expanded from 32 bits to 64 bits. (3) The valid signal TDMII_TXVALID for transmit data and control is expanded from 3 bits to 4 bits. The valid value range of TDMII_TXVALID is extended to {4'b1000, 4'b0100, 4'b0010, 4'b0001, 4'b0000}. When TDMII_TXVALID[3:0]=4'b1000, it means that TDMII_TXDATA[511:0] and TDMII_TXCTRL[63:0] are valid in the current clock cycle; when TDMII_TXVALID[3:0]=4'b0100, it means that TDMII_TXDATA[255:0] and TDMII_TXCTRL[31:0] are valid in the current clock cycle, and the rest of the bit fields are invalid; when TDMII_TXVALID[3:0]=4'b0010, it means that TDMII_TXDATA[127:0] and TDMII_TXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[3:0]=4'b0001, it means that TDMII_TXDATA[63:0] and TDMII_TXCTRL[7:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_TXVALID[2:0]=4'b0000, it means that TDMII_TXDATA[511:0] and TDMII_TXCTRL[63:0] are invalid in the current clock cycle. (4) Expand the receive data signal TDMII_RXDATA from 256 bits to 512 bits. (5) Expand the receive control signal TDMII_RXCTRL from 32 bits to 64 bits. (6) Expand the receive data and control valid signal TDMII_RXVALID from 3 bits to 4 bits. The valid value range of TDMII_RXVALID is extended to {4'b1000, 4'b0100, 4'b0010, 4'b0001, 4'b0000}.When TDMII_RXVALID[3:0]=4'b1000, it means that TDMII_RXDATA[511:0] and TDMII_RXCTRL[63:0] are valid in the current clock cycle; when TDMII_RXVALID[3:0]=4'b0100, it means that TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0] are valid in the current clock cycle, and the rest of the bit fields are invalid; when TDMII_RXVALID[3:0] =4'b0010, it means that TDMII_RXDATA[127:0] and TDMII_RXCTRL[15:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_RXVALID[3:0]=4'b0001, it means that TDMII_RXDATA[63:0] and TDMII_RXCTRL[7:0] are valid in the current clock cycle, and the rest of the bit fields are invalid. When TDMII_RXVALID[3:0]=4'b0000, it means that TDMII_RXDATA[511:0] and TDMII_RXCTRL[63:0] are invalid in the current clock cycle. (7) The TDMII interface channel mode configuration signal CFG_TDMII is extended from 24 bits to 32 bits.The corresponding relationship between the configuration value of the channel mode configuration signal CFG_TDMII[i*4+3 :i*4] and the mode of the i-th channel is extended to: when CFG_TDMII[i*4+3 : i*4]=4'b0001, it means that the mode of the i-th channel is 10G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4]=4'b0010, it means that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4]=4'b0011, it means that the mode of the i-th channel is 40G-R4, and the value range of i is {0, 4}; when CFG_TDMII[i*4+3 : i*4]=4'b00 i*4]=4'b0100, indicating that the mode of the i-th channel is 50G-R2, and the value range of i is {0, 2, 4, 6}; when CFG_TDMII[i*4+3 : i*4]=4'b0101, indicating that the mode of the i-th channel is 50G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when CFG_TDMII[i*4+3 : i*4]=4'b0110, indicating that the mode of the i-th channel is 100G-R4, and the value range of i is {0, 4}; when CFG_TDMII[i*4+3 : i*4]=4'b0111, indicating that the mode of the i-th channel is 100G-R2, and the value range of i is {0, 2, 4, 6}; when CFG_TDMII[i*4+3 : i*4]=4'b1000, indicating that the mode of the i-th channel is 200G-R8, and the value range of i is {0}; when CFG_TDMII[i*4+3 : i*4]=4'b1001, indicating that the mode of the i-th channel is 200G-R4, and the value range of i is {0, 4}; when CFG_TDMII[i*4+3 : i*4]=4'b1010, indicating that the mode of the i-th channel is 400G-R8, and the value range of i is {0}. In the above description of channel mode configuration, the specific meanings of the four extended channel modes are as follows: 50G-R1 means that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 53.125Gbps; 100G-R2 means that the network port has two SERDES channels bound to the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps; 200G-R4 means that the network port has four SERDES channels bound to the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps; 400G-R8 means that the network port has four SERDES channels bound to the bottom layer, and the rate of each SERDES channel is configured to 53.125Gbps.

[0046] 5) TDMII interface timing The TDMII interface in this embodiment is a channelized interface using time division multiplexing technology, and the interface logic runs on the TDMII_CLK clock. In order to ensure that each SERDES channel supports a maximum data transmission rate of 25.78125 Gbps, the minimum operating frequency of TDMII_CLK is (25.78125*64 / 66) / (256 / 8)=0.78125 GHz.

[0047] In the data transmission direction from UMAC to UPCS, the TDMII interface timing is mainly controlled by UMAC, but the TDMII interface channel scheduling rules must be followed, as described in the previous “TDMII interface channel scheduling”. Fig.10(a) in the figure gives an example of the TDMII interface timing in the data transmission direction. Among them, the digital signal driven by the TDMII interface clock TDMII_CLK lasts for a total of 13 complete clock cycles. The TDMII interface transmit channel time slot signal TDMII_TXCHANSLOT[2:0] indicates the scheduling of the TDMII interface channel by UMAC, and the channel scheduling cycle shown is {0, 4, 2, 6, 1, 5, 3, 7}. The TDMII interface transmit enable signal TDMII_TXENABLE indicates the receiving capability of each channel of UPCS for the data characters and control characters sent by UMAC, and the values ​​shown in the 1st clock cycle, the 3rd clock cycle, the 6th clock cycle, the 8th clock cycle, and the 12th clock cycle are 1, indicating that the data characters and control characters sent by UMCA can be received in the 2nd clock cycle, the 4th clock cycle, the 7th clock cycle, the 9th clock cycle, and the 13th clock cycle (that is, the parameter k=1). The TDMII interface transmit direction data control signal (TDMII_TXDATA [255:0] and TDMII_TXCTRL [31:0]) and its valid signal TDMII_TXVALID [2:0] are sent by UMAC to UPCS in the 2nd, 4th, 7th, 9th and 13th clock cycles. The data of TDMII_TXDATA [255:0] in the above five clock cycles are TD [0], TD [1], TD [2], TD [3], TD [4], the data of TDMII_TXCTRL [31:0] in the above five clock cycles are TC [0], TC [1], TC [2], TC [3], TC [4], and the value of TDMII_TXVALD [2:0] in the above five clock cycles is 1 and the value in the remaining clock cycles is 0. Therefore, the data characters sent by UMAC to UPCS through the TDMII interface are TD[0][63:0], TD[1][63:0], TD[2][63:0], TD[3][63:0], TD[4][63:0], and the control characters sent are TC[0][7:0], TC[1][7:0], TC[2][7:0], TC[3][7:0], TC[4][7:0], and the sending channels are numbered 4, 6, 3, 0, and 1 respectively.

[0048] In the data receiving direction from UPCS to UMAC, the TDMII interface timing is mainly controlled by UPCS, but the TDMII interface channel scheduling rules must be followed, as described in the previous "TDMII interface channel scheduling". Fig.10(b) in the figure gives an example of the TDMII interface timing in the data receiving direction. The digital signal driven by the TDMII interface clock TDMII_CLK lasts for 13 complete clock cycles. The TDMII interface receiving channel time slot signal TDMII_RXCHANSLOT[2:0] indicates the scheduling of the TDMII interface channel by UPCS, and the channel scheduling cycle shown is {0, 4, 2, 4, 1, 4, 3, 4}. The 1st clock cycle and the 9th clock cycle belong to receiving channel 0, the 2nd clock cycle, the 4th clock cycle, the 6th clock cycle, the 8th clock cycle, the 10th clock cycle, and the 12th clock cycle belong to receiving channel 4, the 3rd clock cycle and the 11th clock cycle belong to receiving channel 2, the 5th clock cycle and the 13th clock cycle belong to receiving channel 1, and the 7th clock cycle and the 9th clock cycle belong to receiving channel 3. The TDMII interface receive direction data control signal (TDMII_RXDATA[255:0] and TDMII_RXCTRL[31:0]) and its valid signal TDMII_RXVALID[2:0] are sent to UMAC by UPCS in the other 11 clock cycles except the 7th clock cycle and the 10th clock cycle. The data of TDMII_RXDATA [255:0] in the above 11 clock cycles are RD[0], RD[1], RD[2], RD[3], RD[4], RD[5], RD[6], RD[7], RD[8], RD[9], RD

[10] respectively. The data of TDMII_RXCTRL[31:0] in the above 11 clock cycles are RC[0], RC[1], RC[2], RC[3], RC[4], RC[5], RC[6], RC[7], RC[8], RC[9], RC

[10] respectively. The value of TDMII_RXVALD [2:0] in the above 11 clock cycles is 1 or 2 and the value in the remaining clock cycles is 0.Therefore, the data characters received by UMAC from each channel of UPCS through the TDMII interface are: Channel 0 receives {RD[0][63:0], RD[7][63:0]}, Channel 4 receives {RD[1][127:0], RD[3][127:0], RD[5][127:0], RD[6][127:0], RD[9][127:0]}, Channel 2 receives {RD[2][63:0], RD[8][63:0]}, Channel 1 receives {RD[4][63:0], RD

[10] [63:0]}, channel 3 did not receive any valid data characters; the control characters received by each channel are: channel 0 receives {RC[0][7:0], RC[7][7:0]}, channel 4 receives {RC[1][15:0], RC[3][15:0], RC[5][15:0], RC[6][15:0], RC[9][15:0]}, channel 2 receives {RC[2][7:0], RC[8][7:0]}, channel 1 receives {RC[4][7:0], RC

[10] [7:0]}, and channel 3 did not receive any valid control characters.

[0049] 6) TDMII interface application There are two typical application scenarios of the TDMII interface. The first is to build an interface adapter that complies with the TDMII interface timing rules to connect the PCS and MAC of multiple rates in the existing technology. Fig.11 (a) in FIG. 1 shows an example of the first application scenario. In the example, interface adapter 0 converts a CDMII interface of 1 200G MAC, a CGMII interface of 2 100G MAC, a LGMII interface of 4 50G MAC, a XLGMII interface of 2 40G MAC, a MII interface of 8 25G MAC, and a XGMII interface of 8 10G MAC into a TDMII interface. Interface adapter 1 converts a CDMII interface of 1 200G PCS, a CGMII interface of 2 100G PCS, a LGMII interface of 4 50G PCS, a XLGMII interface of 2 40G PCS, a MII interface of 8 25G PCS, and a XGMII interface of 8 10G PCS into a TDMII interface. The TDMII interfaces of interface adapter 0 and interface adapter 1 are then connected. The second is to construct a multi-rate multi-channel UMAC and UPCS so that its connection interface follows the TDMII interface timing. Fig.11(b) in Figure 1 gives an example of the second application scenario. The multi-rate multi-channel UMAC and UPCS adopt channelized design technology, which supports a maximum of 8 channels. The supported network port rates include 200G, 100G, 50G, 40G, 25G, and 10G. The number of SERDES channels that can be bound to a single channel supports ×8, ×4, ×2, and ×1. The channelized multi-rate multi-channel UMAC and UPCS design using TDMII interface technology is conducive to improving the utilization of logic resources and reducing the demand for logic resources.

[0050] As a further improvement to the method of using the time-division multiplexed media independent interface that supports multi-rate multi-channel communication of the present invention: As mentioned above, in order to be suitable for multi-rate multi-channel Ethernet with a larger rate range and more channel modes, it can be expanded by appropriately increasing the data width of each signal of the TDMII interface of the present invention. For example, for an extended TDMII interface that supports 400G, 200G, 100G, 50G, 40G, and 10G multi-channels, a single SERDES channel can be configured as 53.125Gbps, 25.78125Gbps, and 10.3125Gbps multi-rates, and supports Ethernet interface connections divided into 8 channels at most, in the first application scenario, interface adapter 0 and interface adapter 1 need to support converting more MII interfaces (MII interfaces corresponding to 50G-R1, 100G-R2, 200G-R4, and 400G-R8 modes need to be added) into an extended TDMII interface; in the second application scenario, UMAC and UPCS need to support a 400G network port channel mode that binds 8 SERDES channels, a 200G network port channel mode that binds 4 SERDES channels, a 100G network port channel mode that binds 2 SERDES channels, and a 50G network port channel mode that binds a single SERDES channel.

[0051] In summary, the time-division multiplexing medium-independent interface of this embodiment includes a medium access control layer module and a physical coding sublayer module that support multi-rate multi-channel communication. The medium access control layer module and the physical coding sublayer module share the same clock signal and channel mode configuration signal. The signal output by the medium access control layer module to the physical coding sublayer module includes a sending channel time slot signal, a sending data signal, a sending control signal, and a valid signal for sending data and control; the signal output by the physical coding sublayer module to the medium access control layer module includes a sending enable signal, a receiving channel time slot signal, a receiving data signal, a receiving control signal, and a valid signal for receiving data and control. The time-division multiplexing medium-independent interface of this embodiment can solve the problem of numerous interface types and interface signals in the existing medium-independent interface technology, and realize compatibility with multi-rate multi-channel Ethernet with a large rate range. Compared with the medium-independent interface MII technology of the prior art, this embodiment can realize the communication between the multi-rate multi-channel PCS and the multi-rate multi-channel MAC in a channelized time-division multiplexing manner, thereby simplifying the connection signal between the multi-rate multi-channel PCS and the multi-rate multi-channel MAC, and solving the problem of numerous interface types and interface signals in the existing medium-independent interface MII technology. The method of this embodiment is beneficial to the integration of multi-rate multi-channel MAC and multi-rate multi-channel PCS in the front-end design process of the network communication chip, and is also beneficial to the layout and routing of multi-rate multi-channel MAC and multi-rate multi-channel PCS in the back-end design process of the network communication chip.

[0052] The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.

Claims

1. A time-division multiplexing medium-independent interface supporting multi-rate multi-channel communications, characterized in that: The invention comprises a medium access control layer module UMAC and a physical coding sublayer module UPCS which support multi-rate multi-channel communication. The medium access control layer module UMAC and the physical coding sublayer module UPCS share the same clock signal TDMII_CLK and channel mode configuration signal CFG_TDMII[23:0]. The signals output by the medium access control layer module UMAC to the physical coding sublayer module UPCS include a sending channel time slot signal TDMII_TXCHANSLOT[2:0], a sending data signal TDMII_TXDATA, a sending control signal TDMII_TXCTRL and a valid signal TDMII_TXVALID[2:0] for sending data and control; the signals output by the physical coding sublayer module UPCS to the medium access control layer module UMAC include a sending enable signal TDMII_TXENABLE, a receiving channel time slot signal TDMII_RXCHANSLOT[2:0], a receiving data signal TDMII_RXDATA, a receiving control signal TDMII_RXCTRL and a valid signal TDMII_RXVALID[2:0] for receiving data and control.

2. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 1, characterized in that: The channel mode configuration signal CFG_TDMII[23:0] supports a maximum of 8 channels, whose channel numbers are 0, 1, 2, 3, 4, 5, 6, and 7, respectively, and the mode of the i-th channel is controlled by the bit field CFG_TDMII[i*3+2: i*3] of the channel mode configuration signal CFG_TDMII, including: when the bit field CFG_TDMII[i*3+2: i*3]=3'b001, it means that the mode of the i-th channel is 10G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2: i*3]=3'b010, it means that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; when the bit field CFG_TDMII[i*3+2: i*3]=3'b010, it means that the mode of the i-th channel is 25G-R1, and the value range of i is {0, 1, 2, 3, 4, 5, 6, 7}; i*3]=3'b011, indicating that the mode of the i-th channel is 40G-R4, and the value range of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b100, indicating that the mode of the i-th channel is 50G-R2, and the value range of i is {0, 2, 4, 6}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b101, indicating that the mode of the i-th channel is 100G-R4, and the value range of i is {0, 4}; when the bit field CFG_TDMII[i*3+2 : i*3]=3'b110, indicating that the mode of the i-th channel is 200G-R8, and the value range of i is {0}, where 10G-R1 indicates that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 10.3125 Gbps; 25G-R1 indicates that the network port has a single SERDES channel at the bottom layer, and its SERDES channel rate is configured to 25.78125 Gbps; 40G-R4 indicates that the network port has four SERDES channels bound to it at the bottom layer, and the rates of each SERDES channel are Configured as 10.3125Gbps; 50G-R2 means that the network port is bound to 2 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 100G-R4 means that the network port is bound to 4 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps; 200G-R8 means that the network port is bound to 8 SERDES channels at the bottom layer, and the rate of each SERDES channel is configured to 25.78125Gbps.

3. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 2, characterized in that: The valid signal TDMII_TXVALID[2:0] for sending data and control is used to control the effective bit width of the sending data signal TDMII_TXDATA and the sending control signal TDMII_TXCTRL. The effective bit width of the receiving direction of the time-division multiplexing medium-independent interface is controlled in a time-division multiplexing manner. The value of the valid signal TDMII_TXVALID[2:0] for sending data and control in each clock cycle determines the corresponding sending channel number in the current clock cycle. The sending channel mode of the network port in the current clock cycle is determined according to the sending channel number of the current clock cycle and the channel mode configuration signal CFG_TDMII[23:0]. The sending channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for sending data and control in the current clock cycle.

4. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 3, characterized in that: The transmission channel mode of the present clock cycle determines the specific value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control of the present clock cycle, including: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (3) If the channel mode is 40G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}; (4) If the channel mode is 50G-R2, the value range of the valid signal TDMII_TXVALID[2:0] for transmitting data and control is {3'b000}.}; (5) If the channel mode is 100G-R4, the value range of the valid signal TDMII_TXVALID[2:0] for sending data and control is {3'b000}; (6) If the channel mode is 200G-R8, the value range of the valid signal TDMII_TXVALID[2:0] for sending data and control is {3'b000}; In each transmit channel mode, whether the specific value of the valid signal TDMII_TXVALID[2:0] for transmit data and control is 3'b000 or not depends on the value of the transmit enable signal TDMII_TXENABLE k clock cycles ago. If the transmit enable signal TDMII_TXENABLE=1 k clock cycles ago, the valid signal TDMII_TXVALID[2:0] for transmit data and control takes a non-3'b000 value in this clock cycle; otherwise, if the transmit enable signal TDMII_TXENABLE=0 k clock cycles ago, the valid signal TDMII_TXVALID[2:0] for transmit data and control takes a 3'b000 value in this clock cycle.

5. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 4, characterized in that: The valid signal TDMII_RXVALID[2:0] for receiving data and control is used to control the effective bit width of the receiving data signal TDMII_RXDATA and the receiving control signal TDMII_RXCTRL. The effective bit width of the receiving direction of the time-division multiplexing medium-independent interface is controlled in a time-division multiplexing manner. The value of the valid signal TDMII_RXVALID[2:0] for receiving data and control in each clock cycle determines the corresponding receiving channel number in the current clock cycle. The receiving channel mode of the network port in the current clock cycle is determined according to the receiving channel number of the current clock cycle and the channel mode configuration signal CFG_TDMII[23:0]. The receiving channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control in the current clock cycle.

6. The time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 5, characterized in that: The receiving channel mode of the current clock cycle determines the specific value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control of the current clock cycle: (1) If the channel mode is 10G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; (2) If the channel mode is 25G-R1, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b001}; The value range of TDMII_TXVALID[2:0] is {3'b001}; (3) If the channel mode is 40G-R4, the value range of TDMII_TXVALID[2:0] and TDMII_RXVALID[2:0] is {3'b001}; (4) If the channel mode is 50G-R2, the value range of TDMII_RXVALID[2:0], which is the valid signal for receiving data and control, is {3'b001}; (5) If the channel mode is 100G-R 4, then the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b010}; (6) If the channel mode is 200G-R8, the value range of the valid signal TDMII_RXVALID[2:0] for receiving data and control is {3'b100}; In each receiving channel mode, whether the specific value of the valid signal TDMII_RXVALID[2:0] for receiving data and control is 3'b000 or not depends on whether the corresponding receiving channel of the physical coding sublayer module UPCS has data to transmit to the medium access control layer module UMAC in this clock cycle; if there is data to be transmitted, the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a non-3'b000 value in this clock cycle; otherwise, if there is no data to be transmitted, the valid signal TDMII_RXVALID[2:0] for receiving data and control takes a 3'b000 value in this clock cycle.

7. An application method of a time-division multiplexed medium-independent interface supporting multi-rate multi-channel communication as claimed in any one of claims 1 to 6, characterized in that: The invention comprises forming one of the following six homogeneous network port channel modes with multiple time-division multiplexed media-independent interfaces supporting multi-rate multi-channel communications: (1) 8×10G-R1, which means that the time-division multiplexed media-independent interface is sequentially split into 8 network ports with a channel mode of 10G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the value of the channel mode configuration signal CFG_TDMII is {8{3'b001}}; (2) 8×25G-R1, which means that the time-division multiplexed media-independent interface is sequentially split into 8 network ports with a channel mode of 25G-R1, and the assigned channel numbers are {0, 1, 2, 3, 4, 5, 6, 7}, and the value of the channel mode configuration signal CFG_TDMII is {8{3'b001}}. The value of the configuration signal CFG_TDMII is {8{3'b010}}; (3) 2×40G-R4, indicating that the time-division multiplexed medium-independent interface is sequentially split into two network ports with a channel mode of 40G-R4, and the allocated channels are numbered {0, 4} respectively. The value of the channel mode configuration signal CFG_TDMII is {2{{3'b011}, 3{3'bzzz}}}; (4) 4×50G-R2, indicating that the time-division multiplexed medium-independent interface is sequentially split into four network ports with a channel mode of 50G-R2, and the allocated channels are numbered {0, 2, 4, 6} respectively. The value of the channel mode configuration signal CFG_TDMII is {4{{3'b100}, {3'bzzz}}}; (5) 2×100G-R4, indicating that the time-division multiplexed media-independent interface is sequentially split into two network ports with a channel mode of 100G-R4, and the assigned channel numbers are {0, 4} respectively. The value of the channel mode configuration signal CFG_TDMII is {2{{3'b101}, 3{3'bzzz}}}; (6) 1×200G-R8, indicating that the time-division multiplexed media-independent interface is used as a network port with a channel mode of 200G-R8, and the assigned channel number is {0}. The value of the channel mode configuration signal CFG_TDMII is {{3'b101}, 7{3'bzzz}}}, where {3'bzzz} indicates that each bit is a 3-bit signal with an arbitrary value.

8. The application method of the time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 7, characterized in that: In the six homogeneous network port channel modes: (1) In the 8×10G-R1 homogeneous network port channel mode, the values ​​of the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] in the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 2, 6, 1, 5, 3, 7} respectively, and each channel mode allocates 1 / 8 of the clock cycle to the 25G-R1 network port; (2) In the 8×25G-R1 homogeneous network port channel mode, the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] are {0, 4, 2, 6, 1, 5, 3, 7} in the 1st scheduling cycle to the 8th scheduling cycle respectively, and each channel mode allocates 1 / 8 of the clock cycle to the 25G-R1 network port; The values ​​assigned to II_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 2, 6, 1, 5, 3, 7}, respectively, that is, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1. (3) In the 2×40G-R4 homogeneous network port channel mode, the values ​​assigned to the transmit channel time slot signal TDMII_TXCHANSLOT[2:0] and the receive channel time slot signal TDMII_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 0, 4, 0, 4, 0, 4}, respectively, that is, 4 / 8 of the clock cycle is allocated to each network port with a channel mode of 40G-R4. clock cycle; (4) In the 4×50G-R2 homogeneous network port channel mode, the transmission channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 0, 4, 2, 6} in the 1st scheduling cycle to the 8th scheduling cycle, respectively, and 2 / 8 of the clock cycle is allocated to each network port with a channel mode of 50G-R2; (5) In the 2×100G-R4 homogeneous network port channel mode, the transmission channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHAN The values ​​of SLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 4, 0, 4, 0, 4, 0, 4}, respectively, allocating 4 / 8 of the clock cycle to each network port with a channel mode of 100G-R4. (6) In the 1×200G-R8 homogeneous network port channel mode, the values ​​of the transmitting channel time slot signal TDMII_TXCHANSLOT[2:0] and the receiving channel time slot signal TDMII_RXCHANSLOT[2:0] from the 1st scheduling cycle to the 8th scheduling cycle are {0, 0, 0, 0, 0, 0, 0, 0}, respectively, allocating all 8 / 8 of the clock cycle to a single network port with a channel mode of 200G-R8.

9. An application method of a time-division multiplexed medium-independent interface supporting multi-rate multi-channel communication as claimed in any one of claims 1 to 6, characterized in that: The invention comprises forming one of the following four heterogeneous network port channel modes with multiple time-division multiplexed media-independent interfaces supporting multi-rate multi-channel communications: (1) 1×100G-R4+2×50G-R2, in which the time-division multiplexed media-independent interface is sequentially split into one network port with a channel mode of 100G-R4 and two network ports with a channel mode of 50G-R2, and the assigned channel numbers are {0, 4, 6} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={{3'b101}, 3{3'bzzz}, 2{{3'b100}, {3'bzzz}}}; (2) 4×25G-R1+1×40G-R4, in which the time-division multiplexed media-independent interface is sequentially split into four network ports with a channel mode of 25G- The network port of R1 and one network port with a channel mode of 40G-R4 are assigned channel numbers {0, 1, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0]={4{3'b010},{3'b011},3{3'bzzz}}; (3) 1×50G-R2+2×25G-R1+1×100G-R4, the time-division multiplexed medium-independent interface is sequentially split into one network port with a channel mode of 50G-R2, two network ports with a channel mode of 25G-R1 and one network port with a channel mode of 100G-R4, and the assigned channel numbers are {0, 2, 3, 4} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0] ={{3'b100},{3'bzzz}, 2{3'b010},{3'b101},3{3'bzzz}}; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2, the time-division multiplexed medium-independent interface is sequentially split into 2 network ports with a channel mode of 10G-R1, 1 network port with a channel mode of 50G-R2, 2 network ports with a channel mode of 25G-R1, and 1 network port with a channel mode of 50G-R2. The allocated channel numbers are {0, 1, 2, 4, 5, 6} respectively, and the channel mode configuration signal value is CFG_TDMII[23:0] ={2{3'b001},{3'b001},{3'bzzz},2{3'b010},{3'b100},{3'bzzz}}, where {3'bzzz} represents a 3-bit signal where each bit can take any value.

10. The application method of the time-division multiplexing medium-independent interface supporting multi-rate multi-channel communication according to claim 9, characterized in that: In the four heterogeneous network port channel modes: (1) In the 1×100G-R4+2×50G-R2 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 0, 6, 0, 4, 0, 6} in the 1st scheduling cycle to the 8th scheduling cycle, respectively, and 4 / 8 of the clock cycle is allocated to a single network port in the 100G-R4 channel mode, and 2 / 8 of the clock cycle is allocated to each network port in the 50G-R2 channel mode; (2) 4×25G-R1+1×40 In the G-R4 heterogeneous network port channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 4, 1, 4, 3, 4} in the 1st to 8th scheduling cycles, respectively, allocating 1 / 8 of the clock cycle to each network port with a channel mode of 25G-R1, and allocating 4 / 8 of the clock cycle to a single network port with a channel mode of 40G-R4; (3) In the 1×50G-R2+2×25G-R1+1×100G-R4 heterogeneous network port channel mode, the channel time slot signal T The values ​​of DMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] in the 1st to 8th scheduling cycles are {0, 4, 2, 4, 0, 4, 3, 4}, respectively. 2 / 8 of the clock cycle is allocated to a single channel mode 50G-R2 network port, 1 / 8 of the clock cycle is allocated to each channel mode 25G-R1 network port, and 4 / 8 of the clock cycle is allocated to a single channel mode 100G-R4 network port; (4) 2×10G-R1+1×50G-R2+2×25G-R1+1×50G-R2 heterogeneous network port In the channel mode, the channel time slot signals TDMII_TXCHANSLOT[2:0] and TDMII_RXCHANSLOT[2:0] are assigned values ​​of {0, 4, 2, 6, 1, 4, 3, 6} in the 1st to 8th scheduling cycles, respectively. 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 10G-R1, 2 / 8 of the clock cycle is allocated to a network port with a single channel mode of 50G-R2, 1 / 8 of the clock cycle is allocated to each network port with a channel mode of 25G-R1, and 2 / 8 of the clock cycle is allocated to a network port with a single channel mode of 50G-R2.

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