HDLC (High-level Data Link Control) receiver with function of adaptively adjusting synchronous clock phase and operation method

Abstract

The invention provides an HDLC (High-level Data Link Control) receiver with a function of adaptively adjusting a synchronous clock phase and an operation method, belongs to the technical field of data communication, and solves the problem that a traditional HDLC receiver cannot adaptively adjust the clock phase to adapt to different working environments and signal changes. The HDLC receiver comprises a synchronous clock input module, a serial data input module, a clock phase shifter module, a phase difference calculator module, a serial-to-parallel converter module, a zero removal controller module, a '7E' detector module, a received data coding module, an address judgment module, a CRC verification module, a function setting register module, a receiving cache region module and a state register module. The modules in the HDLC receiver designed by the invention are mutually independent, but are mutually connected through signals such as clocks and data, so that the flexibility and expansibility of the system are ensured, and parameters of different modules can be adjusted as required in different application scenes so as to adapt to different communication environments.

Description

Technical Field

[0001] The invention relates to an HDLC receiver with a function of adaptively adjusting a synchronous clock phase and an operating method thereof, belonging to the technical field of data communication. Background Art

[0002] In the communication system of HDLC protocol, the receiving end needs to sample and process the received data correctly through the received data frame and the synchronous clock. However, in practical applications, since the clock and data signals are affected by various factors during the transmission process, such as transmission delay, clock jitter, clock drift, noise and other factors, there may be a certain phase difference between the received data signal and the clock signal. If this phase difference cannot be effectively compensated and adjusted, it will cause data sampling errors or data loss, thereby affecting the reliability and accuracy of data transmission. Therefore, how to accurately adjust the phase of the receiving clock to adapt to the phase change of the input signal is the key to improving the performance of the receiver. Traditional HDLC receivers usually use a fixed clock phase and cannot adaptively adjust the clock phase to adapt to different working environments and signal changes. Developing an HDLC receiver that can automatically detect the phase difference and adjust the clock phase as needed has become an important research direction for improving the performance and robustness of the communication system. The technology of adaptively adjusting the synchronous clock phase proposed in the present invention can monitor the phase difference between the clock signal and the data signal in real time, and automatically adjust the clock phase according to the size of the phase difference, thereby ensuring stable transmission and accurate reception of data. Summary of the invention

[0003] The present invention solves the problem that the traditional HDLC receiver cannot adaptively adjust the clock phase to adapt to different working environments and signal changes, and further proposes an HDLC receiver with the function of adaptively adjusting the synchronous clock phase and an operating method.

[0004] The technical solution adopted by the present invention to solve the above-mentioned problem is: the HDLC receiver with the function of adaptively adjusting the synchronous clock phase proposed by the present invention comprises:

[0005] Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, receiving data encoding module, address judgment module, CRC check module, function setting register module, receiving buffer module and status register module;

[0006] The synchronous clock input module is used to receive the input synchronous clock;

[0007] The serial data input module is used to receive input serial data;

[0008] The phase difference calculator module is used to calculate the phase difference between the synchronous clock and the serial data and transmit it to the clock phase shifter module;

[0009] The clock phase shifter module performs phase shifting processing on the synchronous clock according to the phase difference, and inputs the synchronous clock and serial data after the phase shifting processing into the '7E' detector module;

[0010] The '7E' detector module is used to detect the valid frame header of the serial data;

[0011] The zero removal controller module is used to perform zero removal operation on serial data;

[0012] The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data and inputs the parallel data into the address judgment module;

[0013] The address judgment module is used to judge whether the serial data after the zero removal operation is a valid frame;

[0014] When it is a valid frame, the receiving data encoder receives the instruction of the function setting register module, reads the parallel data from the serial-to-parallel converter module, stores it in the receiving buffer module and updates the status register module;

[0015] The CRC checker is used to perform real-time judgment on the serial data after the zero removal operation, and sends the judgment result to the status register module through the receiving data encoder module at the end of the frame.

[0016] Preferably, the phase difference calculator module includes an XOR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule;

[0017] The XOR operation submodule is used to perform XOR operation on the input synchronous clock and serial data to generate an XOR data signal;

[0018] The phase difference positive and negative judgment submodule is used to measure the xor data signal and judge the phase difference positive and negative according to the measurement result;

[0019] The duty cycle calculation submodule is used to calculate the duty cycle according to the positive and negative judgment results of the phase difference;

[0020] The phase difference calculation submodule is used to calculate the phase difference between the synchronous clock and the serial data according to the duty cycle calculation result.

[0021] Preferably, the clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule;

[0022] The phase difference input submodule is used to receive the phase difference output by the phase difference calculator module;

[0023] The phase difference judgment submodule compares the phase difference with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock.

[0024] The clock delay time calculation submodule is used to calculate the clock delay time and transmit it to the synchronous clock phase shift submodule;

[0025] The synchronous clock phase shift submodule performs a phase shift operation on the synchronous clock according to the received delay time and transmits it to the edge detection and sampling point calculation submodule;

[0026] The edge detection and sampling point calculation submodule performs edge detection and calculates the position of the sampling point in the serial data bit according to the received phase-shifted synchronous clock, and transmits the calculation result to the sampling point judgment submodule;

[0027] The sampling point judgment submodule judges whether the sampling point position is located at the bit center. If it is located at the bit center, it sends a signal to the synchronous clock output submodule to output the current synchronous clock. If it is not located at the bit center, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the bit center.

[0028] The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

[0029] The operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase comprises:

[0030] Step 1: Input the synchronous clock and serial data into the synchronous clock input module and the serial data input module respectively;

[0031] Step 2: Use the phase difference calculator module to calculate the phase difference between the synchronous clock and the serial data;

[0032] Step 3: Input the phase difference into the clock phase shifter module to perform phase shift operation on the synchronous clock, and input the synchronous clock and serial data after phase shift processing into the '7E' detector module;

[0033] Step 4: The '7E' detector module detects the valid frame header of the serial data, and uses the zero removal controller module to perform a zero removal operation on the serial data;

[0034] Step 5: Input the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC checker module respectively;

[0035] Step 6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. When it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module;

[0036] Step 7: The CRC checker module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

[0037] Preferably, step 2 specifically includes:

[0038] Step 2.1: Perform an XOR operation on the input synchronous clock and serial data through the XOR operation submodule to obtain an XOR data signal;

[0039] Step 2.2: The xor data signal after the XOR operation is measured by the phase difference positive and negative judgment submodule to obtain the high level duration T1 of the data rising edge, the high level duration T2 of the data falling edge, and the high level duration T3 of the clock cycle. If the synchronous clocks corresponding to T1 and T2 are low, the phase difference is judged to be positive; if the synchronous clocks corresponding to T1 and T2 are high, the phase difference is judged to be negative.

[0040] Step 2.3: According to the phase difference positive and negative judgment result, the duty cycle is calculated using the duty cycle calculation submodule. If the phase difference positive and negative judgment result is positive, the duty cycle is calculated using the T1 time. If the phase difference positive and negative judgment result is negative, the duty cycle is calculated using the T2+T3 time. The duty cycle calculation formula is: Duty cycle = high level time / period;

[0041] Step 2.4: Input the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference θ between the synchronous clock and the serial data.

[0042] Preferably, step 3 specifically includes:

[0043] Step 3.1: Input the phase difference θ into the phase difference input submodule, and transmit it to the phase difference judgment submodule;

[0044] Step 3.2: The phase difference judgment submodule compares the received phase difference θ with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock.

[0045] Step 3.3: After receiving the trigger signal, the clock delay time calculation submodule calculates the delay time of the clock according to the phase difference θ and the synchronous clock frequency f, wherein the calculation formula of the delay time is t=θ / (2πf);

[0046] Step 3.4: Input the delay time into the synchronous clock phase shift submodule, and adjust the phase by delaying the synchronous clock by a corresponding time on the time axis to ensure that the phase of the synchronous clock is consistent with the phase of the serial data;

[0047] Step 3.5: Input the phase-shifted synchronous clock into the edge detection and sampling point calculation submodule. When the rising edge / falling edge of the synchronous clock is detected, the position of the sampling point in the data bit is calculated according to the clock cycle and the serial data bit cycle.

[0048] Step 3.6: The sampling point judgment submodule compares the sampling point position with the center position of the data bit. If the sampling point is located at the center of the bit, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. If the sampling point is not located at the center of the bit, a feedback signal is sent to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the center of the bit.

[0049] Step 3.7: The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

[0050] The beneficial effects of the present invention are:

[0051] 1. The receiver of the present invention has adaptive adjustment capability, and can automatically calculate and adjust the required clock phase according to the changing phase angle in real time, reducing the need for human intervention and fixed calibration, greatly improving the robustness and flexibility of the system. Due to the dynamic adjustment function of the phase, the receiver can process the phase error in the signal in real time, reducing the transmission error caused by the phase difference, and ensuring the stability and reliability of data transmission.

[0052] 2. The HDLC receiver with the function of adaptively adjusting the synchronous clock phase of the present invention is widely applicable to data reception in high-speed communication systems, especially in the fields of digital communication, data transmission, wireless communication, etc. In these fields, the phase difference of the signal is usually large, and the receiver of the present invention can dynamically adjust the clock phase to ensure the correct reception of data.

[0053] 3. The present invention is implemented using the hardware description language (Verilog), has high integration and scalability, and can be easily integrated into various digital communication systems.

[0054] 4. The present invention uses an exclusive OR (XOR) operation to reflect the phase offset between the input data and the clock signal, and combines the delay control logic to achieve phase adjustment of the clock signal. The adjusted clock signal is used as input to ensure that the received data can maintain precise synchronization with the clock.

[0055] 5. The modules in the HDLC receiver designed by the present invention are independent of each other, but are connected to each other through signals such as clock and data, thereby ensuring the flexibility and scalability of the system. In different application scenarios, the parameters of different modules can be adjusted as needed to adapt to different communication environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A structural block diagram of an HDLC receiver with a function of adaptively adjusting the synchronous clock phase provided by the present invention;

[0057] Figure 2 A structural block diagram of a phase difference calculator module provided by the present invention;

[0058] Figure 3 A structural block diagram of a clock phase shifter module provided by the present invention;

[0059] Figure 4 A schematic flow chart of an operation method of an HDLC receiver with a function of adaptively adjusting a synchronous clock phase provided by the present invention;

[0060] Figure 5 A schematic diagram of the flow chart of the phase difference calculator module provided by the present invention;

[0061] Figure 6 A schematic diagram of the XOR processing of the synchronous clock and serial data provided by the present invention;

[0062] Figure 7 A schematic diagram of the flow of the clock phase shifter module provided by the present invention. DETAILED DESCRIPTION

[0063] Specific implementation method 1: Combination Figure 1-3 To illustrate this embodiment, Figure 1 As shown, the structure of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase described in this embodiment includes:

[0064] Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, receiving data encoding module, address judgment module, CRC check module, function setting register module, receiving buffer module and status register module;

[0065] In this embodiment, the modules are independent of each other, but are connected to each other through signals such as clock and data, thereby ensuring the flexibility and scalability of the system. In different application scenarios, the parameters of different modules can be adjusted as needed to adapt to different communication environments.

[0066] like Figure 2 As shown, the phase difference calculator module includes an XOR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule;

[0067] like Figure 3 As shown, the clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule.

[0068] Specific implementation method 2: Combination Figure 4-7 This embodiment is described as follows. Figure 4 As shown, the operation method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase described in this embodiment includes the following steps:

[0069] S1: input the synchronous clock and serial data into the synchronous clock input module and the serial data input module respectively;

[0070] S2: Calculate the phase difference between the synchronous clock and the serial data using the phase difference calculator module;

[0071] like Figure 5 As shown in the figure, the workflow of the phase difference calculator module includes:

[0072] S201: Perform an XOR operation on the input synchronous clock and serial data through the XOR operation submodule, and the signal generated after the XOR operation is recorded as xor data. As a basic logical operation, the XOR operation can perform preliminary processing on the characteristics of the clock and data signals. Through this operation, the phase difference characteristics between the clock signal and the data signal can be highlighted, which is convenient for the subsequent measurement and calculation of the phase difference.

[0073] S202: Figure 6 As shown, the xor data signal after the XOR operation is measured by the phase difference positive and negative judgment submodule to obtain the high level duration T1 of the data rising edge, the high level duration T2 of the data falling edge, and the high level duration T3 of the clock cycle. According to the measured signal parameters, the positive and negative situation of the phase difference between the clock signal and the data signal is judged. If the clock signal corresponding to the time T1 and T2 is low, it can be judged that the phase difference is positive; conversely, if the clock signal corresponding to the time T1 and T2 is high, the phase difference is negative.

[0074] The present invention uses an exclusive OR (XOR) operation to reflect the phase offset between the input data and the clock signal, and combines the delay control logic to achieve phase adjustment of the clock signal. The adjusted clock signal is used as input to ensure that the received data can maintain precise synchronization with the clock.

[0075] S203: According to the phase difference positive or negative judgment result, the duty cycle is calculated using the duty cycle calculation submodule. If the judgment result is that the phase difference is positive, the T1 time in the xor data signal is used to calculate the duty cycle. The duty cycle calculation submodule calculates the proportional relationship between the high level duration T1 and the entire cycle time, duty cycle = high level time / cycle, thereby obtaining the duty cycle value; if the judgment result is that the phase difference is negative, the T2+T3 time is used to calculate the duty cycle, and the corresponding duty cycle result is obtained according to the established calculation rules.

[0076] S204: Input the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference θ between the synchronous clock and the serial data, where the unit of the phase difference is radian.

[0077] S3: input the phase difference into the clock phase shifter module to perform phase shift operation on the synchronous clock, and input the synchronous clock and serial data after phase shift processing into the '7E' detector module;

[0078] like Figure 7 As shown in the figure, the workflow of the clock phase shifter module includes:

[0079] S301: The phase difference input submodule obtains the phase difference data between the synchronous clock and the data from the phase difference calculator, and transmits it to the phase difference judgment submodule;

[0080] S302: The phase difference judgment submodule compares the received phase difference data with the tolerable phase difference threshold pre-stored in the register. This threshold is determined according to the performance requirements of the system. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule; if the phase difference is not greater than the threshold, a signal is directly sent to the synchronous clock output submodule to make it output the current synchronous clock;

[0081] S303: When the clock delay time calculation submodule receives the trigger signal, it calculates the time required to delay the clock based on the input phase difference data and parameters such as the frequency of the synchronous clock. Assuming that the synchronous clock frequency is f and the phase difference is θ, the delay time t = θ / (2πf). The calculation result is stored in the internal register and transmitted to the synchronous clock phase shift submodule;

[0082] S304: The synchronous clock phase shifting submodule performs a phase shift operation on the synchronous clock signal according to the received delay time. By delaying the clock signal accordingly on the time axis, its phase is adjusted to make it accurately close to the phase of the data signal. The phase-shifted synchronous clock signal is transmitted to the edge detection and sampling point calculation submodule;

[0083] S305: The edge detection and sampling point calculation submodule performs edge detection on the received phase-shifted synchronous clock signal. When the rising edge or falling edge of the clock signal is detected, the position of the sampling point in the data bit is calculated based on information such as the clock cycle and the data bit cycle, and the calculation result is transmitted to the sampling point judgment submodule;

[0084] S306: The sampling point judgment submodule compares the calculated sampling point position with the center position of the data bit to determine whether the sampling point is at the center of the bit. If the sampling point is at the center of the bit, a signal is sent to the synchronous clock output submodule to make it output the current synchronous clock; if the sampling point is not at the center of the bit, a feedback signal is sent to reacquire the phase difference data and enter a new round of adjustment process;

[0085] S307: The synchronous clock output submodule transmits the adjusted synchronous clock to the '7E' detector module according to the received signal to perform data sampling and processing.

[0086] S4: The '7E' detector module detects the valid frame header of the serial data and uses the zero removal controller module to perform a zero removal operation on the serial data;

[0087] S5: inputting the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC checker module respectively;

[0088] S6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. When it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module;

[0089] S7: The CRC checker module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

[0090] In summary, the receiver of the present invention has adaptive adjustment capability, and can automatically calculate and adjust the required clock phase according to the changing phase angle in real time, reducing the need for human intervention and fixed calibration, greatly improving the robustness and flexibility of the system. Due to the dynamic adjustment function of the phase, the receiver can process the phase error in the signal in real time, reducing the transmission error caused by the phase difference, and ensuring the stability and reliability of data transmission.

[0091] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A HDLC receiver with a function of adaptively adjusting the synchronous clock phase, characterized in that: The structure of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase comprises: Synchronous clock input module, serial data input module, clock phase shifter module, phase difference calculator module, serial-to-parallel converter module, zero removal controller module, '7E' detector module, receiving data encoding module, address judgment module, CRC check module, function setting register module, receiving buffer module and status register module; The synchronous clock input module is used to receive an input synchronous clock; The serial data input module is used to receive input serial data; The phase difference calculator module is used to calculate the phase difference between the synchronous clock and the serial data and transmit it to the clock phase shifter module; The clock phase shifter module performs phase shift processing on the synchronous clock according to the phase difference, and inputs the synchronous clock and serial data after the phase shift processing into the '7E' detector module; The '7E' detector module is used to detect a valid frame header of serial data; The zero removal controller module is used to perform a zero removal operation on the serial data; The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data and inputs the parallel data into the address determination module; The address determination module is used to determine whether the serial data after the zero removal operation is a valid frame; When it is a valid frame, the receiving data encoder receives the instruction of the function setting register module, reads the parallel data from the serial-to-parallel converter module, stores it in the receiving buffer module and updates the status register module; The CRC checker is used to perform real-time judgment on the serial data after the zero removal operation, and send the judgment result to the status register module through the receiving data encoder module at the end of the frame.

2. The HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 1, characterized in that: The phase difference calculator module includes an XOR operation submodule, a phase difference positive and negative judgment submodule, a duty cycle calculation submodule and a phase difference calculation submodule; The XOR operation submodule is used to perform an XOR operation on the input synchronous clock and serial data to generate an XOR data signal; The phase difference positive and negative judgment submodule is used to measure the xor data signal and judge the phase difference positive and negative according to the measurement result; The duty cycle calculation submodule is used to calculate the duty cycle according to the phase difference positive and negative judgment result; The phase difference calculation submodule is used to calculate the phase difference between the synchronous clock and the serial data according to the duty cycle calculation result.

3. The HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 1, characterized in that: The clock phase shifter module includes a phase difference input submodule, a phase difference judgment submodule, a clock delay time calculation submodule, a synchronous clock phase shift submodule, an edge detection and sampling point calculation submodule, a sampling point judgment submodule and a synchronous clock output submodule; The phase difference input submodule is used to receive the phase difference output by the phase difference calculator module; The phase difference judgment submodule compares the phase difference with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. The clock delay time calculation submodule is used to calculate the clock delay time and transmit it to the synchronous clock phase shift submodule; The synchronous clock phase shift submodule performs a phase shift operation on the synchronous clock according to the received delay time and transmits the phase shift operation to the edge detection and sampling point calculation submodule; The edge detection and sampling point calculation submodule performs edge detection and calculates the position of the sampling point in the serial data bit according to the received phase-shifted synchronous clock, and transmits the calculation result to the sampling point determination submodule; The sampling point judgment submodule judges whether the sampling point position is located at the bit center. If it is located at the bit center, it sends a signal to the synchronous clock output submodule to output the current synchronous clock. If it is not located at the bit center, it sends a feedback signal to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the bit center. The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

4. An operating method of an HDLC receiver with a function of adaptively adjusting a synchronous clock phase, applied to an HDLC receiver with a function of adaptively adjusting a synchronous clock phase as claimed in any one of claims 1 to 3, characterized in that: include: Step 1: Input the synchronous clock and serial data into the synchronous clock input module and the serial data input module respectively; Step 2: Use the phase difference calculator module to calculate the phase difference between the synchronous clock and the serial data; Step 3: Input the phase difference into the clock phase shifter module to perform phase shift operation on the synchronous clock, and input the synchronous clock and serial data after phase shift processing into the '7E' detector module; Step 4: The '7E' detector module detects the valid frame header of the serial data and uses the zero removal controller module to perform a zero removal operation on the serial data; Step 5: Input the serial data after the zero removal operation into the serial-to-parallel converter module and the CRC checker module respectively; Step 6: The serial-to-parallel converter module converts the serial data after the zero removal operation into parallel data, and inputs the parallel data into the address reader module to detect whether the current data is a valid frame. When it is a valid frame, the receiving data encoder module reads the parallel data from the serial-to-parallel converter module and stores it in the receiving buffer module, and updates the status register module; Step 7: The CRC checker module reads the serial data after the zero removal operation in real time, and sends the reading result to the status register module through the receiving data encoder module at the end of the frame.

5. The operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 4, characterized in that: Step 2 specifically includes: Step 2.1: Perform an XOR operation on the input synchronous clock and serial data through the XOR operation submodule to obtain an xordata signal; Step 2.2: The xor data signal after the XOR operation is measured by the phase difference positive and negative judgment submodule to obtain the high level duration T1 of the data rising edge, the high level duration T2 of the data falling edge, and the high level duration T3 of the clock cycle. If the synchronous clocks corresponding to T1 and T2 are low, the phase difference is judged to be positive; if the synchronous clocks corresponding to T1 and T2 are high, the phase difference is judged to be negative. Step 2.3: According to the phase difference positive and negative judgment result, the duty cycle is calculated using the duty cycle calculation submodule. If the phase difference positive and negative judgment result is positive, the duty cycle is calculated using the T1 time. If the phase difference positive and negative judgment result is negative, the duty cycle is calculated using the T2+T3 time. The duty cycle calculation formula is: Duty cycle = high level time / period; Step 2.4: Input the duty cycle calculation result into the phase difference calculation submodule to calculate the phase difference θ between the synchronous clock and the serial data.

6. The operating method of the HDLC receiver with the function of adaptively adjusting the synchronous clock phase according to claim 4, characterized in that: Step 3 specifically includes: Step 3.1: Input the phase difference θ into the phase difference input submodule, and transmit it to the phase difference judgment submodule; Step 3.2: The phase difference judgment submodule compares the received phase difference θ with the pre-stored phase difference threshold. If the phase difference is greater than the threshold, a trigger signal is sent to the clock delay time calculation submodule. If the phase difference is not greater than the threshold, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. Step 3.3: After receiving the trigger signal, the clock delay time calculation submodule calculates the delay time of the clock according to the phase difference θ and the synchronous clock frequency f, wherein the calculation formula of the delay time is t=θ / (2πf); Step 3.4: Input the delay time into the synchronous clock phase shift submodule, and adjust the phase by delaying the synchronous clock by a corresponding time on the time axis to ensure that the phase of the synchronous clock is consistent with the phase of the serial data; Step 3.5: Input the phase-shifted synchronous clock into the edge detection and sampling point calculation submodule. When the rising edge / falling edge of the synchronous clock is detected, the position of the sampling point in the data bit is calculated according to the clock cycle and the serial data bit cycle. Step 3.6: The sampling point judgment submodule compares the sampling point position with the center position of the data bit. If the sampling point is located at the center of the bit, a signal is sent to the synchronous clock output submodule to output the current synchronous clock. If the sampling point is not located at the center of the bit, a feedback signal is sent to the phase difference calculator module to reacquire the phase difference data and calculate until the sampling point position is located at the center of the bit. Step 3.7: The synchronous clock output submodule transmits the corresponding synchronous clock to the '7E' detector module according to the received signal.

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