CIS device and manufacturing method thereof
By forming two epitaxial layers on the substrate of the CIS device and forming an annular deep well area, the forward bias of the PN junction is controlled by voltage, the dark current problem in the CIS device is solved and the image quality is improved.
Patent Information
- Application Number
- CN202510211282.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-16
AI Technical Summary
The dark current problem in CIS devices is serious, affecting the image quality, especially when the light is weak, resulting in the appearance of white pixels.
By forming two epitaxial layers on the substrate, a deep well region is formed electrically connected to the bottom epitaxial layer, and a voltage is applied on the second epitaxial layer and the deep well region before each exposure, so that the PN junction formed by the deep well region, the first epitaxial layer and the second epitaxial layer is positively biased to extract holes and metal ions.
Lower dark current and improve image quality of CIS devices in dark light.
Smart Images
Figure CN120018607A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a CIS device and a method for manufacturing the same. Background Art
[0002] Among image sensors, complementary metal oxide semiconductor image sensor (CIS) devices are image sensors made using CMOS devices. Due to their advantages such as high integration, low power supply voltage and low technical threshold, they are widely used in photography, security systems, smart portable phones, medical electronics and other fields.
[0003] refer to Figure 1 , which shows a cross-sectional schematic diagram of a CIS device provided in the related art, for example, Figure 1 As shown, an epitaxial layer 111 is formed on a substrate 110, and a photodiode (PD) is formed in the epitaxial layer 111, which includes a depletion region 112, well regions 1131 and 1132 formed on both sides of the depletion region 112, and a floating diffusion region (FD) 114 formed in the depletion region 112. A transfer transistor (TX) 120 is formed on the epitaxial layer 111. In order to reduce the influence of defects at the interface between the epitaxial layer 111 and the dielectric layer on the photodiode, ion implantation is usually performed on the surface of the photodiode to form inversion layers 1151 and 1152.
[0004] For CIS devices, the dark current problem will seriously affect their reliability. In the case of weak light, the dark current will affect the image quality, which is manifested as white pixels (WP) on the image. Among them, the dark current mainly comes from two aspects: on the one hand, it comes from the defects at the interface between the silicon surface and the dielectric layer and the metal impurities introduced during the manufacturing process, and on the other hand, it comes from the intrinsic defects in the substrate. In view of this, it is urgent to improve the CIS devices in the relevant technology to reduce the impact of dark current on its performance. Summary of the invention
[0005] The present application provides a CIS device and a method for manufacturing the same, which can solve the serious dark current problem of the CIS device provided in the related art.
[0006] On the one hand, an embodiment of the present application provides a CIS device, including:
[0007] substrate;
[0008] a first epitaxial layer, wherein the first epitaxial layer is formed on the substrate;
[0009] a second epitaxial layer, wherein the second epitaxial layer is formed on the first epitaxial layer, a photodiode of each pixel unit is formed in the second epitaxial layer, and a transfer transistor is formed on the photodiode;
[0010] A deep well region is also formed in the second epitaxial layer. The deep well region is in contact with the first epitaxial layer. When viewed from a top view, the deep well region is annular. The pixel unit is formed in an area surrounded by the deep well region.
[0011] In some embodiments, the impurities doped into the second epitaxial layer have a conductivity type different from that of the impurities doped into the first epitaxial layer, and the impurities doped into the deep well region have a conductivity type the same as that of the impurities doped into the first epitaxial layer.
[0012] In some embodiments, the photodiode includes a depletion region and a well region formed on both sides of the depletion region, the impurities doped in the depletion region are of a different conductivity type from the impurities doped in the first epitaxial layer, and the impurities doped in the well region are of the same conductivity type as the impurities doped in the first epitaxial layer.
[0013] In some embodiments, a floating diffusion region is further formed in the depletion region, and the impurities doped in the floating diffusion region are of a conductivity type different from that of the impurities doped in the first epitaxial layer.
[0014] On the other hand, an embodiment of the present application provides a method for manufacturing a CIS device, comprising:
[0015] forming a first epitaxial layer on a substrate;
[0016] forming a second epitaxial layer on the first epitaxial layer;
[0017] forming a deep well region in the second epitaxial layer, the deep well region being in contact with the first epitaxial layer, and the deep well region being in a ring shape when viewed from a top view;
[0018] A pixel unit is formed in the area surrounded by the deep well region. During the process of forming the pixel unit, before each exposure, a voltage is applied to the second epitaxial layer and the deep well region to forward bias the PN junction formed by the deep well region, the first epitaxial layer and the second epitaxial layer.
[0019] In some embodiments, the impurities doped into the second epitaxial layer have a conductivity type different from that of the impurities doped into the first epitaxial layer, and the impurities doped into the deep well region have a conductivity type the same as that of the impurities doped into the first epitaxial layer.
[0020] In some embodiments, in the process of applying voltages to the second epitaxial layer and the deep well region, the voltage applied to the second epitaxial layer is greater than the voltage applied to the deep well region.
[0021] The technical solution of this application has at least the following advantages:
[0022] By forming two epitaxial layers on the substrate, a deep well region is formed in the top epitaxial layer and electrically connected to the bottom epitaxial layer. In the process of forming the pixel unit, before each exposure, a voltage is applied to the second epitaxial layer and the deep well region to make the PN junction composed of the deep well region, the first epitaxial layer and the second epitaxial layer forward biased to extract holes and metal ions, thereby reducing dark current and improving the image quality of the CIS device under dark light. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1 is a cross-sectional schematic diagram of a CIS device provided in the related art;
[0025] Figure 2 is a flow chart of a method for manufacturing a CIS device provided by an exemplary embodiment of the present application;
[0026] Figures 3 to 7 It is a schematic diagram of the manufacturing process of a CIS device provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0031] refer to Figure 2 , which shows a flow chart of a method for manufacturing a CIS device provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes:
[0032] Step S1, forming a first epitaxial layer on a substrate.
[0033] refer to Figure 3 , which shows a cross-sectional schematic diagram after the first epitaxial layer is formed on the substrate. Figure 3 As shown, a first epitaxial layer 2111 may be formed on the substrate 210 by an epitaxial growth process. The impurities doped into the substrate 210 and the impurities doped into the first epitaxial layer 2111 have different conductivity types.
[0034] Step S2, forming a second epitaxial layer on the first epitaxial layer.
[0035] refer to Figure 4 , which shows a cross-sectional schematic diagram after the second epitaxial layer is formed on the first epitaxial layer. Figure 4 As shown, a second epitaxial layer 2112 may be formed on the first epitaxial layer 2111 by an epitaxial growth process. The impurities doped into the second epitaxial layer 2112 and the impurities doped into the first epitaxial layer 2111 have different conductivity types.
[0036] Step S3, forming a deep well region in the second epitaxial layer, the deep well region is in contact with the first epitaxial layer, and the deep well region is ring-shaped when viewed from a top view.
[0037] refer to Figure 5 , which shows a cross-sectional schematic diagram after a deep well region is formed in the second epitaxial layer; Figure 6 , which shows a top view schematic diagram after a deep well region is formed in the second epitaxial layer. Figure 5 and Figure 6 As shown, photoresist can be covered on the second epitaxial layer 2112, and the photoresist in the target area (the area corresponding to the deep well region 216) can be removed by exposure and development in sequence, ion implantation is performed to form a deep well region 216 in the second epitaxial layer 2112, and then the photoresist is removed.
[0038] The impurities doped into the deep well region 216 have the same conductivity type as the impurities doped into the first epitaxial layer 2111. From a top view, the deep well region 216 is annular, and the area surrounded by it forms a pixel unit. It should be noted that Figure 6 In the figure, the deep well region 216 is taken as a rectangular ring for exemplary description. In practical applications, the ring shape of the deep well region 216 can be set according to needs, for example, an elliptical ring, a bullet ring, a circular ring, etc. In the subsequent process, before each exposure, a voltage is applied to the second epitaxial layer 2112 and the deep well region 216 to make the PN junction formed by the deep well region 216, the first epitaxial layer 2111 and the second epitaxial layer 2112 forward biased to extract holes and metal ions, thereby reducing dark current and improving the image quality of the CIS device under dark light. Optionally, in the process of applying voltage to the second epitaxial layer 2112 and the deep well region 216, the voltage V2 applied to the second epitaxial layer 2112 is greater than the voltage V1 applied to the deep well region 216.
[0039] Step S4, forming a pixel unit in the area surrounded by the deep well region. In the process of forming the pixel unit, before each exposure, a voltage is applied to the second epitaxial layer and the deep well region to forward bias the PN junction formed by the deep well region, the first epitaxial layer and the second epitaxial layer.
[0040] refer to Figure 7 , which shows a cross-sectional schematic diagram after forming a pixel unit. Figure 7As shown, the pixel unit includes a photodiode and a transfer transistor 220 on the photodiode. The photodiode includes a depletion region 212 formed in the second epitaxial layer 2112 and well regions 2131 and 2132 formed on both sides of the depletion region 212. The impurities doped in the depletion region 212 are of different conductivity types from the impurities doped in the first epitaxial layer 2111. The impurities doped in the well regions 2131 and 2132 are of the same conductivity type as the impurities doped in the first epitaxial layer 2111. Optionally, a floating diffusion region 214 is also formed in the depletion region 212, and the impurities doped in the floating diffusion region 214 have a conductivity type different from that of the impurities doped in the first epitaxial layer 2111; inversion layers 2151 and 2152 are also formed on the well regions 2131 and 2132, and the impurities doped in the inversion layers 2151 and 2152 have a conductivity type different from that of the impurities doped in the first epitaxial layer 2111, and the impurity concentrations doped in the floating diffusion region 214 and the inversion layers 2151 and 2152 are greater than the impurity concentrations doped in other doping regions.
[0041] To summarize, in the embodiment of the present application, two epitaxial layers are formed on the substrate, a deep well region is formed in the top epitaxial layer and is electrically connected to the bottom epitaxial layer. In the process of forming a pixel unit, before each exposure, a voltage is applied to the second epitaxial layer and the deep well region to make the PN junction formed by the deep well region, the first epitaxial layer and the second epitaxial layer forward biased to extract holes and metal ions, thereby reducing dark current and improving the image quality of the CIS device under dark light.
[0042] refer to Figure 7 , which shows a cross-sectional schematic diagram of a CIS device provided by an exemplary embodiment of the present application, the CIS device can be Figure 2 The method provided in the embodiment is used for preparation, such as Figure 7 As shown, the device includes:
[0043] Substrate 210.
[0044] The first epitaxial layer 2111 is formed on the substrate 210 .
[0045] The second epitaxial layer 2112 is formed on the first epitaxial layer 2111 . A photodiode of each pixel unit is formed in the second epitaxial layer 2111 , and a transfer transistor 220 is formed on the photodiode.
[0046] A deep well region 216 is also formed in the second epitaxial layer 2112 . The deep well region 216 contacts the first epitaxial layer 2111 . When viewed from a top view, the deep well region 216 is annular, and the pixel unit is formed in the area surrounded by the deep well region.
[0047] The pixel unit includes a photodiode and a transfer transistor 220 on the photodiode. The photodiode includes a depletion region 212 formed in the second epitaxial layer 2112 and well regions 2131 and 2132 formed on both sides of the depletion region 212. The impurities doped in the depletion region 212 are of different conductivity types from the impurities doped in the first epitaxial layer 2111. The impurities doped in the well regions 2131 and 2132 are of the same conductivity type as the impurities doped in the first epitaxial layer 2111. Optionally, a floating diffusion region 214 is also formed in the depletion region 212, and the impurities doped in the floating diffusion region 214 have a conductivity type different from that of the impurities doped in the first epitaxial layer 2111; inversion layers 2151 and 2152 are also formed on the well regions 2131 and 2132, and the impurities doped in the inversion layers 2151 and 2152 have a conductivity type different from that of the impurities doped in the first epitaxial layer 2111, and the impurity concentrations doped in the floating diffusion region 214 and the inversion layers 2151 and 2152 are greater than the impurity concentrations doped in other doping regions.
[0048] In the embodiment of the present application, if the impurities doped into the substrate 210, the second epitaxial layer 2112, the depletion region 212 and the inversion layers 2151 and 2152 are P (positive) type impurities, then the impurities doped into the first epitaxial layer 2111, the well region 2131, the well region 2312, the deep well region 216 and the floating diffusion region 214 are N (negative) type impurities; if the impurities doped into the substrate 210, the second epitaxial layer 2112, the depletion region 212 and the inversion layers 2151 and 2152 are N type impurities, then the impurities doped into the first epitaxial layer 2111, the well region 2131, the well region 2312, the deep well region 216 and the floating diffusion region 214 are P type impurities.
[0049] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A CIS device, characterized in that: include: substrate; a first epitaxial layer, wherein the first epitaxial layer is formed on the substrate; a second epitaxial layer, wherein the second epitaxial layer is formed on the first epitaxial layer, a photodiode of each pixel unit is formed in the second epitaxial layer, and a transfer transistor is formed on the photodiode; A deep well region is also formed in the second epitaxial layer. The deep well region is in contact with the first epitaxial layer. When viewed from a top view, the deep well region is annular. The pixel unit is formed in an area surrounded by the deep well region.
2. The device according to claim 1, characterized in that The impurities doped into the second epitaxial layer have a conductivity type different from that of the impurities doped into the first epitaxial layer, and the impurities doped into the deep well region have a conductivity type the same as that of the impurities doped into the first epitaxial layer.
3. The device according to claim 2, characterized in that The photodiode includes a depletion region and well regions formed on both sides of the depletion region, the impurities doped in the depletion region are of a different conductivity type from the impurities doped in the first epitaxial layer, and the impurities doped in the well region are of the same conductivity type as the impurities doped in the first epitaxial layer.
4. The device according to claim 3, characterized in that A floating diffusion region is also formed in the depletion region. The impurities doped in the floating diffusion region are of a different conductivity type from the impurities doped in the first epitaxial layer.
5. A method for manufacturing a CIS device, characterized in that: include: forming a first epitaxial layer on a substrate; forming a second epitaxial layer on the first epitaxial layer; forming a deep well region in the second epitaxial layer, the deep well region being in contact with the first epitaxial layer, and the deep well region being in a ring shape when viewed from a top view; A pixel unit is formed in the area surrounded by the deep well region. During the process of forming the pixel unit, before each exposure, a voltage is applied to the second epitaxial layer and the deep well region to forward bias the PN junction formed by the deep well region, the first epitaxial layer and the second epitaxial layer.
6. The method according to claim 5, characterized in that The impurities doped into the second epitaxial layer have a conductivity type different from that of the impurities doped into the first epitaxial layer, and the impurities doped into the deep well region have a conductivity type the same as that of the impurities doped into the first epitaxial layer.
7. The method according to claim 6, characterized in that In the process of applying voltages to the second epitaxial layer and the deep well region, the voltage applied to the second epitaxial layer is greater than the voltage applied to the deep well region.