Chip packaging structure and chip packaging method
By shortening the distance between the photosensitive side and the substrate in the photosensitive chip package and reassigning the I/O pin position, the problem of poor imaging quality in the prior art is solved, and more efficient photoelectric conversion and better imaging quality are achieved.
Patent Information
- Application Number
- CN202510160300.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-05-16
AI Technical Summary
The imaging quality of existing photosensitive chip packages is poor, mainly because the path of light rays when entering the photosensitive side is too long, resulting in increased light reflection and absorption, which in turn affects the photoelectric conversion efficiency.
A chip package structure is designed, including a substrate, a first heavy wiring layer, a chip layer and a second heavy wiring layer. The distance between the photosensitive side and the substrate is reduced to 10 um to 20 um, the light path is reduced, and the I/O pin position is redistributed through the first heavy wiring layer to improve packaging integration and flexibility.
By shortening the path of light entering the photosensitive side, reducing the reflection and absorption of light, increasing the incident angle of light, improving the photoelectric conversion efficiency, and thus improving the imaging quality.
Smart Images
Figure CN120018625A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a chip packaging structure and a chip packaging method. Background Art
[0002] In semiconductor technology, packaging is an important part of the production and processing of semiconductor integrated circuit chips. It can not only place, fix, seal and protect the chip, but also enhance the electrical and thermal performance, and also realize the transmission of data and signals between the internal and external circuits of the chip. However, the existing photosensitive chip packaging still has problems such as poor imaging quality. Summary of the invention
[0003] In order to at least overcome the above-mentioned deficiencies in the prior art, an object of the present application is to provide a chip packaging structure and a chip packaging method.
[0004] In a first aspect, an embodiment of the present application provides a chip packaging structure, the chip packaging structure comprising:
[0005] substrate;
[0006] A first redistribution layer, wherein the first redistribution layer is located at one side of the substrate, and the first redistribution layer is located in a partial area of the substrate;
[0007] A chip layer, the chip layer is located on one side of the substrate, the chip layer includes at least one photosensitive chip and a conductive trace penetrating the chip side and located around the chip, the photosensitive chip includes a photosensitive side and an electrode pin on the same side as the photosensitive side, the photosensitive side faces the substrate, and the electrode pin is electrically connected to the first redistribution layer;
[0008] a second redistribution layer, the second redistribution layer being located at a side of the chip layer away from the substrate, the second redistribution layer being electrically connected to the conductive trace;
[0009] Wherein, in a direction perpendicular to the plane where the substrate is located, the distance between the photosensitive side and the substrate is 10um to 20um.
[0010] In a possible implementation, the photosensitive side includes a photosensitive area, and the electrode pin is located outside the photosensitive area;
[0011] An orthographic projection of the photosensitive region on the substrate does not overlap with an orthographic projection of the first redistribution layer on the substrate.
[0012] In a possible implementation, the chip layer also includes a packaging layer located around the chip and on a side of the chip away from the substrate, and the packaging layer is provided with routing through holes that penetrate the packaging layer, wherein the conductive wiring is located in the routing through holes.
[0013] In a possible implementation manner, an orthographic projection of the routing through hole on the substrate does not overlap with an orthographic projection of the chip on the substrate, and the routing through hole is perpendicular to a plane where the substrate is located.
[0014] In a possible implementation, the chip packaging structure further includes a conductive ball, the conductive ball is located on a side of the second redistribution layer away from the chip, and the conductive ball is connected to a trace in the second redistribution layer.
[0015] In a second aspect, an embodiment of the present application further provides a chip packaging method, the method comprising:
[0016] A carrier board is provided, and a chip layer including at least one photosensitive chip is manufactured on one side of the carrier board, wherein the photosensitive chip includes a photosensitive side and an electrode pin on the same side as the photosensitive side, and the photosensitive side faces the carrier board;
[0017] The carrier board is removed, and a first redistribution layer electrically connected to the electrode pin is formed on the photosensitive side, wherein the orthographic projection of the first redistribution layer on the carrier board partially overlaps with the orthographic projection of the photosensitive chip on the carrier board;
[0018] Providing a substrate, and bonding the substrate to a side of the first redistribution wiring away from the chip layer, wherein the distance between the photosensitive side and the substrate in a direction perpendicular to the plane where the substrate is located is 10 um to 20 um;
[0019] Fabricating conductive traces on the chip layer, which are located around the chip and are electrically connected to the first redistribution layer;
[0020] A second redistribution layer electrically connected to the conductive trace is fabricated on a side of the chip layer away from the first redistribution layer.
[0021] In a possible implementation, the step of providing a carrier board and manufacturing a chip layer including at least one photosensitive chip on one side of the carrier board includes:
[0022] Providing a carrier board, making a bonding layer on one side of the carrier board, placing at least one chip on a side of the bonding layer away from the carrier board, wherein the chip includes a photosensitive chip;
[0023] The carrier board on which the chip is placed is packaged, and a plastic sealing layer is formed on the peripheral side of the chip and on a side away from the carrier board to obtain the chip layer.
[0024] In a possible implementation, the step 200 of manufacturing on the chip layer a conductive trace located on the periphery of the chip and electrically connected to the first redistribution layer includes:
[0025] Performing patterning on the chip layer to form a wiring through hole penetrating the plastic packaging layer, wherein the orthographic projection of the wiring through hole on the substrate does not overlap with the orthographic projection of the chip on the substrate;
[0026] Metal sputtering is performed on the chip layer where the wiring through hole is made to form a conductive wiring located in the wiring through hole, and the conductive wiring is electrically connected to the first redistribution layer.
[0027] In a possible implementation, after the step of forming a second redistribution layer electrically connected to the conductive trace on a side of the chip layer away from the first redistribution layer, the method further includes:
[0028] A ball placement process is performed on a side of the second redistribution layer away from the chip layer to obtain a conductive ball electrically connected to the second redistribution layer, and the conductive ball is electrically connected to the first redistribution layer through a wiring in the second redistribution layer.
[0029] In a possible implementation, when there are multiple chips, after performing ball placement processing on a side of the second redistribution layer away from the chip layer to obtain conductive balls electrically connected to the second redistribution layer, the method further includes:
[0030] The packaging structure including a plurality of the chips is cut to obtain a chip packaging structure including at least one photosensitive chip.
[0031] Based on any of the above aspects, the chip packaging structure and chip packaging method provided in the embodiments of the present application include a substrate, a first redistribution layer, a chip layer and a second redistribution layer, wherein the first redistribution layer is located on one side of the substrate, and the first redistribution layer is located in a partial area of the substrate. The chip layer is located on one side of the substrate, and the chip layer may include multiple chips (for example, photosensitive chips, etc.), and the multiple chips may reallocate I / O pin positions through the first redistribution layer to better adapt to different packaging requirements and improve packaging integration and flexibility. In addition, the distance between the photosensitive side and the substrate is reduced to 10um to 20um, which will significantly reduce the path of light when entering the photosensitive side, reduce the reflection and absorption of light, thereby increasing the incident angle of light, improving the photoelectric conversion efficiency, and improving the imaging quality. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0033] Figure 1 It is a schematic diagram of a packaging structure in the related art;
[0034] Figure 2 A schematic diagram of a chip packaging structure provided in this application Figure 1 ;
[0035] Figure 3 A schematic diagram of a chip packaging structure provided in this application Figure 2 ;
[0036] Figure 4 A step flow chart of the chip packaging method provided in this application;
[0037] Figure 5 for Figure 4 Corresponding process diagram. DETAILED DESCRIPTION
[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0039] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0040] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.
[0041] In the description of this application, it should be noted that the terms "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.
[0042] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed", "connected", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0043] It should be noted that, in the absence of conflict, different features in the embodiments of the present application may be combined with each other.
[0044] The inventor found that in the relevant chip packaging technology, please refer to Figure 1 , its packaging structure generally includes a substrate 100, a protection cavity 600, a chip 700 and a redistribution layer 800, wherein the chip 700 is a photosensitive chip. The protection cavity 600 is located on one side of the substrate 100, the chip 700 is located on the side of the protection cavity 600 away from the substrate 100, and the redistribution layer 800 is located on the side of the chip 700 away from the substrate 100, wherein the chip 700 includes a photosensitive area facing the substrate 100 and an opening penetrating the chip 700, and the wiring in the redistribution layer 800 is electrically connected to the electrode pin 312 of the chip 700 via the opening. However, in the above structure, in order to enable the protective cavity 600 to better protect the chip 700, the height of the protective cavity 600 is usually 30um to 40um, that is, the distance between the photosensitive area and the substrate 100 is greater than 30um to 40um. The light needs to pass through the substrate 100 and the protective cavity 600 before it can reach the photosensitive area of the chip 700. This will greatly limit the incident angle of the light, causing the light to be refracted or reflected when entering the photosensitive area of the chip 700, affecting the imaging quality. In addition, the protective cavity 600 is usually made of organic materials. Since it does not have a rewiring function, the relevant technology can often only integrate one chip 700, and cannot achieve multi-chip integration, and the integration is not high.
[0045] To solve the problems in the prior art, please refer to Figure 2. An embodiment of the present application provides a chip packaging structure 10, which includes a substrate 100, a first redistribution layer 200, a chip layer 300 and a second redistribution layer 400, wherein the material of the substrate 100 includes but is not limited to transparent materials such as glass and resin. Preferably, the material of the substrate 100 is glass.
[0046] The first redistribution layer 200 is located on one side of the substrate 100, and the first redistribution layer 200 is located in a partial area of the substrate 100. The chip layer 300 is located on one side of the substrate 100, and the chip layer 300 may include at least one photosensitive chip 310 and a conductive trace 320 that penetrates the chip layer 300 and is located on the peripheral side of the chip, wherein the conductive trace 320 is electrically connected to the trace in the first redistribution layer 200, and the photosensitive chip 310 includes a photosensitive side 311 and an electrode pin 312 on the same side as the photosensitive side 311, the photosensitive side 311 faces the substrate 100, and the electrode pin 312 is electrically connected to the first redistribution layer 200. It is not difficult to understand that the chip layer 300 may include multiple chips, and the I / O pin positions of the multiple chips may be reallocated through the first redistribution layer 200 to better adapt to different packaging requirements and improve packaging integration and flexibility.
[0047] The second redistribution layer 400 is located on the side of the chip layer 300 away from the substrate 100, and the wiring in the second redistribution layer 400 is connected to the conductive wiring 320. In the direction perpendicular to the plane where the substrate 100 is located, the distance between the photosensitive side 311 and the substrate 100 is 10um to 20um. Compared with the related art, the path of light entering the photosensitive area can be reduced, and the reflection and absorption of light can be reduced, thereby increasing the incident angle of light, improving the photoelectric conversion efficiency, and thus improving the imaging quality.
[0048] In the above structure, the chip layer 300 may include multiple chips (for example, a photosensitive chip 310), and the I / O pin positions of the multiple chips may be reallocated through the first redistribution layer 200 to better adapt to different packaging requirements and improve packaging integration and flexibility. In addition, the distance between the photosensitive side 311 and the substrate 100 is reduced to 10um to 20um, which will significantly reduce the path of light when entering the photosensitive side 311, reduce the reflection and absorption of light, thereby increasing the incident angle of light, improving the photoelectric conversion efficiency, and improving the imaging quality.
[0049] Further, please refer again to Figure 2, the photosensitive side 311 includes a photosensitive area, the electrode pin 312 is located outside the photosensitive area, and the orthographic projection of the photosensitive area on the substrate 100 does not overlap with the orthographic projection of the first redistribution layer 200 on the substrate 100. In this way, the shielding of the photosensitive area by the electrode pin 312 and the first redistribution layer 200 can be reduced, so that more light can be incident on the photosensitive area, thereby improving the incident angle of light and the photoelectric conversion efficiency.
[0050] It should be noted that the first redistribution layer 200 may include multiple stacked redistribution sub-layers, which may be formed by routing and an insulating layer located around the routing. In order to allow more light to be incident on the photosensitive area and increase the incident angle of light, the insulating layer may be made of transparent insulating material.
[0051] The chip layer 300 also includes a packaging layer 330 located on the peripheral side of the chip and on the side of the chip away from the substrate 100. The packaging layer 330 is provided with a wiring through hole that penetrates the packaging layer 330, and the conductive wiring 320 is located in the wiring through hole. In order to prevent damage to the chip during the hole opening process, the orthographic projection of the wiring through hole on the substrate 100 does not overlap with the orthographic projection of the chip on the substrate 100, and the wiring through hole can be perpendicular to the plane where the substrate 100 is located, shortening the signal transmission path and improving the response rate.
[0052] For further information, please refer to Figure 3 The chip packaging structure 10 also includes a conductive ball 500, which is located on a side of the second redistribution layer 400 away from the chip. The conductive ball 500 is connected to the wiring in the second redistribution layer 400. The chip packaging structure 10 can be welded to other electronic devices through the conductive ball 500.
[0053] Based on the same inventive concept, the present application also provides a chip packaging method, for details, please refer to Figure 4 and Figure 5 , Figure 4 FIG. 1 is a flow chart of a chip packaging method. Figure 5 for Figure 4 The corresponding process diagram. Figure 4 and Figure 5 Each step of the chip packaging method is described in detail.
[0054] Step S110: providing a carrier board, and manufacturing a chip layer including at least one photosensitive chip on one side of the carrier board.
[0055] In this step, a carrier 101 made of a material such as resin or glass may be provided first, and then a bonding layer 102 may be made on one side of the carrier 101 using a thermal stripping and / or laser stripping material, and at least one chip may be placed on the side of the bonding layer 102 away from the carrier 101, and the chip includes a photosensitive chip 310. The photosensitive chip 310 includes a photosensitive side 311 and an electrode pin 312 on the same side as the photosensitive side 311, and the photosensitive side 311 faces the carrier 101. Finally, the carrier 101 with the chip placed is placed in a plastic encapsulation mold, and is encapsulated to form a plastic encapsulation layer on the peripheral side of the chip and on the side away from the carrier 101, thereby obtaining a chip layer 300.
[0056] It should be noted that, in other embodiments, the plastic packaging layer may be ground until the side of the chip facing away from the carrier is exposed, so as to ensure good heat dissipation performance of the chip.
[0057] Step S120: removing the carrier board and making a first redistribution layer electrically connected to the electrode pins on the photosensitive side.
[0058] In this step, the carrier 101 can be separated from the chip layer 300 by removing the bonding layer, and then a first redistribution layer 200 electrically connected to the electrode pin 312 is made on the photosensitive side 311, wherein the carrier 101 can be separated from the chip layer 300 by thermal debonding or laser debonding, and the orthographic projection of the first redistribution layer 200 on the chip layer 300 is located in a partial area of the chip.
[0059] Step S130: providing a substrate, and bonding the substrate to a side of the first redistribution layer away from the chip layer.
[0060] In this step, in the direction perpendicular to the plane of the substrate 100, the distance between the photosensitive side 311 and the substrate 100 is 10um to 20um. The material of the substrate 100 includes but is not limited to transparent materials such as glass and resin. Preferably, the material of the substrate 100 can be glass.
[0061] Step S140: fabricating conductive traces on the chip layer, which are located around the chip and electrically connected to the first redistribution layer.
[0062] In this step, the chip layer 300 can be patterned to make a wiring through hole that penetrates the plastic packaging layer, wherein the orthographic projection of the wiring through hole on the substrate 100 does not overlap with the orthographic projection of the chip on the substrate 100, and in order to shorten the signal transmission path and improve the response rate, the wiring through hole can be perpendicular to the plane where the substrate 100 is located. Finally, the chip layer 300 with the wiring through hole is metal sputtered to form a conductive trace 320 located in the wiring through hole, and the conductive trace 320 is electrically connected to the first redistribution layer 200.
[0063] Step S150: fabricating a second redistribution layer electrically connected to the conductive traces on a side of the chip layer away from the first redistribution layer.
[0064] In this step, the wiring in the second redistribution layer 400 is electrically connected to the conductive wiring 320 , and is electrically connected to the first redistribution layer 200 through the conductive wiring 320 .
[0065] In this embodiment, a chip layer 300 including multiple chips is first manufactured, and then the multiple chips are rewired through the first redistribution layer 200, so that the chip packaging structure 10 can better adapt to different packaging requirements and improve the packaging integration and flexibility. In addition, reducing the distance between the photosensitive side 311 and the substrate 100 to 10um to 20um can effectively reduce the path of light when entering the photosensitive side 311, reduce the reflection and absorption of light, thereby increasing the incident angle of light, improving the photoelectric conversion efficiency, and improving the imaging quality.
[0066] Furthermore, after step S150, a ball placement process may be performed on the side of the second redistribution layer 400 away from the chip layer 300 to obtain a conductive ball 500 electrically connected to the second redistribution layer 400. Specifically, the prefabricated conductive ball 500 may be transferred to the pad on the side of the second redistribution layer 400 away from the chip layer 300, so that the conductive ball 500 is electrically connected to the first redistribution layer 200 through the routing in the second redistribution layer 400. The conductive ball 500 can play a role of adhesion and diffusion when the chip packaging structure 10 is welded with other electronic devices.
[0067] In addition, when there are multiple chips, the packaging structure including the multiple chips can also be cut to obtain a chip packaging structure 10 including at least one photosensitive chip 310.
[0068] In summary, the embodiments of the present application provide a chip packaging structure and a chip packaging method, wherein the chip packaging structure includes a substrate, a first redistribution layer, a chip layer and a second redistribution layer, wherein the first redistribution layer is located on one side of the substrate, and the first redistribution layer is located in a partial area of the substrate. The chip layer is located on one side of the substrate, and the chip layer may include multiple chips (for example, photosensitive chips, etc.), and the multiple chips may reallocate I / O pin positions through the first redistribution layer to better adapt to different packaging requirements and improve packaging integration and flexibility. In addition, the distance between the photosensitive side and the substrate is reduced to 10um to 20um, which will significantly reduce the path of light when entering the photosensitive side, reduce the reflection and absorption of light, thereby increasing the incident angle of light, improving the photoelectric conversion efficiency, and improving the imaging quality.
[0069] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A chip packaging structure, characterized in that: include: substrate; A first redistribution layer, wherein the first redistribution layer is located at one side of the substrate, and the first redistribution layer is located in a partial area of the substrate; A chip layer, the chip layer is located on one side of the substrate, the chip layer includes at least one photosensitive chip and a conductive trace penetrating the chip layer and located around the chip, wherein the conductive trace is electrically connected to the first redistribution layer, the photosensitive chip includes a photosensitive side and an electrode pin on the same side as the photosensitive side, the photosensitive side faces the substrate, and the electrode pin is electrically connected to the first redistribution layer; a second redistribution layer, the second redistribution layer being located at a side of the chip layer away from the substrate, the second redistribution layer being electrically connected to the conductive trace; Wherein, in a direction perpendicular to the plane where the substrate is located, the distance between the photosensitive side and the substrate is 10um to 20um.
2. The chip packaging structure according to claim 1, characterized in that: The photosensitive side includes a photosensitive area, and the electrode pin is located outside the photosensitive area; An orthographic projection of the photosensitive region on the substrate does not overlap with an orthographic projection of the first redistribution layer on the substrate.
3. The chip packaging structure according to claim 1, characterized in that: The chip layer also includes a packaging layer located on the peripheral side of the chip and on the side of the chip away from the substrate, and the packaging layer is provided with a routing through hole penetrating the packaging layer, wherein the conductive wiring is located in the routing through hole.
4. The chip packaging structure according to claim 3, characterized in that: The orthographic projection of the wiring through hole on the substrate does not overlap with the orthographic projection of the chip on the substrate, and the wiring through hole is perpendicular to the plane where the substrate is located.
5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a conductive ball, which is located on a side of the second redistribution layer away from the chip, and is connected to a wiring in the second redistribution layer.
6. A chip packaging method, characterized in that: The method comprises: A carrier board is provided, and a chip layer including at least one photosensitive chip is manufactured on one side of the carrier board, wherein the photosensitive chip includes a photosensitive side and an electrode pin on the same side as the photosensitive side, and the photosensitive side faces the carrier board; The carrier board is removed, and a first redistribution layer electrically connected to the electrode pin is formed on the photosensitive side, wherein the orthographic projection of the first redistribution layer on the carrier board partially overlaps with the orthographic projection of the photosensitive chip on the carrier board; Providing a substrate, and bonding the substrate to a side of the first redistribution wiring away from the chip layer, wherein the distance between the photosensitive side and the substrate in a direction perpendicular to the plane where the substrate is located is 10 um to 20 um; Fabricating conductive traces on the chip layer, which are located around the chip and are electrically connected to the first redistribution layer; A second redistribution layer electrically connected to the conductive trace is fabricated on a side of the chip layer away from the first redistribution layer.
7. The chip packaging method according to claim 6, characterized in that: The step of providing a carrier board and manufacturing a chip layer including at least one photosensitive chip on one side of the carrier board comprises: Providing a carrier board, making a bonding layer on one side of the carrier board, placing at least one chip on a side of the bonding layer away from the carrier board, wherein the chip includes a photosensitive chip; The carrier board on which the chip is placed is packaged, and a plastic sealing layer is formed on the peripheral side of the chip and on a side away from the carrier board to obtain the chip layer.
8. The chip packaging method according to claim 7, characterized in that: The step of making a conductive trace on the chip layer that is located around the chip and electrically connected to the first redistribution layer includes: Performing patterning on the chip layer to form a wiring through hole penetrating the plastic packaging layer, wherein the orthographic projection of the wiring through hole on the substrate does not overlap with the orthographic projection of the chip on the substrate; Metal sputtering is performed on the chip layer where the wiring through hole is made to form a conductive wiring located in the wiring through hole, and the conductive wiring is electrically connected to the first redistribution layer.
9. The chip packaging method according to claim 6, characterized in that: After the step of manufacturing a second redistribution layer electrically connected to the conductive trace on a side of the chip layer away from the first redistribution layer, the method further comprises: A ball placement process is performed on a side of the second redistribution layer away from the chip layer to obtain a conductive ball electrically connected to the second redistribution layer, and the conductive ball is electrically connected to the first redistribution layer through a wiring in the second redistribution layer.
10. The chip packaging method according to claim 9, characterized in that: When there are multiple chips, after performing ball placement processing on a side of the second redistribution layer away from the chip layer to obtain conductive balls electrically connected to the second redistribution layer, the method further includes: The packaging structure including a plurality of the chips is cut to obtain a chip packaging structure including at least one photosensitive chip.