Quantum circuit optimization method and device and medium

Abstract

The invention discloses a quantum circuit optimization method and device and a medium, and the method comprises the steps: firstly obtaining an initial quantum logic gate in a to-be-optimized quantum circuit, converting the initial quantum logic gate into a basic quantum logic gate, then traversing the basic quantum logic gate, sequentially judging whether each basic quantum logic gate accords with an optimization condition or not, and if yes, determining that the basic quantum logic gate meets the optimization condition; and finally, in response to the condition that a plurality of basic quantum logic gates in the basic quantum logic gates meet the optimization condition, generating a target quantum circuit which is equivalent to the to-be-optimized quantum circuit and supports operation of the quantum chip, and by setting the optimization condition, obtaining the quantum circuit meeting the optimization condition and executing optimization operation. The number of quantum logic gates in the quantum circuit is reduced, the depth of the optimized quantum circuit is smaller, and a basis is provided for improving the calculation efficiency of the quantum circuit on a quantum chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of quantum computing, and particularly relates to an optimization method, device, and medium for quantum circuits. Background Art

[0002] A quantum computer is a physical device that follows the laws of quantum mechanics to perform high-speed mathematical and logical operations, store, and process quantum information. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Due to its relatively more efficient ability to process mathematical problems compared to ordinary computers, for example, it can accelerate the time to crack RSA keys from hundreds of years to a few hours, quantum computers have become a key technology under research.

[0003] Due to hardware limitations, current quantum chips can only run some basic and specific quantum logic gates. Therefore, it is necessary to compile and optimize quantum circuits so that the compiled quantum circuits can run on quantum chips. However, there are often some redundant circuits in the compiled quantum circuits, which affects the operating efficiency of the quantum circuits. How to solve the above problems has become an important research content at present. Summary of the Invention

[0004] The purpose of the present invention is to provide an optimization method, device, and medium for quantum circuits to solve the deficiencies in the prior art. By setting optimization conditions, a quantum circuit that meets the optimization conditions is obtained and an optimization operation is performed, so as to reduce the number of quantum logic gates in the quantum circuit, make the depth of the optimized quantum circuit smaller, and provide a basis for improving the computing efficiency of the quantum circuit on the quantum chip.

[0005] An embodiment of the present application provides an optimization method for a quantum circuit, and the method includes:

[0006] Obtain the initial quantum logic gates in the quantum circuit to be optimized, and convert the initial quantum logic gates into basic quantum logic gates, where the basic quantum logic gates include: CZ gates, RX gates, and RZ gates;

[0007] Traverse the basic quantum logic gates, and sequentially determine whether each basic quantum logic gate meets the optimization conditions; where the optimization conditions include replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate;

[0008] In response to multiple basic quantum logic gates in the basic quantum logic gates meeting the optimization conditions, generate a target quantum circuit that is equivalent to the quantum circuit to be optimized and supported by the quantum chip for operation, where the depth of the target quantum circuit is smaller.

[0009] Optionally, obtaining the initial quantum logic gates in the quantum circuit to be optimized and converting the initial quantum logic gates into basic quantum logic gates includes:

[0010] Obtaining the quantum logic gates that the quantum chip does not support direct operation in the quantum circuit to be optimized as the initial quantum logic gates;

[0011] Equivalently converting the initial quantum logic gates into target U3 gates and CNOT gates;

[0012] Converting the target U3 gates into the RX gates and the RZ gates; and converting the CNOT gates into the CZ gates supported by the quantum chip.

[0013] Optionally, before traversing the basic quantum logic gates and sequentially determining whether each basic quantum logic gate meets the optimization conditions, the method further includes:

[0014] Querying all the RZ gates in the basic logic gates, adjusting all the RZ gates to the last-layer timing of the quantum circuit to be optimized, and merging all the RZ gates at the last-layer timing.

[0015] Optionally, querying all the RZ gates in the basic logic gates and adjusting all the RZ gates to the last-layer timing of the quantum circuit to be optimized includes:

[0016] Obtaining one of the RZ gates and obtaining the quantum logic gate at the next timing of the RZ gate as the adjacent quantum logic gate;

[0017] If the adjacent quantum logic gate is the CZ gate, then adjusting the RZ gate after the CZ gate.

[0018] Optionally, after obtaining one of the RZ gates and obtaining the quantum logic gate at the next timing of the RZ gate as the adjacent quantum logic gate, the method further includes:

[0019] If the adjacent quantum logic gate is the RX gate, then adjusting the RZ gate after the RX gate and converting the RX gate into a specific quantum logic gate; wherein, the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate, and the specific quantum logic gate includes the RPhi gate, and the RPhi gate is used to rotate the quantum state by an arbitrary rotation axis in the XY-axis plane by an angle.

[0020] Optionally, if there are two adjacent specific quantum logic gates with an angular parameter of π in the quantum circuit to be optimized, a merging operation is directly performed.

[0021] Another embodiment of the present application provides an optimization device for a quantum circuit, the device comprising:

[0022] An acquisition module, configured to acquire an initial quantum logic gate in a quantum circuit to be optimized, and convert the initial quantum logic gate into a basic quantum logic gate, where the basic quantum logic gate includes: a CZ gate, an RX gate, and an RZ gate;

[0023] A traversal module, configured to traverse the basic quantum logic gates, and sequentially determine whether each of the basic quantum logic gates meets the optimization condition; where the optimization condition includes replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate;

[0024] A generation module, configured to generate a target quantum circuit that is equivalent to the quantum circuit to be optimized and supported by a quantum chip for operation, where the depth of the target quantum circuit is smaller, in response to the existence of multiple basic quantum logic gates in the basic quantum logic gates that meet the optimization condition.

[0025] Optionally, the acquisition module includes:

[0026] A first acquisition unit, configured to acquire a quantum logic gate that is not directly supported by the quantum chip in the quantum circuit to be optimized as the initial quantum logic gate;

[0027] A first conversion unit, configured to equivalently convert the initial quantum logic gate into a target U3 gate and a CNOT gate;

[0028] A second conversion unit, configured to convert the target U3 gate into the RX gate and the RZ gate; and convert the CNOT gate into the CZ gate supported by the quantum chip.

[0029] Optionally, before the traversal module, the device further includes:

[0030] A query module, configured to query all the RZ gates in the basic logic gates, adjust all the RZ gates to the last layer timing of the quantum circuit to be optimized, and merge all the RZ gates at the last layer timing.

[0031] Optionally, the query module includes:

[0032] A second acquisition unit, configured to acquire one of the RZ gates, and acquire the quantum logic gate at the next timing of the RZ gate as an adjacent quantum logic gate;

[0033] A first adjustment unit, configured to, if the adjacent quantum logic gate is the CZ gate, adjust the RZ gate after the CZ gate.

[0034] Optionally, the query module further includes:

[0035] A second adjustment unit, configured to, if the adjacent quantum logic gate is the RX gate, adjust the RZ gate after the RX gate and convert the RX gate into a specific quantum logic gate; wherein, the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate, and the specific quantum logic gate includes an RPhi gate, and the RPhi gate is used to rotate the quantum state by an angle around an arbitrary rotation axis in the XY-axis plane.

[0036] An embodiment of the present application provides a quantum computer operating system, which optimizes quantum circuits by using the optimization method described in any one of the above.

[0037] An embodiment of the present application provides a storage medium, in which a computer program is stored, and wherein the computer program is configured to execute the method described in any one of the above when running.

[0038] An embodiment of the present application provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of the above.

[0039] Compared with the prior art, the present invention first obtains the initial quantum logic gates in the quantum circuit to be optimized and converts the initial quantum logic gates into basic quantum logic gates, then traverses the basic quantum logic gates, sequentially determines whether each basic quantum logic gate meets the optimization conditions, and finally, in response to multiple basic quantum logic gates in the basic quantum logic gates meeting the optimization conditions, generates a target quantum circuit equivalent to the quantum circuit to be optimized and supported by the quantum chip to run. By setting the optimization conditions, a quantum circuit that meets the optimization conditions is obtained and an optimization operation is performed, so as to reduce the number of quantum logic gates in the quantum circuit, make the depth of the optimized quantum circuit smaller, and provide a basis for improving the computing efficiency of the quantum circuit on the quantum chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a system network block diagram of an optimization method for a quantum circuit provided by an embodiment of the present invention;

[0041] Figure 2 is a flowchart of an optimization method for a quantum circuit provided by an embodiment of the present invention;

[0042] Figure 3 is a structural diagram of an optimization device for a quantum circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0044] The embodiments of the present invention first provide an optimization method for quantum circuits, which can be applied to electronic devices, such as computer terminals, specifically, ordinary computers, quantum computers, etc.

[0045] The following takes the operation on a computer terminal as an example to illustrate it in detail. Figure 1 It is a system network block diagram of an optimization method for quantum circuits provided by the embodiments of the present invention. The system applied to the quantum circuit optimization method may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0046] The network 110 is a medium that provides a communication link between various devices and computers connected together within the system network applied to the quantum circuit optimization method, including but not limited to the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can adopt wired, wireless communication links, or fiber optic cables, etc.

[0047] The server 120 and the client 140 are conventional data processing systems, which may contain data and application programs or software tools for performing conventional computing processes. The client 140 can be a personal computer or a network computer, so the data can also be provided by the server 120. The wireless device 130 can be a smart phone, a tablet, a laptop computer, a smart wearable device, etc. The storage unit 150 may include a database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0048] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) can be a boot file, an operating system image, and an application program 162 (application program 173). The application program 162 (application program 173) can be used to implement a quantum algorithm compiled according to the optimization method for quantum circuits provided by the embodiments of the present invention.

[0049] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner. Similarly, any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0050] It should be noted that a real quantum computer has a hybrid structure and it includes at least Figure 1 two major parts: a classical processing system 160, responsible for performing classical computing and control; and a quantum processing system 170, responsible for running quantum programs to implement quantum computing.

[0051] The above-mentioned classical processing system 160 and quantum processing system 170 can be integrated in one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, and storage and network services required for quantum applications are also provided. Users develop quantum applications through the quantum application development tools and services on it, and send quantum programs to the second device including the quantum processing system 170 through the network services on it. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0052] In the classical processing system 160 based on a silicon chip, the unit of the classical processor 161 is a CMOS transistor. Such a computing unit is not restricted by time and coherence, that is, such a computing unit is not restricted by the usage duration and is available at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. Currently, the number of computing units in a classical processor is in the thousands. The sufficient number of computing units and the fixed computing logic that can be selected by the CMOS transistor, for example: AND logic. When operating with CMOS transistors, a large number of CMOS transistors are combined with limited logic functions to achieve the operation effect.

[0053] Different from such logic units in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a qubit. The input of a qubit is restricted by coherence and also by the coherence time, that is, a qubit is restricted by the usage duration and is not available at any time. Making full use of qubits within their available usage duration is a key problem in quantum computing. In addition, the number of qubits in a quantum computer is one of the representative indicators of the performance of the quantum computer. Each qubit realizes its computing function through logic functions configured on demand. Given the limited number of qubits, and the logic functions in the field of quantum computing are diverse, for example: Hadamard gate (H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, and so on. During quantum computing, it is necessary to combine a limited number of qubits with diverse logic functions to achieve the operation effect.

[0054] Based on these differences, the design of the action of logic functions on qubits (including the design of whether to use qubits and the design of the usage efficiency of each qubit) is the key to improving the operation performance of a quantum computer and requires special design. And the above design for qubits is a technical problem that ordinary computing devices do not need to consider and do not need to face. Due to the limitation of hardware conditions in this application, the current quantum chips can only run some basic and specific quantum logic gates. Therefore, it is necessary to compile and optimize the quantum circuit so that the compiled quantum circuit can run on the quantum chip. However, there are often some redundant circuits in the compiled quantum circuit, which affects the operation efficiency of the quantum circuit. How to solve the above problems has become an important research content at present. This application provides an optimization method, device and medium for quantum circuits to solve the deficiencies in the prior art. By setting optimization conditions, a quantum circuit that meets the optimization conditions is obtained and an optimization operation is performed to reduce the number of quantum logic gates in the quantum circuit, making the depth of the optimized quantum circuit smaller, providing a basis for improving the computing efficiency of the quantum circuit on the quantum chip.

[0055] See Figure 2 , Figure 2 is a schematic flowchart of an optimization method for a quantum circuit provided by an embodiment of the present invention.

[0056] This embodiment provides an embodiment of an optimization method for a quantum circuit. The optimization method for the quantum circuit may include:

[0057] S201: Obtain the initial quantum logic gates in the quantum circuit to be optimized, and convert the initial quantum logic gates into basic quantum logic gates, where the basic quantum logic gates include: CZ gate, RX gate, and RZ gate.

[0058] Specifically, due to hardware limitations, current quantum chips can only run some basic and specific quantum logic gates. To enable a quantum circuit to run on a quantum chip, the quantum circuit needs to be optimized, that is, the initial quantum logic gates not directly supported by the quantum chip in the quantum circuit to be optimized are converted into basic quantum logic gates, and then the basic quantum logic gates are converted according to the following optimization conditions to obtain quantum logic gates that can directly run on the quantum chip, thereby ensuring that the optimized quantum circuit to be optimized can run normally on the quantum chip.

[0059] Exemplarily, each initial logic gate that the quantum chip does not directly support running in the quantum circuit to be optimized and the quantum bits corresponding to each initial quantum logic gate can be obtained as the logic gates to be decomposed and their corresponding quantum bits. Then the logic gates to be decomposed are converted into basic logic gates, or the logic gates to be decomposed are converted into a combination of quantum logic gates that can run on the quantum chip.

[0060] In an alternative embodiment, obtaining the initial quantum logic gates in the quantum circuit to be optimized and converting the initial quantum logic gates into basic quantum logic gates may include:

[0061] 1. Obtaining the quantum logic gates that the quantum chip does not support direct operation in the quantum circuit to be optimized as the initial quantum logic gates;

[0062] 2. Equivalently converting the initial quantum logic gates into target U3 gates and CNOT gates;

[0063] 3. Converting the target U3 gates into the RX gates and the RZ gates; and converting the CNOT gates into the CZ gates supported by the quantum chip.

[0064] Specifically, the basic quantum logic gates may include CZ gates, RX gates, and RZ gates. According to the different types of logic gates supported by different quantum chips, in specific embodiments, the basic quantum logic gates may also be other single-quantum logic gates or two-quantum logic gates. The initial quantum logic gates are multi-controlled quantum logic gates not supported by the quantum chip, so the initial quantum logic gates cannot directly run on the quantum chip and need to be first decomposed into a combination of multiple basic quantum logic gates.

[0065] For example, first, by obtaining each multi-controlled quantum logic gate in the quantum circuit to be optimized and the operation qubits corresponding to each multi-controlled quantum logic gate, and taking each multi-controlled quantum logic gate and the operation qubits corresponding to each multi-controlled quantum logic gate as the initial quantum logic gate and its corresponding operation qubits in sequence. Among them, the multi-controlled quantum logic gate includes at least one control qubit and one controlled quantum logic gate. The controlled quantum logic gate in the multi-controlled quantum logic gate can be a controlled single-quantum logic gate or a controlled two-quantum logic gate.

[0066] When the controlled quantum logic gate is a controlled two-quantum logic gate, first decompose the controlled two-quantum logic gate into a combination of multiple controlled single-quantum logic gates and CNOT gates, and then continue to decompose each controlled single-quantum logic gate until the multi-controlled quantum logic gate including the controlled two-quantum logic gate is decomposed into basic quantum logic gates. When the controlled quantum logic gate is a controlled single-quantum logic gate, it can also be decomposed into a combination of basic quantum logic gates.

[0067] Among them, the initial quantum logic gate is equivalently converted into a target U3 gate and a CNOT gate. The target U3 gate includes three angle parameters, that is, U(θ,φ,λ), and θ, φ, and λ are the three angle parameters corresponding to the U3 gate. Taking U3(0.000000,1.570796,0.000000) as an example, the first 0.000000 corresponds to the θ angle parameter, 1.570796 corresponds to the φ angle parameter, and the second 0.000000 corresponds to the λ angle parameter.

[0068] The matrix corresponding to the U(θ,φ,λ) gate is:

[0069]

[0070] And the decomposition process of the U3 gate can be expressed by the following formula:

[0071]

[0072] It can be seen from the above formula that the decomposition of the U3 gate will generate three RZ gates and two RX gates. At this time, two RPhi gates will be generated during the backward movement of the RZ gates, and the rotation angles of these two RPhi gates are both

[0073] The CNOT gate can be decomposed into the CZ gate supported by the quantum chip. In an alternative embodiment, the CNOT gate can also be decomposed into 1 controlled H gate, 1 CZ gate, and 1 controlled H gate in sequence, and then the controlled H gate is further decomposed, that is, decomposed into three basic logic gates of RZ gate, RX gate, and RZ gate in sequence.

[0074] S202: Traverse the basic quantum logic gates, and sequentially determine whether each of the basic quantum logic gates meets the optimization condition; wherein, the optimization condition includes replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate.

[0075] Specifically, before traversing the basic quantum logic gates and sequentially determining whether each of the basic quantum logic gates meets the optimization condition, the method may further include:

[0076] Query all RZ gates in the basic logic gates, adjust all the RZ gates to the last-layer timing of the quantum circuit to be optimized, and merge all the RZ gates at the last-layer timing.

[0077] Specifically, the first step of quantum logic gate conversion is to convert the quantum circuit to be optimized into a quantum circuit composed of basic quantum logic gates through multi-controlled gate decomposition technology. At this time, the generated quantum circuit includes three basic quantum logic gates: RX, RZ, and CZ; subsequently, query all RZ gates in the basic logic gates, move all the RZ gates backward, and merge all the RZ gates. For example, the effect can be intuitively seen through the corresponding formula:

[0078] R Z (θ Z2 )·R Z (θ Z1 )=R Z (θ Z1 +θ Z2 )

[0079] In an alternative embodiment, the querying all RZ gates in the basic logic gates and adjusting all the RZ gates to the last-layer timing of the quantum circuit to be optimized may include:

[0080] Obtain one of the RZ gates, and obtain the quantum logic gate at the next timing of the RZ gate as the adjacent quantum logic gate; if the adjacent quantum logic gate is the CZ gate, then adjust the RZ gate after the CZ gate.

[0081] That is, it is intuitively shown through the following formula:

[0082]

[0083] If the adjacent quantum logic gate is the RX gate, adjust the RZ gate to behind the RX gate and convert the RX gate into a specific quantum logic gate; wherein, the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate, the specific quantum logic gate includes the RPhi gate, and the RPhi gate is used to rotate a quantum state by an angle around an arbitrary rotation axis in the XY-axis plane.

[0084] That is, it is visually shown by the following formula:

[0085]

[0086] Therefore, after processing, the RX gate is replaced by the RPhi gate with the rotation axis being θ Z and the angle being θ X At this time, the RPhi gate is added to the quantum circuit. Therefore, there will be new situations during the process of moving the RZ gate backward. There is one more logic gate, the RPhi gate. When encountering the RPhi gate:

[0087]

[0088] It can be concluded from this that there will be situations where there are multiple RPhi gates during the conversion process of the entire quantum circuit to be optimized, and the angles corresponding to each RPhi gate are sometimes the same and sometimes different.

[0089] It should be noted that the corresponding matrix of the RPhi gate is:

[0090]

[0091] wherein, R φ (θ) is the RPhi(θ,φ) gate.

[0092] S203: In response to multiple basic quantum logic gates in the basic quantum logic gates meeting the optimization conditions, generate a target quantum circuit that is equivalent to the quantum circuit to be optimized and supported by the quantum chip to run, wherein the depth of the target quantum circuit is smaller.

[0093] Specifically, in this application, after converting each initial quantum logic gate in the quantum circuit to be optimized into a basic logic gate, further in the quantum circuit to be optimized, move the RZ gate in the basic quantum logic gate backward until all the RZ gates in the quantum circuit to be optimized are moved to the end of the quantum circuit, that is, the backward movement operation of the RZ gate is completed.

[0094] Further, obtain one of the RZ gates, and obtain the quantum logic gate at the next timing of the RZ gate as the adjacent quantum logic gate;

[0095] If the adjacent quantum logic gate is the CZ gate, move the RZ gate behind the CZ gate; if the adjacent quantum logic gate is the RX gate, move the RZ gate behind the RX gate and convert the RX gate into a specific quantum logic gate; wherein, the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate.

[0096] The RZ gate and the RX gate are quantum logic gates that need to be moved backward and eliminated in the quantum circuit to be optimized. Among them, the RZ gate realizes the backward movement of the rotation gate in the direction where the RZ gate is located (i.e., the Z-axis direction) in the quantum circuit to be optimized, and finally eliminates all rotation gates in the Z-axis direction (i.e., the RZ gate) in the quantum circuit; the RX gate realizes the backward movement of the rotation gate in the direction where the RX gate is located (i.e., the X-axis direction) in the quantum circuit to be optimized, and finally eliminates all rotation gates in the X-axis direction (i.e., the RX gate) in the quantum circuit.

[0097] Further, during the process of moving the RZ gate backward, in order to eliminate the influence of the backward movement of the RZ gate on the quantum circuit to be optimized, the circuit behind the backward-moved RZ gate is further converted accordingly, that is, the next logic gate of the RZ gate to be backward-moved is obtained as the adjacent quantum logic gate, and the adjacent quantum logic gate is correspondingly converted according to the type of the adjacent quantum logic gate. It can be understood that since there are three logic gates including the CZ gate, the RX gate, and the RPhi gate in addition to the RZ gate in the basic quantum logic gates, it can be explained in three cases.

[0098] When the adjacent quantum logic gate is the CZ gate, since the unitary matrix product corresponding to the RZ gate and the CZ gate is the same as the unitary matrix product corresponding to the CZ gate and the RZ gate, moving the RZ gate before the CZ gate behind the CZ gate has no influence on the quantum circuit to be optimized, that is, when the adjacent quantum logic gate is the CZ gate, the RZ gate can be directly moved backward.

[0099] When the adjacent quantum logic gate is the RX gate, since the unitary matrix product of the RZ gate and the adjacent quantum logic gate is the same as the unitary matrix product of the specific logic gate and the RZ gate, that is:

[0100]

[0101] It should be noted that according to the left multiplication of matrices, the matrix corresponding to the quantum logic gate with an earlier timing in the quantum circuit should be on the left of the matrix corresponding to the logic gate with a later timing, that is, if the RZ gate is before the RX gate, the unitary matrix of the RZ gate and the RX should be R X (θ X )R Z (θ Z )。

[0102] Therefore, move the RZ gate behind the RX gate and further convert the RX gate into the RPhi gate.

[0103] When the adjacent quantum logic gate is an RPhi gate, move the RZ gate before the RPhi gate to after the RPhi gate and correspondingly adjust the angular parameter, that is:

[0104] RPhi(θ,φ)R Z (θ Z )=R Z (θ Z )RPhi(θ,φ - θ Z )

[0105] It should be noted that if the two adjacent specific quantum logic gates with angular parameter π are included in the quantum circuit to be optimized, a direct merging operation is performed.

[0106] Exemplarily, taking the decomposition process expression of the above U3 gate as an example:

[0107]

[0108] It can be seen that the U3 gate finally generates two RPhi gates with the same rotation angle but possibly different rotation axes. At this time, if the optimization condition is met, that is, when θ = π, the rotation axes of the two RPhi gates are also the same. Therefore, it can be concluded that when decomposing the U3 gate, if the parameter θ = π, the decomposed basic quantum logic gates are an RZ gate and an RPhi gate, with one less RPhi gate than the original, making the depth of the target quantum circuit smaller when generating a target quantum circuit equivalent to the quantum circuit to be optimized.

[0109] Furthermore, the optimization condition can also include performing a merging operation on two adjacent RX gates and / or two adjacent RZ gates in the quantum circuit to be optimized.

[0110] Specifically, in order to further optimize the quantum circuit, reduce the number of logic gates in the quantum circuit, and improve the execution efficiency of the quantum circuit, before directly merging two adjacent specific quantum logic gates with angular parameter π, a merging operation can be first performed on two adjacent RX gates or two adjacent RZ gates in the basic quantum logic gates. The merging operation is to use the sum of the angles corresponding to the two RX gates or RZ gates as the angular parameter of the merged RX gate, that is:

[0111]

[0112]

[0113] It should be noted that after the RZ gate is moved to the end of the quantum circuit, only the CZ gate, RPhi gate, and the RZ gate at the last timing of the circuit remain in the quantum circuit to be optimized. Since the quantum circuit needs to be measured on the axis corresponding to the RZ gate (such as the Z axis), after all the RZ gates in the quantum circuit to be optimized are moved to the last timing of the circuit, the RZ gate can be directly deleted without affecting the measurement result of the quantum circuit. Then, according to the remaining quantum logic gates (i.e., RPhi gate and CZ gate) and their corresponding operation bits in the circuit to be optimized after conversion and elimination, a target quantum circuit is constructed. At this time, the target quantum circuit only contains the CZ gate and RPhi gate that can be directly executed on the quantum chip.

[0114] Compared with the prior art, the present invention first obtains the initial quantum logic gates in the quantum circuit to be optimized, converts the initial quantum logic gates into basic quantum logic gates, then traverses the basic quantum logic gates, and sequentially determines whether each basic quantum logic gate meets the optimization conditions. Finally, in response to the existence of multiple basic quantum logic gates that meet the optimization conditions among the basic quantum logic gates, a target quantum circuit equivalent to the quantum circuit to be optimized and supported by the quantum chip is generated. By setting the optimization conditions, a quantum circuit that meets the optimization conditions is obtained and the optimization operation is performed, so as to reduce the number of quantum logic gates in the quantum circuit, make the depth of the optimized quantum circuit smaller, and provide a basis for improving the computing efficiency of the quantum circuit on the quantum chip.

[0115] See Figure 3 , Figure 3 is a schematic structural diagram of an optimization device for a quantum circuit provided by an embodiment of the present invention, corresponding to the Figure 2 shown process. The device includes:

[0116] An obtaining module 301, configured to obtain the initial quantum logic gates in the quantum circuit to be optimized and convert the initial quantum logic gates into basic quantum logic gates, where the basic quantum logic gates include: CZ gate, RX gate, and RZ gate;

[0117] A traversing module 302, configured to traverse the basic quantum logic gates and sequentially determine whether each basic quantum logic gate meets the optimization conditions; where the optimization conditions include replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate;

[0118] A generating module 303, configured to generate a target quantum circuit equivalent to the quantum circuit to be optimized and supported by the quantum chip in response to the existence of multiple basic quantum logic gates that meet the optimization conditions among the basic quantum logic gates, where the depth of the target quantum circuit is smaller.

[0119] Specifically, the obtaining module includes:

[0120] A first acquisition unit, configured to acquire a quantum logic gate that is not directly supported for operation by a quantum chip in the quantum circuit to be optimized as the initial quantum logic gate;

[0121] A first conversion unit, configured to equivalently convert the initial quantum logic gate into a target U3 gate and a CNOT gate;

[0122] A second conversion unit, configured to convert the target U3 gate into the RX gate and the RZ gate; and convert the CNOT gate into the CZ gate supported by the quantum chip.

[0123] Specifically, before the traversal module, the apparatus further includes:

[0124] A query module, configured to query all RZ gates in the basic logic gates, adjust all the RZ gates to the last-layer timing of the quantum circuit to be optimized, and merge all the RZ gates in the last-layer timing.

[0125] Specifically, the query module includes:

[0126] A second acquisition unit, configured to acquire one of the RZ gates and acquire the quantum logic gate at the next timing of the RZ gate as the adjacent quantum logic gate;

[0127] A first adjustment unit, configured to, if the adjacent quantum logic gate is the CZ gate, adjust the RZ gate after the CZ gate.

[0128] Specifically, the query module further includes:

[0129] A second adjustment unit, configured to, if the adjacent quantum logic gate is the RX gate, adjust the RZ gate after the RX gate and convert the RX gate into a specific quantum logic gate; wherein, the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate, and the specific quantum logic gate includes an RPhi gate, and the RPhi gate is used to rotate a quantum state by an angle around an arbitrary rotation axis in the XY-axis plane.

[0130] Compared with the prior art, the present invention first obtains the initial quantum logic gates in the quantum circuit to be optimized, and converts the initial quantum logic gates into basic quantum logic gates. Then, it traverses the basic quantum logic gates and sequentially determines whether each basic quantum logic gate meets the optimization conditions. Finally, in response to the existence of multiple basic quantum logic gates that meet the optimization conditions among the basic quantum logic gates, a target quantum circuit equivalent to the quantum circuit to be optimized and supported by the quantum chip for operation is generated. By setting the optimization conditions, a quantum circuit that meets the optimization conditions is obtained and an optimization operation is performed, so as to reduce the number of quantum logic gates in the quantum circuit, make the depth of the optimized quantum circuit smaller, and provide a basis for improving the computing efficiency of the quantum circuit on the quantum chip.

[0131] An embodiment of the present invention further provides a storage medium, in which a computer program is stored. Wherein, the computer program is set to execute the steps in any one of the above method embodiments when running.

[0132] Specifically, in this embodiment, the above storage medium may be set to store a computer program for executing the following steps:

[0133] S201: Obtain the initial quantum logic gates in the quantum circuit to be optimized, and convert the initial quantum logic gates into basic quantum logic gates, where the basic quantum logic gates include: CZ gates, RX gates, and RZ gates;

[0134] S202: Traverse the basic quantum logic gates and sequentially determine whether each basic quantum logic gate meets the optimization conditions; where the optimization conditions include replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate;

[0135] S203: In response to the existence of multiple basic quantum logic gates that meet the optimization conditions among the basic quantum logic gates, generate a target quantum circuit equivalent to the quantum circuit to be optimized and supported by the quantum chip for operation, where the depth of the target quantum circuit is smaller.

[0136] Specifically, in this embodiment, the above storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks, or optical discs that can store computer programs.

[0137] An embodiment of the present invention further provides an electronic device, including a memory and a processor. It is characterized in that a computer program is stored in the memory, and the processor is set to run the computer program to execute the steps in any one of the above method embodiments.

[0138] Specifically, the above electronic device may further include a transmission device and an input / output device. Among them, the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0139] Specifically, in this embodiment, the above processor may be configured to execute the following steps through a computer program:

[0140] S201: Obtain the initial quantum logic gates in the quantum circuit to be optimized, and convert the initial quantum logic gates into the basic quantum logic gates supported by the quantum chip. Among them, the basic logic gates supported by the quantum chip include: CZ gate, RX gate, and RZ gate;

[0141] S202: Traverse the basic quantum logic gates, and sequentially determine whether each basic quantum logic gate meets the optimization conditions; among them, the optimization conditions include replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate;

[0142] S203: In response to the existence of multiple basic quantum logic gates in the basic quantum logic gates that meet the optimization conditions, generate a target quantum circuit equivalent to the quantum circuit to be optimized, where the depth of the target quantum circuit is smaller.

[0143] An embodiment of the present invention may further provide a quantum computer operating system, and the quantum computer operating system performs quantum circuit optimization according to any of the above method embodiments provided in the embodiments of the present invention.

[0144] An embodiment of the present application may further provide a quantum computer, and the quantum computer includes the above quantum computer operating system.

[0145] The above has detailed the structure, features, and function effects of the present invention according to the illustrated embodiments. The above is only a preferred embodiment of the present invention, but the present invention is not limited to the scope defined by the drawings. Any changes made according to the concept of the present invention, or equivalent embodiments modified into equivalent changes, still within the spirit covered by the specification and the drawings, should be within the protection scope of the present invention.

Claims

1. A method for optimizing a quantum circuit, characterized in that: The method comprises: Obtaining an initial quantum logic gate in the quantum circuit to be optimized, and converting the initial quantum logic gate into a basic quantum logic gate, wherein the basic quantum logic gate includes: a CZ gate, an RX gate, and an RZ gate; Traversing the basic quantum logic gates, and determining in turn whether each of the basic quantum logic gates meets the optimization condition; wherein the optimization condition includes replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate; In response to the existence of multiple basic quantum logic gates in the basic quantum logic gates that meet the optimization condition, a target quantum circuit that is equivalent to the quantum circuit to be optimized and supported by a quantum chip is generated, wherein the depth of the target quantum circuit is smaller.

2. The optimization method according to claim 1, characterized in that: The step of obtaining an initial quantum logic gate in the quantum circuit to be optimized and converting the initial quantum logic gate into a basic quantum logic gate comprises: Acquire a quantum logic gate that is not supported for direct operation by a quantum chip in the quantum circuit to be optimized as the initial quantum logic gate; Convert the initial quantum logic gate into a target U3 gate and a CNOT gate; The target U3 gate is converted into the RX gate and the RZ gate; and the CNOT gate is converted into the CZ gate supported by the quantum chip.

3. The optimization method according to claim 2, characterized in that: Before traversing the basic quantum logic gates and determining in turn whether each basic quantum logic gate meets the optimization condition, the method further includes: All RZ gates in the basic logic gates are queried, all the RZ gates are adjusted to the last layer timing of the quantum circuit to be optimized, and all the RZ gates in the last layer timing are merged.

4. The optimization method according to claim 3, characterized in that: The querying of all RZ gates in the basic logic gates and adjusting all the RZ gates to the last layer timing of the quantum circuit to be optimized includes: Obtaining the RZ gate, and obtaining the quantum logic gate of the next time sequence of the RZ gate as an adjacent quantum logic gate; If the adjacent quantum logic gate is the CZ gate, the RZ gate is adjusted to be after the CZ gate.

5. The optimization method according to claim 4, characterized in that: After obtaining the RZ gate and obtaining the quantum logic gate of the next time sequence of the RZ gate as an adjacent quantum logic gate, the method further includes: If the adjacent quantum logic gate is the RX gate, the RZ gate is adjusted to be after the RX gate, and the RX gate is converted into a specific quantum logic gate; wherein the unitary matrix product of the RZ gate and the RX gate is equal to the unitary matrix product of the specific quantum logic gate and the RZ gate, and the specific quantum logic gate includes an RPhi gate, and the RPhi gate is used to rotate the quantum state around any rotation axis in the XY axis plane.

6. The optimization method according to claim 5, characterized in that: If the quantum circuit to be optimized includes two adjacent specific quantum logic gates whose angle parameter is π, a merging operation is directly performed.

7. A quantum circuit optimization device, characterized in that: The device comprises: An acquisition module is used to obtain an initial quantum logic gate in the quantum circuit to be optimized, and convert the initial quantum logic gate into a basic quantum logic gate, wherein the basic quantum logic gate includes: a CZ gate, an RX gate, and an RZ gate; A traversal module, used to traverse the basic quantum logic gates, and determine in turn whether each of the basic quantum logic gates meets the optimization condition; wherein the optimization condition includes replacing multiple basic quantum logic gates with a single quantum logic gate, and the rotation angles of the multiple basic quantum logic gates are different from those of the single quantum logic gate; A generating module is used for generating a target quantum circuit which is equivalent to the quantum circuit to be optimized and supported by the quantum chip in response to the presence of multiple basic quantum logic gates in the basic quantum logic gates meeting the optimization condition, wherein the depth of the target quantum circuit is smaller.

8. A quantum computer operating system, characterized in that: Quantum circuit optimization is performed using the optimization method described in any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to execute the method according to any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to perform the method according to any one of claims 1 to 6.

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