Display partition refreshing method, display system and electronic equipment

Abstract

The embodiment of the invention provides a display partition refreshing method, a display system and electronic equipment. According to the embodiment of the invention, more enable signal lines are introduced into the display, so that enable signals can be continuously provided for the cascaded GOA units for a longer time, and conditions are provided for widening the pulse width of data retention signals output by the GOA units and creating a non-coupling region; moreover, in the display partition refreshing method, by widening the pulse width of the data holding signal output by the GOA and controlling the data write-in control signal to appear behind the coupling region, the data write-in aiming at the pixel unit can be prevented from being interfered by the burr of the data holding signal, so that the generation of screen cross grains can be avoided.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and in particular, to a method for refreshing a display in zones, a display system, and an electronic device. Background Art

[0002] With the development of display technologies, in order to display smooth pictures, the screen refresh rates supported by electronic devices such as mobile phones and tablet computers are continuously increasing. However, the power consumption of displays poses a great challenge to power saving of devices or battery life. For this reason, in recent years, displays that support reducing the refresh rate to a low refresh rate or even an ultra-low refresh rate have been gradually introduced into the market. For example, low-temperature polycrystalline oxide (LTPO) displays support reducing the refresh rate to 1 Hz. However, the current refresh method of display devices is to refresh the entire screen. When only a small part of the screen needs to be updated, the display driver integrated circuit (DDIC) still has to refresh the entire screen, resulting in waste of power consumption. Summary of the Invention

[0003] Embodiments of this application provide a method for refreshing a display in zones and an electronic device, which can solve one or more problems such as screen horizontal stripes, brightness differences between low-refresh-rate zones and high-refresh-rate zones, and screen flickering while supporting the function of variable frequency in zones.

[0004] In a first aspect, embodiments of this application provide a method for refreshing a display in zones. This method can be applied to a display, which may include: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit. Among them, the display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines. One enable signal line is connected to N levels of first GOA units. The first GOA unit is used to output a data holding signal to the pixel unit. The second GOA circuit includes cascaded second GOA units. The second GOA unit is used to output a data writing control signal to the pixel unit. M and N are positive integers, and M is greater than or equal to 2.

[0005] This method may include:

[0006] At time h, control the initial first GOA unit to output a data holding signal, and the data holding signal lasts for X row scanning times, where X > N.

[0007] At time k, control the initial second GOA unit to output a data writing control signal. Time k is later than time h + N*H and earlier than time h + X*H, where H represents a row scanning time.

[0008] In the first aspect, the display may be the display 10 mentioned in the subsequent embodiments, and the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in the subsequent embodiments; the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in the subsequent embodiments.

[0009] Implementing the method provided in the first aspect, introducing more enable signal lines into the display 10 can continuously provide an enable signal to the cascaded GOA unit 220 for a longer time, providing conditions for broadening the pulse width of the data holding signal S1 and creating a non-coupling region. Moreover, the pulse width of the data holding signal S1 is at least greater than N line scanning times to ensure that the pulse width of the data holding signal S1 output by each GOA unit 220 includes a non-coupling region. Additionally, the time k is later than the time h + N*H, which can cause the data write control signal G1 to appear after the coupling region of the data holding signal S1, thereby realizing that the data writing to the pixel unit is not affected by the glitch of S1 and preventing screen horizontal streaks.

[0010] Combined with the first aspect, in some embodiments, controlling the initial first GOA unit to output a data holding signal may specifically include: among the cascaded M*N first GOA units, controlling the i-th first GOA unit to output a data holding signal at the time h + (i - 1)*Q*H. i is a positive integer, i ≤ M*N, and Q represents that the data holding signal S1 output by the i-th GOA unit 220 is Q line scanning times earlier than the data holding signal S1 output by the (i + 1)-th GOA unit 220, and Q can take positive integer values such as 1, 2, etc.

[0011] Combined with the first aspect, in some embodiments, controlling the initial first GOA unit to output a data holding signal may specifically include: at the time h - Q*H, inputting a column start STV signal to the input end of the initial first GOA unit, and Q represents that the i-th first GOA unit outputs a data holding signal Q line scanning times earlier than the (i + 1)-th first GOA unit.

[0012] Combined with the first aspect, in some embodiments, the maximum value X max of X can be calculated as follows: X max = M*Y - (M*N - 1)*Q, where Y represents the pulse width of the enable signal on the enable signal line, and Q represents that the i-th first GOA unit outputs a data holding signal Q line scanning times earlier than the (i + 1)-th first GOA unit. It can be seen that the larger M is, the larger X max is, that is, increasing the number of VFE signals can broaden the pulse width of the S1 signal.

[0013] In combination with the first aspect, in some embodiments, controlling the initial second GOA unit to output a data write control signal may specifically include: in the cascaded second GOA units, the j-th second GOA unit starts to output a data write control signal at time k+(j - 1)*q; q represents the time delay of the j-th second GOA unit relative to the (j - 1)-th second GOA unit when outputting the data write control signal; j is a positive integer and j is less than or equal to the number of cascaded second GOA units.

[0014] In combination with the first aspect, in some embodiments, controlling the initial second GOA unit to output a data write control signal may specifically include: at time k - q, inputting a column start STV signal to the input terminal of the initial second GOA unit; q represents the time delay of the j-th second GOA unit relative to the (j - 1)-th second GOA unit when outputting the data write control signal.

[0015] In combination with the first aspect, in some embodiments, the VFE signal may be a high-level signal, and the data hold signal may also be a high-level signal; the method provided by the first aspect may further include: controlling the time when the enable signal on the enable signal line switches from high level to low level to be later than a first time, where the first time is the time when the data hold signal output by the last first GOA unit connected to the enable signal line switches from high level to low level.

[0016] In a second aspect, an embodiment of the present application provides a method for refreshing a display in partitions. The method can be applied to a display, and the display may include: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit. Among them, the display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines, and one enable signal line is connected to N levels of first GOA units. The first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit includes cascaded second GOA units, and the second GOA unit is used to output a data write control signal to the pixel unit; M and N are positive integers, and M is greater than or equal to 2;

[0017] The method may include:

[0018] Determine the time for performing data writing on the pixel units in the first screen area;

[0019] When performing data writing on the pixel units in the first screen area, perform a first biasing process on the reset voltage of the pixel units in the first screen area. The reset voltage after the first biasing process is the reset voltage corresponding to the first reference brightness at the first refresh rate during data writing;

[0020] Among them, the first reference brightness is less than the brightness corresponding to the reset voltage of the pixel units in the first screen area before the first bias processing at the first refresh rate.

[0021] In the second aspect, the display may be the display 10 mentioned in the subsequent embodiments, and the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in the subsequent embodiments; the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in the subsequent embodiments.

[0022] By implementing the method provided in the second aspect, the brightness of the first screen area with a low refresh rate during data writing can be adjusted to the first reference brightness by adjusting the reset voltage Vref of the pixel units, thereby improving the brightness difference between different screen partitions.

[0023] In combination with the second aspect, in some embodiments, the first reference brightness may specifically be the brightness corresponding to the first reset voltage at the second refresh rate during data writing. The first reset voltage is the reset voltage of the pixel units in the second screen area when data is written to the second screen area at the second refresh rate; the second refresh rate is higher than the first refresh rate.

[0024] Among them, the first reference brightness may specifically be the brightness corresponding to the first reset voltage at the second refresh rate during data writing. The first reset voltage is the reset voltage of the pixel units in the second screen area when data is written to the second screen area at the second refresh rate, and it can be measured by the DDIC. The first refresh rate is lower than the second refresh rate. In this way, the brightness of the first screen area with a low refresh rate can be adjusted to the brightness of the second screen area with a high refresh rate, thereby unifying the brightness of different refresh rate partitions and improving the brightness difference.

[0025] In combination with the second aspect, in some embodiments, there are different corresponding relationships between the brightness during data writing and the reset voltage Vref at different refresh rates. Moreover, this corresponding relationship can also be measured and recorded in advance for adjusting the reset voltage during data writing to unify the screen brightness. The first mapping table can be used to record the corresponding relationship between the reset voltage and the brightness during data writing at the second refresh rate; the second mapping table can be used to record the corresponding relationship between the reset voltage and the brightness during data writing at the first refresh rate.

[0026] The method provided in the second aspect may further include: in the first mapping table, finding the brightness corresponding to the first reset voltage, and determining the found brightness as the first reference brightness; in the second mapping table, finding the reset voltage corresponding to the first reference brightness, and determining the found reset voltage as the reset voltage after the first bias processing.

[0027] In a third aspect, an embodiment of the present application provides a method for refreshing a display partition. The method can be applied to a display, which may include: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit. The display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines. One enable signal line is connected to N stages of first GOA units. The first GOA unit is configured to output a data holding signal to the pixel unit. The second GOA circuit includes cascaded second GOA units. The second GOA unit is configured to output a data writing control signal to the pixel unit. M and N are positive integers, and M is greater than or equal to 2.

[0028] The method may include:

[0029] Determine the time when data writing is not performed on the pixel units in the third screen area, and the refresh rate of the third screen area is the third refresh rate;

[0030] When data writing is not performed on the pixel units in the third screen area, perform a second biasing process on the reset voltage of the pixel units in the third screen area. The reset voltage after the second biasing process is the reset voltage corresponding to the second reference brightness during data holding at the third refresh rate;

[0031] Wherein, the second reference brightness is the brightness corresponding to the second reset voltage during data writing at the third refresh rate; the second reset voltage is the reset voltage when data is written in the third screen area at the third refresh rate.

[0032] In the third aspect, the display may be the display 10 mentioned in subsequent embodiments, and the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in subsequent embodiments; the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in subsequent embodiments.

[0033] By implementing the method provided in the third aspect, the brightness of the screen area during data holding can be adjusted to the brightness of the screen area during data writing by adjusting the reset voltage Vref of the pixel units, and the brightness of the screen area can be kept from jumping when switching between data holding and data writing, avoiding screen flickering.

[0034] In combination with the third aspect, in some embodiments, the second reset voltage is the reset voltage when data is written in the third screen area at the third refresh rate and can be measured by the DDIC. The method provided in the third aspect may further include: measuring the second reset voltage.

[0035] In combination with the third aspect, in some embodiments, the method provided by the third aspect may further include: determining the time for performing data writing to the pixel units in the third screen area.

[0036] In combination with the third aspect, in some embodiments, the corresponding relationships between the brightness and the reset voltage Vref at different refresh rates can be measured and recorded in advance for adjusting the reset voltage during data retention. According to this corresponding relationship, the brightness value corresponding to a certain reset voltage at a specific refresh rate during data writing can be determined, and the reset voltage corresponding to a certain brightness at a specific refresh rate during data writing can also be determined. Among them, the third mapping table is used to record the corresponding relationship between the reset voltage and the brightness during data writing at the third refresh rate; the fourth mapping table is used to record the corresponding relationship between the reset voltage and the brightness during data retention at the third refresh rate.

[0037] The method provided by the third aspect may further include: in the third mapping table, finding the brightness corresponding to the second reset voltage, and determining the found brightness as the second reference brightness; in the fourth mapping table, finding the reset voltage corresponding to the second reference brightness, and determining the found reset voltage as the reset voltage after the second biasing process.

[0038] In combination with the third aspect, in some embodiments, the third screen area may be a low-refresh-rate screen area, such as the aforementioned first screen area; at this time, the third refresh rate is a low refresh rate, which may be the same as the aforementioned first refresh rate, and the third mapping table may be the same as the aforementioned second mapping table. The third screen area may also be a high-refresh-rate screen area, such as the aforementioned second screen area; at this time, the third refresh rate is a high refresh rate, which may be the same as the aforementioned second refresh rate, and the fourth mapping table may be the same as the aforementioned first mapping table.

[0039] In combination with the third aspect, in some embodiments, when the third screen area is a low-refresh-rate screen area, the second reset voltage may further be the reset voltage after the first biasing process in the method provided by the second aspect.

[0040] The method provided by the third aspect may further include: before performing the second biasing process, determining the time for performing data writing to the pixel units in the first screen area; when performing data writing to the pixel units in the first screen area, performing a first biasing process on the reset voltage of the pixel units in the first screen area, and the reset voltage after the first biasing process is the reset voltage corresponding to the first reference brightness at the first refresh rate during data writing. Among them, the first reference brightness is specifically the brightness corresponding to the first reset voltage at the second refresh rate during data writing, and the first reset voltage is the reset voltage of the pixel units in the second screen area when data is written to the second screen area at the second refresh rate; the second refresh rate is higher than the first refresh rate.

[0041] In combination with the third aspect, in some embodiments, the first reset voltage is the reset voltage of the pixel units in the second screen area when data is written while the second screen area is refreshed at the second refresh rate, and it can be measured by the DDIC. The method provided by the third aspect may further include: measuring the first reset voltage.

[0042] In combination with the third aspect, in some embodiments, the second screen area may be the screen area with the highest refresh rate.

[0043] In combination with the third aspect, in some embodiments, the first mapping table can be used to record the correspondence between the reset voltage and the brightness when data is written at the second refresh rate; the second mapping table can be used to record the correspondence between the reset voltage and the brightness when data is written at the first refresh rate.

[0044] The method provided by the third aspect may further include: in the first mapping table, looking up the brightness corresponding to the first reset voltage, and determining the looked-up brightness as the first reference brightness; in the second mapping table, looking up the reset voltage corresponding to the first reference brightness, and determining the looked-up reset voltage as the reset voltage after the first bias processing.

[0045] Fourth aspect, embodiments of the present application provide a method for refreshing a display in zones. The method can be applied to a display, and the display may include: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit. Among them, the display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines, and one enable signal line is connected to N levels of first GOA units. The first GOA unit is used to output a data holding signal to the pixel units; the second GOA circuit includes cascaded second GOA units, and the second GOA unit is used to output a data writing control signal to the pixel units; M and N are positive integers, and M is greater than or equal to 2;

[0046] The method may include:

[0047] Determining the gray level of the pixel units in the first screen area;

[0048] When performing data writing to the first pixel unit in the first screen area, performing a third bias processing on the data voltage of the first pixel unit. The data voltage after the third bias processing is the data voltage corresponding to the third reference brightness at the first refresh rate when data is written; the first pixel unit is the pixel unit with the first gray level in the first screen area;

[0049] Among them, the third reference brightness is the brightness corresponding to the first data voltage at the second refresh rate. The first data voltage is the data voltage when the second pixel unit is written with data at the second refresh rate. The second pixel unit is a pixel unit with the first gray level in the second screen area. The refresh rate of the second screen area is the second refresh rate, and the second refresh rate is greater than the first refresh rate.

[0050] In the fourth aspect, the display may be the display 10 mentioned in the subsequent embodiments, and the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in the subsequent embodiments; the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in the subsequent embodiments.

[0051] Implementing the method provided in the fourth aspect can improve the brightness difference between the high-refresh-rate area and the low-refresh-rate area at the same gray level by adjusting the data voltage Vdata of the pixel unit.

[0052] Combined with the fourth aspect, in some embodiments, the method may further include: measuring the first data voltage.

[0053] Combined with the fourth aspect, in some embodiments, the corresponding relationship between the brightness and the data voltage Vdata at different refresh rates during data writing can be measured and recorded in advance for adjusting the data voltage Vdata. According to this corresponding relationship, the brightness value corresponding to a certain data voltage Vdata at a specific refresh rate can be determined, and the data voltage Vdata corresponding to a certain brightness at a specific refresh rate can also be determined. Among them, the fifth mapping table is used to record the corresponding relationship between the data voltage and the brightness during data writing at the second refresh rate; the sixth mapping table is used to record the corresponding relationship between the data voltage and the brightness during data writing at the first refresh rate.

[0054] The method provided in the fourth aspect may further include:

[0055] In the fifth mapping table, find the brightness corresponding to the first data voltage, and determine the found brightness as the third reference brightness; in the sixth mapping table, find the data voltage corresponding to the third reference brightness, and determine the found brightness as the data voltage after the third offset processing.

[0056] Fifth aspect, an embodiment of the present application provides a method for refreshing a display partition. The method can be applied to a display, which may include: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit. The display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines, and one enable signal line is connected to N levels of first GOA units. The first GOA unit is configured to output a data holding signal to the pixel unit. The second GOA circuit includes cascaded second GOA units. The second GOA unit is configured to output a data writing control signal to the pixel unit. M and N are positive integers, and M is greater than or equal to 2;

[0057] The method may include:

[0058] Determine the time when data writing is not performed on the pixel units in the fourth screen area, and the refresh rate of the fourth screen area is the fourth refresh rate;

[0059] When data writing is not performed on the pixel units in the fourth screen area, perform a fourth biasing process on the data voltage of the third pixel units in the fourth screen area. The data voltage after the fourth biasing process is the data voltage corresponding to the fourth reference brightness at the fourth refresh rate during data holding;

[0060] Wherein, the fourth reference brightness is the brightness corresponding to the second data voltage at the fourth refresh rate when data writing is performed on the fourth screen area; the second data voltage is the data voltage when the third pixel unit is written with data at the fourth refresh rate.

[0061] In the fifth aspect, the display may be the display 10 mentioned in the subsequent embodiments, and the display circuit, the first GOA circuit, and the second GOA circuit may be the display circuit 21, the GOA circuit 22, and the GOA circuit 23 mentioned in the subsequent embodiments; the first GOA unit and the second GOA unit may be the GOA unit 220 and the GOA unit 230 mentioned in the subsequent embodiments.

[0062] Implementing the method provided in the fifth aspect can improve screen flicker by adjusting the data voltage Vdata of the pixel units.

[0063] In combination with the fifth aspect, in some embodiments, the method may further include: measuring the second data voltage.

[0064] In combination with the fifth aspect, in some embodiments, the method may further include: determining the time when data writing is not performed on the fourth screen area.

[0065] In combination with the fifth aspect, in some embodiments, the corresponding relationships between the brightness and the data voltage Vdata at different refresh rates during data retention can be measured and recorded in advance for adjusting the data voltage during data retention. According to the corresponding relationships, the brightness value corresponding to a certain data voltage at a specific refresh rate during data retention can be determined, and the data voltage corresponding to a certain brightness at a specific refresh rate during data retention can also be determined. Among them, the seventh mapping table is used to record the corresponding relationship between the data voltage and the brightness during data writing at the fourth refresh rate; the eighth mapping table is used to record the corresponding relationship between the data voltage and the brightness during data retention at the fourth refresh rate.

[0066] The method provided in the fifth aspect may further include: in the seventh mapping table, searching for the brightness corresponding to the second data voltage, and determining the searched brightness as the fourth reference brightness; in the eighth mapping table, searching for the data voltage corresponding to the fourth reference brightness, and determining the searched data voltage as the data voltage after the fourth bias processing.

[0067] In combination with the fifth aspect, in some embodiments, the fourth screen area may be a screen area with a low refresh rate, such as the aforementioned first screen area; at this time, the fourth refresh rate is a low refresh rate, which may be the same as the aforementioned first refresh rate, and the seventh mapping table may be the same as the aforementioned sixth mapping table. The fourth screen area may also be a screen area with a high refresh rate, such as the aforementioned second screen area; at this time, the fourth refresh rate is a high refresh rate, which may be the same as the aforementioned second refresh rate, and the eighth mapping table may be the same as the aforementioned fifth mapping table.

[0068] In combination with the fifth aspect, in some embodiments, if the fourth screen area is specifically the first screen area and the fourth refresh rate is specifically the first refresh rate, then before performing the fourth bias, the method may further include: determining the gray level of the pixel units in the first screen area; when performing data writing to the first pixel unit in the first screen area, performing a third bias processing on the data voltage of the first pixel unit, and the data voltage after the third bias processing is the data voltage corresponding to the third reference brightness at the first refresh rate during data writing; the first pixel unit is a pixel unit with the first gray level in the first screen area; among them, the third reference brightness is the brightness corresponding to the first data voltage at the second refresh rate, and the first data voltage is the data voltage when the second pixel unit is written with data at the second refresh rate; the second pixel unit is a pixel unit with the first gray level in the second screen area, the refresh rate of the second screen area is the second refresh rate, and the second refresh rate is greater than the first refresh rate.

[0069] In combination with the fifth aspect, in some embodiments, the method may further include: measuring the first data voltage.

[0070] In combination with the fifth aspect, in some embodiments, the method may further include: in the fifth mapping table, looking up the brightness corresponding to the first data voltage, and determining the found brightness as the third reference brightness; in the sixth mapping table, looking up the data voltage corresponding to the third reference brightness, and determining the found brightness as the data voltage after the third offset processing. The fifth mapping table is used to record the correspondence between the data voltage and the brightness when data is written at the second refresh rate; the sixth mapping table is used to record the correspondence between the data voltage and the brightness when data is written at the first refresh rate.

[0071] In a sixth aspect, an embodiment of the present application provides an electronic device, which may include a display, a processor, and a memory; wherein, the display is coupled to the processor, and the memory is coupled to the processor;

[0072] Among them, the display includes: a display panel, a first array substrate row driving GOA circuit, and a second GOA circuit. The display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines, and one enable signal line is connected to N levels of first GOA units. The first GOA unit is used to output a data holding signal to the pixel unit; the second GOA circuit includes cascaded second GOA units, and the second GOA unit is used to output a data writing control signal to the pixel unit; M and N are positive integers, and M is greater than or equal to 2;

[0073] The memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device can execute the method described in any one or more of the foregoing first aspect, second aspect, third aspect, fourth aspect, or fifth aspect.

[0074] In a seventh aspect, an embodiment of the present application provides a display system, which may include a display and a control circuit;

[0075] Among them, the display includes: a display panel, a first array substrate row driving GOA circuit, and a second GOA circuit. The display panel includes a plurality of pixel units. The first GOA circuit includes M*N cascaded first GOA units. The first GOA circuit is connected to M enable signal lines, and one enable signal line is connected to N levels of first GOA units. The first GOA unit is used to output a data holding signal to the pixel unit; the second GOA circuit includes cascaded second GOA units, and the second GOA unit is used to output a data writing control signal to the pixel unit; M and N are positive integers, and M is greater than or equal to 2. The control circuit is used to call computer instructions so that the display system can execute the method described in any one or more of the foregoing first aspect, second aspect, third aspect, fourth aspect, or fifth aspect.

[0076] In an eighth aspect, an embodiment of the present application provides a chip system, which is applied to an electronic device. The chip system includes one or more processors, and the processors are configured to call computer instructions to enable the electronic device to execute any one or more of the methods described in the embodiments of the foregoing first aspect, second aspect, third aspect, fourth aspect, or fifth aspect.

[0077] In a ninth aspect, the present application provides a computer-readable storage medium including computer-executable programs. When the computer-executable programs run on an electronic device, the electronic device is enabled to execute any one or more of the methods described in the embodiments of the foregoing first aspect, second aspect, third aspect, fourth aspect, or fifth aspect.

[0078] In a tenth aspect, the present application provides a computer program product containing instructions. When the computer program product runs on an electronic device, the electronic device is enabled to execute any one or more of the methods described in the embodiments of the foregoing first aspect, second aspect, third aspect, fourth aspect, or fifth aspect. Description of the Drawings

[0079] To more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the following will describe the drawings required to be used in the embodiments of the present application or the background art.

[0080] Figure 1 Shows a display 10 provided by an embodiment of the present application;

[0081] Figure 2 Shows an example of a screen area with zoned variable frequency display;

[0082] Figure 3 Shows a basic structure of an LPTO pixel unit;

[0083] Figure 4 Briefly shows the timing logic of output signals and input signals of each component of the display 10;

[0084] Figure 5 Shows screen streaks generated by a display with zoned variable frequency function;

[0085] Figure 6 Shows the signal timing when the display uses 2 VFE signal lines;

[0086] Figure 7 Shows the overall process of a method for zoned refresh of a display provided by an embodiment of the present application;

[0087] Figure 8 Shows Figure 7The signal timing generated by the method shown;

[0088] Figure 9 Shows the screen dark lines generated by a display with a zoned frequency conversion function;

[0089] Figure 10 Shows the brightness difference problem of each screen partition of a display with a zoned frequency conversion function;

[0090] Figure 11 Shows the brightness difference between the write frame and the hold frame at a 1 Hz refresh rate;

[0091] Figure 12 Shows the overall process of another method for zoned refresh of a display provided by an embodiment of the present application;

[0092] Figure 13 Shows the correspondence between brightness and reset voltage during data writing at 1 Hz and 120 Hz refresh rates;

[0093] Figure 14 Shows the overall process of another method for zoned refresh of a display provided by an embodiment of the present application;

[0094] Figure 15 Shows the correspondence between brightness and reset voltage during data holding at 1 Hz and 120 Hz refresh rates;

[0095] Figure 16 Shows the voltage bias of the reset voltage in the low refresh rate area relative to the reset voltage in the high refresh rate area during data writing, and the voltage bias of the reset voltage during data holding relative to the reset voltage during data writing;

[0096] Figure 17 Shows the overall process of another method for zoned refresh of a display provided by an embodiment of the present application;

[0097] Figure 18 Shows the correspondence between brightness and data voltage during data writing at 1 Hz and 120 Hz refresh rates;

[0098] Figure 19 Shows the voltage bias of the data voltage in the low refresh rate area relative to the data voltage in the high refresh rate area for writing the same grayscale data;

[0099] Figure 20 Shows the overall process of another method for zoned refresh of a display provided by an embodiment of the present application;

[0100] Figure 21 Shows the correspondence between brightness and data voltage during data holding at 1 Hz and 120 Hz refresh rates;

[0101] Figure 22 It shows the voltage bias of the data voltage in the low refresh rate area relative to the data voltage in the high refresh rate area when writing the same grayscale data, and the voltage bias of the data voltage during data retention relative to the data voltage during data writing;

[0102] Figure 23 It shows a display system provided by an embodiment of the present application;

[0103] Figure 24 It shows an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0104] The terms used in the following embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0105] As used in the specification and appended claims of the present application, the singular forms "a", "an", "the", "above", "said", "this" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used in the present application refers to and includes any or all possible combinations of one or more of the listed items.

[0106] Figure 1 It shows a display 10 provided by an embodiment of the present application.

[0107] The display 10 has a function of variable frequency for different regions, that is, different regions of the screen can adopt different refresh rates to balance high refresh rate and power consumption reduction. When the picture of a screen region needs to be updated, the DDIC can write data to this screen region, while for other screen regions that do not need to update the picture, the DDIC does not need to perform data writing, thereby reducing the power consumption of the driving chip. For example, as Figure 2 shown, the screen is divided into three regions. The refresh rates of the upper and lower regions are 120 Hz, and the refresh rate of the middle region is 1 Hz. The middle region is set to a low refresh rate because the picture does not need to be updated for a long time. In this way, the whole screen does not need to adopt a high refresh rate of 120 Hz, significantly reducing the power consumption of the driving chip.

[0108] The refresh rate is the number of times the display refreshes the display picture within 1 second. For example, a refresh rate of 60 Hz means that the display refreshes the display picture 60 times within 1 second.

[0109] To support the function of variable frequency for different regions, the display 10 can adopt the Gate On Array (GOA) technology. GOA can realize the function of progressive scanning drive of the display.

[0110] Such as Figure 1As shown in the figure, the display 10 may include a display circuit 21, a GOA circuit 22, and a GOA circuit 23.

[0111] Among them, the display circuit 21 may include M * N * P pixel units 210. M represents the number of enable signals connected to the GOA circuit 22, N represents the number of GOA units 220 connected to one enable signal, and P represents the number of pixel units 210 connected to one GOA unit 220, and also represents the number of pixel rows it drives. M, N, and P are positive integers.

[0112] In the embodiments of the present application, the "*" in each operation expression represents a multiplication operation. Not limited to "*", the multiplication operation can also be represented by "×".

[0113] A pixel unit 210 can be responsible for the display of one row. A pixel unit 210 may have: a data holding signal input terminal (labeled 2), a data writing control signal input terminal (labeled 1), a data signal input terminal (labeled Data), and one or more reset voltage input terminals, such as Vref1 and Vref2. Among them, the input terminal 2 is connected to the output terminal of the GOA unit 220 (labeled NScan1) in the same row, and can be used for the pixel unit 210 to receive the data holding signal (labeled S1) output by the GOA unit 220, so as to control the light-emitting diode in the pixel unit to maintain the brightness. The input terminal S2 is connected to the output terminal of the GOA unit 230 (labeled PScan1) in the same row, and can be used for the pixel unit 210 to receive the data writing control signal (labeled G1) output by the GOA unit 230, so as to enable the input terminal Data of the pixel unit to receive the data writing of the DDIC, and this data writing is reflected as the data voltage Vdata loaded on the input terminal Data. The input terminal Data can be connected to the DDIC, and can be used for the pixel unit to receive the data writing (data voltage Vdata) of the DDIC and adjust the light emission of the light-emitting component. The reset voltage input terminal can be connected to the DDIC, and can be used for the pixel unit to receive the reset voltage provided by the external (such as the DDIC) and perform a reset process. For example, the data signal is reset according to the reset voltage of the input terminal Vref1 (also known as the reset voltage Vref1), and the data signal is restored to the default value, and this default value can generally be set to a darker brightness value. For another example, the anode voltage of the light-emitting component (such as OLED) in the pixel unit is reset according to the reset voltage of the input terminal Vref2 (also known as the reset voltage Vref2).

[0114] Figure 3 Shows the basic structure of an LPTO pixel unit. As Figure 3As shown, the pixel unit 210 may include transistors M1 to M7 and a light-emitting component OLED. Among them, transistor M1 is a driving transistor, transistor M2 is a data input transistor, transistor M3 is a compensation transistor, transistors M5 and M6 are light-emitting control transistors, and transistors M4 and M7 are reset transistors. The control electrode (gate in the figure) of transistor M2 is electrically connected to input terminal 1 to access the data write control signal G1 output by the GOA unit 230. The (drain in the figure) of transistor M2 is electrically connected to input terminal Data to receive the data write (data voltage Vdata) of the DDIC. The control electrode (gate in the figure) of transistor M3 is electrically connected to input terminal 2 to access the row scan signal S1 (also known as the data holding signal) output by the GOA unit 220. The control electrodes of transistors M4 and M7 are electrically connected to the reset control terminal Reset to access the reset control signal, and their sources are connected to input terminals Vref1 and Vref2 to access the externally provided reset voltage. Figure 3 In this, Vdd and Vss may respectively represent the positive power supply and the negative power supply.

[0115] The voltage magnitudes of the reset voltage and the data voltage Vdata will affect the brightness of the light-emitting component OLED. In the embodiments of the present application, the light emission of the OLED can be adjusted by adjusting the voltage magnitudes of the reset voltage and the data voltage Vdata, so as to improve the screen display effect. This will be described in detail in subsequent embodiments and will not be elaborated here first.

[0116] Among them, the GOA circuit 22 may include M*N cascaded GOA units 220 (labeled NScan1). These M*N GOA units 220 can be connected to M enable signal lines, such as variable frequency enable (VFE) signal lines, to receive enable signals. One enable signal line is connected to N cascaded GOA units 220. Figure 1 In an example, M = 4, N = 8, a total of 32 Nscan1. Among them, the first to the eighth NScan1 are connected to the enable signal VFE1, the ninth to the sixteenth Nscan1 are connected to the enable signal VFE2, the seventeenth to the twenty-fourth Nscan1 are connected to the enable signal VFE3, and the twenty-fifth to the thirty-second Nscan1 are connected to the enable signal VFE4.

[0117] The M*N cascaded GOA units 220 may mean that the column start (startvertical, STV) signal input terminal of the (i + 1)-th GOA unit 220 is connected to the output terminal of the i-th GOA unit 220, that is, the STV signal input of the next GOA unit 220 is affected by the output of the previous GOA unit 220. i is a positive integer, and i ≤ M*N. The column start (STV) signal is also called the frame start signal. In particular,Figure 3 As shown, the STV signal input terminal of the first GOA unit 220 is connected to the STVN signal line, that is, the first row is triggered by the frame start signal STVN. The first GOA unit 220 specifically refers to the first GOA unit 220 among these M*N GOA units 220 that is connected to the first enable signal, such as the first GOA unit 220 connected to VFE1.

[0118] The output terminal of a GOA unit 220 can be connected to the input terminals 2 of P pixel units, and can be used to output the data holding signal S1 to P pixel units. Figure 1 In the example, P = 2.

[0119] Among them, the GOA circuit 23 can include M*N*P cascaded GOA units 230 (labeled as PScan1). The output terminal of a GOA unit 230 can be connected to the input terminal 1 of a pixel unit 210, and can be used to output the data writing control signal G1 to a pixel unit 210.

[0120] The M*N*P cascaded GOA units 230 can mean that the STV signal input terminal of the (j + 1)-th GOA unit 230 is connected to the output terminal of the j-th GOA unit 230, that is, the STV signal input of the next GOA unit 230 is affected by the output of the previous GOA unit 230. j is a positive integer, j ≤ M*N*P. In particular, as Figure 3 shown, the STV signal input terminal of the first GOA unit 230 is connected to the STVP signal line.

[0121] Figure 4 Briefly shown is the timing logic of the output signals and input signals of each component part of the display 10. Among them:

[0122] VFE signal: High level is valid. In the data refresh area, the VFE signal maintains a high level; in the data holding area, the VFE signal maintains a low level. When the VFE signal is valid when turned on, the data voltage Vdata can be written into the data pixel unit; when the VFE signal is invalid when turned off, the data voltage cannot be written into the data pixel unit. As Figure 4 shown, the VFE signals on the M enable signals appear successively. Among them, the high level duration (pulse width) of one VFE signal can be a*N line scan times, a is a positive integer, and the i-th VFE signal can be N line scan times later than the (i - 1)-th VFE signal. The value of N is equal to the number of stages of the GOA units 220 connected to one VFE signal line. H represents the line scan time, that is, the time to complete one row of scanning. Figure 4 The interval between two adjacent vertical dotted lines in represents 1H.

[0123] STVN signal: active high. After the VFE1 signal, the STVN signal arrives and can be input to the STV signal input terminal of the first GOA unit 220, triggering the first GOA unit 220 to output a data holding signal S1-1. As Figure 4 shown, the STVN signal has the same pulse width as the data holding signal S1 output by each GOA unit 220; the signal S1-1 is 1H later than the STVN signal. The S1-1 signal is the data holding signal output by the first GOA unit 220.

[0124] Data holding signal S1: Also known as the line scan signal. The data holding signals S1 output by each GOA unit 220 have the same pulse width. The data holding signal S1 output by the i-th GOA unit 220 is 1H or 2H earlier than the data holding signal S1 output by the (i + 1)-th GOA unit 220. Taking 1H as an example, as Figure 4 shown, S1-1, S1-2, S1-3, S1-4 respectively represent the S1 signals output by the 1st, 2nd, 3rd, and 4th GOA units 220. Among them, S1-1 is 1H earlier than S1-2, S1-2 is 1H earlier than S1-3, and S1-3 is 1H earlier than S1-4. Figure 4 Only the timing of S1-1 to S1-4 is shown in the figure, but the timing logic that S1-i is 1H or 2H earlier than S1-(i + 1) also exists in the subsequent circuit.

[0125] STVP signal: can be active high or active low. During the duration of the S1 signal, the STVP signal arrives and can be input to the STV signal input terminal of the first GOA unit 230, triggering the first GOA unit 230 to output a data write control signal G1-1. As Figure 4 shown, the STVP signal has the same pulse width as the data write control signal G1 output by each GOA unit 230; the signal G1-1 is later than the STVP signal by a second duration, such as 0.5H. The STVP signal and the data write control signal G1 have equal and relatively small pulse widths, such as 0.7H.

[0126] Data write control signal G1: The data write control signals G1 output by each GOA unit 230 have the same pulse width. The G1 signal output by the (i + 1)-th GOA unit 230 is also later than the data holding signal G1 output by the i-th GOA unit 230 by a second duration. As Figure 4 shown, G1-1, G1-2, G1-3, G1-4... G1-8 respectively represent the G1 signals output by the 1st, 2nd, 3rd, 4th... 8th GOA units 230. G1-1, G1-2, G1-3, G1-4... G1-8 arrive in sequence, and the difference between adjacent two G1 signals is the second duration.

[0127] In the embodiments of the present application, increasing the number M of VFE signals can broaden the pulse width of the data holding signal S1. There is the following relationship between the pulse width Y of the VFE signal and the pulse width X of the signal S1: M*Y≥X+(M*N - 1)*Q, where M represents the number of VFE signals, N represents the number of GOA units 220 connected to one VFE signal, and Q represents that the data holding signal S1 output by the i-th GOA unit 220 is Q row scanning times earlier than the data holding signal S1 output by the (i + 1)-th GOA unit 220, and Q can take values such as 1, 2, etc. In this relational expression, M*Y represents the maximum pulse width that can be covered by M VFE signals together, and X+(M*N - 1)*Q represents the pulse width covered by the data holding signals S1 output by all levels of GOA units 220 on M VFE signals together.

[0128] Through the limitation of this relational expression, it can be ensured that the GOA units 220 connected to M VFE signal lines can all effectively output the S1 signal. And through this relational expression, the maximum pulse width X of the signal S1 can be determined. max = M*Y-(M*N - 1)*Q. It can be seen that the larger M is, the larger X max is, that is, increasing the number of VFE signals can broaden the pulse width of the S1 signal. In this limiting formula of X max , there is also an implicit condition: Y > Q*N, that is, the pulse width of the VFE signal is greater than the width of the coupling area of the S1 signal.

[0129] Embodiment 1

[0130] This embodiment provides a method for refreshing a display in partitions, which can be applied to the Figure 1 display 10 shown. This method can broaden the pulse width of the data holding signal S1 output by the GOA unit 220, avoid the data writing for pixel units being interfered by the glitch of the S1 signal, and thus avoid the occurrence of Figure 5 the screen horizontal stripes shown.

[0131] Currently, displays with the function of partition frequency conversion are prone to generate Figure 5 the screen horizontal stripes shown.

[0132] Through research, it is found that the data holding signals S1 output by each GOA unit 220 connected to the same VFE signal will interfere with each other. The rising edge of the S1 signal output by the subsequent GOA unit 220 will cause a glitch in the S1 signal output by the previous GOA unit 220, and the glitch will affect the data writing of the pixel unit, ultimately resulting in the generation of horizontal stripes.

[0133] Figure 6 shows the signal timing diagram when the display uses 2 VFE signal lines. As Figure 6As shown, when the S1-2 signal arrives, the rising edge of the S1-2 signal causes a glitch in the S1-1 signal at that moment. Similarly, when the S1-3 signal arrives, the rising edge of the S1-3 signal causes glitches in both the S1-1 and S1-2 signals at that moment. And so on. If there are 8 GOA units 220 connected to a VFE signal line, then the S1-1 signal will have 7 glitches, affecting 8 row scanning times; the S1-2 signal will have 6 glitches, affecting 7 row scanning times. And so on.

[0134] In this article, the time period affected by glitches during the duration of an S1 signal can be called the coupling area, and the time not affected by it can be called the non-coupling area. If the GOA unit 230 outputs the G1 signal in the coupling area, then the data writing for the pixel unit will be affected, thus generating horizontal stripes on the screen. As Figure 6 shown, the coupling area of S1-1 is relatively long, and the G1-1 and G1-2 signals appear in the coupling area, which will cause horizontal stripes to be generated; the coupling area of S1-2 is also relatively long, and the G1-3 and G1-4 appear in the coupling area, which will also cause horizontal stripes to be generated; however, the coupling area of S1-3 gradually becomes shorter, and the G1-5 and G1-6 do not appear in the coupling area, so horizontal stripes will not be generated; the coupling areas of subsequent S1 signals are shorter, and the G1 signals fall in the non-coupling area, so horizontal stripes will not be generated.

[0135] As Figure 7 shown, the method for partitioned refreshing of a display provided by an embodiment of the present application may include:

[0136] S11. At time h, control the initial GOA unit 220 to output the data holding signal S1.

[0137] In other words, at time h, control the GOA circuit 22 to start outputting the data holding signal S1. The initial GOA unit 220 is the first GOA unit 220 among the cascaded M*N GOA units 220, and it is triggered by the STVN signal to output the data holding signal S1.

[0138] Among these cascaded M*N GOA units 220, the i-th GOA unit 220 specifically starts to output the data holding signal S1 at time h+(i-1)*Q*H. i is a positive integer, i≤M*N. Q represents that the i-th first GOA unit outputs the data holding signal Q row scanning times earlier than the (i + 1)-th first GOA unit, and Q can take positive integer values such as 1, 2, etc. H represents a row scanning time, which is a concept of time length, such as a few microseconds.

[0139] For example, as Figure 8As shown, the first GOA unit 220 starts to output S1-1 at time h, the second GOA unit 220 starts to output S1-2 at time h+H, the third GOA unit 220 starts to output S1-3 at time h+2*H, and the fourth GOA unit 220 starts to output S1-4 at time h+3*H.

[0140] Moreover, the data holding signal S1 output by each GOA unit 220 can last for X line scan times. X is a positive integer and X > N. That is to say, the pulse width of the data holding signal S1 is at least greater than N line scan times to ensure that the pulse width of the data holding signal S1 output by each GOA unit 220 includes the non-coupling region. Because the longest coupling region of the data holding signal S1 is equal to N line scan times and exists during the duration of the signal S1 output by the first-stage GOA unit 220 on the VFE signal line.

[0141] For example, as Figure 8 shown, S1-1 represents the signal S1 output by the first-stage GOA unit 220 on the VFE signal line, and its coupling region is the longest coupling region. When 8 GOA units 220 are connected to one VFE signal line (i.e., N = 8), S1-1 has 7 glitches, and the longest coupling region is 8 line scan times affected before and after these 7 glitches.

[0142] In this embodiment, M > 2, such as M = 4, that is, more enable signal lines are introduced into the display 10. In this way, the enable signal can be provided to the cascaded GOA units 220 for a longer time, providing conditions for broadening the pulse width of the data holding signal S1 and creating a non-coupling region.

[0143] According to the calculation formula of the maximum value X max of X, the larger X is, the larger the non-coupling region is. If the G1 signal output by the GOA unit 230 falls within the non-coupling region, the data writing for the pixel unit will not be affected by the glitches of the signal S1, and no horizontal stripe problem will occur.

[0144] S12. At time k, control the initial GOA unit 230 to output a data writing control signal G1.

[0145] In other words, at time k, the GOA circuit 23 starts to output a data writing control signal G1. The initial GOA unit 230 is the first GOA unit 230 among the cascaded M*N*P GOA units 230, and it is triggered by the STVP signal to output a data writing control signal G1.

[0146] The moment k is later than the moment h + N*H, where N*H represents the length of the longest coupling region and H represents a line scanning time, such as a few microseconds. This setting enables the data write control signal G1 to appear after the coupling region of the data hold signal S1, so as to ensure that the data writing to the pixel unit is not affected by the glitch of S1 and there will be no horizontal streaks on the screen.

[0147] Moreover, the moment k is earlier than the moment h + X*H. As described above, X represents the duration of the data hold signal S1. This setting enables the data write control signal G1 to be generated before the end of the data hold signal S1, ensuring normal data writing.

[0148] As Figure 8 shown, among the cascaded M*N*P GOA units 230, the first GOA unit 230 starts to output the data write control signal G1-1 at the moment k, the second GOA unit 230 starts to output the data write control signal G1-2 at the moment k + q, and the third GOA unit 230 starts to output the data write control signal G1-3 at the moment k + 2*q. And so on, the j-th GOA unit 230 starts to output the data write control signal G1 at the moment k+(j - 1)*q. q represents the time delay of the data write control signal G1 output by the j-th GOA unit 230 relative to the data write control signal G1 output by the (j - 1)-th GOA unit 230, that is, the aforementioned second duration.

[0149] The duration of the data write control signal G1 is very short and the pulse width is narrow. Two adjacent GOA units 230 can successively complete the output of the G1 signal within the same line scanning time H, which can be referred to Figure 8 .

[0150] The method for partitioned refreshing of a display provided by the embodiments of the present application may further include the following steps:

[0151] At the moment h - Q*H, provide the STVN signal, that is, transmit the STV signal to the input end of the initial GOA unit 220 to trigger the initial GOA unit 220 to output the data hold signal S1 at the moment h. Q represents that the i-th first GOA unit outputs the data hold signal Q line scanning times earlier than the (i + 1)-th first GOA unit, and its value can be a positive integer such as 1, 2, etc.

[0152] At the moment k - q, provide the STVP signal, that is, transmit the STV signal to the input end of the initial GOA unit 230 to trigger the initial GOA unit 230 to output the data write control signal G1 at the moment k.

[0153] In addition, the method may further include: before time h - H, controlling the VFE signal line to start providing the VFE signal. The VFE signal on each VFE signal line lasts for Y line scan times (H). For example, as Figure 8 shown, controlling the first VFE signal line to start providing the VFE signal at time s, controlling the second VFE signal line to start providing the VFE signal at time s + N, controlling the third VFE signal line to start providing the VFE signal at time s + 2*N, and controlling the fourth VFE signal line to start providing the VFE signal at time s + 3*N. And so on, the wth VFE signal line starts providing the VFE signal at time s+(w - 1)*N. N represents the time delay of the ith VFE signal relative to the (i - 1)th VFE signal, and its value is equal to the number of stages of the GOA unit 220 connected to one VFE signal line.

[0154] The method for refreshing the display area provided by the embodiment of the present application can be executed by the DDIC connected to the display 10, or by a display system including the display 10 and the DDIC, or by an electronic device including the display 10 and the DDIC.

[0155] This embodiment also provides the following steps to avoid the falling edge of signal S1 being affected by the falling edge of the VFE signal: controlling the time when the VFE signal on the Mth VFE signal line switches from high level to low level to be equal to or later than a specific time, where the specific time is the time when the signal S1 output by the last GOA unit 220 connected to the VFE signal switches from high level to low level. In this way, the falling edge of the VFE signal will be later than the falling edge of the last-stage S1 signal on the VFE signal line, which can avoid the influence of the level drop of S1 by the VFE drop, thereby avoiding Figure 9 the screen dark line problem shown.

[0156] This requires that there is the following relationship between the pulse width Y of a single VFE signal and the pulse width X of the signal S1 output by a single GOA unit 220: Y≥X+(N - 1)*Q. Wherein, N represents the number of GOA units 220 connected to one VFE signal, and Q represents that the data holding signal S1 output by the ith GOA unit 220 is Q line scan times earlier than the data holding signal S1 output by the (i + 1)th GOA unit 220, and Q can take values such as 1, 2, etc. In this relational expression, X+(N - 1)*Q represents the pulse width covered by the data holding signals S1 output by all stages of GOA units 220 on one VFE signal together. Through the limitation of this relational expression, it can be ensured that the falling edge of a VFE signal is later than the falling edge of the S1 signal output by the last-stage GOA unit on the VFE signal line, and the screen dark line problem can be avoided.

[0157] The method steps provided in this embodiment can be combined with other embodiments. For example, when combined with Embodiment 2, more problems during variable frequency of display partitions can be comprehensively solved.

[0158] Embodiment 2

[0159] This embodiment provides a method for refreshing display partitions, which can be applied to Figure 1 the display 10 shown in the figure. By adjusting the reset voltage Vref of the pixel unit, the brightness difference between different screen partitions can be improved, and screen flicker can be avoided.

[0160] Figure 10 The figure shows the brightness difference problem of different screen partitions: the area with a lower refresh rate has a higher brightness than the area with a higher refresh rate. Among them, A, B, and C represent three screen partitions. The reason for the brightness difference problem is that: as Figure 11 shown in the figure, when the DDIC writes picture data to the display (write frame), the display brightness is low, and when the DDIC does not write picture data to the display (hold frame), the display brightness is high; at a low refresh rate, such as 1Hz, the hold frames are significantly more than the write frames; while at a high refresh rate, such as 120Hz, the write frames are significantly more than the hold frames. Therefore, the brightness of the low refresh rate area will be significantly higher than that of the high refresh rate area. Moreover, when switching from the hold frame to the write frame or from the write frame to the hold frame, the brightness difference will cause screen flicker.

[0161] This embodiment improves the brightness difference between different screen partitions through the following strategies, which are briefly summarized as follows:

[0162] Strategy 1: When writing data to the pixel unit, the Vref of the screen area with a low refresh rate biases the voltage with reference to the Vref of the screen area with a high refresh rate, so that the brightness of the low refresh rate area is adjusted to the brightness of the high refresh rate area, unifying the screen brightness and saving the power consumption of the display at the same time. The method can be referred to Figure 12 the method shown in the figure;

[0163] Strategy 2: For the screen area with a high refresh rate, the Vref of the hold frame biases the voltage with reference to the Vref of the write frame, so that the high brightness during the hold frame is adjusted to the low brightness during the write frame, and the screen brightness can be kept unchanged when switching between the hold frame and the write frame, avoiding the screen flicker problem. The method can be referred to Figure 14 the method shown in the figure;

[0164] Strategy 3: For the screen area with a low refresh rate, the Vref of the hold frame biases the voltage with reference to the Vref of the write frame, so that the high brightness during the hold frame is adjusted to the low brightness during the write frame, and the screen brightness can be kept unchanged when switching between the hold frame and the write frame, avoiding the screen flicker problem of the low refresh rate screen. The method can also be referred to Figure 14 the method shown in the figure.

[0165] Such asFigure 12 As shown, the method for refreshing the display partition provided in this embodiment may include:

[0166] S21. Determine the time for writing data to the pixel units in the first screen area, that is, the time range of the write frame.

[0167] Exemplarily, it is possible to determine when to start writing data according to the refresh rate, and the duration of the next write frame is known under the known refresh rate.

[0168] S22. When writing data to the pixel units in the first screen area, perform a first biasing process on the reset voltage Vref of the pixel units in the first screen area. The Vref after the first biasing process is the reset voltage corresponding to the first reference brightness at the first refresh rate during data writing. In this way, the brightness of the first screen area with a low refresh rate during data writing can be adjusted to the first reference brightness.

[0169] In the implementation of this application, the first reference brightness may be less than the brightness corresponding to the reset voltage Vref of the pixel units in the first screen area before the first biasing process at the first refresh rate, so as to reduce the brightness of the first screen area with a low refresh rate and save the power consumption of the display.

[0170] There are different corresponding relationships between the brightness during data writing and the reset voltage Vref at different refresh rates. Moreover, this corresponding relationship can also be measured and recorded in advance for adjusting the reset voltage during data writing to unify the screen brightness.

[0171] Figure 13 Shows the mapping relationship between the brightness and Vref1 at 1Hz and 120Hz during data writing. As Figure 13 shown, at these two refresh rates, during data writing, the larger the Vref1 (absolute value), the greater the brightness; generally, for the same Vref1, the brightness at 1Hz is higher than that at 120Hz. During data writing, at the same brightness, the Vref1 of the pixel units in the low refresh rate area is smaller than that of the pixel units in the high refresh rate area. For example, during data writing, to achieve a reference brightness of 8.0nits, the Vref1 at 120Hz is set to about 1.0V, while the Vref1 at 1Hz is set to about 0.5V. Figure 13 The various numerical values in [] are only for illustration to facilitate readers' understanding of the solution and should not constitute a limitation to the embodiments of this application.

[0172] Similarly, during data writing, there is also a mapping relationship between the brightness and the reset voltage Vref2 at different refresh rates.

[0173] Figure 13The corresponding relationship between the brightness and the reset voltage Vref at different refresh rates during data writing is schematically shown in a curve graph, where one curve is equivalent to a mapping table of the brightness and the reset voltage Vref. Without limitation, this corresponding relationship can also be recorded in a mapping table. The data representation form of this corresponding relationship is not limited in the embodiments of the present application.

[0174] In the implementation of the present application, the first reference brightness can specifically be the brightness corresponding to the first reset voltage at the second refresh rate during data writing. The first reset voltage is the reset voltage of the pixel units in the second screen area when data is written to the second screen area at the second refresh rate, and it can be measured by the DDIC. The first refresh rate is lower than the second refresh rate. In this way, the brightness of the first screen area with a low refresh rate can be adjusted to the brightness of the second screen area with a high refresh rate, so as to unify the brightness of different refresh rate partitions and improve the brightness difference.

[0175] The second screen area can specifically be the screen area with the highest refresh rate, which is more conducive to saving the power consumption of the display.

[0176] The method for refreshing the display in partitions provided in this embodiment may further include the following steps: S23. Determine the refresh rates of each area of the screen; S24. Select the reset voltage of the pixel units in the second screen area as the first reset voltage; S25. In the first mapping table, find the brightness corresponding to the first reset voltage, and determine the found brightness as the first reference brightness; S26. In the second mapping table, find the reset voltage corresponding to the first reference brightness, and determine the found reset voltage as the reset voltage Vref after the first bias processing, which is used for the aforementioned step S22.

[0177] Among them, the first mapping table may record the brightness when the pixel units use different reset voltages Vref during data writing at the second refresh rate; the second mapping table may record the brightness when the pixel units use different reset voltages Vref during data writing at the first refresh rate.

[0178] The first reference brightness may not be the brightness of any screen partition, but only a default brightness, so that the brightness of each screen partition can be adjusted to this empirical brightness, thereby realizing the unification of the screen brightness.

[0179] As Figure 14 shown, the method for refreshing the display in partitions provided in this embodiment may include:

[0180] S31. Determine the time when data writing is not performed on the pixel units in the third screen area, that is, the time range of the hold frame. The refresh rate of the third screen area is the third refresh rate.

[0181] Exemplarily, it is possible to determine when data writing will not be performed according to the third refresh rate, and the duration of maintaining a frame at a known refresh rate is fixedly known.

[0182] S32. When data writing is not performed on the pixel units in the third screen area, a second biasing process is performed on the reset voltage Vref of the pixel units in the third screen area, and the Vref after the second biasing process is the reset voltage corresponding to the second reference brightness during data holding at the third refresh rate.

[0183] Among them, the second reference brightness may be the brightness corresponding to the second reset voltage during data writing at the third refresh rate. The second reset voltage is the reset voltage when data is written to the third screen area at the third refresh rate and can be measured by the DDIC. In this way, the brightness of the third screen area during data holding can be adjusted to the brightness of the third screen area during data writing, so that the brightness of the third screen area does not jump during the switching between data holding and data writing, avoiding screen flickering.

[0184] Figure 15 A curve graph schematically shows the corresponding relationship between the brightness and the reset voltage Vref at different refresh rates during data holding. One of the curves is equivalent to a mapping table of the brightness and the reset voltage Vref. This corresponding relationship can be measured and recorded in advance for adjusting the reset voltage during data holding. Based on this corresponding relationship, the brightness value corresponding to a certain reset voltage at a specific refresh rate during data writing can be determined, and the reset voltage corresponding to a certain brightness at a specific refresh rate during data writing can also be determined.

[0185] The method for display area refreshing provided in this embodiment may further include the following steps: S33. Determine the time for performing data writing on the third screen area; S34. Take the reset voltage when data is written to the third screen area at the third refresh rate as the second reset voltage; S35. In the third mapping table, find the brightness corresponding to the second reset voltage, and determine the found brightness as the second reference brightness; S36. In the fourth mapping table, find the reset voltage corresponding to the second reference brightness, and determine the found reset voltage as the reset voltage Vref after the second biasing process for the foregoing step S32.

[0186] Among them, the third mapping table may record the brightness when different reset voltages Vref are used for the pixel units during data writing at the third refresh rate; the fourth mapping table may record the brightness when different reset voltages Vref are used for the pixel units during data holding at the third refresh rate.

[0187] The third screen area may be a screen area with a low refresh rate, such as the aforementioned first screen area; at this time, the third refresh rate is a low refresh rate, which may be the same as the aforementioned first refresh rate, and the third mapping table may be the same as the aforementioned second mapping table. The third screen area may also be a screen area with a high refresh rate, such as the aforementioned second screen area; at this time, the third refresh rate is a high refresh rate, which may be the same as the aforementioned second refresh rate, and the fourth mapping table may be the same as the aforementioned first mapping table.

[0188] When the third screen area is a screen area with a low refresh rate, the second reset voltage may further be the reset voltage after the first biasing process in step S22. That is, for the screen area with a low refresh rate, the reset voltage can be biased once (i.e., the first biasing process) with reference to the first reference brightness (such as the brightness of the screen area with a high refresh rate) during data writing to solve the problem of different brightness between the low refresh rate area and the high refresh rate area during data writing and save power consumption; then, during data holding, the reset voltage is biased again (i.e., the first biasing process) with reference to the second reference brightness (such as the brightness during data writing) to solve the problem of different brightness between data holding and data writing and save power consumption.

[0189] The above steps S31 - step S32 can be combined into Figure 12 the method shown to take into account the solution of the brightness difference problem of each screen partition and the screen flicker problem.

[0190] In the embodiments of the present application, biasing the reset voltage means adjusting the magnitude of the reset voltage to adjust to the target voltage that can achieve the reference brightness, such as the reset voltage corresponding to the first reference brightness at the first refresh rate during data writing mentioned in the above step S22, and the reset voltage corresponding to the second reference brightness at the first refresh rate during data holding mentioned in the above step S22. The reset voltage may include one or more of the aforementioned Vref1 and Vref2, and is not limited thereto. It may also include other reset voltages, specifically depending on the circuit structure of the pixel unit.

[0191] Figure 16 Exemplarily shows the biasing amount of the reset voltage used to achieve the same brightness in different refresh rate areas during data writing and data holding. As Figure 16 shown, during data writing, to achieve the same brightness, the biasing amount of Vref1 in the low refresh rate area relative to Vref1 in the high refresh rate area is △V11; in the same high refresh rate area, to keep the brightness from jumping, the biasing amount of Vref1 during data holding relative to Vref1 during data writing is △V12; in the same low refresh rate area, to keep the brightness from jumping, the biasing amount of Vref1 during data holding relative to Vref1 during data writing is △V13. As Figure 16As shown, △V13 is determined based on Vref1 after the first bias processing (with △V11 added) during data writing, so as to take into account and solve the problem of brightness difference between the low-refresh-rate area and the high-refresh-rate area during data writing, as well as the problem of brightness jump in the low-refresh-rate area during data retention and data writing. Figure 16 The bias processing of Vref2 is also shown in [reference], which can refer to Vref1 and will not be elaborated here. Figure 16 It is only used to explain the embodiments of the present application. The number of screen partitions, the number of reset voltages, the magnitude of the bias amount, the bias direction, etc. shown therein do not constitute a limitation to the embodiments of the present application. In the embodiments of the present application, the bias amount can take values between -10V and +10V.

[0192] In the embodiments of the present application, for the pixel units in the entire screen area, the number of times of bias processing (including the first bias processing and the second bias processing) of the reset voltage per unit time depends on the number of screen partitions, the number of reset voltages, and the number of holding frames.

[0193] The method for refreshing the display area provided in this embodiment can be executed by a display system including the display 10 and the DDIC, or by an electronic device including the display 10 and the DDIC.

[0194] Embodiment 3

[0195] This embodiment provides a method for refreshing the display area, which can be applied to Figure 1 the shown display 10. By adjusting the data voltage Vdata of the pixel unit, the brightness difference between the high-refresh-rate area and the low-refresh-rate area under the same gray level can be improved.

[0196] The brightness of pixel units of the same gray level in different refresh-rate areas may not be consistent, which will result in inconsistent presentation effects of the same gray level in different screen areas. For example, pixel unit a in the high-refresh-rate area and pixel unit b in the low-refresh-rate area are to present the same gray level, but the actual brightness values of a and b are inconsistent, which affects the overall expression of the picture gray scale.

[0197] This embodiment improves the brightness difference of the same gray level in different refresh-rate areas through the following strategies, which are briefly summarized as follows: for the same gray level, the Vdata of the low-refresh-rate screen area refers to the Vdata of the high-refresh-rate screen area to perform voltage bias, so that the performance of the same gray level in the low-refresh-rate area and the high-refresh-rate area is consistent, and at the same time, the power consumption of the display can be reduced. Reference can be made to Figure 17 the shown method.

[0198] As Figure 17 shown, the method for refreshing the display area provided in this embodiment may include:

[0199] S41. Determine the gray level of the pixel units in the first screen area.

[0200] Exemplarily, the gray levels of the pixel units in each screen area can be determined according to the gray scale information of the screen to be refreshed. The gray level of a pixel is the gray scale value of the pixel, which represents the brightness presented by the pixel in the screen. This step can be executed by the DDIC or by the SOC and then the result is transmitted to the DDIC.

[0201] S42. When performing data writing to the first pixel unit in the first screen area, perform a third biasing process on the data voltage Vdata of the first pixel unit. The Vdata after the third biasing process is the data voltage Vdata corresponding to the third reference brightness at the first refresh rate during data writing. The first pixel unit is the pixel unit with the first gray level in the first screen area.

[0202] Among them, the third reference brightness is the brightness corresponding to the first Vdata at the second refresh rate. The first Vdata is the Vdata when data is written to the second pixel unit at the second refresh rate, and it can be measured by the DDIC. The second pixel unit is the pixel unit with the first gray level in the second screen area. The refresh rate of the second screen area is the second refresh rate, and the second refresh rate is greater than the first refresh rate. In this way, during data writing, the brightness of a gray level in the low refresh rate area can be adjusted to the brightness of the gray level in the high refresh rate area, so that the performance of the same gray level in the low refresh rate area and the high refresh rate area is consistent, and at the same time, the power consumption of the display can be reduced.

[0203] Figure 18 A curve graph schematically shows the corresponding relationship between the brightness and the data voltage Vdata at different refresh rates during data writing. One of the curves is equivalent to a mapping table of the brightness and the data voltage Vdata. This corresponding relationship can be measured and recorded in advance for adjusting the data voltage Vdata. Based on this corresponding relationship, the brightness value corresponding to a certain data voltage Vdata at a specific refresh rate can be determined, and the data voltage Vdata corresponding to a certain brightness at a specific refresh rate can also be determined.

[0204] The method for area refresh of the display provided in this embodiment may further include the following steps: S43. Determine the refresh rates of each area of the screen; S44. Select the pixel unit with the first gray level (i.e., the aforementioned second pixel unit) from the second screen area, and use the Vdata of this pixel unit as the first Vdata; S45. In the fifth mapping table, find the brightness corresponding to the first Vdata, and determine the found brightness as the third reference brightness;

[0205] S46. In the sixth mapping table, find the Vdata corresponding to the third reference brightness, and determine the found Vdata as the Vdata after the third offset processing for use in the aforementioned step S42.

[0206] Among them, the fifth mapping table can record the brightness when different Vdatas are adopted by pixel units during data writing at the second refresh rate; the sixth mapping table can record the brightness when different Vdatas are adopted by pixel units during data writing at the first refresh rate.

[0207] In the embodiments of the present application, performing offset processing on the data voltage Vdata means adjusting the magnitude of the data voltage Vdata to an objective voltage capable of achieving the reference brightness, such as the Vdata corresponding to the third reference brightness during data writing at the first refresh rate mentioned in the above step S42.

[0208] Figure 19 Exemplarily shows the offset amounts of Vdatas adopted by pixel units achieving the same gray level in different refresh rate regions. For example Figure 19 As shown, to achieve gray level 1, the offset amount of Vdata in the low refresh rate region relative to Vdata in the high refresh rate region is △V1; to achieve gray level 2, the offset amount of Vdata in the low refresh rate region relative to Vdata in the high refresh rate region is △V2; to achieve gray level 3, the offset amount of Vdata in the low refresh rate region relative to Vdata in the high refresh rate region is △V3; to achieve gray level 4, the offset amount of Vdata in the low refresh rate region relative to Vdata in the high refresh rate region is △V4. Figure 19 It is only used to explain the embodiments of the present application, and the number of screen partitions, the number of gray levels, the magnitude of the offset amount, the offset direction, etc. shown therein do not constitute a limitation on the embodiments of the present application. In the embodiments of the present application, the offset amount of the data voltage can take values between -10V and +10V.

[0209] In the embodiments of the present application, for the pixel units in the entire screen area, the number of times of performing offset processing on Vdata per unit time depends on the number of screen partitions and the number of gray levels.

[0210] The method for refreshing the display partition provided in this embodiment can be executed by a display system including the display 10 and the DDIC, or by an electronic device including the display 10 and the DDIC.

[0211] Embodiment 4

[0212] This embodiment provides a method for refreshing the display partition, which can be applied to Figure 1 the display 10 shown, and the screen flicker can be improved by adjusting the data voltage Vdata of the pixel unit.

[0213] In this embodiment, the following strategies are adopted to improve screen flickering, which are briefly summarized as follows:

[0214] Strategy 1: For the screen area with high refresh rate, keep the Vdata reference of the hold frame biased to the Vdata execution voltage of the write frame, so that the high brightness during the hold frame is adjusted to the low brightness during the write frame. This can keep the screen brightness from jumping when switching between the hold frame and the write frame, avoiding the screen flickering problem. Refer to the method shown in Figure 20 the figure;

[0215] Strategy 2: For the screen area with low refresh rate, keep the Vdata reference of the hold frame biased to the Vdata execution voltage of the write frame, so that the high brightness during the hold frame is adjusted to the low brightness during the write frame. This can keep the screen brightness from jumping when switching between the hold frame and the write frame, avoiding the screen flickering problem. Refer to the method shown in Figure 20 the figure.

[0216] As shown in Figure 20 the figure, the method for partitioned refreshing of the display provided in this embodiment may include:

[0217] S51. Determine the time when data writing is not performed on the pixel units in the fourth screen area, that is, the time range of the hold frame. The refresh rate of the fourth screen area is the fourth refresh rate.

[0218] Exemplarily, it is possible to determine when data writing will not be performed according to the fourth refresh rate, and the duration of the next hold frame is known under the known refresh rate.

[0219] S52. When data writing is not performed on the pixel units in the fourth screen area, perform a fourth biasing process on the data voltage Vdata of the third pixel units in the fourth screen area. The Vdata after the fourth biasing process is the data voltage Vdata corresponding to the fourth reference brightness during data holding at the fourth refresh rate.

[0220] Among them, the fourth reference brightness may be the brightness corresponding to the second Vdata when data writing is performed on the fourth screen area at the fourth refresh rate. The second Vdata is the Vdata when the third pixel units are written with data at the fourth refresh rate and can be measured by the DDIC. In this way, the brightness of the third pixel units during data holding can be adjusted to the brightness of the third pixel units during data writing, and the brightness of the third pixel units can be kept from jumping when switching between data holding and data writing, avoiding screen flickering.

[0221] The gray levels of different pixel units in the fourth screen area may be different, and the Vdata of different pixel units will also be different. Therefore, in the embodiment of the present application, the Vdata during data holding is specifically biased with respect to the Vdata during data writing in units of pixel units.

[0222] Figure 21 The corresponding relationship between the luminance and the data voltage Vdata at different refresh rates during data retention is schematically shown in a curve graph. One of the curves is equivalent to a mapping table of the luminance and the data voltage Vdata. This corresponding relationship can be measured and recorded in advance for use in adjusting the data voltage during data retention. Based on this corresponding relationship, the luminance value corresponding to a certain data voltage at a specific refresh rate during data retention can be determined, and the data voltage corresponding to a certain luminance at a specific refresh rate during data retention can also be determined.

[0223] The method for partitioning and refreshing the display provided in this embodiment may further include the following steps: S53. Determine the time when data writing is not performed on the fourth screen area; S54. Use the data voltage when data is written to the fourth screen area at the fourth refresh rate as the second Vdata; S55. In the seventh mapping table, find the luminance corresponding to the second Vdata, and determine the found luminance as the fourth reference luminance; S56. In the eighth mapping table, find the data voltage corresponding to the fourth reference luminance, and determine the found data voltage as the data voltage Vref after the fourth bias processing for the foregoing step S52.

[0224] Among them, the seventh mapping table may record the luminance when different data voltages Vdata are adopted by pixel units during data writing at the fourth refresh rate; the eighth mapping table may record the luminance when different data voltages Vdata are adopted by pixel units during data retention at the fourth refresh rate.

[0225] The fourth screen area may be a screen area with a low refresh rate, such as the foregoing first screen area; at this time, the fourth refresh rate is a low refresh rate, which may be the same as the foregoing first refresh rate, and the seventh mapping table may be the same as the foregoing sixth mapping table. The fourth screen area may also be a screen area with a high refresh rate, such as the foregoing second screen area; at this time, the fourth refresh rate is a high refresh rate, which may be the same as the foregoing second refresh rate, and the eighth mapping table may be the same as the foregoing fifth mapping table.

[0226] When the fourth screen area is a screen area with a low refresh rate, the second Vdata may further be the data voltage after the third bias processing in step S42. That is, for a screen area with a low refresh rate, the data voltage can be biased once (i.e., the third bias processing) with reference to the third reference luminance (such as the luminance of a screen area with a high refresh rate) during data writing to solve the problem of different luminances between the low-refresh-rate area and the high-refresh-rate area during data writing and save power; then, the data voltage can be biased again (i.e., the fourth bias processing) with reference to the fourth reference luminance (such as the luminance during data writing) during data retention to solve the problem of different luminances between data retention and data writing and save power.

[0227] The above steps S51 - S52 can be incorporated into Figure 17 the method shown, taking into account the brightness difference problem of each screen partition and the solution to the screen flicker problem.

[0228] Figure 22 Exemplarily shown is the bias amount of the data voltage Vdata used to achieve the same brightness in different refresh rate regions during data writing and data holding. As Figure 22 shown, in the same high refresh rate region, to keep the brightness from jumping, the bias amount of Vdata during data holding relative to Vdata during data writing is △V1. Figure 21 In, during data writing, the Vdata in the low refresh rate region can be the data voltage after the third bias processing in step S42. Figure 22 It is also shown in that, during data holding, the bias amount of Vdata in the low refresh rate region relative to Vdata in the high refresh rate region is △V2 to unify the brightness of the screen regions with different refresh rates during data holding. During data writing, Vdata reflects the gray scale difference; during data holding, Vdata does not reflect the gray scale difference. △V1 can be the difference between Vdata during data holding and the highest Vdata during data writing (such as the Vdata of 0 gray scale pixels). Figure 22 It is only used to explain the embodiments of the present application. The number of screen partitions, the number of gray scales, the size of the bias amount, the bias direction, etc. shown therein do not constitute a limitation to the embodiments of the present application. In the embodiments of the present application, the bias amount of the data voltage can take values between - 10V and + 10V.

[0229] In the embodiments of the present application, for the pixel units in the entire screen region, the number of times of bias processing of Vdata per unit time depends on the number of screen partitions, the number of gray scales, and the number of holding frames.

[0230] The above - mentioned method embodiments can be combined with each other to comprehensively solve more problems generated during the variable frequency of the display partitions.

[0231] Based on the method for refreshing display partitions provided in the above embodiments, the display system and electronic device provided in the embodiments of the present application are introduced below.

[0232] Figure 23 Shown is the display system 60 provided in the embodiments of the present application. As Figure 23 shown, the display system 60 may include: a display 61 and a control circuit 62.

[0233] Among them, the display 61 may include a plurality of pixel units. It can be an organic light - emitting diode (OLED) display panel, where each pixel unit includes an OLED. The display 61 can be Figure 1 the display 10 described in the embodiment.

[0234] Among them, the control circuit 62 may include a display driver circuit, such as a DDIC, for controlling and driving the display 61 to display. Its main function is to send driving signals and data to the display 61 in the form of electrical signals. By controlling the brightness and color, the image information can be presented on the display 61. The control circuit 62 may also include a circuit part for timing control, such as a time controller (TCON). The timing controller can set the timing of the control signal and the data signal, and transmit the control signal and the data signal to the display driver circuit according to the timing. The control signal may be, for example, the VFE signal, the STVP signal, and the STVN signal mentioned in the foregoing method embodiments. Once the timing of the STVP signal and the STVN signal is determined, the timing of the S1 signal output by the GOA unit 220 and the G1 signal output by the GOA unit 230 is also determined.

[0235] A storage unit may also be provided in the control circuit 62 to store the code instructions of the method for refreshing the display partition provided in the embodiments of the present application. When the code instructions are read from the storage unit and run, the display system 60 can execute the method.

[0236] The control circuit 62 can be implemented by hardware, software, or a combination of hardware and software, and can be implemented by, for example, digital logic circuits and registers that execute the functions described in the foregoing method embodiments. The control circuit 62 can be implemented as one or more chips. When it is implemented as one chip, its various functions are integrated in this chip; when it is implemented as multiple chips, such as a chip system, its various functions can be separately integrated into different independent chips.

[0237] Figure 24 The electronic device 100 provided in the embodiments of the present application is shown.

[0238] In the embodiments of the present application, the device type of the electronic device 100 may be a mobile phone, a tablet computer, a handheld computer, a desktop computer, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), and smart home devices such as a smart large screen and a smart speaker, wearable devices such as a smart bracelet, a smart watch, and smart glasses, extended reality (XR) devices such as augmented reality (AR), virtual reality (VR), and mixed reality (MR), in-vehicle devices, or smart city devices, etc.

[0239] As Figure 24 shown, the electronic device 100 may include: a processor 110, a memory 120, a display 130, a display driver integrated circuit (DDIC) 140, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone jack 170D, a sensor module 180, a button 190, a motor 191, an indicator 192, a camera 193, and a subscriber identification module (SIM) card interface 195, etc. Among them, the sensor module 180 may include a gyro sensor 180B, an acceleration sensor 180E, and a touch sensor 180K, etc. Each component in the electronic device 100 may be connected through a bus.

[0240] Among them, the processor 110 may be one or more, and they may be integrated within an integrated circuit of a system on chip (SOC). The SOC is a system-level chip. The processor 110 may include a central processing unit (CPU), a graphic processing unit (GPU), and a display driver integrated circuit (DDIC). The CPU may be an application processor (AP). The CPU and the GPU may be used to render and synthesize the picture to be sent to the display 130. The processor 110 may further include a neural-network processing unit (NPU), a modulation and demodulation processor, etc.

[0241] The processor 110 may include one or more interfaces, such as an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a general-purpose input / output (GPIO) interface, a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc.

[0242] A cache memory may be provided inside the processor 110, which can be used to store the instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to use the instruction or data again, it can be directly called from the cache memory, which can reduce the waiting time of the processor 110 and improve the program running efficiency.

[0243] Among them, the memory 120 may include a program storage area and a user data storage area. The program storage area can store an operating system and one or more application programs (such as game applications), and the data storage area can store the data created by the user during the use of the electronic device 100 (such as photos, contacts). The memory 120 can be a high-speed random access memory or a non-volatile memory, such as a disk, a flash memory, a universal flash storage (UFS), etc. The memory 120 can also be an external memory card, such as a Micro SD card.

[0244] The memory 120 may also store the code instructions of the method for refreshing the display partition provided in the embodiments of the present application. When the processor 110 reads the code instructions from the memory 120 and runs the code instructions, the electronic device 100 can execute the method.

[0245] The memory 120 can also be integrated with the processor 110 in the integrated circuit of the SOC.

[0246] The electronic device 100 can implement the display function through the SOC, the DDIC 140, and the display 130, etc.

[0247] Among them, the display 130 can have a zoning variable frequency function and can be the display 10 described in the foregoing embodiments. The display 130 may include a display panel, a timing controller (TCON), etc. Among them, the display panel may include a plurality of pixel units, which may be an organic light emitting diode (OLED) display panel, and each pixel unit includes an OLED. The TCON is mainly used to connect the GPU or SOC to the display panel. After receiving the image data or control signal transmitted from the GPU or SOC, it sets the timing of the control signal and data signal according to the relevant data or signal, and transmits the control signal and data signal to the display driver circuit according to the timing, so as to achieve the purpose of driving the display panel to perform graphic display.

[0248] Among them, the display driver integrated circuit (DDIC) 140 can be used as the control core of the display 130, drive the display 130 to work, and receive data from the SOC (processor 110), such as image data and some instructions. The DDIC 140 can send drive signals and data to the display panel of the display 130 in the form of electrical signals, and then realize the control of the screen brightness and color, so that image information such as letters and pictures can be displayed on the screen to complete the screen refresh.

[0249] The image data of the picture to be displayed sent by the SOC to the DDIC 140 can be sent to the frame buffer (Frame Buffer) for storage to complete the display (or picture sending). Then, the DDIC 140 extracts the image data from the frame buffer and drives the display 130 to display.

[0250] The wireless communication function of the electronic device 100 can be realized by the antenna 1, antenna 2, mobile communication module 150, wireless communication module 160, modulation and demodulation processor, and baseband processor, etc.

[0251] The antenna 1 and antenna 2 are used to transmit and receive electromagnetic wave signals. Each antenna in the electronic device 100 can be used to cover a single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization rate of the antennas. For example: the antenna 1 can be multiplexed as the diversity antenna of the wireless local area network. In some other embodiments, the antenna can be used in combination with a tuning switch.

[0252] The mobile communication module 150 may provide solutions for wireless communications such as 2G / 3G / 4G / 5G applied to the electronic device 100. The mobile communication module 150 may include at least one filter, switch, power amplifier, low noise amplifier (LNA), etc. The mobile communication module 150 may receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and then transmit them to the modulation and demodulation processor for demodulation. The mobile communication module 150 may also amplify the signal modulated by the modulation and demodulation processor and convert it into electromagnetic waves through the antenna 1 for radiation. In some embodiments, at least some functional modules of the mobile communication module 150 may be provided in the processor 110. In some embodiments, at least some functional modules of the mobile communication module 150 and at least some modules of the processor 110 may be provided in the same device.

[0253] The modulation and demodulation processor may include a modulator and a demodulator. Among them, the modulator is used to modulate the low-frequency baseband signal to be transmitted into a medium-high frequency signal. The demodulator is used to demodulate the received electromagnetic wave signal into a low-frequency baseband signal. Subsequently, the demodulator transmits the demodulated low-frequency baseband signal to the baseband processor for processing. After being processed by the baseband processor, the low-frequency baseband signal is transmitted to the application processor. The application processor outputs a sound signal through an audio device (not limited to the speaker 170A, receiver 170B, etc.), or displays an image or video through the display 130. In some embodiments, the modulation and demodulation processor may be an independent device. In other embodiments, the modulation and demodulation processor may be independent of the processor 110 and be provided in the same device as the mobile communication module 150 or other functional modules.

[0254] The wireless communication module 160 may provide solutions for wireless communications applied to the electronic device 100, including wireless local area networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), Bluetooth (BT), global navigation satellite systems (GNSSs), frequency modulation (FM), near field communication (NFC), infrared (IR), etc. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on the electromagnetic wave signals, and sends the processed signals to the processor 110. The wireless communication module 160 may also receive signals to be sent from the processor 110, perform frequency modulation and amplification on them, and convert them into electromagnetic waves through the antenna 2 for radiation.

[0255] In some embodiments, antenna 1 of electronic device 100 is coupled to mobile communication module 150, and antenna 2 is coupled to wireless communication module 160, such that electronic device 100 can communicate with a network and other devices via wireless communication technologies. The wireless communication technologies may include global system for mobile communications (GSM), general packet radio service (GPRS), code division multiple access (CDMA), wideband code division multiple access (WCDMA), time-division code division multiple access (TD-SCDMA), long term evolution (LTE), BT, GNSS, WLAN, NFC, FM, and / or IR technologies, etc. The GNSS may include global positioning system (GPS), global navigation satellite system (GLONASS), beidou navigation satellite system (BDS), quasi-zenith satellite system (QZSS), and / or satellite based augmentation systems (SBAS).

[0256] Electronic device 100 can implement a shooting function via ISP, camera 193, video codec, GPU, display 130, and application processor, etc.

[0257] The ISP is used to process the data fed back by camera 193. For example, when taking a photo, the shutter is opened, and light is transmitted through the lens to the camera photosensitive element, where the optical signal is converted into an electrical signal. The camera photosensitive element transmits the electrical signal to the ISP for processing and converts it into an image visible to the naked eye. The ISP can also perform algorithm optimization on the noise, brightness, and skin of the image. The ISP can also optimize parameters such as the exposure and color temperature of the shooting scene. In some embodiments, the ISP may be disposed in camera 193.

[0258] The camera 193 is used to capture static images or videos. An object generates an optical image through the lens and projects it onto the photosensitive element. The photosensitive element can be a charge coupled device (CCD) or a complementary metal-oxide-semiconductor (CMOS) phototransistor. The photosensitive element converts the optical signal into an electrical signal, and then transfers the electrical signal to the ISP to be converted into a digital image signal. The ISP outputs the digital image signal to the DSP for processing. The DSP converts the digital image signal into an image signal in standard formats such as RGB and YUV. In some embodiments, the electronic device 100 may include one or N cameras 193, where N is a positive integer greater than 1.

[0259] The digital signal processor is used to process digital signals. In addition to processing digital image signals, it can also process other digital signals. For example, when the electronic device 100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the frequency point energy, etc.

[0260] The video codec is used to compress or decompress digital videos. The electronic device 100 can support one or more video codecs. In this way, the electronic device 100 can play or record videos in multiple encoding formats, such as Moving Picture Experts Group (MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

[0261] The NPU is a neural-network (NN) computing processor. By learning from the biological neural network structure, such as learning from the transmission mode between human brain neurons, it can quickly process the input information and can also continuously self-learn. Through the NPU, applications such as intelligent cognition of the electronic device 100 can be realized, such as image recognition, face recognition, voice recognition, text understanding, etc.

[0262] The electronic device 100 can implement audio functions through the audio module 170, the speaker 170A, the receiver 170B, the microphone 170C, the headphone jack 170D, and the application processor, etc. Such as music playback, recording, etc.

[0263] The audio module 170 is used to convert digital audio information into an analog audio signal for output, and is also used to convert analog audio input into digital audio signals. The audio module 170 can also be used to encode and decode audio signals. In some embodiments, the audio module 170 can be set in the processor 110, or some functional modules of the audio module 170 can be set in the processor 110.

[0264] The speaker 170A, also known as the "loudspeaker", is used to convert an audio electrical signal into a sound signal. The electronic device 100 can listen to music or a hands-free call through the speaker 170A.

[0265] The receiver 170B, also known as the "earpiece", is used to convert an audio electrical signal into a sound signal. When the electronic device 100 answers a call or a voice message, the voice can be listened to by bringing the receiver 170B close to the human ear.

[0266] The microphone 170C, also known as the "microphone" or "transmitter", is used to convert a sound signal into an electrical signal. When making a call or sending a voice message, the user can speak by bringing the mouth close to the microphone 170C to input the sound signal into the microphone 170C. The electronic device 100 can be provided with at least one microphone 170C. In some other embodiments, the electronic device 100 can be provided with two microphones 170C, which can not only collect sound signals but also implement a noise reduction function. In some other embodiments, the electronic device 100 can also be provided with three, four or more microphones 170C to collect sound signals, reduce noise, identify the sound source, and implement functions such as directional recording.

[0267] The headphone jack 170D is used to connect a wired headphone. The headphone jack 170D can be a USB interface or a 3.5 mm open mobile terminal platform (OMTP) standard interface, or a cellular telecommunications industry association of the USA (CTIA) standard interface.

[0268] The keys 190 include a power key, volume keys, etc. The keys 190 can be mechanical keys or touch keys. The electronic device 100 can receive key inputs to generate key signal inputs related to the user settings and function controls of the electronic device 100. The motor 191 can generate a vibration prompt. The SIM card interface 195 is used to connect a SIM card. The SIM card can be inserted into or removed from the SIM card interface 195 to achieve contact and separation from the electronic device 100.

[0269] Figure 24 The schematic structure does not specifically limit the electronic device 100. The electronic device 100 can include more or fewer components than those shown in the figure, or combine certain components, or split certain components, or have different component arrangements. The components shown in the figure can be implemented in hardware, software, or a combination of software and hardware.

[0270] The steps of the methods or algorithms described in connection with the disclosed content of the embodiments of the present application may be implemented in hardware or by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a RAM, flash memory, ROM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, removable hard disk, CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an ASIC. Additionally, the ASIC may be located in a transceiver or a relay device. Of course, the processor and the storage medium may also exist as discrete components in a radio access network device or a user equipment.

[0271] Those skilled in the art should be able to realize that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transfer of a computer program from one place to another. The storage media can be any available medium that can be accessed by a general or special computer.

[0272] The above specific embodiments have further elaborated on the objectives, technical solutions, and beneficial effects of the embodiments of the present application. It should be understood that the above are only the specific embodiments of the embodiments of the present application and are not used to limit the protection scope of the embodiments of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A method for refreshing a display partition, characterized in that: The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N levels of first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The method comprises: At time h, the first GOA unit is initially controlled to output the data holding signal, and the data holding signal lasts for X row scanning times, where X>N; At time k, the initial second GOA unit is controlled to output the data write control signal; the time k is later than time h+N*H and earlier than time h+X*H, where H represents a row scan time.

2. The method according to claim 1, characterized in that The controlling the initial first GOA unit to output the data hold signal specifically includes: among the M*N first GOA units in the cascade, controlling the i-th first GOA unit to output the data hold signal at time h+(i-1)*Q*H; i is a positive integer, i≤M*N, and Q indicates that the i-th first GOA unit outputs the data hold signal Q row scanning times earlier than the i+1-th first GOA unit.

3. The method according to claim 1 or 2, characterized in that The controlling the initial first GOA unit to output the data hold signal specifically includes: at time hQ*H, inputting a column start STV signal to the input end of the initial first GOA unit, where Q indicates that the i-th first GOA unit outputs the data hold signal Q row scan times earlier than the i+1-th first GOA unit.

4. The method according to any one of claims 1 to 3, characterized in that The maximum value of X max The calculation formula is as follows: max =M*Y-(M*N-1)*Q, wherein Y represents the pulse width of the enable signal on the enable signal line, and Q represents that the i-th first GOA unit outputs the data hold signal Q row scan times earlier than the i+1-th first GOA unit.

5. The method according to any one of claims 1 to 4, characterized in that The control of the initial second GOA unit outputting the data write control signal specifically includes: in the cascaded second GOA units, the jth second GOA unit starts to output the data write control signal at time k+(j-1)*q; q represents the delay time of the jth second GOA unit outputting the data write control signal relative to the j-1th second GOA unit; j is a positive integer, and j is less than or equal to the number of the cascaded second GOA units.

6. The method according to any one of claims 1 to 5, characterized in that The control of the initial second GOA unit outputting the data write control signal specifically includes: at time kq, inputting a column start STV signal to the input end of the initial second GOA unit; q represents the delay time of the jth second GOA unit outputting the data write control signal relative to the j-1th second GOA unit.

7. The method according to any one of claims 1 to 6, characterized in that The VFE signal is a high-level signal, and the data hold signal is also a high-level signal; the method also includes: controlling the time when the enable signal on the enable signal line switches from a high level to a low level to be later than a first time, and the first time is the time when the data hold signal output by the last first GOA unit connected to the enable signal line switches from a high level to a low level.

8. A method for refreshing a display partition, characterized in that: The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N levels of first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The method comprises: Determine the time to write data to the pixel unit of the first screen area; When data is written to the pixel units in the first screen area, a first biasing process is performed on the reset voltage of the pixel units in the first screen area, wherein the reset voltage after the first biasing process is a reset voltage corresponding to the first reference brightness at the first refresh rate when data is written; The first reference brightness is less than the brightness corresponding to the reset voltage of the pixel unit in the first screen area at the first refresh rate before the first bias processing.

9. The method according to claim 8, characterized in that The first reference brightness is specifically the brightness corresponding to the first reset voltage at the second refresh rate when data is written, and the first reset voltage is the reset voltage of the pixel unit of the second screen area when data is written to the second screen area at the second refresh rate; the second refresh rate is higher than the first refresh rate.

10. The method according to claim 9, characterized in that Also includes: The first reset voltage is measured and obtained.

11. The method according to claim 9 or 10, characterized in that The second screen area is the screen area with the highest refresh rate.

12. The method according to any one of claims 8 to 11, characterized in that Also includes: In a first mapping table, searching for a brightness corresponding to the first reset voltage, and determining the searched brightness as the first reference brightness; In a second mapping table, searching for a reset voltage corresponding to the first reference brightness, and determining the searched reset voltage as the reset voltage after the first bias processing; Among them, the first mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is written at the second refresh rate; the second mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is written at the first refresh rate.

13. A method for refreshing a display partition, characterized in that: The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N levels of first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The method comprises: Determine a time when no data is written to the pixel units in the third screen area; the refresh rate of the third screen area is a third refresh rate; When no data is written to the pixel units in the third screen area, a second biasing process is performed on the reset voltage of the pixel units in the third screen area, wherein the reset voltage after the second biasing process is a reset voltage corresponding to the second reference brightness at the third refresh rate when data is maintained; Among them, the second reference brightness is the brightness corresponding to the second reset voltage at the third refresh rate when data is written; the second reset voltage is the reset voltage when data is written to the third screen area at the third refresh rate.

14. The method according to claim 13, characterized in that Also includes: The second reset voltage is measured and obtained.

15. The method according to claim 13 or 14, characterized in that Also includes: The time for writing data to the pixel units in the third screen area is determined.

16. The method according to any one of claims 13 to 15, characterized in that Also includes: In a third mapping table, searching for a brightness corresponding to the second reset voltage, and determining the searched brightness as the second reference brightness; In a fourth mapping table, searching for a reset voltage corresponding to the second reference brightness, and determining the searched reset voltage as the reset voltage after the second bias processing; Among them, the third mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is written at the third refresh rate; the fourth mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is maintained at the third refresh rate.

17. The method according to any one of claims 13 to 16, characterized in that The third screen area is specifically the first screen area, and the third refresh rate is specifically the first refresh rate; Before performing the second biasing process, the method further includes: Determining a time to write data to pixel units in the first screen area; When data is written to the pixel units in the first screen area, a first biasing process is performed on the reset voltage of the pixel units in the first screen area, wherein the reset voltage after the first biasing process is a reset voltage corresponding to the first reference brightness at the first refresh rate when data is written; Among them, the first reference brightness is specifically the brightness corresponding to the first reset voltage at the second refresh rate when data is written, and the first reset voltage is the reset voltage of the pixel unit of the second screen area when data is written to the second screen area at the second refresh rate; the second refresh rate is higher than the first refresh rate.

18. The method according to claim 17, characterized in that Also includes: The first reset voltage is measured and obtained.

19. The method according to claim 17 or 18, characterized in that The second screen area is the screen area with the highest refresh rate.

20. The method according to any one of claims 17 to 19, characterized in that Also includes: In a first mapping table, searching for a brightness corresponding to the first reset voltage, and determining the searched brightness as the first reference brightness; In a second mapping table, searching for a reset voltage corresponding to the first reference brightness, and determining the searched reset voltage as the reset voltage after the first bias processing; Among them, the first mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is written at the second refresh rate; the second mapping table is used to record the corresponding relationship between the reset voltage and the brightness when data is written at the first refresh rate.

21. A method for refreshing a display partition, characterized in that: The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N levels of first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The method comprises: Determining the grayscale of the pixel unit of the first screen area; When data is written to a first pixel unit in the first screen area, a third bias processing is performed on a data voltage of the first pixel unit, and the data voltage after the third bias processing is a data voltage corresponding to a third reference brightness at a first refresh rate when data is written; the first pixel unit is a pixel unit having a first grayscale in the first screen area; Among them, the third reference brightness is the brightness corresponding to the first data voltage at the second refresh rate, the first data voltage is the data voltage when data is written to the second pixel unit at the second refresh rate; the second pixel unit is a pixel unit in the second screen area whose grayscale is the first grayscale, the refresh rate of the second screen area is the second refresh rate, and the second refresh rate is greater than the first refresh rate.

22. The method according to claim 21, characterized in that Also includes: The first data voltage is measured and obtained.

23. The method according to claim 21 or 22, characterized in that Also includes: In a fifth mapping table, searching for a brightness corresponding to the first data voltage, and determining the searched brightness as the third reference brightness; In a sixth mapping table, searching for a data voltage corresponding to the third reference brightness, and determining the searched brightness as the data voltage after the third bias processing; The fifth mapping table is used to record the corresponding relationship between data voltage and brightness when data is written at the second refresh rate; The sixth mapping table is used to record the corresponding relationship between data voltage and brightness when data is written at the first refresh rate.

24. A method for refreshing a display partition, characterized in that: The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N-level first GOA units, the first GOA unit is used to output a data holding signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; the method comprises: determining a time when no data is written to the pixel units of the fourth screen area; the refresh rate of the fourth screen area is a fourth refresh rate; When data writing is not performed on the pixel unit of the fourth screen area, a fourth bias processing is performed on the data voltage of the third pixel unit of the fourth screen area, and the data voltage after the fourth bias processing is a data voltage corresponding to the fourth reference brightness at the fourth refresh rate when data is maintained; Among them, the fourth reference brightness is the brightness corresponding to the second data voltage at the fourth refresh rate when data is written to the fourth screen area; the second data voltage is the data voltage when data is written to the third pixel unit at the fourth refresh rate.

25. The method of claim 24, wherein: Also includes: The second data voltage is measured and obtained.

26. The method according to claim 24 or 25, characterized in that Also includes: A time during which data writing is not performed on the fourth screen area is determined.

27. The method according to any one of claims 24 to 26, characterized in that Also includes: In a seventh mapping table, searching for a brightness corresponding to the second data voltage, and determining the searched brightness as the fourth reference brightness; In an eighth mapping table, searching for a data voltage corresponding to the fourth reference brightness, and determining the searched data voltage as the data voltage after the fourth bias processing; The seventh mapping table is used to record the corresponding relationship between data voltage and brightness when data is written at the fourth refresh rate; The eighth mapping table is used to record the corresponding relationship between data voltage and brightness when data is maintained at the fourth refresh rate.

28. The method according to any one of claims 24 to 26, characterized in that The fourth screen area is specifically the first screen area, and the fourth refresh rate is specifically the first refresh rate; Before performing the fourth biasing, the method further includes: Determining the grayscale of the pixel unit of the first screen area; When data is written to a first pixel unit in the first screen area, a third bias processing is performed on a data voltage of the first pixel unit, and the data voltage after the third bias processing is a data voltage corresponding to a third reference brightness at the first refresh rate when data is written; the first pixel unit is a pixel unit having a first grayscale in the first screen area; Among them, the third reference brightness is the brightness corresponding to the first data voltage at the second refresh rate, the first data voltage is the data voltage when data is written to the second pixel unit at the second refresh rate; the second pixel unit is a pixel unit in the second screen area whose grayscale is the first grayscale, the refresh rate of the second screen area is the second refresh rate, and the second refresh rate is greater than the first refresh rate.

29. The method of claim 28, wherein: Also includes: The first data voltage is measured and obtained.

30. The method according to claim 28 or 29, characterized in that Also includes: In a fifth mapping table, searching for a brightness corresponding to the first data voltage, and determining the searched brightness as the third reference brightness; In a sixth mapping table, searching for a data voltage corresponding to the third reference brightness, and determining the searched brightness as the data voltage after the third bias processing; The fifth mapping table is used to record the corresponding relationship between data voltage and brightness when data is written at the second refresh rate; The sixth mapping table is used to record the corresponding relationship between data voltage and brightness when data is written at the first refresh rate.

31. An electronic device, characterized in that: The device comprises a display, a processor and a memory; wherein the display is coupled to the processor, and the memory is coupled to the processor; The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N-level first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The memory is used to store computer program codes, and the computer program codes include computer instructions. When the processor executes the computer instructions, the method according to any one of claims 1 to 30 is executed.

32. A display system, characterized in that: The display system includes a display and a control circuit; The display comprises: a display circuit, a first array substrate row driving GOA circuit, and a second GOA circuit, wherein the display circuit comprises a plurality of pixel units, the first GOA circuit comprises M*N cascaded first GOA units, the first GOA circuit is connected to M enable signal lines, one enable signal line is connected to N-level first GOA units, the first GOA unit is used to output a data hold signal to the pixel unit; the second GOA circuit comprises a cascaded second GOA unit, the second GOA unit is used to output a data write control signal to the pixel unit; M, N are positive integers, M is greater than or equal to 2; The control circuit is used to call computer instructions to execute the method as claimed in any one of claims 1 to 29.

33. A computer-readable storage medium comprising instructions, characterized in that: When the instructions are executed on an electronic device, the method according to any one of claims 1 to 30 is executed.

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