Display panel and display device

Abstract

This application provides a display panel and display device, relating to the field of display technology, aimed at improving display uniformity. The display panel's fan-out area includes a first region, a second region, and a third region. The display panel includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate. The resistivity of the material of the first conductive layer is greater than the resistivity of the material of the second conductive layer. The first conductive layer includes a first data fan-out line disposed in the first region and a sixth data fan-out line disposed in the third region. The second conductive layer includes a fourth data fan-out line disposed in the first region, a second data fan-out line and a fifth data fan-out line disposed in the second region, and a third data fan-out line disposed in the third region. The first, second, and third data fan-out lines are connected sequentially, as are the fourth, fifth, and sixth data fan-out lines. The aforementioned display panel can be used to display images.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In the display panel of a Liquid Crystal Display (LCD), in order to narrow the bezel width, the data fan-out lines in the fan-out area of ​​the display panel are laid out in an interleave manner. That is, in the material of each data fan-out line, the proportion of low resistivity material is half and the proportion of high resistivity material is also half.

[0003] However, when the data fan-out lines located on both sides of the fan-out area extend to the far end of the IC, the data line impedance (SourceLoading) is too high, and the impedance difference between adjacent data fan-out lines is also large, which affects the display uniformity of the display panel located at the far end of the IC. Summary of the Invention

[0004] This application discloses a display panel and display device designed to improve display uniformity.

[0005] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0006] On one hand, a display panel is provided, comprising a display area and a fan-out area located on one side of the display area. The fan-out area includes a first wiring area and a second wiring area arranged along a first direction, the fan-out area including a boundary near the display area, the first direction being parallel to the boundary. The second wiring area includes a first region, a second region, and a third region arranged sequentially along a second direction, the second direction intersecting the first direction, the first region being closer to the display area than the third region. The display panel includes a substrate, and a first conductive layer and a second conductive layer stacked on the substrate, the resistivity of the material of the first conductive layer being greater than the resistivity of the material of the second conductive layer. The first conductive layer includes a first data fan-out line disposed in the first region, the second conductive layer includes a second data fan-out line disposed in the second region and a third data fan-out line disposed in the third region, the first data fan-out line, the second data fan-out line and the third data fan-out line being sequentially connected. The second conductive layer also includes a fourth data fan-out line disposed in the first region and a fifth data fan-out line disposed in the second region, the first conductive layer also includes a sixth data fan-out line disposed in the third region, the fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line being sequentially connected.

[0007] In embodiments of this application, the display panel includes a display area and a fan-out area located on one side of the display area. The fan-out area includes the boundary of the display area and further includes a first wiring area and a second wiring area arranged along a first direction parallel to the boundary. Along a second direction intersecting the first direction, a first region, a second region, and a third region of the second wiring area are sequentially arranged outside the display area. The display panel also includes a substrate and a first conductive layer and a second conductive layer sequentially stacked on the substrate. The resistivity of the material of the first conductive layer is greater than the resistivity of the material of the second conductive layer.

[0008] The first conductive layer includes a first data fan-out line disposed in a first region, and the second conductive layer includes a second data fan-out line disposed in a second region and a third data fan-out line disposed in a third region. The first, second, and third data fan-out lines are sequentially connected to form the second fan-out line. It can be understood that the second fan-out line comprises three segments, one of which uses the first conductive layer with higher impedance, and the other two segments use the second conductive layer with lower impedance. The second fan-out line has a higher proportion of low-impedance conductive layer material, resulting in lower resistance. This helps reduce the resistance of the data lines connected to the second fan-out line, thereby reducing the load on the traces.

[0009] The second conductive layer also includes a fourth data fan-out line disposed in the first region and a fifth data fan-out line disposed in the second region. The first conductive layer also includes a sixth data fan-out line disposed in the third region. The fourth, fifth, and sixth data fan-out lines are sequentially connected to form the first fan-out line. It can be understood that the first fan-out line comprises three segments, one of which uses the first conductive layer with higher impedance, and the other two segments use the second conductive layer with lower impedance. The first fan-out line has a higher proportion of low-impedance conductive layer material, resulting in lower resistance. This helps reduce the resistance of the data lines connected to the first fan-out line, thereby reducing the load on the traces.

[0010] Furthermore, each of the aforementioned first and second fan-out lines includes a trace in the first conductive layer and two traces in the second conductive layer. Therefore, the resistance values ​​of the first and second fan-out lines are similar, and their loads are also similar. When the first and second fan-out lines are adjacent, the data signals transmitted via the first and second fan-out lines are transmitted to the pixels at the far end of the display area (the side of the display area away from the fan-out area), which can improve the uneven display phenomenon at the far end of the display area.

[0011] In some embodiments, the orthographic projection of the first data fan-out line onto the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line onto the substrate. The orthographic projection of the third data fan-out line onto the substrate at least partially overlaps with the orthographic projection of the sixth data fan-out line onto the substrate.

[0012] In some embodiments, the first conductive layer is a light-shielding layer, and the second conductive layer is a gate conductive layer.

[0013] In some embodiments, the display panel further includes a first insulating layer disposed between the first conductive layer and the second conductive layer. A second data fan-out line passes through the first insulating layer and is connected to the first data fan-out line, and a fifth data fan-out line passes through the first insulating layer and is connected to the sixth data fan-out line.

[0014] In some embodiments, the display panel includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a source / drain conductive layer stacked sequentially. The source / drain conductive layer includes a first connection electrode and a second connection electrode. The first connection electrode passes through the second insulating layer and the first insulating layer to connect to a first data fan-out line, and also passes through the second insulating layer to connect to a second data fan-out line. The second connection electrode passes through the second insulating layer to connect to a fifth data fan-out line, and also passes through the second insulating layer and the first insulating layer to connect to a sixth data fan-out line.

[0015] In some embodiments, the source and drain conductive layers further include touch signal lines, wherein the orthographic projection of the touch signal lines on the substrate does not overlap with the orthographic projection of the first connection electrode on the substrate, and does not overlap with the orthographic projection of the second connection electrode on the substrate.

[0016] In some embodiments, the first conductive layer is a gate conductive layer and the second conductive layer is a source / drain conductive layer.

[0017] In some embodiments, the display panel further includes a third insulating layer disposed between the first conductive layer and the second conductive layer. A second data fan-out line passes through the third insulating layer and is connected to the first data fan-out line, and a fifth data fan-out line passes through the third insulating layer and is connected to the sixth data fan-out line.

[0018] In some embodiments, the display panel further includes multiple data lines disposed in the display area, arranged sequentially along a first direction. The multiple data lines include adjacent first and second data lines. The first data line is sequentially connected to a first, second, and third data fan-out line, and the second data line is sequentially connected to a fourth, fifth, and sixth data fan-out line. The difference between the sum of the resistances of the first, second, and third data fan-out lines and the sum of the resistances of the fourth, fifth, and sixth data fan-out lines is less than or equal to 20Ω.

[0019] In some embodiments, the first wiring area includes a fourth region and a fifth region arranged along a second direction, wherein the fourth region is closer to the display area than the fifth region;

[0020] The first conductive layer further includes a seventh data fan-out line disposed in the fourth region, and the second conductive layer further includes an eighth data fan-out line disposed in the fifth region, with the seventh data fan-out line connected to the eighth data fan-out line. The second conductive layer further includes a ninth data fan-out line disposed in the fourth region, and the first conductive layer further includes a tenth data fan-out line disposed in the fifth region, with the ninth data fan-out line connected to the tenth data fan-out line. The orthographic projection of the seventh data fan-out line onto the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line onto the substrate. The orthographic projection of the eighth data fan-out line onto the substrate at least partially overlaps with the orthographic projection of the tenth data fan-out line onto the substrate.

[0021] In some embodiments, the fan-out area includes a first wiring area and two second wiring areas. Along a first direction, the two second wiring areas are disposed on opposite sides of the first wiring area.

[0022] On the other hand, a display device is provided, which includes the display panel in any of the above embodiments and a controller electrically connected to the display panel.

[0023] The above-described display device has the same structure and beneficial technical effects as the display panel provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0025] Figure 1 A structural diagram of the display device provided in the embodiments of this application;

[0026] Figure 2 for Figure 1 A magnified view of multiple traces in the second wiring area;

[0027] Figure 3 for Figure 1 A magnified view of multiple traces in the first wiring area;

[0028] Figure 4 for Figure 1 A magnified view of the second wiring area in the image;

[0029] Figures 5-8 They are respectively Figure 4 The second wiring area is shown in a magnified view of regions A to D.

[0030] Figure 9 for Figure 5 A partial sectional view of a jumper along section line PP';

[0031] Figure 10 for Figure 7 A partial sectional view of a jumper along section line QQ';

[0032] Figure 11 A partial enlarged view of another second wiring area provided in an embodiment of this application;

[0033] Figure 12 for Figure 11 A partial sectional view of another type of jumper along section line PP';

[0034] Figure 13 for Figure 11 A partial sectional view of another type of jumper along section line QQ';

[0035] Figure 14 This is a partial sectional view of another type of jumper along section line PP';

[0036] Figure 15 This is a partial sectional view of another type of jumper along section line QQ';

[0037] Figure 16 for Figure 1 A magnified view of a portion of the traces on the display panel at point N. Detailed Implementation

[0038] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0039] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0042] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0043] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0044] This document describes exemplary embodiments with reference to cross-sectional views, which are intended as idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations caused, for example, by manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0045] Embodiments of this application provide a display device, which can be a liquid crystal display (LCD). Figure 1 This is a structural diagram of a display device provided in an embodiment of this application.

[0046] See Figure 1 The display device 100 includes a display panel 10 and a controller 20 electrically connected to the display panel 10. The controller 20 can be located on the non-display side of the display panel 10 and is used to control the display panel 10 to display images.

[0047] The aforementioned display device 100 can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images), and whether it contains text or images. More specifically, the embodiments described are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, aesthetic structures (e.g., displays of images of a piece of jewelry), laptops, and touch panel computers (TPCs), etc.

[0048] See also Figure 1 The display panel 10 provided in this application includes an active area (AA) 11 and a fanout area 12 located on one side of the active area 11. For example, the fanout area 12 is located below the active area 11, corresponding to the lower bezel of the display device 100. The display panel 10 also includes a source driver circuit (source IC) 30 disposed in the fanout area 12. The source driver circuit 30 is used to transmit data signals to the display panel 10, thereby controlling the image display of the display panel 10. For example, the display panel 10 provided in this application can be a touch and display driver integration (TDDI) display panel, or it can be a regular display panel without touch functionality.

[0049] The fan-out area 12 includes a boundary 120 near the display area 11, with a first direction X parallel to the boundary 120. The fan-out area 12 includes a first wiring area 1 and a second wiring area 2 arranged along the first direction X.

[0050] For example, see Figure 1 The fan-out area 12 includes a first wiring area 1 and two second wiring areas 2. Along the first direction X, the two second wiring areas 2 are disposed on opposite sides of the first wiring area 1.

[0051] Figure 2 for Figure 1 A magnified view of multiple traces in the second wiring area.

[0052] See Figure 2The second wiring area 2 includes a first area 21, a second area 22, and a third area 23 arranged sequentially along the second direction Y. The second direction Y intersects the first direction X. In the embodiments of this application, the second direction Y is perpendicular to the first direction X as an example. The first area 21 is closer to the display area 11 than the third area 23, that is, the first area 21, the second area 22, and the third area 23 are arranged sequentially on the outside of the display area 11.

[0053] See also Figure 2 The display panel 10 includes a substrate, and a first conductive layer M1 and a second conductive layer M2 stacked on the substrate. The resistivity of the material of the first conductive layer M1 is greater than that of the material of the second conductive layer M2. For example, the sheet resistance of the material of the first conductive layer M1 is greater than that of the material of the second conductive layer M2.

[0054] The first conductive layer M1 includes a first data fan-out line 41 disposed in the first region 21, and the second conductive layer M2 includes a second data fan-out line 42 disposed in the second region 22 and a third data fan-out line 43 disposed in the third region 23. The first data fan-out line 41, the second data fan-out line 42 and the third data fan-out line 43 are connected in sequence to form the second fan-out line S2.

[0055] For example, among the first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43, data fan-out lines located on the same conductive layer can be directly connected, while data fan-out lines located on different conductive layers can be connected across the film layers (also known as "jump wires"). In the embodiments of this application, the first data fan-out line 41 is disposed on the first conductive layer M1, the second data fan-out line 42 is disposed on the second conductive layer M2, and the two are connected by a jumper wire. The second data fan-out line 42 and the third data fan-out line 43 are both disposed on the second conductive layer M2, and the two are directly connected.

[0056] See also Figure 2 The second conductive layer M2 also includes a fourth data fan-out line 44 disposed in the first region 21 and a fifth data fan-out line 45 disposed in the second region 22. The first conductive layer M1 also includes a sixth data fan-out line 46 disposed in the third region 23. The fourth data fan-out line 44, the fifth data fan-out line 45 and the sixth data fan-out line 46 are connected in sequence to form the first fan-out line S1.

[0057] For example, among the fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46, data fan-out lines located on the same conductive layer can be directly connected, while data fan-out lines located on different conductive layers can be connected by jumpers. In the embodiments of this application, the fourth data fan-out line 44 and the fifth data fan-out line 45 are both disposed on the second conductive layer M2 and are directly connected; the fifth data fan-out line 45 is disposed on the first conductive layer M1, and the sixth data fan-out line 46 is disposed on the second conductive layer M2 and are connected by jumpers.

[0058] In the above embodiments of this application, the display panel 10 includes a display area 11 and a fan-out area 12 located on one side of the display area 11. The fan-out area 12 includes the boundary 120 of the display area 11, and also includes a first wiring area 1 and a second wiring area 2 arranged along a first direction X parallel to the boundary 120. Along a second direction Y intersecting the first direction X, a first region 21, a second region 22, and a third region 23 of the second wiring area 2 are sequentially arranged outside the display area 11. The display panel 10 also includes a substrate and a first conductive layer M1 and a second conductive layer M2 sequentially stacked on the substrate. The resistivity of the material of the first conductive layer M1 is greater than the resistivity of the material of the second conductive layer M2.

[0059] The first conductive layer M1 includes a first data fan-out line 41 disposed in the first region 21. The second conductive layer M2 includes a second data fan-out line 42 disposed in the second region 22 and a third data fan-out line 43 disposed in the third region 23. The first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43 are sequentially connected to form the second fan-out line S2. It can be understood that the second fan-out line S2 includes three segments, one of which uses the first conductive layer M1 with higher impedance, and the other two segments use the second conductive layer M2 with lower impedance. The proportion of low-impedance conductive layer material in the second fan-out line S2 is relatively high, and the resistance of the second fan-out line S2 is low, which helps to reduce the resistance of the data line connected to the second fan-out line S2, thereby reducing the load on the trace.

[0060] The second conductive layer M2 also includes a fourth data fan-out line 44 disposed in the first region 21 and a fifth data fan-out line 45 disposed in the second region 22. The first conductive layer M1 also includes a sixth data fan-out line 46 disposed in the third region 23. The fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46 are sequentially connected to form the first fan-out line S1. It can be understood that the first fan-out line S1 includes three segments, one of which uses the first conductive layer M1 with higher impedance, and the other two segments use the second conductive layer M2 with lower impedance. The proportion of low-impedance conductive layer material in the first fan-out line S1 is relatively high, and the resistance of the first fan-out line S1 is low, which helps to reduce the resistance of the data lines connected to the first fan-out line S1, thereby reducing the load on the traces.

[0061] Furthermore, each of the aforementioned first fan-out line S1 and second fan-out line S2 includes a trace in the first conductive layer M1 and two traces in the second conductive layer M2. Therefore, the resistance values ​​of the first fan-out line S1 and the second fan-out line S2 are also similar, and their loads are also similar. When the first fan-out line S1 and the second fan-out line S2 are adjacent, the data signal transmitted through the first fan-out line S1 and the second fan-out line S2 is transmitted to the pixels at the far end of the display area 11 (the side of the display area 11 away from the fan-out area 12), which can improve the uneven display phenomenon at the far end of the display area 11.

[0062] In some embodiments, see Figure 2 The orthographic projection of the first data fan-out line 41 onto the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line 44 onto the substrate. The orthographic projection of the third data fan-out line 43 onto the substrate at least partially overlaps with the orthographic projection of the sixth data fan-out line 46 onto the substrate.

[0063] It is understandable that the first data fan-out line 41 and the fourth data fan-out line 44 located in the first region 21 are interleaved and stacked, and the third data fan-out line 43 and the sixth data fan-out line 46 located in the third region 23 are also interleaved and stacked. This can reduce the area occupied by the data fan-out lines in the second wiring area 2, which is beneficial to reducing the area of ​​the second wiring area 2, thereby helping to narrow the bezel width of the display device 100.

[0064] Figure 3 for Figure 1 A magnified view of multiple traces in the first wiring area.

[0065] In some embodiments, see Figure 3 The first wiring area 1 includes a fourth area 24 and a fifth area 25 arranged along the second direction Y. The fourth area 24 is closer to the display area 11 than the fifth area 25.

[0066] The first conductive layer M1 further includes a seventh data fan-out line 47 disposed in the fourth region 24, and the second conductive layer M2 further includes an eighth data fan-out line 48 disposed in the fifth region 25. The seventh data fan-out line 47 and the eighth data fan-out line 48 are connected to form a third fan-out line S3. For example, the seventh data fan-out line 47 and the eighth data fan-out line 48 are located in different conductive layers and are connected by a jumper.

[0067] The second conductive layer M2 further includes a ninth data fan-out line 49 disposed in the fourth region 24, and the first conductive layer M1 further includes a tenth data fan-out line 40 disposed in the fifth region 25. The ninth data fan-out line 49 and the tenth data fan-out line 40 are connected to form the fourth fan-out line S4. For example, the ninth data fan-out line 49 and the tenth data fan-out line 40 are located in different conductive layers and are connected by a jumper.

[0068] See also Figure 3 The orthographic projection of the seventh data fan-out line 47 on the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line 49 on the substrate. The orthographic projection of the eighth data fan-out line 48 on the substrate at least partially overlaps with the orthographic projection of the tenth data fan-out line 40 on the substrate. It is understood that the seventh data fan-out line 47 and the ninth data fan-out line 49 located in the fourth region 24 are stacked in an interleaved wiring manner, and the eighth data fan-out line 48 and the tenth data fan-out line 40 located in the fifth region 25 are also stacked in an interleaved wiring manner, which reduces the area occupied by the data fan-out lines in the first wiring region 1, which is beneficial to reducing the area of ​​the first wiring region 1, thereby helping to narrow the bezel width of the display device 100.

[0069] Understandably, see Figure 1 and Figure 3 Compared to the second wiring area 2, the first wiring area 1 is closer to the center line L of the display panel 10 along the first direction X. Therefore, the first wiring area 1 is called the "near end area" and the second wiring area 2 is called the "far end area". Thus, the length of the fan-out line of the first wiring area 1 is less than the length of the fan-out line of the second wiring area 2.

[0070] The fan-out lines in the first wiring area 1 are "jumped" at the junction of the fourth area 24 and the fifth area 25. That is, a fan-out line consists of two segments: one segment uses the first conductive layer M1 with higher impedance, and the other segment uses the second conductive layer M2 with lower impedance.

[0071] For example, the jumper is located at the middle of the fan-out line, thus dividing a fan-out line into two segments of equal length. In each fan-out line, the proportion of low-impedance conductive material is half, and the proportion of high-impedance conductive material is also half.

[0072] In the second wiring area 2, see Figure 2 One part of the fan-out lines are first jumpered at the junction of the first region 21 and the second region 22, and another part of the fan-out lines are second jumpered at the junction of the second region 22 and the third region 23. Each fan-out line includes three segments: one segment uses the first conductive layer M1 with higher impedance, and the two segments use the second conductive layer M2 with lower impedance.

[0073] For example, in the second wiring area 2, each fan-out line has an equal length in the first area 21, the second area 22, and the third area 23. In the second fan-out line S2, the first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43 have equal lengths, the proportion of high-impedance conductive material is one-third, and the proportion of low-impedance conductive material is two-thirds.

[0074] Similarly, in the first fan-out line S1, the fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46 are of equal length, with high-resistance conductive material accounting for one-third and low-resistance conductive material accounting for two-thirds.

[0075] In the above embodiments of this application, the length of the fan-out line of the second wiring area 2 is greater than the length of the fan-out line of the first wiring area 1, that is, the length of the fan-out line located in the far end area is greater than the length of the fan-out line located in the near end area, which makes the wiring resistance of the far end area larger and the load higher.

[0076] Based on this, by improving the wiring design of the second wiring area 2, compared with the first wiring area 1, the proportion of low-impedance conductive material (second conductive material) in the fan-out lines of the second wiring area 2 is increased from one-half to two-thirds, and the proportion of high-impedance conductive material (first conductive material) is reduced from one-half to one-third. This reduces the sheet resistance of the multiple fan-out lines located in the second wiring area 2, reduces the load on the fan-out lines, and helps to reduce the sheet resistance difference between adjacent fan-out lines, thereby improving the display uniformity of the display area 11 located at the far end of the source drive circuit 30.

[0077] Figure 4 for Figure 1 A magnified view of the second wiring area in the image; Figures 5-8 They are respectively Figure 4 The second wiring area is shown in a magnified view of multiple traces in areas A to D.

[0078] In some embodiments, see Figures 4-8 The first conductive layer M1 is a light-shielding layer (LS), and the second conductive layer M2 is a gate conductive layer. See also... Figure 4 The second wiring area 2 is divided into four areas: area A, area B, area C, and area D.

[0079] Among them, see Figure 5Region A is closest to the display area 11 compared to regions B, C and D. Region A corresponds to the boundary between the first region 21 and the second region 22. Multiple fan-out lines are first jumpered in region A. For example, the second data fan-out line 42 located in the gate conductive layer crosses the film layer and is connected to the first data fan-out line 41 located in the light-shielding layer. The fourth data fan-out line 44 and the fifth data fan-out line 45 located in the gate conductive layer are directly connected.

[0080] See Figure 6 Region B corresponds to the second region 22. After the first jumper, the multiple fan-out lines are all located in the gate conductive layer M2, that is, the second data fan-out line 42 and the fifth data fan-out line 45 are set in the same layer in region B.

[0081] See Figure 7 Region C corresponds to the second region 22. At region C, multiple fan-out lines undergo a second jumper. For example, the second data fan-out line 42 and the third data fan-out line 43 located in the gate conductive layer M2 are directly connected. The fifth data fan-out line 45 located in the gate conductive layer is connected to the sixth data fan-out line 46 located in the light-shielding layer by crossing the film layer. See also... Figure 8 Region D corresponds to the third region 23. In region D, the third data fan-out line 43 and the sixth data fan-out line 46 after the second jumper are stacked to reduce the area occupied by the data fan-out lines in region D.

[0082] For example, the sheet resistance of the light-shielding layer (first conductive layer) M1 is about 0.33Ω / □ ("Ω / □" means "ohms per square", which refers to the resistance value between the edges of a square thin film conductive material), the sheet resistance of the gate conductive layer (second conductive layer) M2 is about 0.1Ω / □, and the sheet resistance of the light-shielding layer is about three times that of the sheet resistance of the gate conductive layer. In the embodiments of this application, the second fan-out line S2 is composed of two-thirds of the gate conductive layer material (the second data fan-out line 42 and the third data fan-out line 43) and one-third of the light-shielding layer material (the first data fan-out line 41). The first fan-out line S1 is composed of two-thirds of the gate conductive layer material (the fourth data fan-out line 44 and the fifth data fan-out line 45) and one-third of the light-shielding layer material (the sixth data fan-out line 46). Compared with related technologies, each fan-out line of the fan-out area 12 of this application increases the amount of low-impedance material (gate conductive layer material), thereby reducing the resistance of the data line connected to the second fan-out line S2, thereby reducing the load on the wiring and optimizing the display uniformity at the far end of the display area 11.

[0083] Figure 9 for Figure 5 A partial sectional view of a jumper along section line PP'; Figure 10 for Figure 7 A partial sectional view of a jumper along section line QQ'.

[0084] In some embodiments, see Figure 9 and Figure 10 The display panel 10 further includes a first insulating layer 5 disposed between the first conductive layer M1 and the second conductive layer M2. For example, the first insulating layer 5 includes a stacked buffer layer 51 and a gate insulating layer (GI) 52. The first insulating layer 5 is located between the light-shielding layer (first conductive layer) M1 and the gate conductive layer (second conductive layer) M2, and is used to isolate the gate conductive layer M2 from the light-shielding layer M1. The buffer layer 51 is disposed on the substrate 7, and the light-shielding layer M1 is disposed within the buffer layer 51. The gate insulating layer (GI) 52 and the buffer layer 51 are patterned using a mask, so that the first insulating layer 5 has a first via 50. The gate conductive layer M2 is electrically connected to the light-shielding layer M1 through the first via 50.

[0085] In this embodiment, LS and Gate are used as data signal lines, and a jumper is established between LS-GI-Gate. For example, see [link to example]. Figure 9 The second data fan-out line 42, located in the second conductive layer M2, penetrates the first insulating layer 5 and is electrically connected to the first data fan-out line 41 located in the first conductive layer M1, thus realizing the first jumper for multiple data fan-out lines. For example, see... Figure 10 The fifth data fan-out line 45, located in the second conductive layer M2, passes through the first insulating layer 5 and connects to the sixth data fan-out line 46 located in the first conductive layer M1, thus realizing a second jumper for multiple fan-out lines. For example, the resistance of the multiple fan-out lines located in the second wiring area 2 can be reduced by approximately 12%, thereby reducing the charging loss of the display panel 10.

[0086] Figure 11 A partial enlarged view of another second wiring area provided in an embodiment of this application; Figure 12 for Figure 11 A partial sectional view of another type of jumper along section line PP'; Figure 13 for Figure 11 Another type of jumper is shown in a partial sectional view along section line QQ'.

[0087] In some embodiments, see Figure 11 The source and drain conductive layer M3 also includes a touch signal line (Tx) 9, which is used to send drive signals to the touch electrodes to achieve touch positioning.

[0088] In some embodiments, see Figure 12 and Figure 13The display panel 10 includes a substrate 7, and a first conductive layer M1, a first insulating layer 5, a second conductive layer M2, a second insulating layer 8, and a source / drain conductive layer (SD) M3 sequentially stacked on the substrate 7. Exemplarily, the first insulating layer 5 includes a stacked buffer layer 51 and a gate insulating layer (GI) 52. The second insulating layer 8 is an interlayer dielectric (ILD) layer, used to isolate the source / drain conductive layer M3 from the second conductive layer (gate conductive layer) M2. The source / drain conductive layer M3 includes a first connection electrode 91 and a second connection electrode 92. The second insulating layer 8 is provided with a through-hole second via 80 and a third via 81.

[0089] In this embodiment, no additional mask is required for patterning the GI. After forming the second via 80 and the third via 81 in the second insulating layer (ILD) 8 using the mask of the ILD, etching continues downward along the second via 80 until the portion of the first conductive layer M1 located below the second via 80 is exposed. LS and Gate are used as data signal lines, and LS and Gate are connected via LS-ILD-SD-ILD-Gate to form a jumper.

[0090] For example, see Figure 10 The first connecting electrode 91 passes through the second insulating layer 8 via the second via 80, and through the first insulating layer 5 via a via to connect to the first data fan-out line 41. Furthermore, the first connecting electrode 91 passes through the second insulating layer 8 via the third via 81 to connect to the second data fan-out line 42. That is, the second data fan-out line 42 located on the gate conductive layer (Gate) M2 is electrically connected to the first data fan-out line 41 located on the light-shielding layer (LS) M1 via the first connecting electrode (SD) 91, thus realizing the first jumper for multiple fan-out lines.

[0091] For example, see Figure 11 The second connecting electrode 92 passes through the second insulating layer 8 via the third via 81 and is connected to the fifth data fan-out line 45. The second connecting electrode 92 passes through the second insulating layer 8 via the second via 80 and through the first insulating layer 5 via the first insulating layer 5 to be electrically connected to the sixth data fan-out line 46, thus realizing the second jumper of multiple fan-out lines.

[0092] In the embodiments of this application, see also... Figure 11The touch signal line 9 is located in the source-drain conductive layer M3. The first connecting electrode 91 and the second connecting electrode 92 are also located in the source-drain conductive layer M3. To prevent short circuits, the orthographic projection of the touch signal line 9 on the substrate 7 must not overlap with the orthographic projection of the first connecting electrode 91 on the substrate 7, and the orthographic projection of the touch signal line 9 and the second connecting electrode 92 on the substrate 7 must also not overlap. That is, the touch signal line 9 must avoid the position where the fan-out line jumpers twice.

[0093] Figure 14 This is a partial sectional view of another type of jumper along section line PP'; Figure 15 This is a partial sectional view of another type of jumper along section line QQ'.

[0094] In some embodiments, see Figure 14 and Figure 15 The first conductive layer M1 is the gate conductive layer, and the second conductive layer M2 is the source / drain conductive layer (SD).

[0095] The display panel 10 also includes a third insulating layer 8 disposed between the first conductive layer (Gate) M1 and the second conductive layer (SD) M1. For example, the third insulating layer 8 is an interlayer dielectric (ILD), and the ILD 8 is used to isolate the second conductive layer (SD) M2 and the first conductive layer (Gate) M1. The third insulating layer 8 is provided with a through fourth via 82.

[0096] In this embodiment, there is no need to set up an additional mask for patterning GI. The fourth via 82 is formed in the third insulating layer (ILD) 8 using the mask of ILD. The Gate and SD are used as data signal lines, and the Gate and SD are connected by a jumper through Gate-ILD-SD.

[0097] For example, see Figure 14 The second data fan-out line 42 passes through the fourth via 82 and through the third insulation layer 8 to be electrically connected to the first data fan-out line 41, realizing the first jumper of multiple fan-out lines.

[0098] For example, see Figure 15 The fifth data fan-out line 45 passes through the fourth via 82, penetrates the third insulation layer 8, and is electrically connected to the sixth data fan-out line 46, realizing the second jumper of multiple fan-out lines.

[0099] Using the positions of the two jumpers mentioned above as boundaries, each fan-out line can be divided into three segments. For example, the lengths of the three fan-out lines are equal, namely, the lengths of the first data fan-out line 41 and the fourth data fan-out line 44 are equal, the lengths of the second data fan-out line 42 and the fifth data fan-out line 45 are equal, and the lengths of the third data fan-out line 43 and the sixth data fan-out line 46 are equal.

[0100] The sheet resistance of the second conductive layer M2 is less than that of the first conductive layer M1. For example, the sheet resistance of the gate conductive layer is about 0.1Ω / □, and the sheet resistance of the source and drain conductive layers is about 0.06Ω / □. By using two jumpers, the proportion of SD lines in the multiple fan-out lines is about two-thirds, and the proportion of Gate lines is about one-third. Since the second wiring area 2 uses more SD lines with lower sheet resistance, the overall impedance reduction effect of the multiple fan-out lines is more obvious, further improving the display uniformity at the far end of the display area 11.

[0101] Figure 16 for Figure 1 A magnified view of a portion of the traces on the display panel at point N.

[0102] In some embodiments, see Figure 16 Along the first direction X, the display panel 10 also includes a plurality of data lines arranged sequentially in the display area 11. For example, the plurality of data lines include a first data line S101, a second data line S102...a sixteenth data line S116 arranged sequentially, with the first data line S101 and the second data line S102 adjacent to each other. The second data line S102 is sequentially connected to a first data fan-out line 41, a second data fan-out line 42, and a third data fan-out line 43. The first data line S101 is sequentially connected to a fourth data fan-out line 44, a fifth data fan-out line 45, and a sixth data fan-out line 46. The first data fan-out line 41 and the fourth data fan-out line 44 are adjacent to each other and located on different conductive layers.

[0103] The sum of the resistances of the first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43 is less than or equal to the sum of the resistances of the fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46. Since the resistance values ​​of the first data line S101 and the second data line S102 are similar, it can be understood that the difference between the sum of the resistances of the second data line S102, the first data fan-out line 41, the second data fan-out line 42, and the third data fan-out line 43 and the sum of the resistances of the first data line S101, the fourth data fan-out line 44, the fifth data fan-out line 45, and the sixth data fan-out line 46 is less than or equal to 20Ω. That is, the resistance difference between adjacent data lines in the display panel 10 is less than or equal to 20Ω, thereby improving the display uniformity of the display panel 10 in the region far from the source drive circuit 30, which reduces the appearance of vertical lines and other display defects.

[0104] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, It includes a display area and a fan-out area located on one side of the display area; the fan-out area includes a first wiring area and a second wiring area arranged along a first direction, and the fan-out area includes a boundary close to the display area, wherein the first direction is parallel to the boundary; The second wiring area includes a first area, a second area, and a third area arranged sequentially along a second direction, the second direction intersecting the first direction; the first area is closer to the display area than the third area. The display panel includes a substrate, and a first conductive layer and a second conductive layer stacked on the substrate. The resistivity of the material of the first conductive layer is greater than that of the material of the second conductive layer. The first conductive layer includes a first data fan-out line disposed in the first region, and the second conductive layer includes a second data fan-out line disposed in the second region and a third data fan-out line disposed in the third region. The first data fan-out line, the second data fan-out line and the third data fan-out line are connected in sequence. The second conductive layer further includes a fourth data fan-out line disposed in the first region and a fifth data fan-out line disposed in the second region. The first conductive layer further includes a sixth data fan-out line disposed in the third region. The fourth data fan-out line, the fifth data fan-out line and the sixth data fan-out line are connected in sequence.

2. The display panel according to claim 1, characterized in that, The orthographic projection of the first data fan-out line on the substrate at least partially overlaps with the orthographic projection of the fourth data fan-out line on the substrate; The orthographic projection of the third data fan-out line on the substrate at least partially overlaps with the orthographic projection of the sixth data fan-out line on the substrate.

3. The display panel according to claim 1, characterized in that, The first conductive layer is a light-shielding layer, and the second conductive layer is a gate conductive layer.

4. The display panel according to claim 3, characterized in that, The display panel further includes a first insulating layer disposed between the first conductive layer and the second conductive layer; The second data fan-out line passes through the first insulation layer and is connected to the first data fan-out line, and the fifth data fan-out line passes through the first insulation layer and is connected to the sixth data fan-out line.

5. The display panel according to claim 3, characterized in that, The display panel includes a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a source / drain conductive layer stacked sequentially. The source / drain conductive layer includes a first connection electrode and a second connection electrode; The first connecting electrode penetrates the second insulating layer and the first insulating layer to connect to the first data fan-out line, and also penetrates the second insulating layer to connect to the second data fan-out line; the second connecting electrode penetrates the second insulating layer to connect to the fifth data fan-out line, and also penetrates the second insulating layer and the first insulating layer to connect to the sixth data fan-out line.

6. The display panel according to claim 5, characterized in that, The source and drain conductive layer also includes a touch signal line, the orthographic projection of which on the substrate does not overlap with the orthographic projection of the first connecting electrode on the substrate, and does not overlap with the orthographic projection of the second connecting electrode on the substrate.

7. The display panel according to claim 1, characterized in that, The first conductive layer is a gate conductive layer, and the second conductive layer is a source / drain conductive layer.

8. The display panel according to claim 7, characterized in that, The display panel further includes a third insulating layer disposed between the first conductive layer and the second conductive layer; The second data fan-out line passes through the third insulating layer and is connected to the first data fan-out line, and the fifth data fan-out line passes through the third insulating layer and is connected to the sixth data fan-out line.

9. The display panel according to claim 1, characterized in that, The display panel also includes multiple data lines disposed in the display area, which are arranged sequentially along the first direction; The multiple data lines include an adjacent first data line and a second data line. The first data line is sequentially connected to the first data fan-out line, the second data fan-out line, and the third data fan-out line. The second data line is sequentially connected to the fourth data fan-out line, the fifth data fan-out line, and the sixth data fan-out line. The difference between the sum of the resistances of the first, second, and third data fan-out lines and the sum of the resistances of the fourth, fifth, and sixth data fan-out lines is less than or equal to 20Ω.

10. The display panel according to claim 1, characterized in that, The first wiring area includes a fourth area and a fifth area arranged along the second direction, wherein the fourth area is closer to the display area than the fifth area; The first conductive layer further includes a seventh data fan-out line disposed in the fourth region, and the second conductive layer further includes an eighth data fan-out line disposed in the fifth region, wherein the seventh data fan-out line is connected to the eighth data fan-out line; the second conductive layer further includes a ninth data fan-out line disposed in the fourth region, and the first conductive layer further includes a tenth data fan-out line disposed in the fifth region, wherein the ninth data fan-out line is connected to the tenth data fan-out line; The orthographic projection of the seventh data fan-out line on the substrate at least partially overlaps with the orthographic projection of the ninth data fan-out line on the substrate; The orthographic projection of the eighth data fan-out line onto the substrate at least partially overlaps with the orthographic projection of the tenth data fan-out line onto the substrate.

11. The display panel according to claim 1, characterized in that, The fan-out area includes a first wiring area and two second wiring areas; Along the first direction, the two second wiring areas are disposed on opposite sides of the first wiring area.

12. A display device, characterized in that, include: The display panel as described in any one of claims 1 to 11; The controller is electrically connected to the display panel.

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