Screen cleaning method and device, electronic equipment and readable medium

Abstract

The embodiment of the invention provides a screen cleaning method and device, electronic equipment and a readable medium, and relates to the technical field of display, in the method, vertex coordinates, width pixel values and height pixel values defined in a predefined screen cleaning area structural body and screen cleaning color values defined in a screen cleaning color structural body are pushed to a designated register of a GPU. And respectively reading the vertex coordinate, the width pixel value, the height pixel value and the clear screen color value from the specified register by a shader. And rendering all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the screen cleaning color value to realize screen cleaning. The vertex coordinate, the width pixel value, the height pixel value and the screen cleaning color value are directly pushed to the specified register, so that a shader can directly and conveniently obtain the vertex coordinate, the width pixel value, the height pixel value and the screen cleaning color value required by screen cleaning from the specified register. The screen cleaning efficiency can be improved, and efficient screen cleaning is achieved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a screen clearing method, device, electronic equipment and readable medium. Background Art

[0002] Currently, in the display process, before starting to render a new frame, a screen clearing operation is required to clear the previous frame and prepare for drawing the new frame. Since the screen clearing operation requires the GPU to use rendering commands to execute the entire graphics pipeline in real time, involving a large number of pixel updates, and the screen clearing operation needs to be performed frequently as the image frame is refreshed in real time, it consumes a lot of resources and has a great impact on GPU performance.

[0003] Accordingly, how to efficiently achieve screen clearing has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present invention provide a screen clearing method, device, electronic device and readable medium, which can solve the technical problem of how to efficiently achieve screen clearing, which has become an urgent problem to be solved.

[0005] In order to solve the above problem, an embodiment of the present invention discloses a screen clearing method, which includes:

[0006] Push the vertex coordinates, width pixel value, height pixel value defined in the pre-defined clear screen area structure and the clear screen color value defined in the clear screen color structure to the specified registers of the GPU respectively;

[0007] The shader reads the vertex coordinates, the width pixel value, the height pixel value and the clear screen color value from the designated register respectively;

[0008] According to the clear screen color value, all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value are rendered to achieve a clear screen.

[0009] On the other hand, an embodiment of the present invention discloses a screen clearing device, the device comprising:

[0010] A push module is used to push the vertex coordinates, width pixel value, height pixel value defined in a predefined clear screen area structure and the clear screen color value defined in a clear screen color structure to the specified registers of the GPU respectively;

[0011] A reading module, configured to read the vertex coordinates, the width pixel value, the height pixel value, and the clear screen color value from the designated registers respectively by a shader;

[0012] The rendering module is used to render all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the clear screen color value to achieve clear screen.

[0013] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0014] The embodiment of the present invention further discloses a machine-readable medium on which instructions are stored. When executed by one or more processors, the processors are enabled to execute the method described above.

[0015] The embodiment of the present invention includes the following advantages: In the screen clearing method provided by the embodiment of the present invention, the vertex coordinates, width pixel values, height pixel values ​​defined in the predefined screen clearing area structure and the screen clearing color value defined in the screen clearing color structure are pushed to the designated register of the GPU respectively. The vertex coordinates, width pixel values, height pixel values ​​and screen clearing color values ​​are read from the designated register by the shader respectively. According to the screen clearing color value, all pixels in the display area indicated by the vertex coordinates, width pixel values ​​and height pixel values ​​are rendered to achieve screen clearing. In this way, by directly pushing the vertex coordinates, width pixel values, height pixel values ​​and screen clearing color values ​​to the designated register, the shader can directly and conveniently obtain the vertex coordinates, width pixel values, height pixel values ​​and screen clearing color values ​​required for screen clearing from the designated register. At the same time, the display area required for screen clearing can be determined based on the vertex coordinates, width pixel values ​​and height pixel values, so the screen clearing efficiency of the GPU can be improved to achieve efficient screen clearing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0017] Figure 1 is a flowchart of the steps of a screen clearing method provided by an embodiment of the present invention;

[0018] Figure 2 It is a schematic diagram of a processing flow provided by an embodiment of the present invention;

[0019] Figure 3is a block diagram of a screen clearing device provided by an embodiment of the present invention;

[0020] Figure 4 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] Figure 1 is a flowchart of a screen clearing method provided by an embodiment of the present invention. Figure 1 As shown, the screen clearing method may include the following steps:

[0023] Step 101: Push the vertex coordinates, width pixel value, height pixel value defined in a predefined clear screen area structure and the clear screen color value defined in a clear screen color structure to designated registers of a GPU respectively.

[0024] Step 102: The shader reads the vertex coordinates, the width pixel value, the height pixel value, and the clear screen color value from the designated register respectively.

[0025] Step 103 : Render all pixels in the display area indicated by the vertex coordinates, the width pixel value, and the height pixel value according to the clear screen color value to achieve clear screen.

[0026] The screen clearing method provided in an embodiment of the present invention can be applied to an electronic device including a graphics processing unit (GPU). The screen clearing area structure and the screen clearing color structure can be pre-set structures for transmitting screen clearing parameters. Among them, the screen clearing parameters may include vertex coordinates, width pixel values, height pixel values ​​for indicating the screen clearing area, and screen clearing color values ​​for indicating the screen clearing color. Specifically, the vertex coordinates may be the lower left corner coordinates. The vertex coordinates, width pixel values, and height pixel values ​​can be expressed as: (x, y, width, height). Among them, x, y represent vertex coordinates, x, y can be specifically the pixel coordinates of the lower left corner of the screen clearing area, width represents the width pixel value, height represents the height pixel value, the units of width and height are pixels, and (x, y, width, height) can represent a rectangular drawing area. In this way, the display area required to clear the screen can be determined based on the vertex coordinates, width pixel values, and height pixel values. The clear screen color value can be a 4-dimensional vector parameter: (r, g, b, a), where r represents the red proportion, g represents the green proportion, b represents the blue proportion, and a represents transparency. The specific values ​​of the vertex coordinates, width pixel values, and height pixel values ​​in the clear screen area structure, and the specific values ​​of the clear screen color value in the clear screen color structure can be pre-specified by the user. Exemplarily, when pushing, the clear screen area parameters in the clear screen area structure: coordinate parameters, width pixel value parameters, and height pixel value parameters can be set according to the pre-set specific values ​​of the vertex coordinates, width pixel values, and height pixel values ​​to define the vertex coordinates, width pixel values, and height pixel values ​​in the clear screen area structure. According to the specific values ​​of the pre-set clear screen color values, the clear screen color parameters in the clear screen color structure are set to define the clear screen color value in the clear screen color structure.

[0027] The designated register is a register allocated for the shader, and the register allocated for the shader can be given by the compiler. Accordingly, the vertex coordinates, width pixel value, height pixel value, and clear screen color value can be pushed to the designated register as constants. Since the register is a storage unit inside the graphics processing unit (GPU), it can be directly accessed without memory access instructions, so the access speed is fast. Accordingly, when the shader is running, the written vertex coordinates, width pixel value, height pixel value, and clear screen color value can be quickly read from the designated register, thereby improving the overall implementation efficiency of clearing the screen.

[0028] Further, the display area indicated by the vertex coordinates, the width pixel value, and the height pixel value may be a pixel area that needs to be cleared, and the pixel area may be located in a rendering buffer. The clearing operation of rendering each pixel corresponding to the pixel area may reset the rendering buffer and update all pixels in the rendering buffer to the clearing color value. Assuming that the resolution of the display area is 1920x1080, 1920*1080 pixels are updated to the clearing color value when clearing the screen. Among them, the rendering buffer is a container for storing image data, and the rendering buffer stores the pixel data of the corresponding position in the image. During the rendering process, the final color value of each pixel is calculated and then written to the rendering buffer. Correspondingly, the window system displays the pixel data of the rendering buffer to the screen. Clearing the screen is essentially a rendering operation. Specifically, clearing the screen is to render all pixels to the clearing color value. Among them, the clearing color value may be preset by the user, and the clearing color value may be a single color, that is, a single color fill is implemented, and a single color image is stored in the rendering buffer.

[0029] In summary, in the screen clearing method provided by the embodiment of the present invention, the vertex coordinates, width pixel values, height pixel values ​​defined in the predefined screen clearing area structure, and the screen clearing color value defined in the screen clearing color structure are pushed to the designated register of the GPU respectively. The vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​are read from the designated registers by the shader respectively. According to the screen clearing color value, all pixels in the display area indicated by the vertex coordinates, width pixel values, and height pixel values ​​are rendered to achieve screen clearing. In this way, by directly pushing the vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​to the designated register, the shader can directly and conveniently obtain the vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​required for screen clearing from the designated register. At the same time, the display area required for screen clearing can be determined based on the vertex coordinates, width pixel values, and height pixel values, so the screen clearing efficiency of the GPU can be improved to achieve efficient screen clearing.

[0030] Optionally, the above-mentioned pushing the vertex coordinates, width pixel value, height pixel value defined in the predefined clear screen area structure and the clear screen color value defined in the clear screen color structure to the specified registers of the GPU respectively includes:

[0031] Step 1011: Determine the first register corresponding to the clear screen area structure and the second register corresponding to the clear screen color structure according to the configured push range information; the designated register includes the first register and the second register.

[0032] Step 1012: Push the vertex coordinates, the width pixel value, and the height pixel value to the first register respectively, and push the clear screen color value to the second register.

[0033] Among them, the push range information is information used to characterize which register the vertex coordinates, width pixel value, height pixel value defined in the clear screen area structure, and the clear screen color value defined in the clear screen color structure are pushed to. Specifically, the push range information may include the first push range information of the clear screen area structure and the second push range information of the clear screen color structure. The first push range information and the second push range information can characterize which register the clear screen area parameters and the clear screen color parameters are pushed to when the display area is cleared. Specifically, the first push range information is used to characterize which register the vertex coordinates, width pixel value, and height pixel value are pushed to, and the second push range information is used to characterize which register the clear screen color value is pushed to. The register defined in the first push range information can be determined as the first register, and the register defined in the second push range information can be determined as the second register. The first register is a register allocated to the shader that receives the clear screen area parameter, and the second register is a register allocated to the shader that receives the clear screen color parameter. Specifically, the push range information may be information described by the push range structure, and exemplarily, the push range structure may be a VkPushConstantRange structure.

[0034] In the embodiment of the present invention, a clear screen region structure and a clear screen color structure may be declared in advance to facilitate the transmission of clear screen parameters. Exemplarily, the clear screen region structure and the clear screen color structure may be represented as ClearRegionData and ClearColorData, respectively.

[0035] In this embodiment, the clear screen region structure can be declared by the following statement: struct ClearRegionData{x, y, width; height;}. The clear screen color structure can be declared by the following statement: struct ClearColorData{color}, where color represents the clear screen color value. Taking the vertex coordinates as the pixel coordinates of the lower left corner (0,0), the width pixel value is 800 (i.e., there are 800 pixels in the width direction), and the height pixel value is 600 (i.e., there are 600 pixels in the height direction) as an example, the following data can be defined based on ClearRegionData: ClearRegionDataclearRegion={0.0f,0.0f,800.0f,600.0f}. Taking the clear screen color as red as an example, the following data can be defined based on ClearColorData: ClearColorDataclearColor={1.0f,0.0f,0.0f,0.0f}. By pre-declaring the clear screen region structure and the clear screen color structure, it is convenient to pass the clear screen parameters when pushing. Furthermore, based on ClearRegionData and ClearColorData, first push range information of the clear screen region structure and second push range information of the clear screen color structure may be declared in advance.

[0036] In the embodiment of the present invention, the vertex coordinates, the width pixel value and the height pixel value can be written into a first register, and the clear screen color value can be written into a second register.

[0037] In an embodiment of the present invention, first, according to the configured push range information, the first register corresponding to the clear screen area structure and the second register corresponding to the clear screen color structure are determined respectively. Then, the vertex coordinates, width pixel value, and height pixel value are pushed to the first register respectively, and the clear screen color value is pushed to the second register. In this way, based on the configured push range information, the vertex coordinates, width pixel value, height pixel value, and clear screen color value can be accurately pushed to their respective corresponding registers, thereby ensuring that the subsequent clear screen parameters can be correctly read.

[0038] The first register is a register allocated to the first shader, and the second register is a register allocated to the second shader. That is, the first shader receives a clear screen area parameter, and the second shader receives a clear screen color parameter. The first shader and the second shader are two important shader types in the graphics rendering pipeline, and the first shader and the second shader are responsible for processing different stages of graphics data, respectively. In an embodiment of the present invention, the first shader may be responsible for determining a pixel area to be rendered based on vertex coordinates, width pixel values, and height pixel values, and the second shader may be responsible for updating the color values ​​of all pixels in the pixel area to clear screen color values. Exemplarily, the first shader may be a vertex shader (VertexShader) and the second shader may be a fragment shader (Fragment Shader)

[0039] In an embodiment of the present invention, the first push range information of the clear screen region structure and the second push range information of the clear screen color structure can be declared in advance. For example, the first push range information pushConstantRegion of the clear screen region structure can be declared by the following statement:

[0040] VkPushConstantRange pushConstantRegion

[0041] pushConstantRegion{stageFlags=VK_SHADER_STAGE_VERTEX_BIT

[0042] size=sizeof(ClearRegionData)

[0043] Among them, the VK_SHADER_STAGE_VERTEX_BIT parameter specifies that the clearing region parameters carried in ClearRegionData are pushed to the registers allocated for the vertex shader for the vertex shader to read and use. Push constant: the clearing region parameters carried in ClearRegionData. That is, for this example, the first register is the register allocated for the vertex shader. At the same time, sizeof(ClearRegionData) defines that the size of the clearing region parameters pushed is the byte size of the ClearRegionData declared above.

[0044] The second push range information pushConstantColor of the clear screen color structure can be declared by the following statement:

[0045] VkPushConstantRange pushConstantColor

[0046] pushConstantColor{stageFlags=VK_SHADER_STAGE_FRAGMENT_BITsize=sizeof(ClearColorData)

[0047] Among them, the VK_SHADER_STAGE_FRAGMENT_BIT parameter specifies that the clear screen color parameters carried in ClearColorData are pushed to the registers allocated for the fragment shader for the fragment shader to read and use. Push constant: the clear screen color parameters carried in ClearColorData. That is, for this example, the second register is the register allocated for the fragment shader. At the same time, sizeof(ClearColorData) defines that the size of the clear screen area parameter pushed is the byte size of the ClearColorData declared above.

[0048] Furthermore, the register allocated to the vertex shader can be determined as the first register, and the register allocated to the fragment shader can be determined as the second register. Accordingly, the clearing region parameters carried in ClearRegionData: vertex coordinates, width pixel value, and height pixel value can be written into the first register, and the clearing color parameters carried in ClearColorData: clearing color value can be written into the second register, thereby achieving push.

[0049] Exemplarily, the push operation can be implemented based on a push command provided by a preset drawing application programming interface (Application Programming Interface, API). Among them, the drawing API can be Vulkan, which is a cross-platform 2D and 3D drawing API. Since the data volume of vertex coordinates, width pixel values, height pixel values, and clear screen color values ​​is small, they can be pushed based on constant push. Among them, constant push can support data push between tens to hundreds of bytes. The amount of data supported by constant push on different hardware is different. In some hardware environments, it can support data between 128 and 256 bytes. The specific supported data volume can be determined by the model parameters of the GPU hardware and the Vulkan implementation. Since the push constant directly transfers data between the CPU and the GPU, there is no need for additional memory allocation and management processes, and the efficiency of clearing the screen is higher.

[0050] Furthermore, the push command may be vkCmdPushConstants, which is a command used to push a small amount of data to the shader.

[0051] Exemplarily, the preset push interface (vkCmdPushConstants interface) may be called to execute the following vkCmdPushConstants command:

[0052] Void vkCmdPushConstants(VkCommandBuffer commandBuffer,VkPipelineLayout layout,VkShaderStageFlags stageFlags,uint32_t offset,uint32_t size,const void*pValues);

[0053] Among them, commandBuffer in vkCmdPushConstants represents the created command buffer, and layout represents the created pipeline layout.

[0054] When pushing the clear region parameters in ClearRegionData, set stageFlags to VK_SHADER_STAGE_VERTEX_BIT to indicate that the clear region parameters in ClearRegionData correspond to the registers pushed to the vertex shader for the vertex shader stage. The size of the clear region parameters can be sizeof(ClearRegionData), which specifies the number of bytes of the constant pushed this time as the bytes occupied by ClearRegionData, and pValues ​​is &clearRegion, which indicates that the actual clear region parameters are passed to the vertex shader.

[0055] When pushing the clear color parameters defined in ClearColorData, set stageFlags to VK_SHADER_STAGE_FRAGMENT_BIT to indicate that the clear color parameters in ClearColorData correspond to the registers pushed to the fragment shader for use in the fragment shader stage. The size of the clear color parameters can be sizeof(ClearColorData), which specifies that the number of bytes of the constant pushed this time is the number of bytes occupied by ClearColorData, and pValues ​​is &clearColor, which indicates that the actual clear color parameters are passed to the fragment shader.

[0056] In the embodiment of the present invention, the vertex coordinates, the width pixel value and the height pixel value are written into the first register, and the screen clearing color value is written into the second register. Since the first register is a register allocated for the first shader and the second register is a register allocated for the second shader, the first shader and the second shader can obtain the parameters required by each, thereby ensuring that the screen clearing operation can be performed normally.

[0057] Optionally, in the embodiment of the present invention, the first shader pre-defines a first receiving structure for receiving the vertex coordinates, the width pixel value and the height pixel value, and the second shader pre-defines a second receiving structure for receiving the clear screen color value.

[0058] Accordingly, the above-mentioned step of reading the vertex coordinates, the width pixel value, the height pixel value and the clear screen color value from the designated register by the shader may specifically include:

[0059] Step 1021: The first shader reads the vertex coordinates, the width pixel value, and the height pixel value from the first register, and stores them in the first receiving structure.

[0060] Step 1022: The second shader reads the clear screen color value from the second register and stores it into the second receiving structure.

[0061] The first receiving structure may be predefined in the code of the first shader, and the second receiving structure may be predefined in the code of the second shader. The code of the first shader and the code of the second shader may be written based on the shader programming language (OpenGL Shading Language, GLSL).

[0062] Specifically, the first receiving structure and the second receiving structure can be structures declared using a specified declaration statement. Exemplarily, the first receiving structure and the second receiving structure can be structures of uniform type declared using a layout(push_constant) statement, and the members of the structure can be used to store the clearing parameters that need to be passed to the shader. The shader can directly read the clearing parameters pushed to the register from the register. Among them, layout(push_constant) is a layout modifier used to define a push constant in GLSL. Through the declared layout(push_constant), the compiler can allocate corresponding registers to the first shader and the second shader when compiling the GLSL code into GPU hardware instructions. When calling the vkCmdPushConstants interface for pushing, the clearing area parameters can be pushed to the register corresponding to the first shader, and the clearing color parameters can be pushed to the register corresponding to the second shader for subsequent pixel rendering.

[0063] Specifically, the members of the first receiving structure declared in the GLSL code of the first shader can be used to store the vertex coordinates, width pixel values, and height pixel values ​​that need to be passed to the first shader. The members of the second receiving structure declared in the GLSL code of the second shader can be used to store the clearing color value that needs to be passed to the second shader.

[0064] For example, the first receiving structure declared in the GLSL code of the vertex shader may be:

[0065] layout(push_constant)uniform PushConstantRegion{

[0066] float x;

[0067] float y;

[0068] float width;

[0069] float height;

[0070] }PushConstantRegion

[0071] Furthermore, the second receiving structure declared in the GLSL code of the fragment shader may be:

[0072] layout(push_constant)uniform PushConstantColor{

[0073] vec4 color;

[0074] }PushConstantColor

[0075] By declaring the first receiving structure in the GLSL code of the vertex shader and the second receiving structure in the GLSL code of the fragment shader, and accordingly, calling vkCmdPushConstant in the program, the clearing parameters can be finally pushed to the first receiving structure and the second receiving structure variables defined in GLSL.

[0076] Accordingly, when performing a screen clearing operation, in the vertex shader stage, the vertex coordinates, width pixel values, and height pixel values ​​can be directly read from the first register by the vertex shader module, and stored in the first receiving structure for subsequent pixel rendering. In the fragment shader stage, the screen clearing color value can be directly read from the second register by the fragment shader module, and stored in the second receiving structure for use. Among them, the vertex shader module is the vertex shader, and the fragment shader module is the fragment shader.

[0077] In an embodiment of the present invention, the shader can directly read vertex coordinates, width pixel values, height pixel values ​​and clear screen color values ​​from registers based on the predefined first receiving structure and the second receiving structure, without using memory access instructions, thereby improving screen clearing performance.

[0078] Optionally, before the step of pushing the vertex coordinates, width pixel value, height pixel value defined in the predefined clear screen area structure and the clear screen color value defined in the clear screen color structure to the designated register of the GPU, the embodiment of the present invention may further include the following steps:

[0079] Step S21, defining a specified primitive type in a first creation information structure of the GPU; wherein the specified primitive type is a primitive type that supports pixel rendering based on the vertex coordinates, the width pixel value, and the height pixel value, and the first creation information structure is used to describe creation information of a graphics pipeline object.

[0080] Step S22, creating the graphics pipeline object based on the first creation information structure;

[0081] Step S23: Bind the graphics pipeline object to a command buffer, so as to write a clear screen instruction to the command buffer according to the graphics pipeline object; the command buffer is used to provide the clear screen instruction to the GPU.

[0082] Correspondingly, the above-mentioned step of performing pixel rendering on each pixel in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the clear screen color value may specifically include: Step 1031, the GPU executes the clear screen instruction to render all pixels in the display area to the clear screen color value through the shader according to the read clear screen color value, the vertex coordinates, the width pixel value and the height pixel value.

[0083] Among them, the graphics pipeline object is the graphics pipeline, and the graphics pipeline can also be called a rendering pipeline, a graphics rendering pipeline, and the like. The graphics pipeline object can define multiple processing stages, each of which can process data through a shader or a fixed-function operation, and the screen can be cleared after these stages. The first creation information structure can be VkGraphicsPipelineCreateInfo, and the first creation information structure can be used to describe the creation information of the graphics pipeline object. That is, the first creation information structure provides the information required to create a graphics pipeline object, and the various processing stages of the rendering process executed on the GPU are defined through the graphics pipeline object, including the shading stage implemented by the shader, that is, the shader runs on the GPU, and the GPU can communicate with the shader to call the shader to perform shading. The creation information may include all parameter configurations required to create a graphics pipeline object, and the creation information can be used to set the various processing stages and parameters of the rendering process. Exemplarily, processing stages such as vertex processing, primitive assembly, rasterization, and fragment processing can be set.

[0084] The GPU in the embodiment of the present invention is a Loongson GPU. The specified primitive type may be a BLIT primitive. Among them, the BLIT primitive is a rendering primitive supported by the Loongson GPU. The BLIT primitive type may support a graphics rendering function that performs pixel-level operations. BLIT is a data operation in computer graphics. BLIT uses a Boolean function to combine multiple bitmaps into one bitmap. BLIT involves at least two bitmaps: a source bitmap and a target bitmap. Exemplarily, there may also be a third mask bitmap. Accordingly, the combination result may be written into a fourth bitmap. The BLIT primitive supports rectangular primitives that determine the pixel level according to vertex coordinates, width pixel values, and height pixel values, thereby achieving pixel-level rendering. That is, the BLIT primitive may directly perform pixel rendering in a rectangular form. In the embodiment of the present invention, by setting the primitive assembly type to a specified primitive type supported by the GPU, the GPU may be supported to perform pixel-level drawing, thereby improving the efficiency of screen clearing.

[0085] When configuring the first creation information structure, the primitive type can be configured as BLIT in VkGraphicsPipelineCreateInfo. Exemplarily, a primitive assembly state structure (e.g., VkPipelineInputAssemblyStateCreateInfo) can be created first, in which information representing the specified primitive type can be set. Then, a pointer to the primitive assembly state structure is set in the first creation information structure, thereby defining BLIT in the first creation information structure.

[0086] In specific implementation, a shader module is required in the shader stage, and accordingly, a vertex shader module and a fragment shader module may be created first. Exemplarily, the vertex shader code and the fragment shader code may be compiled into SPIR-V format codes to obtain two compiled files. The two compiled files may be represented as: vert.spv and frag.spv. Then, the first preset creation interface may be called to create a vertex shader module and a fragment shader module based on the two compiled files.

[0087] Exemplarily, the first preset creation interface may be vkCreateShaderModule, and the created vertex shader module and fragment shader module may be represented as: vsModule, fsModule, respectively. Next, the vertex shader module and the fragment shader module are configured based on the shader stage structure provided by the first creation information structure VkGraphicsPipelineCreateInfo.

[0088] Exemplarily, the shader stage structure may be VkPipelineShaderStageCreateInfo, and accordingly, vsModule and fsModul may be configured in VkPipelineShaderStageCreateInfo. Further, other information may be configured in the graphics pipeline creation information structure, and exemplarily, the rasterization state and color mixing mode in the first creation information structure VkGraphicsPipelineCreateInfo may also be configured, so as to better control the graphics rendering effect.

[0089] Specifically, in an embodiment of the present invention, the first creation information structure can be configured first, and then, based on the configured first creation information structure, the second preset creation interface is called to create a graphics pipeline object. Exemplarily, the second preset creation interface can be vkCreateGraphicsPipelines. Then the third preset creation interface is called to create a command buffer. Among them, the command buffer is a container for storing instructions executed by the GPU. The command buffer only stores commands and does not perform any operations itself. The command buffer and the rendering buffer are two independent areas. The GPU executes the clear screen command in the command buffer and renders all pixels in the rendering buffer corresponding to the above display area as clear screen color values. The third preset creation interface can be vkAllocateCommandBuffers. Accordingly, the instructions to be executed can be first stored in the command buffer, and can be extracted from the command buffer when execution is required for GPU execution.

[0090] Furthermore, after creating the command buffer, the preset recording interface can be called to start recording the command buffer, thereby setting the command buffer to an initial state, so as to write commands in the command buffer, and calling the preset binding interface to bind the graphics pipeline object to the command buffer, thereby writing a clear screen instruction to the command buffer according to the graphics pipeline object. Among them, the preset recording interface can be vkBeginCommandBuffer, and the preset binding interface can be vkCmdBindPipeline. In this way, the subsequent instructions can be written into the command buffer according to the graphics pipeline object, thereby ensuring that the clear screen operation can be performed according to the information defined by the graphics pipeline object.

[0091] Furthermore, the preset initiation drawing interface can be called to write a clear screen instruction to the command buffer to start the clear screen operation. Finally, the preset submission interface can be called to submit the clear screen instruction in the command buffer to the GPU, so that the GPU can execute the clear screen instruction in the command buffer, thereby realizing the clear screen operation. Among them, the preset initiation drawing interface can be a vkCmdDraw interface, and the preset submission interface can be a vkQueueSubmit interface. Specifically, after calling the vkCmdDraw interface, the driver corresponding to the vkCmdDraw interface will configure the drawing command package provided by the GPU according to the information defined by the bound graphics pipeline object, and then write the configured drawing command package to the command buffer, so as to realize the writing of the clear screen instruction to the command buffer according to the graphics pipeline object. Accordingly, the clear screen instruction refers to all the instructions required to realize the clear screen operation, and writing to the command buffer is the clear screen instruction.

[0092] Specifically, the information defined by the graphics pipeline object may include: the configured specified primitive assembly type and the configured shader module. Accordingly, the primitive type instruction, primitive generation instruction and pixel rendering instruction may be configured. The primitive type instruction is used to indicate the use of the specified primitive type. The primitive generation instruction is used to indicate the use of the configured vertex shader module to process according to the read vertex coordinates, width pixel value and height pixel value to obtain a pixel-level rectangular primitive instruction. The pixel rendering instruction is used to indicate the use of the configured fragment shader module to render each pixel in the pixel area as the read clear screen color value. In this way, by executing the clear screen instruction, the vertex shader module can determine the pixel area according to the read vertex coordinates, width pixel value and height pixel value, and then the fragment shader module renders all pixels in the pixel area as the read clear screen color value, thereby achieving clear screen.

[0093] Correspondingly, according to the clear screen color value, all pixels in the display area indicated by the vertex coordinates, width pixel values ​​and height pixel values ​​are rendered to achieve clear screen. When the GPU executes the primitive type instruction and the primitive generation instruction, it will respond to the primitive type instruction and the primitive generation instruction. In the vertex processing stage, the vertex shader generates 4 vertices of the rectangular area based on the read vertex coordinates, width pixel values ​​and height pixel values ​​(i.e., the vertex coordinates, width pixel values ​​and height pixel values ​​stored in the first receiving structure of the vertex shader). The coordinates of these 4 vertices represent the points of the four corners of the clear screen area (lower left, upper left, lower right and upper right). Among them, the vertex processing node can also be called the vertex shading stage, and the primitive assembly is a fixed function stage located after the vertex shader in the rendering pipeline. In the primitive assembly stage, the vertices are organized into specific primitives according to the data output by the vertex shader. Since the BLIT primitive is defined in the first creation information structure used when creating the graphics pipeline object, in the primitive assembly stage, these 4 vertices are assembled into a rectangle to obtain a pixel-level rectangular primitive. Among them, the primitive assembly stage can also be called the geometry rendering stage. The GPU executes the pixel rendering instruction, and in response to the pixel rendering instruction, it converts the pixel-level rectangular primitives into fragments in the rasterization stage, where a fragment can represent a pixel. Finally, in the fragment processing stage, the fragment shader sets all fragments to the clear screen color value based on the read clear screen color value (i.e., the vertex coordinates, width pixel value, height pixel value stored in the second receiving structure of the fragment shader) and writes them to the rendering buffer. The fragment processing stage can also be called the pixel processing stage.

[0094] In this embodiment, the GPU supports four primitive types: A, B, C, and BLIT. These four primitive types can be represented by 0, 1, 2, and 3, respectively. Accordingly, according to the specified primitive type defined by the graphics pipeline object, the specific bit in the command of the corresponding primitive type in the drawing command packet can be set to 3 to indicate the use of the BLIT type, and the command is written to the command buffer. In this way, when the GPU subsequently executes the clear screen instruction in the command buffer, it can ensure that the GPU uses the processing method for the BLIT type to render all pixels in the display area. Furthermore, the information defined by the graphics pipeline object can also include other information, such as rasterization status, color mixing mode, and the like. Exemplarily, it is assumed that the rasterization status information includes: information for characterizing the polygon mode (VK_POLYGON_MODE_FILL), and the color mixing mode information includes information for characterizing that all color channels are allowed to be written:

[0095] VK_COLOR_COMPONENT_r_bit, VK_COLOR_COMPONENT_g_bit, VK_COLOR_COMPONENT_b_bit, VK_COLOR_COMPONENT_a_bit,

[0096] The GPU can then convert the defined polygons (i.e. the above-mentioned rectangular primitives) into fragments in the rasterization stage. In the fragment processing stage, the values ​​of all color channels in the clear screen color value can be written into all color channels of all fragments through the fragment shader.

[0097] Accordingly, instructions for instructing to set the rasterization state and instructions for instructing to set the color mixing mode may also be configured to ensure that the primitive type, rasterization state and color mixing mode set during the screen clearing process conform to the information defined by the graphics pipeline object.

[0098] In one implementation, the drawing command packet may include multiple bytes, different bytes may correspond to different commands, and the content of the corresponding bytes may be set to implement the configuration of the above commands. For example, assuming that the drawing command packet is 2000 bytes, where the 1000th byte represents a command corresponding to the primitive type, then the 1000th byte may be set to 3 to obtain a primitive type instruction for indicating the use of the BLIT primitive.

[0099] In an embodiment of the present invention, a specified primitive type is defined in a first creation information structure; wherein the specified primitive type is a primitive type that supports pixel rendering based on vertex coordinates, width pixel values, and height pixel values. A graphics pipeline object is created based on the first creation information structure, and the graphics pipeline object is bound to a command buffer so as to write a clear screen instruction to the command buffer according to the graphics pipeline object. The GPU executes the clear screen instruction to render all pixels in the display area as clear screen color values ​​through a shader according to the read clear screen color values, vertex coordinates, width pixel values, and height pixel values. In this way, by configuring the specified primitive type, it can be ensured that pixel rendering can be performed according to vertex coordinates, width pixel values, and height pixel values, thereby ensuring the efficiency of the clear screen operation.

[0100] Optionally, in the embodiment of the present invention, the configuration may be implemented through the following steps:

[0101] Step S31: Create a second creation information structure based on the pre-declared first push range information of the clear screen area structure and the second push range information of the clear screen color structure; the second creation information structure is used to describe the creation information of the pipeline layout object.

[0102] Step S32: Create the pipeline layout object based on the second creation information structure, and bind the pipeline layout object to the first creation information structure to configure the push range information.

[0103] In an embodiment of the present invention, a second creation information structure can be generated based on the first push range information of the clear screen region structure declared above and the second push range information of the clear screen color structure declared above (for example, the pushConstantRegion and pushConstantColor described above). In this way, by creating a pipeline layout object based on the second creation information structure, it is possible to declare the push range information to be used in the pipeline layout object, so that the shader can correctly access the corresponding clear screen parameters based on the pipeline layout object. Accordingly, the push range can be configured by binding the pipeline layout object to the first creation information structure, so that the push range can be known later. The handle of the pipeline layout object can be assigned to a specified field in the first creation information structure to achieve binding. Exemplarily, the specified field can be a layout field. Further, the graphics pipeline object is created based on the first creation information structure, and the GPU can obtain the defined push range information from the pipeline layout object to which the graphics pipeline object is bound.

[0104] The second creation information structure and the aforementioned first creation information structure are used to create two different objects. Exemplarily, the second creation information structure may be VkPipelineLayoutCreateInfo, and the second creation information structure may be used to store the creation information of the pipeline layout object. The second creation information structure is used to describe how to create a pipeline layout object, and the pipeline layout object is used to define the resource layout used in the image pipeline created based on the first creation information structure. In this embodiment, the resource layout includes the above-mentioned push range information.

[0105] Furthermore, the first push range information, the second push range information and the number of push range information can be defined in the initial information structure to obtain a second creation information structure. For example, assuming that the number of push range information is 2, the generated second creation information structure can be expressed as:

[0106] VkPipelineLayoutCreateInfo pipelineLayoutInfo;

[0107] pipelineLayoutInfo.pushConstantRangeCount=2;

[0108] pipelineLayoutInfo.pPushConstantRanges

[0109] {

[0110] &pushConstantRegion,pushConstantColor

[0111] }

[0112] The number of push range information is defined in the second creation information structure: 2, and “&pushConstantRegion, pushConstantColo” in the second creation information structure represents the defined first push range information and second push range information.

[0113] Further, after obtaining the second creation information structure, the fourth preset creation interface can be called to create a pipeline layout object based on the second creation information structure. Exemplarily, the fourth preset creation interface can be a vkCreatePipelineLayout interface, which can be used to create a pipeline layout object based on the following command:

[0114] VkPipelineLayout pipelineLayout;

[0115] vkCreatePipelineLayout(&pipelineLayoutInfo,&pipelineLayout)

[0116] The created graphics pipeline object is represented by pipelineLayout. Accordingly, after configuring the specified primitive type, pipelineLayout can be bound to VkGraphicsPipelineCreateInfo so that the GPU can easily know the push range information of the clearing parameters.

[0117] In an embodiment of the present invention, a second creation information structure is created based on the first push range information of the pre-declared clear screen region structure and the second push range information of the clear screen color structure. A pipeline layout object is created based on the second creation information structure, and the pipeline layout object is bound to the first creation information structure to configure the push range information. In this way, when clearing the screen later, the GPU can easily obtain the push range information of the clear screen parameters, thereby ensuring processing efficiency.

[0118] In the embodiment of the present invention, the vertex coordinates, the pixel-level width pixel value, and the height pixel value are directly pushed to the first register through the constant push mechanism of the shader, and the screen clearing color value is pushed to the second register. At the same time, the specified primitive type is set, so that the pixel-level rectangular primitive can be determined based on the vertex coordinates, the pixel-level width pixel value, and the height pixel value. Accordingly, the similar fragment shader can directly perform rendering to achieve pixel-level rendering. In this way, there is no need to find the corresponding resource descriptor, and then access the content in the descriptor through vector memory access to obtain data such as vertex coordinates, so that the use of memory access instructions can be reduced, memory access operations can be reduced, and the workload of the GPU can be reduced. At the same time, there is no need to perform viewport transformation and primitive clipping. In this way, the screen clearing operation is optimized, efficient rendering is achieved, and the screen clearing efficiency can be improved to achieve efficient screen clearing.

[0119] It should be noted that the various interfaces called above (for example, the preset push interface, the first preset creation interface, the second preset creation interface, the third preset creation interface, the preset recording interface, the preset binding interface, the preset initiation drawing interface, the preset submission interface, and the fourth preset creation interface) can be interfaces provided by the drawing API. In an embodiment of the present invention, before using the drawing API, the drawing API environment can be initialized to perform a basic configuration process. Exemplarily, taking Vulkan as the drawing API, you can first create a Vulkan instance, then select a physical device, create a logical device based on the physical device, and create a graphics rendering queue on the logical device to complete the initialization of the drawing API environment. Next, create a window surface and an image exchange chain.

[0120] Accordingly, Figure 2 is a schematic diagram of a processing flow provided by an embodiment of the present invention, such as Figure 2 As shown, the drawing API environment can be initialized first, and then the window surface and the image exchange chain can be created. Next, a pipeline layout object is created, a first creation information structure is configured, and the pipeline layout object is bound to the first creation information structure. A graphics pipeline object is created based on the first creation information structure. Next, a command buffer is created, and the graphics pipeline object is bound to the command buffer. Then, the clear screen area parameters are pushed to the vertex shader, and the clear screen color parameters are pushed to the fragment shader. Specifically, the clear screen area parameters can be pushed to the first register, and the clear screen color parameters can be pushed to the second register. The vertex shader receives the clear screen area parameters in the first register, and the fragment shader receives the clear screen color parameters in the second register. Then, a clear screen instruction is written to the command buffer, and the GPU extracts the clear screen instruction from the command buffer and executes it, thereby achieving clear screen.

[0121] Among them, creating a Vulkan instance is equivalent to starting the context of the drawing API. The Vulkan instance can maintain the Vulkan environment throughout the application life cycle and provide a basis for all operations. The physical device is a hardware device that provides computing resources. For example, the physical device can be the above-mentioned GPU. The logical device is the core operation object of Vulkan, which represents the abstraction of the physical device. The graphics rendering queue is a pipeline for executing rendering instructions in Vulkan. The program can add the clear screen instruction in the command buffer to the rendering queue through the logical device request, and then submit it to the GPU for execution. Furthermore, the window surface is an object related to the window system. The window surface enables Vulkan to communicate with the window system, and then facilitates the window system to display the pixel data of the rendering buffer to the screen after rendering the pixel data of the rendering buffer to the clear screen color value. The image exchange chain is a group of images for alternating display in the window. Specifically, the pixel data of the rendering buffer can be stored in the image exchange chain, and then displayed on the screen by the window system, that is, the screen is cleared before displaying the image frame to be displayed in the image exchange chain.

[0122] Reference Figure 3 , shows a block diagram of a screen clearing device provided by an embodiment of the present invention, such as Figure 3 As shown, the screen cleaning device may specifically include:

[0123] The push module 201 is used to push the vertex coordinates, width pixel value, height pixel value defined in the predefined clear screen area structure and the clear screen color value defined in the clear screen color structure to the designated registers of the GPU respectively;

[0124] A reading module 202, configured to read the vertex coordinates, the width pixel value, the height pixel value and the clear screen color value from the designated registers respectively by a shader;

[0125] The rendering module 203 is used to render all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the clear screen color value to achieve clear screen.

[0126] Optionally, the push module 201 is specifically used for:

[0127] According to the configured push range information, respectively determine the first register corresponding to the clear screen area structure and the second register corresponding to the clear screen color structure; the designated register includes the first register and the second register;

[0128] The vertex coordinates, the width pixel value, and the height pixel value are pushed to the first register respectively, and the clear screen color value is pushed to the second register.

[0129] Optionally, the first register is a register allocated to the first shader, the second register is a register allocated to the second shader, the first shader pre-defines a first receiving structure for receiving the vertex coordinates, the width pixel value and the height pixel value, and the second shader pre-defines a second receiving structure for receiving the clear screen color value.

[0130] The reading module 202 is specifically used for:

[0131] The first shader reads the vertex coordinates, the width pixel value, and the height pixel value from the first register, and stores them in the first receiving structure;

[0132] The second shader reads the clear screen color value from the second register and stores it into the second receiving structure.

[0133] Optionally, the device further comprises:

[0134] a setting module, configured to define a specified primitive type in a first creation information structure of the GPU; wherein the specified primitive type is a primitive type that supports pixel rendering based on the vertex coordinates, the width pixel value, and the height pixel value, and the first creation information structure is used to describe creation information of a graphics pipeline object;

[0135] A first creation module, used for creating the graphics pipeline object based on the first creation information structure;

[0136] A first processing module is used to bind the graphics pipeline object to a command buffer, so as to write a screen clearing instruction to the command buffer according to the graphics pipeline object; the command buffer is used to provide the screen clearing instruction to the GPU;

[0137] The rendering module 203 is specifically used for the GPU to execute the clear screen instruction so as to render all pixels in the display area as the clear screen color value through the shader according to the read clear screen color value, the vertex coordinates, the width pixel value and the height pixel value.

[0138] Optionally, the device further comprises:

[0139] A second creation module is used to create a second creation information structure based on the first push range information of the clear screen area structure and the second push range information of the clear screen color structure declared in advance; the second creation information structure is used to describe the creation information of the pipeline layout object;

[0140] The second processing module is used to create the pipeline layout object based on the second creation information structure, and bind the pipeline layout object to the first creation information structure to configure the push range information.

[0141] In summary, in the screen clearing device provided by the embodiment of the present invention, the vertex coordinates, width pixel values, height pixel values ​​defined in the predefined screen clearing area structure, and the screen clearing color value defined in the screen clearing color structure are pushed to the designated register of the GPU respectively. The vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​are read from the designated registers by the shader respectively. According to the screen clearing color value, all pixels in the display area indicated by the vertex coordinates, width pixel values, and height pixel values ​​are rendered to achieve screen clearing. In this way, by directly pushing the vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​to the designated register, the shader can directly and conveniently obtain the vertex coordinates, width pixel values, height pixel values, and screen clearing color values ​​required for screen clearing from the designated register. At the same time, the display area required for screen clearing can be determined based on the vertex coordinates, width pixel values, and height pixel values, so the screen clearing efficiency can be improved and efficient screen clearing can be achieved.

[0142] Reference Figure 4 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus.

[0143] The processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the screen clearing method of the above embodiment. The executable instructions can form a program.

[0144] An embodiment of the present invention provides a machine-readable medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the screen clearing method of the aforementioned embodiment.

[0145] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0146] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0147] It should be noted that all actions of acquiring signals, information or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0148] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0149] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0150] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0151] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0152] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0153] Moreover, the terms "include", "comprises" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of more restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or terminal device that includes the element.

[0154] The screen clearing method, screen clearing device, electronic device and one or more readable media provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A screen cleaning method, characterized in that: The method comprises: Push the vertex coordinates, width pixel value, height pixel value defined in the pre-defined clear screen area structure and the clear screen color value defined in the clear screen color structure to the specified registers of the GPU respectively; The shader reads the vertex coordinates, the width pixel value, the height pixel value and the clear screen color value from the designated register respectively; According to the clear screen color value, all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value are rendered to achieve a clear screen.

2. The method according to claim 1, characterized in that The step of pushing the vertex coordinates, width pixel value, height pixel value defined in the predefined clear screen area structure and the clear screen color value defined in the clear screen color structure to the designated registers of the GPU respectively includes: According to the configured push range information, respectively determine the first register corresponding to the clear screen area structure and the second register corresponding to the clear screen color structure; the designated register includes the first register and the second register; The vertex coordinates, the width pixel value, and the height pixel value are pushed to the first register respectively, and the clear screen color value is pushed to the second register.

3. The method according to claim 2, characterized in that The first register is a register allocated for the first shader, and the second register is a register allocated for the second shader; Then, the shader reads the vertex coordinates, the width pixel value, the height pixel value, and the clear screen color value from the designated register respectively, including: The first shader reads the vertex coordinates, the width pixel value, and the height pixel value from the first register, and stores them in a first receiving structure; The second shader reads the clear screen color value from the second register and stores it in a second receiving structure.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Defining a specified primitive type in a first creation information structure of the GPU; wherein the specified primitive type is a primitive type that supports pixel rendering based on the vertex coordinates, the width pixel value, and the height pixel value; Creating a graphics pipeline object based on the first creation information structure; Binding the graphics pipeline object to a command buffer to write a screen clearing instruction to the command buffer according to the graphics pipeline object; the command buffer is used to provide the screen clearing instruction to the GPU; Then, rendering all pixels in the display area indicated by the vertex coordinates, the width pixel value, and the height pixel value according to the clear screen color value includes: The GPU executes the clear screen instruction to render all pixels in the display area to the clear screen color value through the shader according to the read clear screen color value, the vertex coordinates, the width pixel value, and the height pixel value.

5. The method according to claim 4, characterized in that The method further comprises: Creating a second creation information structure based on the pre-declared first push range information of the clear screen area structure and the second push range information of the clear screen color structure; A pipeline layout object is created based on the second creation information structure, and the pipeline layout object is bound to the first creation information structure to configure the push range information.

6. A screen cleaning device, characterized in that: The device comprises: A push module is used to push the vertex coordinates, width pixel value, height pixel value defined in a predefined clear screen area structure and the clear screen color value defined in a clear screen color structure to the specified registers of the GPU respectively; A reading module, configured to read the vertex coordinates, the width pixel value, the height pixel value, and the clear screen color value from the designated registers respectively by a shader; The rendering module is used to render all pixels in the display area indicated by the vertex coordinates, the width pixel value and the height pixel value according to the clear screen color value to achieve clear screen.

7. The device according to claim 6, characterized in that The push module is specifically used for: According to the configured push range information, respectively determine the first register corresponding to the clear screen area structure and the second register corresponding to the clear screen color structure; the designated register includes the first register and the second register; The vertex coordinates, the width pixel value, and the height pixel value are pushed to the first register respectively, and the clear screen color value is pushed to the second register.

8. The device according to claim 7, characterized in that The first register is a register allocated for the first shader, and the second register is a register allocated for the second shader; The reading module is specifically used for: The first shader reads the vertex coordinates, the width pixel value, and the height pixel value from the first register, and stores them in a first receiving structure; The second shader reads the clear screen color value from the second register and stores it in a second receiving structure.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the method according to any one of claims 1 to 5.

10. One or more machine-readable media, characterized in that Instructions are stored thereon, which, when executed by one or more processors, cause the processors to perform the method according to any one of claims 1 to 5.

Images