Data access method of system-on-chip, system-on-chip and electronic equipment

Abstract

The invention discloses a data access method of a system-on-chip, the system-on-chip and electronic equipment, and belongs to the field of chips. In the method, for any AHB master device in the system on chip, at least two access links exist between the AHB master device and any APB slave device, on the basis, when the AHB master device sends an access request to the APB slave device through one of the access links, a data bridge connected with the APB slave device can temporarily store data of the access request to release an APB bus in advance, and the APB slave device can release the APB bus in advance. According to the method and the device, the AHB master device can access the APB slave device through other access links, or access other APB slave devices, so that the use efficiency and the utilization rate of the bus in the system on chip are improved.

Description

Technical Field

[0001] The present application relates to the field of chips, and in particular to a data access method for a system on chip, a system on chip, and an electronic device. Background Art

[0002] Advanced High-performance Bus (AHB) and Advanced Peripheral Bus (APB) are commonly used bus protocols in chip design. Currently, in a system on chip (SoC) using AHB and APB, only one AHB master device can access an APB slave device at the same time.

[0003] In the related art, for some APB slave devices (also called low-speed devices or low-speed modules, etc.) with low operating frequency and low data transmission rate, when the AHB master device performs write operations on the low-speed devices through APB, due to the slow processing speed of these low-speed devices, the AHB master device can only wait for the low-speed devices to complete the operation before releasing the APB bus, resulting in the APB bus being occupied by the low-speed devices for a long time, affecting the use efficiency and utilization of the APB bus. Summary of the invention

[0004] The embodiments of the present application provide a data access method for a system on chip, a system on chip, and an electronic device, which can improve the use efficiency and utilization rate of the bus in the system on chip. The technical solution is as follows.

[0005] In a first aspect, a data access method of a system on chip is provided, which is applied to the system on chip, wherein the system on chip includes a first bus system using an advanced high performance bus AHB and a second bus system using an advanced peripheral bus APB, wherein the first bus system and the second bus system are connected via a plurality of AHB-APB bridges, and there are at least two access links between each AHB master device in the first bus system and each APB slave device in the second bus system, and each APB slave device is connected to a data bridge, wherein the method includes:

[0006] A first AHB master device in the first bus system sends a first access request to a first APB slave device in the second bus system through a first access link;

[0007] The first data bridge connected to the first APB slave device receives the first access request, and if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, sends an APB release signal to the first AHB master device; or, if the first access request is a read request, after reading the data of the first access request from the first APB slave device and storing the read data in the first data bridge, sends an APB release signal to the first AHB master device;

[0008] After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, or sends a third access request to a second APB slave device in the second bus system through a third access link;

[0009] The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0010] In some embodiments, the method further comprises:

[0011] If the first access request is a write request, after the first data bridge stores the data of the first access request in the first data bridge, when the first APB slave device is in an idle state, writing the data of the first access request into the first APB slave device;

[0012] If the first access request is a read request, the first data bridge transmits the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device.

[0013] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, sending an APB release signal to the first AHB master device includes:

[0014] The first data bridge determines the storage level of the data based on the type of the data in the first access request, where different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances;

[0015] The first data bridge stores the data in a storage area corresponding to the storage level in the first data bridge based on the storage level of the data.

[0016] In some embodiments, the first data bridge stores the data in a storage area corresponding to the storage level in the first data bridge based on the storage level of the data, including:

[0017] The first data bridge stores the data in a first storage area in the first data bridge based on the storage level of the data;

[0018] The method further comprises:

[0019] The first data bridge predicts the state of the first APB slave device. If the prediction result indicates that the first APB slave device will change from the busy state to the idle state within a preset time period, the data is transferred from the first storage area to the second storage area in the first data bridge, and the access performance of the second storage area is higher than the access performance of the first storage area.

[0020] In some embodiments, the method further comprises:

[0021] The first AHB master device records execution information of access requests sent to the first APB slave device through different access links, where the execution information includes at least one of execution duration and execution success rate of the access request;

[0022] After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, including:

[0023] After receiving the APB release signal, the first AHB master device determines the second access link from multiple access links based on the execution information, and sends the second access request to the first APB slave device through the second access link, wherein the multiple access links do not include the first access link.

[0024] In some embodiments, the first access link includes a first arbitrator, a first AHB-APB bridge, and a second arbitrator; the first AHB master device sends a first access request to a first APB slave device in the second bus system through the first access link, including:

[0025] The first AHB master device sends the first access request to the first arbitrator;

[0026] After the first arbitrator arbitrates the received first access request and the fourth access request sent by the second AHB master device, the first access request is sent to the second arbitrator through the first AHB-APB bridge;

[0027] The second arbitrator arbitrates the received first access request and the fifth access request sent by the third AHB master device, and then sends the first access request to the first data bridge.

[0028] In some embodiments, the first arbiter, the first AHB-APB bridge, and the second arbiter all have a fault detection function, and the method further includes:

[0029] In the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, if any one of the first arbitrator, the first AHB-APB bridge and the second arbitrator detects that the first access link fails, the node switches the first access request to a fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link.

[0030] In a second aspect, a system on chip is provided, the system on chip comprising a first bus system using an advanced high performance bus AHB and a second bus system using an advanced peripheral bus APB, the first bus system and the second bus system are connected via a plurality of AHB-APB bridges, at least two access links exist between each AHB master device in the first bus system and each APB slave device in the second bus system, and each APB slave device is connected to a data bridge;

[0031] a first AHB master device in the first bus system, configured to send a first access request to a first APB slave device in the second bus system via a first access link;

[0032] a first data bridge connected to the first APB slave device, configured to receive the first access request, and if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, send an APB release signal to the first AHB master device; or, if the first access request is a read request, after reading the data of the first access request from the first APB slave device and storing the read data in the first data bridge, send an APB release signal to the first AHB master device;

[0033] The first AHB master device is further configured to, after receiving the APB release signal, send a second access request to the first APB slave device through a second access link, or send a third access request to a second APB slave device in the second bus system through a third access link;

[0034] The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0035] In some embodiments, if the first access request is a write request, the first data bridge is also used to, after storing the data of the first access request in the first data bridge, write the data of the first access request to the first APB slave device when the first APB slave device is in an idle state; if the first access request is a read request, the first data bridge is also used to transmit the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device.

[0036] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, the first data bridge is used to determine the storage level of the data based on the type of data in the first access request, different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances; based on the storage level of the data, the data is stored in the storage area corresponding to the storage level in the first data bridge.

[0037] In some embodiments, the first data bridge is used to store the data in a first storage area in the first data bridge based on the storage level of the data; predict the state of the first APB slave device, and if the prediction result indicates that the first APB slave device will change from the busy state to the idle state within a preset time period, transfer the data from the first storage area to a second storage area in the first data bridge, and the access performance of the second storage area is higher than the access performance of the first storage area.

[0038] In some embodiments, the first AHB master device is further used to record execution information of access requests sent to the first APB slave device through different access links, the execution information including at least one of the execution duration and execution success rate of the access request; after receiving the APB release signal, based on the execution information, determine the second access link from multiple access links, and send the second access request to the first APB slave device through the second access link, and the multiple access links do not include the first access link.

[0039] In some embodiments, the first access link includes a first arbitrator, a first AHB-APB bridge and a second arbitrator; the first AHB master device is used for the first AHB master device to send the first access request to the first arbitrator; the first arbitrator is used to arbitrate the first access request received and the fourth access request sent by the second AHB master device, and then send the first access request to the second arbitrator through the first AHB-APB bridge; the second arbitrator is used to arbitrate the first access request received and the fifth access request sent by the third AHB master device, and then send the first access request to the first data bridge.

[0040] In some embodiments, the first arbitrator, the first AHB-APB bridge and the second arbitrator all have a fault detection function. In the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, if any one of the first arbitrator, the first AHB-APB bridge and the second arbitrator detects that the first access link has a fault, the node is used to switch the first access request to a fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link.

[0041] According to a third aspect, an electronic device is provided, comprising a memory and a processor, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip provided in the first aspect.

[0042] In a fourth aspect, a computer-readable storage medium is provided, characterized in that at least one computer program is stored in the computer-readable storage medium, and the at least one computer program is loaded and executed by a processor to implement the data access method of the on-chip system provided in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 It is a schematic diagram of an implementation environment provided by an embodiment of the present application;

[0045] Figure 2is a flow chart of a data access method of a system on chip provided by an embodiment of the present application;

[0046] Figure 3 It is a structural schematic diagram of a data bridge provided in an embodiment of the present application;

[0047] Figure 4 is a schematic diagram of a data access device of a system on chip provided by an embodiment of the present application;

[0048] Figure 5 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0050] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions. For example, the access requests and device priorities involved in this application are all obtained with full authorization.

[0051] Figure 1 Schematic diagram of an implementation environment provided by the embodiment of the present application. Figure 1 As shown, the implementation environment includes a system on chip 100, which includes a first bus system 110 using an advanced high-performance bus AHB and a second bus system 120 using an advanced peripheral bus APB, and the first bus system 110 and the second bus system 120 are connected via multiple AHB-APB bridges. There are at least two access links between each AHB master device in the first bus system 110 and each APB slave device in the second bus system 120, and each APB slave device is connected to a data bridge.

[0052] Taking any access link between any AHB master device and any APB slave device as an example, the access link includes: an AHB master device, a multiplexer, an arbiter, an AHB-APB bridge, an arbiter, an APB interface, a data bridge and an APB slave device.

[0053] Among them, the AHB master device is, for example, a central processing unit (CPU), a direct memory access (DMA) controller or other auxiliary operators, and the present application does not limit the type of the AHB master device. The multiplexer is also called an address selector, which is used to select any one of the multiple data transmissions as needed, and is also called a multiplexer or a multi-way switch. The input end of the multiplexer is connected to the AHB master device, and the multiple output ends of the multiplexer are respectively connected to multiple arbitrators, and the output end of each arbitrator is respectively connected to an AHB-APB bridge. For any AHB-APB bridge, the multiple output ends of the AHB-APB bridge are respectively connected to multiple arbitrators, and the output end of each arbitrator is respectively connected to an APB interface, and the multiple output ends of each APB interface are respectively connected to multiple data bridges, and each data bridge is respectively connected to an APB slave device. APB slave devices refer to peripheral devices, such as universal asynchronous receivers and transmitters, serial peripheral interfaces, timers, etc. It should be understood that since these peripheral devices have a slower data transmission speed than APB, when these peripheral devices interact with the AHB master device in the system through APB, due to their own slow speed, APB will wait for the peripheral device operation to complete before releasing the bus, which will affect the efficiency and utilization of the bus. These peripheral devices can also be called a low-speed intellectual property (IP) module. It should be understood that IP in the field of chip design refers to a circuit module design with specific functions and reusable, and low speed means that the data transmission speed of the peripheral device is slower than that of APB.

[0054] As shown above, in the system on chip 100, through a multiplexer, an AHB master device can be interconnected and accessed with multiple different AHB-APB bridges (in this process, the AHB-APB bridge can be understood as an AHB slave device relative to the AHB master device). Furthermore, each AHB-APB bridge is connected to an arbiter to ensure that a single AHB-APB bridge is only accessed by one AHB master device at the same time. The arbiter also ensures that the APB interface connected at the same time can only be accessed by one AHB-APB bridge, that is, an AHB-APB bridge can be interconnected and accessed with multiple different APB slave devices (in this process, the AHB-APB bridge can be understood as an APB master device relative to the APB slave device), but at the same time, a single APB slave device can only be accessed by one AHB-APB bridge.

[0055] In addition, in the system on chip 100, there are at least two non-interfering access links between any AHB master device and any APB slave device, so that the AHB master device can simultaneously access the APB slave device using at least two non-interfering access links, thereby improving the system processing performance. Figure 1 The above is only an example and does not constitute a limitation of the present application. As the number of AHB master devices, AHB-APB bridges and APB interfaces increases, the number of master-slave access links that do not interfere with each other can be further increased, and the system processing speed can be further improved.

[0056] The above-mentioned system on chip 100 can be deployed in electronic devices. The electronic devices are, for example, vehicle terminals, smart phones, tablet computers, laptop computers, desktop computers, smart watches, etc., but are not limited thereto. Exemplarily, the electronic device is a vehicle terminal carried by the vehicle itself. In some embodiments, the vehicle is a new energy vehicle, such as a pure electric vehicle, a plug-in hybrid vehicle, a fuel cell electric vehicle, etc., which is not limited in this application. When the system on chip 100 is deployed in a vehicle terminal, the AHB master device is, for example, a CPU, which is responsible for running an operating system, various vehicle applications, and processing data received from different sensors and devices. The AHB master device is also, for example, a DMA controller. There is a large amount of data in the vehicle terminal that needs to be quickly transferred between different storage areas or devices, such as reading map data from a flash memory to a memory. As an AHB master device, the DMA controller can directly perform high-speed data transmission between the memory and other devices without occupying CPU resources, and control the data flow through the AHB to achieve efficient data handling. The APB slave device is, for example, a universal asynchronous receiver and transmitter, which is used for serial communication between the vehicle terminal and the external device. Another example is a timer, a serial peripheral interface SPI, and an integrated circuit bus I2C interface. Among them, SPI and I2C interfaces are used to connect various low-speed peripheral devices, such as sensors (temperature sensors, tire pressure sensors, etc.) and some simple actuators. These interfaces act as APB slave devices, reading sensor data or sending control signals to actuators according to the instructions of the APB master device to realize the interaction between the vehicle system and external devices. For example, the data of the tire pressure sensor is read through the SPI interface and the data is transmitted to the vehicle terminal for tire pressure monitoring and alarm.

[0057] Figure 2 1 is a flow chart of a data access method of a system on chip provided by an embodiment of the present application. Figure 2 As shown, this method is applied to Figure 1 The system on chip shown takes the interaction between various components in the system on chip as an example to introduce the data access method of the system on chip. The method includes the following steps 201 to 204.

[0058] 201. A first AHB master device in a first bus system sends a first access request to a first APB slave device in a second bus system through a first access link.

[0059] In an embodiment of the present application, the system on chip includes a first bus system using AHB and a second bus system using APB. The first AHB master device is any AHB master device in the first bus system, and the first APB slave device is any APB slave device accessible by the first AHB master device in the second bus system. The first access request is a write request or a read request, which is not limited in the present application.

[0060] Schematically, the first access link includes a first AHB master device, a multiplexer, a first arbitrator, a first AHB-APB bridge, a second arbitrator, an APB interface, a first data bridge, and a first APB slave device. The first arbitrator and the second arbitrator can both receive multiple access requests at the same time, and arbitrate the received multiple access requests to determine the priority of each access request, or determine the order in which each access request is sent.

[0061] In some embodiments, during the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, the first AHB master device sends the first access request to the first arbitrator through the multiplexer, and the first arbitrator arbitrates the received first access request and the fourth access request sent by the second AHB master device, and then sends the first access request to the second arbitrator through the first AHB-APB bridge. After the second arbitrator arbitrates the received first access request and the fifth access request sent by the third AHB master device, it sends the first access request to the first data bridge connected to the first APB slave device. That is, when the first arbitrator and the second arbitrator both receive multiple access requests at the same time, arbitration is used to determine whether to send the first access request first. Among them, the second AHB master device is any AHB master device other than the first AHB master device in the first bus system, and the third AHB master device is any AHB master device other than the first AHB master device in the first bus system, and the second AHB master device and the third AHB master device are the same or different.

[0062] In some embodiments, the first arbitrator arbitrates the received first access request and the fourth access request based on the priority of the first AHB master device and the priority of the second AHB master device, and sends the first access request to the second arbitrator through the first AHB-APB bridge when the priority of the first AHB master device is higher than the priority of the second AHB master device. Among them, the priority of the first AHB master device and the second AHB master device can be pre-set, or it can be determined by the first arbitrator based on the access requests received in the historical time period. For example, the first arbitrator records the access requests of each AHB master device in the historical time period, such as recording the historical information such as the request frequency, the data transmission volume and the transmission delay requirement, and determines the priority weight of each AHB master device based on the historical information. When multiple access requests arrive at the first arbitrator at the same time, it is determined which request is processed first according to these weights. For example, for AHB master devices that often need to transmit a large amount of real-time data and are delay-sensitive, a higher priority is given, so that the transmission requirements of different types of data in the system can be better met and the overall performance can be improved. It should be noted that the second arbitrator can adopt the same arbitration method as the first arbitrator, which will not be repeated here.

[0063] 202. A first APB receives a first access request from a first data bridge to which the device is connected.

[0064] In an embodiment of the present application, a first APB slave device is connected to a first data bridge, and the first data bridge is connected to an APB interface. When a first access request of a first AHB master device reaches the APB interface through the AHB on the first access link and the first AHB-APB bridge, the APB interface receives the first access request, parses the first access request to obtain an access type, and transmits a corresponding signal to the first data bridge based on the access type so that the first data bridge writes data or reads data to the first APB slave device. For example, the APB interface parses the first access request based on a predefined control signal encoding format, and when it is identified that a specific write operation flag is set, it determines that the access type is a write request, and when it is identified that a specific read operation flag is set, it determines that the access type is a read request.

[0065] Typically, the APB interface parses the first access request. If it is determined that the access type is a write request, the write request, access address, and write data signal are transmitted to the first data bridge. The first data bridge synchronizes the write data signal to the interface timing of the first APB slave device. If the completion signal of the current first APB slave device is high, the write data is written to the first APB slave device. It should be understood that only when the first APB slave device is ready (the completion signal is high) to write data can data integrity be guaranteed, and errors caused by forced writing when the first APB slave device is not ready can be avoided. In the above process, the first data bridge returns a write data completion signal upon receiving the write request, access address, and write data signal. Through this signal, the PREADY signal in the APB is pulled high, the APB bus is released, and the first AHB master device is allowed to access the APB slave device through the above APB interface again.

[0066] Alternatively, the APB interface parses the first access request, and if it is determined that the access type is a read request, the read request, the access address, and the read data signal are transmitted to the first data bridge, and the first data bridge synchronizes the read data signal to the interface timing of the first APB slave device. If the current first APB slave device is in an idle state, the data is read and transmitted to the APB interface through the first data bridge, and the APB interface returns the data to the first AHB master device.

[0067] In the present application, there are at least two non-interfering access links between the first AHB master device and the first APB slave device. Based on this, when the first access request is a write request and the first APB slave device is in a busy state, the first data bridge can store the data of the first access request to the first data bridge, and then send an APB release signal to the first AHB master device in advance. Alternatively, when the first access request is a read request, the first data bridge reads the data of the first access request from the first APB slave device and stores the read data to the first data bridge, and then sends an APB release signal to the first AHB master device. These two situations are introduced below through step 203A and step 203B respectively.

[0068] 203A: The first access request is a write request and the first APB slave device is in a busy state. After the first data bridge stores the data of the first access request in the first data bridge, it sends an APB release signal to the first AHB master device.

[0069] After storing the data of the first access request in the first data bridge, the first data bridge sends an APB release signal to the first AHB master device, and writes the data of the first access request into the first APB slave device when the first APB slave device is in an idle state.

[0070] In some embodiments, the first data bridge is configured with multiple storage areas, different storage areas correspond to different access performances, and different storage areas correspond to different storage levels. Schematically, the first data bridge determines the storage level of the data based on the type of data in the first access request; the first data bridge stores the data in the storage area corresponding to the storage level in the first data bridge based on the storage level of the data. For example, the types of data include real-time data, control data and batch data, and accordingly, the storage levels of the data are level one, level two and level three from high to low, that is, for frequently accessed real-time data, its storage level is determined to be level one, and it is stored in a storage area with higher access performance, which can improve the speed of subsequently writing data to the first APB slave device. Schematically, taking the deployment of the system on chip on the vehicle terminal as an example, the real-time obstacle detection data from the laser radar belongs to real-time data, and its storage level is level one; the control instruction data for the vehicle power system belongs to control data, and its storage level is level two; the regularly collected vehicle driving history data is used for background analysis, and belongs to batch data, and its storage level is level three.

[0071] In addition, the capacity of each storage area in the first data bridge can be dynamically configured according to the average traffic and peak demand of the corresponding type of data in the system. Taking the storage area corresponding to real-time data as an example, 1KB of space is initially allocated. When the usage rate of this area exceeds 80%, the replacement mechanism based on the Least Recently Used (LRU) algorithm is started to ensure that there is always enough space to store frequently accessed real-time data.

[0072] In other embodiments, after the first data bridge stores the data in a storage area with lower access performance, when the first data bridge determines that the first APB slave device is about to be idle, the data can be pre-fetched from the storage area with lower access performance to the storage area with higher access performance in advance, so that when the first APB slave device is idle, the data can be quickly acquired, reducing the delay in data transmission. Schematically, the first data bridge stores the data in a storage area corresponding to the storage level in the first data bridge based on the storage level of the data, including: the first data bridge stores the data in a first storage area in the first data bridge based on the storage level of the data; the first data bridge predicts the state of the first APB slave device, and if the prediction result indicates that the first APB slave device will change from a busy state to an idle state within a preset time period, the data is transferred from the first storage area to a second storage area in the first data bridge, and the access performance of the second storage area is higher than the access performance of the first storage area.

[0073] 203B: The first access request is a read request. After the first data bridge reads the data of the first access request from the first APB slave device and stores the read data in the first data bridge, it sends an APB release signal to the first AHB master device.

[0074] Among them, after the first data bridge stores the data of the first access request to the first data bridge, it sends an APB release signal to the first AHB master device, and transmits the data of the first access request to the first AHB master device. It should be understood that APB adopts an operation mode based on signal control. When performing a read operation, the APB slave device will occupy the bus to transmit data. When the data bridge returns to release the APB release signal, it indicates that the data bridge determines that the APB slave device has completed the main operation of the data reading phase, that is, sending the data to the bus to prepare for transmission to the master device. In the process of data being transmitted from the APB slave device to the AHB master device through the APB bus, the transmission of data is relatively independent of the allocation of bus resources. Once the data has been sent to the bus, it will be transmitted to the destination according to the transmission mechanism of the bus (such as clock drive, etc.). At this time, the APB slave device no longer needs to occupy the bus all the time to ensure the transmission of data, so that the bus can be released.

[0075] 204. After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through the second access link, or sends a third access request to the second APB slave device in the second bus system through the third access link.

[0076] In an embodiment of the present application, after the first AHB master device receives the APB release signal, it can continue to access the first APB slave device through the second access link, and can also access other APB slave devices in the second bus system, that is, the second APB slave device, through the third access link. Among them, the access link between the first AHB master device and the first APB slave device includes a first access link and a second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different. In addition, the second APB slave device is connected to a second data bridge, and the second data bridge has the same function as the first data bridge, which will not be repeated.

[0077] In some embodiments, the first AHB master device records the execution information of the access request sent to the first APB slave device through different access links, and the execution information includes at least one of the execution time and execution success rate of the access request; after the first AHB master device receives the APB release signal, the second access request is sent to the first APB slave device through the second access link, including: after the first AHB master device receives the APB release signal, based on the execution information, the second access link is determined from multiple access links, and the second access request is sent to the first APB slave device through the second access link, and the multiple access links do not include the first access link. For example, by setting a monitoring point on each AHB-APB bridge, the data flow, transmission delay and other parameters of each access link are counted in real time, so that the first AHB master device can record the execution information of the access request sent to the first APB slave device through different access links based on these parameters. When a new access link needs to be selected, the first AHB master device selects an access link with a large number of successful data transmissions and a low error rate within a period of time based on the recorded execution information, which can improve the efficiency and reliability of data transmission.

[0078] In other embodiments, the first arbitrator, the first AHB-APB bridge, and the second arbitrator on the first access link all have a fault detection function. Based on this, in the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, if any node in the first arbitrator, the first AHB-APB bridge, and the second arbitrator detects that the first access link has a fault, the node switches the first access request to the fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link. Schematically, the first arbitrator, the first AHB-APB bridge, and the second arbitrator are configured with an additional fault detection circuit for detecting data transmission errors, signal integrity problems, etc. When any node detects a fault, the recovery mechanism is started in time to switch the link to improve the reliability and stability of the system. Moreover, the node can feedback the fault information to the first AHB master device for further fault diagnosis and processing. For example, the first arbitrator, the first AHB-APB bridge, and the second arbitrator use 100ns as a detection cycle, and check the transmitted data through the built-in parity check circuit. Once the number of error bits detected exceeds the threshold (such as 2 bits), the fault detection process is triggered. After the link is switched to the fourth access link, the handshake signal is used for data synchronization to ensure the continuity of the data before and after the switch, and the data of the previous cycle is verified by retransmitting the data to ensure stable operation of the system. Schematically, taking the deployment of the system on a chip on a vehicle terminal as an example, the data transmission link may fail due to factors such as vehicle vibration and electromagnetic interference. For example, when the data transmission link of the vehicle communication module fails, the system can quickly switch to the backup link to ensure the continuity of communication and avoid data loss, thereby improving the reliability and stability of the entire vehicle terminal in complex environments.

[0079] Reference below Figure 3 The data bridge shown is used to illustrate the data access method of the above-mentioned system on chip. Figure 3 Schematic diagram of a data bridge provided by an embodiment of the present application. Figure 3As shown in the figure, the data bridge serves as a link for data transmission between the APB and the APB slave device (i.e., IP module), and includes the following modules: data synchronization module, control signal buffer module, address buffer module, write data buffer module, and IP interface conversion module. These modules can collaboratively implement the following functions: transmit and receive data buffer, data clock domain synchronization, and generation of release bus control signals. In the figure, PWRITE is a write enable signal, PSEL is a chip select signal, PENABLE is an enable signal, PADDR is an address signal, PWDATA is a write data signal, PSLVERR is a slave device error signal, PREADY is a ready signal, REG_EN is a register enable signal, IP_IDLE is an IP module idle signal, IP_RDATA is an IP module read data signal, IP_WDATA is an IP module write data signal, DATA_ERR is a data error signal, read_en is a read enable signal, and write_en is a write enable signal.

[0080] Taking the access request received by the data bridge as a write request as an example, if the write data control signals such as PWRITE, PSEL, PENABLE are valid, and the storage area in the data bridge is not full (REG_EN=1), the data bridge returns the PREADY signal to the AHB master device to inform it that the current write operation is ready. The AHB master device can decide whether to continue to send subsequent data or perform other related operations based on this signal. If the storage area in the A data bridge is full, APB needs to wait and cannot release the APB bus until the storage area can be written. During this period, the AHB master device can operate normally on other APB slave devices. When data can be written to the APB slave device, the PSEL, PENABLE, PWRITE signals and WDATA are synchronized to the clock domain of the APB slave device. Then PWDATA is stored in the cache module of the data bridge, converted into the interface timing of the APB slave device and transmitted to the APB slave device.

[0081] Taking the access request received by the data bridge as a read request as an example, the data bridge synchronizes PSEL, PENABLE, and PWRITE to the clock domain of the APB slave device, and converts them into interface signals of the APB slave device and sends them to the APB slave device. If the APB slave device has no operation at this time and can execute a read request, the APB slave device will transmit write_en and read_en signals to the IP interface conversion module. If both signals are valid (that is, write_en and read_en signals are valid markers), it means that the APB slave device is idle at this time and can perform a read operation. At this time, the IP interface conversion module transmits the read request to the APB slave device.

[0082] In addition, the address cache module is used to control the address delay. Schematically, if the current access request has not been completed (i.e. IP_IDLE≠1), it will wait until the APB slave device reads and writes data operations are completed (i.e. IP_IDLE=1); otherwise, the address cache module transmits the address to the IP interface conversion module to execute the access request.

[0083] The write data cache module is used to control the delay of writing data. In schematic form, if the current access request has not been completed (i.e. IP_IDLE≠1), it will wait until the APB slave device read and write data operations are completed (i.e. IP_IDLE=1); otherwise, the write data cache module will transfer the write data to the IP interface conversion module to execute the access request.

[0084] The read / write control signal buffer module is used to control the delay of the read / write control signal. If the current access request has not been completed (i.e. IP_IDLE≠1), it will wait until the APB slave device completes (i.e. IP_IDLE=1); otherwise, the read / write control signal buffer module transmits the read / write control signal to the IP interface conversion module to execute the access request.

[0085] The data synchronization module is used to synchronize PSEL, PENABLE, PWDATA, PWRITE, etc. of APB to the clock domain of APB slave device during the execution of write request. Also, in the process of executing read request, it synchronizes data such as IP_RDATA and DATA_ERR of APB to the clock domain of APB slave device, and then transmits it to APB, and finally returns the data signal to AHB master device.

[0086] In summary, in the data access method of the system on chip provided in the embodiment of the present application, for any AHB master device in the system on chip, there are at least two access links between the AHB master device and any APB slave device. Based on this, when the AHB master device sends an access request to the APB slave device through one of the access links, the data bridge connected to the APB slave device can temporarily store the data of the access request to release the APB bus in advance, so that the AHB master device can access the APB slave device through other access links, or access other APB slave devices, thereby improving the use efficiency and utilization rate of the bus in the system on chip.

[0087] In addition, when the above-mentioned system on chip is deployed in a vehicle terminal, since there are multiple data that need to be processed simultaneously in the vehicle terminal, such as navigation data, multimedia data, vehicle sensor data, etc., by using the above-mentioned system on chip, there are at least two non-interfering access links between the first AHB master device and the first APB slave device, which enables different types of data to be transmitted through different links, avoiding the bottleneck of data transmission. For example, when the navigation system needs to frequently update the map data (through write requests), the vehicle status monitoring system can read the sensor data through another link, which improves the concurrent processing capability of the system and effectively improves the data access efficiency.

[0088] See also Figure 4 An embodiment of the present application provides a data access device of a system on chip, which can be configured in the system on chip. Schematically, the device includes a first sending module 401, a receiving module 402 and a second sending module 403.

[0089] A first sending module 401, configured in a first AHB master device in a first bus system, is used to send a first access request to a first APB slave device in a second bus system through a first access link;

[0090] A receiving module 402, configured at a first data bridge connected to a first APB slave device, for receiving a first access request, and if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, sending an APB release signal to the first AHB master device, or, if the first access request is a read request, after reading the data of the first access request from the first APB slave device and storing the read data in the first data bridge, sending an APB release signal to the first AHB master device;

[0091] The second sending module 403 is configured in the first AHB master device, and is used to send a second access request to the first APB slave device through the second access link after receiving the APB release signal, or send a third access request to the second APB slave device in the second bus system through the third access link;

[0092] The access link between the first AHB master device and the first APB slave device includes a first access link and a second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

[0093] In some embodiments, the apparatus further comprises:

[0094] a writing module, configured on the first data bridge, for, if the first access request is a write request, storing the data of the first access request in the first data bridge, and writing the data of the first access request into the first APB slave device when the first APB slave device is in an idle state;

[0095] The transmission module is configured on the first data bridge, and is used for transmitting the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device if the first access request is a read request.

[0096] In some embodiments, if the first access request is a write request and the first APB slave device is in a busy state, the write module is used to: determine the storage level of the data based on the type of data in the first access request, different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances; based on the storage level of the data, store the data in the storage area corresponding to the storage level in the first data bridge.

[0097] In some embodiments, the writing module is used to: store the data to a first storage area in the first data bridge based on the storage level of the data;

[0098] The device also includes a transfer module, which is configured on the first data bridge and is used to predict the state of the first APB slave device. If the prediction result indicates that the first APB slave device will change from a busy state to an idle state within a preset time period, the data is transferred from the first storage area to the second storage area in the first data bridge, and the access performance of the second storage area is higher than the access performance of the first storage area.

[0099] In some embodiments, the apparatus further includes: a recording module, configured in the first AHB master device, for recording execution information of access requests sent to the first APB slave device through different access links, the execution information including at least one of execution duration and execution success rate of the access request;

[0100] The second sending module 403 is used to determine a second access link from multiple access links based on the execution information after receiving the APB release signal, and send a second access request to the first APB slave device through the second access link, wherein the multiple access links do not include the first access link.

[0101] In some embodiments, the first access link includes a first arbitrator, a first AHB-APB bridge and a second arbitrator; sending a first access request to the first APB slave device in the second bus system through the first access link includes: the first AHB master device sends the first access request to the first arbitrator; after the first arbitrator arbitrates the received first access request and the fourth access request sent by the second AHB master device, the first access request is sent to the second arbitrator through the first AHB-APB bridge; after the second arbitrator arbitrates the received first access request and the fifth access request sent by the third AHB master device, the first access request is sent to the first data bridge.

[0102] In some embodiments, the first arbitrator, the first AHB-APB bridge and the second arbitrator all have a fault detection function. The device also includes: a link switching module, which is used to switch the first access request to the first APB slave device through the first access link if any one of the first arbitrator, the first AHB-APB bridge and the second arbitrator detects that the first access link has a fault. The node switches the first access request to the fourth access link to send the first access request to the first APB slave device through the fourth access link. The access link between the first AHB master device and the first APB slave device includes the fourth access link.

[0103] In summary, in the data access device of the system on chip provided in the embodiment of the present application, for any AHB master device in the system on chip, there are at least two access links between the AHB master device and any APB slave device. Based on this, when the AHB master device sends an access request to the APB slave device through one of the access links, the data bridge connected to the APB slave device can temporarily store the data of the access request to release the APB bus in advance, so that the AHB master device can access the APB slave device through other access links, or access other APB slave devices, thereby improving the use efficiency and utilization rate of the bus in the system on chip.

[0104] It should be noted that: the data access device of the system on chip provided in the above embodiment only uses the division of the above functional modules as an example when executing the data access of the system on chip. In actual application, the above functions can be assigned to different functional modules as needed, that is, the internal structure can be divided into different functional modules to complete all or part of the functions described above. In addition, the data access device of the system on chip provided in the above embodiment and the data access method embodiment of the system on chip belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0105] refer to Figure 5 , the embodiment of the present application further provides an electronic device, Figure 5It is a structural diagram of an electronic device provided in an embodiment of the present application. The electronic device 500 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 601 and one or more memories 502, wherein the memory 502 stores at least one computer program, and the at least one computer program is loaded and executed by the processor 501 to implement the data access method of the on-chip system provided in the above method embodiment. Of course, the electronic device may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output, and the electronic device may also include other components for implementing the functions of the device, which will not be described in detail here.

[0106] The embodiment of the present application also provides a computer-readable storage medium, in which at least one computer program is stored, and the at least one computer program is loaded and executed by a processor of an electronic device to implement the data access method of the system on chip of the above embodiment. For example, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0107] An embodiment of the present application further provides a computer program product, including a computer program, wherein the computer program is loaded and executed by a processor to implement the data access method of the system on chip as described in the above embodiment.

[0108] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0109] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data access method for a system on chip, characterized in that: Applied to a system on chip, the system on chip includes a first bus system using an advanced high performance bus AHB and a second bus system using an advanced peripheral bus APB, the first bus system and the second bus system are connected via a plurality of AHB-APB bridges, at least two access links exist between each AHB master device in the first bus system and each APB slave device in the second bus system, and each APB slave device is connected to a data bridge, the method includes: A first AHB master device in the first bus system sends a first access request to a first APB slave device in the second bus system through a first access link; The first data bridge connected to the first APB slave device receives the first access request, and if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, sends an APB release signal to the first AHB master device; or, if the first access request is a read request, after reading the data of the first access request from the first APB slave device and storing the read data in the first data bridge, sends an APB release signal to the first AHB master device; After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, or sends a third access request to a second APB slave device in the second bus system through a third access link; The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

2. The method according to claim 1, characterized in that The method further comprises: If the first access request is a write request, after the first data bridge stores the data of the first access request in the first data bridge, when the first APB slave device is in an idle state, writing the data of the first access request into the first APB slave device; If the first access request is a read request, the first data bridge transmits the data of the first access request to the first AHB master device after sending an APB release signal to the first AHB master device.

3. The method according to claim 1, characterized in that If the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, sending an APB release signal to the first AHB master device includes: The first data bridge determines the storage level of the data based on the type of the data in the first access request, where different storage levels correspond to different storage areas in the first data bridge, and different storage areas correspond to different access performances; The first data bridge stores the data in a storage area corresponding to the storage level in the first data bridge based on the storage level of the data.

4. The method according to claim 3, characterized in that The first data bridge stores the data in a storage area corresponding to the storage level in the first data bridge based on the storage level of the data, including: The first data bridge stores the data in a first storage area in the first data bridge based on the storage level of the data; The method further comprises: The first data bridge predicts the state of the first APB slave device. If the prediction result indicates that the first APB slave device will change from the busy state to the idle state within a preset time period, the data is transferred from the first storage area to the second storage area in the first data bridge, and the access performance of the second storage area is higher than the access performance of the first storage area.

5. The method according to claim 1, characterized in that The method further comprises: The first AHB master device records execution information of access requests sent to the first APB slave device through different access links, where the execution information includes at least one of execution duration and execution success rate of the access request; After receiving the APB release signal, the first AHB master device sends a second access request to the first APB slave device through a second access link, including: After receiving the APB release signal, the first AHB master device determines the second access link from multiple access links based on the execution information, and sends the second access request to the first APB slave device through the second access link, wherein the multiple access links do not include the first access link.

6. The method according to claim 1, characterized in that The first access link includes a first arbitrator, a first AHB-APB bridge and a second arbitrator; the first AHB master device sends a first access request to a first APB slave device in the second bus system through the first access link, including: The first AHB master device sends the first access request to the first arbitrator; After the first arbitrator arbitrates the received first access request and the fourth access request sent by the second AHB master device, the first access request is sent to the second arbitrator through the first AHB-APB bridge; The second arbitrator arbitrates the received first access request and the fifth access request sent by the third AHB master device, and then sends the first access request to the first data bridge.

7. The method according to claim 6, characterized in that The first arbiter, the first AHB-APB bridge and the second arbiter all have a fault detection function, and the method further includes: In the process of the first AHB master device sending the first access request to the first APB slave device through the first access link, if any one of the first arbitrator, the first AHB-APB bridge and the second arbitrator detects that the first access link fails, the node switches the first access request to a fourth access link to send the first access request to the first APB slave device through the fourth access link, and the access link between the first AHB master device and the first APB slave device includes the fourth access link.

8. A system on chip, characterized in that: The system on chip includes a first bus system using an advanced high-performance bus AHB and a second bus system using an advanced peripheral bus APB, the first bus system and the second bus system are connected via a plurality of AHB-APB bridges, at least two access links exist between each AHB master device in the first bus system and each APB slave device in the second bus system, and each APB slave device is connected to a data bridge; a first AHB master device in the first bus system, configured to send a first access request to a first APB slave device in the second bus system via a first access link; a first data bridge connected to the first APB slave device, configured to receive the first access request, and if the first access request is a write request and the first APB slave device is in a busy state, after storing the data of the first access request in the first data bridge, send an APB release signal to the first AHB master device; or, if the first access request is a read request, after reading the data of the first access request from the first APB slave device and storing the read data in the first data bridge, send an APB release signal to the first AHB master device; The first AHB master device is further configured to, after receiving the APB release signal, send a second access request to the first APB slave device through a second access link, or send a third access request to a second APB slave device in the second bus system through a third access link; The access link between the first AHB master device and the first APB slave device includes the first access link and the second access link, and the AHB-APB bridges on the first access link and the second access link are the same or different.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one computer program, and the at least one computer program is loaded and executed by the processor to implement the data access method of the system on chip according to any one of claims 1 to 7.

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