Digital filter output truncation method and device based on multiple decimation rates

Abstract

The invention discloses a digital filter output truncation method and device based on multiple decimation rates, a digital filter comprises a CI C filter, a compensation filter and a half-band filter, and the method comprises the following steps: calculating the bit width of output data of the CI C filter according to a current decimation factor, cutting off the bit width of the output data of the CI C filter according to a preset cut data bit width to obtain a first output signal, and outputting the first output signal to a compensation filter; calculating the bit width of the output data of the compensation filter, cutting off the bit width of the output data of the compensation filter to obtain a second output signal, and outputting the second output signal to a half-band filter; and calculating the bit width of the output data of the half-band filter, cutting off the bit width of the output data of the half-band filter, and taking a cut-off signal as an output signal of the digital filter. By dynamically adjusting the bit width of the output data of the multi-extraction-rate digital filter, the precision loss is reduced to the greatest extent on the basis of ensuring the integrity of the main information of the signal.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a method and device for truncating a digital filter output based on multiple decimation rates. Background Art

[0002] In the field of digital signal processing, digital filters are the core components of signal analysis and processing and are widely used in communications, audio processing, image recognition and many other fields. The output data of the filter usually needs to be truncated to adapt to different storage or transmission requirements, especially in resource-constrained environments such as embedded systems or low-power devices. Traditional digital filter output truncation methods mainly focus on operations at a fixed sampling rate, that is, after the input signal is processed by the filter, the output signal is sampled or bit truncated according to a preset fixed multiple to reduce the amount of data.

[0003] However, with the continuous advancement of signal processing technology and the diversification of application scenarios, the application of variable magnification filters (i.e. filters with variable decimation or interpolation rates) is becoming more and more widespread. Such filters can flexibly adjust their processing parameters according to signal characteristics or processing requirements, thereby achieving more efficient data processing while maintaining signal quality. In the process of digital signal processing, due to the limitation of data bit width, it is often necessary to truncate the output of these filters.

[0004] Most of the existing truncation methods are designed based on the assumption of fixed bit width and fixed decimation rate. When the decimation rate changes dynamically, the applicability of these methods will be severely limited. If these methods continue to be used, it will either lead to excessive information loss at high decimation rates, affecting signal quality; or retain too much unnecessary data at low decimation rates, resulting in a waste of storage or transmission resources. Therefore, it is particularly important to explore output truncation methods suitable for variable magnification digital filters. Summary of the invention

[0005] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention is to provide a method and device for truncation of digital filter output based on multiple sampling rates, which can minimize accuracy loss and reduce resource consumption while ensuring the integrity of the main information of the signal.

[0006] In order to solve the above technical problems, a technical solution adopted by the present invention is: to provide a digital filter output truncation method based on multiple decimation rates, wherein the digital filter includes a CIC filter, a compensation filter and a half-band filter, and the decimation factor of the CIC filter changes dynamically. The method includes the following steps:

[0007] Calculating the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, truncating the bit width of the CIC filter output data according to the preset truncated data bit width, obtaining a first output signal, and outputting the first output signal to the compensation filter;

[0008] Calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data according to the truncated data bit width to obtain a second output signal, and outputting it to the half-band filter;

[0009] The bit width of the half-band filter output data is calculated according to the bit width of the second output signal, and the bit width of the half-band filter output data is truncated according to the truncated data bit width, and the truncated signal is used as the output signal of the digital filter.

[0010] Further, in the step of calculating the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, truncating the bit width of the CIC filter output data according to the preset truncated data bit width, obtaining the first output signal, and outputting it to the compensation filter, the following sub-steps are included:

[0011] Obtaining the bit width of current input data and parameters of a CIC filter, wherein the parameters of the CIC filter include a decimation factor, a delay factor, and an order;

[0012] Calculate the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter;

[0013] The data output by the CIC filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits;

[0014] After truncation, a first output signal is obtained, and the first output signal is output to the compensation filter.

[0015] Further, in the step of calculating the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter, the calculation formula of the bit width of the CIC filter output data is as follows:

[0016] W 0 =ceil[Nlog 2 (RM)+B in ] (one)

[0017] In formula (1), W 0 represents the bit width of the CIC filter output data, ceil() represents the rounding function, N represents the order of the CIC filter, R represents the decimation factor of the CIC filter, M represents the delay factor of the CIC filter, Bin Indicates the bit width of the CIC filter input data.

[0018] Furthermore, the step of dividing the data output by the CIC filter into high-order bits and low-order bits, and intercepting the corresponding number of bits from the high-order bits toward the low-order bits to achieve the intercepted data bit width includes the following sub-steps:

[0019] Arrange the valid bits of the data output by the CIC filter from left to right from high-order bits to low-order bits;

[0020] The leftmost high-order bit of the data output by the CIC filter is retained as a sign bit, and then the data bits are intercepted from the sign bit to the right according to the intercepted data bit width, and the remaining low-order bit data is discarded, and the sign bit plus the data bit is equal to the intercepted data bit width.

[0021] Further, the step of calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data according to the bit width of the intercepted data to obtain the second output signal, and outputting it to the half-band filter includes the following sub-steps:

[0022] Calculating the gain of the compensation filter according to the set coefficient of the compensation filter;

[0023] Calculating the bit width of the compensation filter output data according to the bit width of the first output signal and the gain of the compensation filter;

[0024] The data output by the compensation filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits;

[0025] After truncation, a second output signal is obtained, and the second output signal is output to a half-band filter.

[0026] Further, in the step of calculating the bit width of the half-band filter output data according to the bit width of the second output signal, and truncating the bit width of the half-band filter output data according to the truncated data bit width, and using the truncated signal as the output signal of the digital filter, the following sub-steps are included:

[0027] Calculate the gain of the half-band filter according to the set coefficients of the half-band filter;

[0028] Calculating the bit width of the half-band filter output data according to the bit width of the second output signal and the gain of the half-band filter;

[0029] The data output by the half-band filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits;

[0030] The truncated signal is output as an output signal of the digital filter.

[0031] Further, in the step of calculating the bit width of the compensation filter output data according to the bit width of the first output signal and the gain of the compensation filter, the calculation formula of the bit width of the compensation filter output data is as follows:

[0032] W 0 '=ceil(W i +log 2 D)(II)

[0033] In formula (II), W 0 ' represents the bit width of the compensation filter output data, W i represents the bit width of the first output signal, and D represents the gain of the compensation filter.

[0034] In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a digital filter output truncation device based on multiple decimation rates, comprising:

[0035] A first truncation module is used to calculate the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, set the truncated data bit width and truncate the bit width of the CIC filter output data to obtain a first output signal, and output it to the compensation filter;

[0036] A second truncation module, used for calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data to obtain a second output signal, and outputting it to the half-band filter;

[0037] The third truncation module is used to calculate the bit width of the half-band filter output data according to the bit width of the second output signal, and truncate the bit width of the half-band filter output data, and use the truncation signal as the output signal of the digital filter.

[0038] Furthermore, the first truncation module includes:

[0039] A first acquisition submodule, used to acquire the bit width of current input data and parameters of a CIC filter, wherein the parameters of the CIC filter include a decimation factor, a delay factor, and an order;

[0040] A first calculation submodule, used for calculating the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter;

[0041] A first interception submodule is used to divide the data output by the CIC filter into high-order bits and low-order bits, and intercept the number of bits corresponding to the set interception data bit width from the high-order bits to the low-order bits;

[0042] The first output submodule is used to output the first output signal obtained after truncation to the compensation filter.

[0043] In order to solve the above technical problems, the present invention adopts a technical solution: providing a method for optimizing a multi-decimation rate digital filter, using the multi-decimation rate based digital filter output truncation method to truncate the bit width of the multi-decimation rate digital filter output data.

[0044] The method and device for truncation of digital filter output based on multiple decimation rates of the present invention have at least the following beneficial effects: the present invention reduces the precision loss to the maximum extent while ensuring the integrity of the main information of the signal by dynamically adjusting the bit width of the output data of the digital filter with multiple decimation rates. In particular, when processing high decimation factors, the present invention accurately calculates the output bit width of each level of the filter and performs truncation in combination with the preset bit width of the truncated data, thereby effectively avoiding the consumption of a large amount of register resources and the reduction of the calculation speed, and ensuring the accuracy and efficiency of signal processing; the present invention reduces the bit width of the filter output data, and thus also correspondingly reduces the amount of calculation required for data processing, which helps to improve the calculation speed of the digital filter, so that it can respond to the changes of the input signal more quickly, thereby improving the actual performance of the system. The truncation method of the present invention can dynamically adjust the retained high-order significant bits to adapt to different extraction factors and input signal characteristics, so that the present invention can be widely used in various digital signal processing scenarios to meet different application requirements; at the same time, the dynamic adjustment of the truncation bit width is also helpful to optimize the system performance, so that it can maintain the best state under different working conditions; the truncation method of the present invention can significantly reduce the bit width of the output data of each level of the filter, thereby reducing the consumption of register resources by the entire digital filter, and reducing the consumption of hardware resources. In the hardware implementation, by efficiently and dynamically adjusting the truncation bit width, the use of hardware resources is further optimized. This resource optimization is crucial for low power consumption and small area design, which not only reduces the hardware cost, but also improves the overall performance and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0046] Figure 1 Schematic diagram of the overall structure of a multi-decimation rate digital filter.

[0047] Figure 2 Schematic diagram of the structure of the CIC filter.

[0048] Figure 3 This is a schematic diagram of the compensation filter structure.

[0049] Figure 4 This is a schematic diagram of the structure of a half-band filter.

[0050] Figure 5 The flowchart is a method for truncating a digital filter output based on multiple decimation rates according to an embodiment of the present invention.

[0051] Figure 6 for Figure 5 Flow chart of step S1 in FIG.

[0052] Figure 7 for Figure 5 Flowchart of step S2 in FIG.

[0053] Figure 8 for Figure 5 Flow chart of step S3 in FIG.

[0054] Fig. 9 It is a structural block diagram of an embodiment of a digital filter output truncation device based on multiple decimation rates of the present invention. DETAILED DESCRIPTION

[0055] The present invention will be further described below in conjunction with the accompanying drawings.

[0056] The present invention is described by taking a multi-decimation rate digital filter as an example. Figure 1 The digital filter is divided into three stages. The first stage is a cascade comb CIC filter with a variable decimation factor, the second stage is a compensation filter, and the third stage is a half-band filter. First, the analog signal outputs a 1-bit high-frequency signal through the modulator, which is transmitted as the input signal of the CIC filter. After high-multiple decimation by the CIC filter, its output is connected to the input of the compensation filter, and after double frequency reduction, it is output to the input of the half-band filter. Finally, the half-band filter doubles the frequency and outputs the final output signal.

[0057] See also Figure 2 , which is a schematic diagram of the structure of the CIC filter. According to the Noble identity, by changing the position of the extractor, a multi-stage CIC filter with the least resource consumption can be obtained (such as Figure 2 As shown in Figure 1, this filter structure is called a Hogenauer decimation filter, also known as a recursive structure. In this structure, the integrator is placed in front of the decimator and works in the high-frequency region, and the comb filter is placed behind the decimator and works in the low-frequency region, reducing the overall power consumption of the filter. Based on the Hogenauer theory, the calculation of the CIC filter output bit width when the delay factor is M can be derived:

[0058] W 0 =ceil[Nlog 2 (RM)+Bin ]

[0059] Among them, W 0 represents the bit width of the CIC filter output data, ceil() represents the rounding function, N represents the order of the CIC filter, R represents the decimation factor of the CIC filter, M represents the delay factor of the CIC filter, B in Indicates the bit width of the CIC filter input data. Assuming the input data bit width is 1, the delay factor is 1, the decimation factor is 8, and the order is 5, the bit width of the CIC filter output data is calculated to be 16 bits. When the decimation factor increases to 64, the output bit width becomes 31 bits, and even when it can reach 128 or 256 times, the output bit width reaches 41 or 51 bits. Directly sending such a large output without truncation will result in a large consumption of register resources and a reduction in computing speed, so it is necessary to truncate the output of each filter to reduce the bit width.

[0060] See also Figure 3 and Figure 4 , respectively, are schematic diagrams of the structures of the compensation filter and the half-band filter. In this embodiment, the compensation filter and the half-band filter are both FIR filters, and the transfer functions of the compensation filter and the half-band filter are expressed as:

[0061] F FIR (z) = h(0) + h(1) * z -1 +h(2)*z -2 +...+h(N-1)*z -N

[0062] Among them, F FIR (z) represents the transfer function of the FIR filter (i.e., the compensation filter and the half-band filter), z is a complex variable, h(0), h(1), h(2)...h(N-1) represent coefficients of each order of the FIR filter, and N represents the order of the FIR filter.

[0063] See also Figure 5 , is a flow chart of an implementation method of a digital filter output truncation method based on multiple decimation rates of the present invention. This implementation method may include the following steps:

[0064] S1. Truncate the output bit width of the CIC filter.

[0065] Specifically, the bit width of the CIC filter output data is calculated according to the current decimation factor of the CIC filter, and the bit width of the CIC filter output data is truncated according to the preset intercepted data bit width to obtain the first output signal, and output it to the compensation filter. In this embodiment, the intercepted data bit width is set to 16 bits.

[0066] See also Figure 6 , this step S1 may include the following sub-steps:

[0067] S11. Obtain parameters of the CIC filter.

[0068] Specifically, the bit width of the current input data and the parameters of the CIC filter are obtained, and the parameters of the CIC filter include a decimation factor, a delay factor, and an order. The decimation factor of the CIC filter changes dynamically. In specific operations, the bit width of the current input data is read from the system configuration or the data interface, and the decimation factor, the delay factor, and the order of the CIC filter are obtained from the system configuration.

[0069] S12, calculating the bit width of the CIC filter output data.

[0070] Specifically, the bit width of the CIC filter output data is calculated according to the bit width of the current input data and the parameters of the CIC filter. The bit width of the CIC filter output data is obtained by the following formula:

[0071] W 0 =ceil[Nlog 2 (RM)+B in ]

[0072] Among them, W 0 represents the bit width of the CIC filter output data, ceil() represents the rounding function, N represents the order of the CIC filter, R represents the decimation factor of the CIC filter, M represents the delay factor of the CIC filter, B in Indicates the bit width of the CIC filter input data.

[0073] In this embodiment, the input data bit width is 1, the delay factor is 1, and the order is 5. Substituting different decimation factors into the above formula, the bit width of the corresponding CIC filter output data is calculated. For specific data, see Table 1:

[0074]

[0075] Table 1

[0076] S13, divide the data and truncate it.

[0077] The data output by the CIC filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits. Specifically, please refer to Table 2, the valid bits of the data output by the CIC filter are arranged from left to right according to the high-order bits to the low-order bits; the leftmost high-order bit of the data output by the CIC filter is reserved as a sign bit, and then the data bits are intercepted from the sign bit to the right according to the bit width of the intercepted data, and the remaining low-order bit data is discarded, and the sign bit plus the data bit is equal to the bit width of the intercepted data. The output bit width design of the CIC filter must cover all possible extraction factors R to avoid overflow, but if the complete bit width is always retained, storage redundancy will result. The dynamic truncation of this scheme can ensure that the main information of the signal is not lost by directly retaining the most significant bit, thereby avoiding the error caused by overflow, and at the same time reduce the loss of precision by discarding the low-order irrelevant bits, because the influence of the high-order bit on the accuracy of the result is much higher than that of the low-order bit.

[0078]

[0079] Table 2

[0080] In this embodiment, the maximum decimation factor of the CIC filter is 64, and the corresponding output bit width is 31 bits, so the bit width of the last-stage register must be greater than or equal to 31 bits to prevent the filter from overflowing when it is decimated by 64 times. When truncating the output bit width, the most significant bit (MSB) to be retained varies according to the decimation factor R. The truncation process should start from the MSB (bold in the figure) under the current decimation factor to the 16th bit, and the effective data bit width obtained is the final output of the CIC filter.

[0081] S14, outputting a first output signal after truncation.

[0082] Specifically, a truncated first output signal is generated according to the truncation result of step S13, and the first output signal is passed as an input to the compensation filter to correct the frequency response distortion introduced by the CIC filter.

[0083] S2. truncate the output bit width of the compensation filter.

[0084] Specifically, the bit width of the compensation filter output data is calculated according to the bit width of the first output signal, and the bit width of the compensation filter output data is truncated according to the truncated data bit width to obtain the second output signal, which is output to the half-band filter.

[0085] See also Figure 7 , this step S2 includes the following sub-steps:

[0086] S21. Calculate the gain of the compensation filter.

[0087] Specifically, the gain of the compensation filter is calculated according to the set coefficient of the compensation filter, and the gain of the compensation filter is obtained by the following formula:

[0088]

[0089] Wherein, D represents the gain of the compensation filter, N represents the order of the compensation filter, and h(0), h(1), h(2)...h(N-1) represent the coefficients of each order of the compensation filter.

[0090] S22, calculating the bit width of the compensation filter output data.

[0091] Specifically, the bit width of the compensation filter output data is calculated according to the bit width of the first output signal and the gain of the compensation filter. The bit width of the compensation filter output data is obtained by the following formula:

[0092] W 0 '=ceil(W i +log 2 D)

[0093] In formula (II), W 0 ' represents the bit width of the compensation filter output data, W i represents the bit width of the first output signal, and D represents the gain of the compensation filter.

[0094] S23, divide the data and truncate it.

[0095] Specifically, the data output by the compensation filter is divided into high-order bits and low-order bits, and bits corresponding to the set bit width of the intercepted data are intercepted from the high-order bits to the low-order bits. The specific operation can be found in the content of step S13, which will not be described here one by one.

[0096] S24, outputting a second output signal after truncation.

[0097] Specifically, a truncated second output signal is generated according to the truncation result of step S23, and the second output signal is passed as input to the half-band filter.

[0098] S3. truncate the output bit width of the half-band filter.

[0099] Specifically, the bit width of the half-band filter output data is calculated according to the bit width of the second output signal, and the bit width of the half-band filter output data is truncated according to the truncated data bit width, and the truncated signal is used as the output signal of the digital filter.

[0100] See also Figure 8 , this step S3 includes the following sub-steps:

[0101] S31. Calculate the gain of the half-band filter.

[0102] Specifically, the gain of the half-band filter is calculated according to the set coefficients of the half-band filter. The calculation method of the gain of the half-band filter is the same as the calculation method of the gain of the compensation filter, which will not be described in detail here.

[0103] S32, calculating the bit width of the half-band filter output data.

[0104] Specifically, the bit width of the half-band filter output data is calculated according to the bit width of the second output signal and the gain of the half-band filter. The bit width of the compensation filter output data is obtained by the following formula:

[0105] W 0 ”=ceil(W i '+log 2 D')

[0106] In formula (II), W 0 " represents the bit width of the half-band filter output data, W i ' represents the bit width of the second output signal, and D' represents the gain of the half-band filter.

[0107] S33, divide the data and truncate it.

[0108] Specifically, the data output by the half-band filter is divided into high-order bits and low-order bits, and bits corresponding to the set bit width of the intercepted data are intercepted from the high-order bits to the low-order bits. The specific operation can be found in the content of step S13, which will not be described here one by one.

[0109] S34. Obtain the final output signal.

[0110] Specifically, a truncated signal is generated according to the truncation result of step S33 and output as the final output signal of the digital filter.

[0111] See also Fig. 9 , is a structural block diagram of an embodiment of a digital filter output truncation device based on multiple decimation rates of the present invention. The digital filter output truncation device based on multiple decimation rates of this embodiment is used to implement the digital filter output truncation method based on multiple decimation rates described in the above embodiment. Specifically, the digital filter output truncation device based on multiple decimation rates of this embodiment includes a first truncation module 100, a second truncation module 200 and a third truncation module 300. Wherein:

[0112] The first truncation module 100 is used to calculate the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, set the bit width of the truncated data and truncate the bit width of the CIC filter output data to obtain a first output signal, and output it to the compensation filter. Specifically, the first truncation module 100 of this embodiment includes a first acquisition submodule 110, a first calculation submodule 120, a first truncation submodule 130 and a first output submodule 140. Among them: the first acquisition submodule 110 is used to obtain the bit width of the current input data and the parameters of the CIC filter, and the parameters of the CIC filter include the decimation factor, the delay factor and the order; the first calculation submodule 120 is used to calculate the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter; the first truncation submodule 130 is used to divide the data output by the CIC filter into high-order bits and low-order bits, and intercept the number of bits corresponding to the set bit width of the truncated data from the high-order bits to the low-order bits; the first output submodule 140 is used to output the first output signal obtained after truncation to the compensation filter.

[0113] The second truncation module 200 is used to calculate the bit width of the compensation filter output data according to the bit width of the first output signal, and truncate the bit width of the compensation filter output data to obtain a second output signal, and output it to the half-band filter. Specifically, the second truncation module 200 of this embodiment includes a second calculation submodule 210, a third calculation submodule 220, a second truncation submodule 230 and a second output submodule 240. Among them: the second calculation submodule 210 is used to calculate the gain of the compensation filter according to the set coefficient of the compensation filter; the third calculation submodule 220 is used to calculate the bit width of the compensation filter output data according to the bit width of the first output signal and the gain of the compensation filter; the second truncation submodule 230 is used to divide the data output by the compensation filter into high-order bits and low-order bits, and intercept the number of bits corresponding to the set bit width of the intercepted data from the high-order bits to the low-order bits; the second output submodule 240 is used to output the second output signal obtained after truncation to the half-band filter.

[0114] The third truncation module 300 is used to calculate the bit width of the output data of the half-band filter according to the bit width of the second output signal, and truncate the bit width of the output data of the half-band filter, and use the signal obtained after truncation as the output signal of the digital filter. Specifically, the third truncation module 300 of this embodiment includes a fourth calculation submodule 310, a fifth calculation submodule 320, a third interception submodule 330 and a third output submodule 340. Among them: the fourth calculation submodule 310 is used to calculate the gain of the half-band filter according to the set coefficient of the half-band filter; the fifth calculation submodule 320 is used to calculate the bit width of the output data of the half-band filter according to the bit width of the second output signal and the gain of the half-band filter; the third interception submodule 330 is used to divide the data output by the half-band filter into high-order bits and low-order bits, and intercept the number of bits corresponding to the set bit width of the intercepted data from the high-order bits to the low-order bits; the third output submodule 340 is used to output the signal obtained after truncation as the output signal of the digital filter.

[0115] The present invention also discloses a method for optimizing a multi-decimation rate digital filter, which uses the multi-decimation rate-based digital filter output truncation method to truncate the bit width of the multi-decimation rate digital filter output data.

[0116] The retained high-order significant bits can be adjusted dynamically, which can reduce the loss of precision while ensuring that the main information of the signal is not lost. It can effectively reduce the truncation error without significantly sacrificing the performance of the filter. When the extraction factor R changes dynamically, the position of the most significant bit corresponding to each R value will also change accordingly. In hardware implementation, efficient dynamic adjustment of truncation is also a great help for hardware resource optimization. Reducing register resource consumption is very important for low power consumption and small area design. Effectively reduce the word length of the output of each level of the filter, thereby reducing the consumption of register resources by the entire digital extraction filter.

[0117] The present invention reduces the precision loss to the maximum extent while ensuring the integrity of the main information of the signal by dynamically adjusting the bit width of the output data of the digital filter with multiple decimation rates. In particular, when processing high decimation factors, the present invention accurately calculates the output bit width of each level of the filter and performs truncation in combination with the preset bit width of the intercepted data, thereby effectively avoiding the consumption of a large number of register resources and the reduction of the calculation speed, and ensuring the accuracy and efficiency of signal processing; the present invention reduces the bit width of the filter output data, and thus also correspondingly reduces the amount of calculation required for data processing, which helps to improve the calculation speed of the digital filter, so that it can respond to the changes of the input signal more quickly, thereby improving the real-time performance and responsiveness of the system; the truncation method of the present invention can dynamically adjust the bit width of the output data of the filter, and can effectively adjust the output bit width of the filter, so that the output bit width of the filter can be adjusted according to the preset bit width of the intercepted data, thereby ensuring the accuracy and efficiency of signal processing; the present invention reduces the bit width of the filter output data, and thus also reduces the amount of calculation required for data processing, which helps to improve the calculation speed of the digital filter, so that it can respond to the changes of the input signal more quickly, thereby improving the real-time performance and responsiveness of the system; the truncation method of the present invention can dynamically adjust the output bit width of the filter, and can effectively adjust the output bit width of the filter, so that the output bit width of the filter can be adjusted according to the preset bit width of the intercepted data, thereby ensuring the accuracy and efficiency of signal processing; the present invention reduces the bit width of the filter output data, and thus reduces the amount of calculation required for data processing, thereby improving the real-time performance and responsiveness of the system; the truncation method of the present invention can dynamically adjust the output bit width of the filter, and can effectively adjust the output bit width of the filter, so that the output bit width of the filter can be adjusted according to the preset bit width of the intercepted data, thereby ensuring the accuracy and efficiency of signal processing; the present invention reduces the bit width of The retained high-order significant bits are dynamically adjusted to adapt to different extraction factors and input signal characteristics, so that the present invention can be widely used in various digital signal processing scenarios to meet different application requirements; at the same time, the dynamic adjustment of the truncation bit width is also helpful to optimize the system performance, so that it can maintain the best state under different working conditions; the truncation method of the present invention can significantly reduce the bit width of the output data of each level of filters, thereby reducing the consumption of register resources by the entire digital filter and reducing the consumption of hardware resources. In the hardware implementation, the use of hardware resources is further optimized by efficiently and dynamically adjusting the truncation bit width. This resource optimization is crucial for low power consumption and small area design, which not only reduces the hardware cost, but also improves the overall performance and reliability of the system.

Claims

1. A method for truncation of digital filter output based on multiple decimation rates, wherein the digital filter comprises a CIC filter, a compensation filter and a half-band filter, and the decimation factor of the CIC filter changes dynamically, characterized in that: The following steps are involved: Calculating the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, truncating the bit width of the CIC filter output data according to the preset truncated data bit width, obtaining a first output signal, and outputting the first output signal to the compensation filter; Calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data according to the truncated data bit width to obtain a second output signal, and outputting it to the half-band filter; The bit width of the half-band filter output data is calculated according to the bit width of the second output signal, and the bit width of the half-band filter output data is truncated according to the truncated data bit width, and the truncated signal is used as the output signal of the digital filter.

2. The digital filter output truncation method based on multiple decimation rates as claimed in claim 1, characterized in that: The step of calculating the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, truncating the bit width of the CIC filter output data according to the preset truncated data bit width, obtaining a first output signal, and outputting it to the compensation filter includes the following sub-steps: Obtaining the bit width of current input data and parameters of a CIC filter, wherein the parameters of the CIC filter include a decimation factor, a delay factor, and an order; Calculate the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter; The data output by the CIC filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits; After truncation, a first output signal is obtained, and the first output signal is output to the compensation filter.

3. The digital filter output truncation method based on multiple decimation rates as claimed in claim 2, characterized in that: In the step of calculating the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter, the calculation formula of the bit width of the CIC filter output data is as follows: W0=ceil[Nlog2(RM)+B in ](one) In formula (1), W0 represents the bit width of the CIC filter output data, ceil() represents the rounding function, N represents the order of the CIC filter, R represents the decimation factor of the CIC filter, M represents the delay factor of the CIC filter, and B in Indicates the bit width of the CIC filter input data.

4. The digital filter output truncation method based on multiple decimation rates as claimed in claim 2, characterized in that: The step of dividing the data output by the CIC filter into high-order bits and low-order bits, and intercepting corresponding bits from the high-order bits toward the low-order bits to achieve the intercepted data bit width includes the following sub-steps: Arrange the valid bits of the data output by the CIC filter from left to right from high-order bits to low-order bits; The leftmost high-order bit of the data output by the CIC filter is retained as a sign bit, and then the data bits are intercepted from the sign bit to the right according to the intercepted data bit width, and the remaining low-order bit data is discarded, and the sign bit plus the data bit is equal to the intercepted data bit width.

5. The digital filter output truncation method based on multiple decimation rates as claimed in claim 1, characterized in that: The step of calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data according to the truncated data bit width to obtain a second output signal, and outputting it to the half-band filter includes the following sub-steps: Calculating the gain of the compensation filter according to the set coefficient of the compensation filter; Calculating the bit width of the compensation filter output data according to the bit width of the first output signal and the gain of the compensation filter; The data output by the compensation filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits; After truncation, a second output signal is obtained, and the second output signal is output to a half-band filter.

6. The digital filter output truncation method based on multiple decimation rates as claimed in claim 1, characterized in that: The step of calculating the bit width of the half-band filter output data according to the bit width of the second output signal, truncating the bit width of the half-band filter output data according to the truncated data bit width, and using the truncated signal as the output signal of the digital filter includes the following sub-steps: Calculate the gain of the half-band filter according to the set coefficients of the half-band filter; Calculating the bit width of the half-band filter output data according to the bit width of the second output signal and the gain of the half-band filter; The data output by the half-band filter is divided into high-order bits and low-order bits, and the number of bits corresponding to the set bit width of the intercepted data is intercepted from the high-order bits to the low-order bits; The truncated signal is output as an output signal of the digital filter.

7. The digital filter output truncation method based on multiple decimation rates as claimed in claim 5, characterized in that: In the step of calculating the bit width of the compensation filter output data according to the bit width of the first output signal and the gain of the compensation filter, the calculation formula of the bit width of the compensation filter output data is as follows: W0'=ceil(W i +log2D)(II) In formula (2), W0' represents the bit width of the compensation filter output data, W i represents the bit width of the first output signal, and D represents the gain of the compensation filter.

8. A digital filter output truncation device based on multiple decimation rates, characterized in that: include: A first truncation module is used to calculate the bit width of the CIC filter output data according to the current decimation factor of the CIC filter, set the truncated data bit width and truncate the bit width of the CIC filter output data to obtain a first output signal, and output it to the compensation filter; A second truncation module, used for calculating the bit width of the compensation filter output data according to the bit width of the first output signal, and truncating the bit width of the compensation filter output data to obtain a second output signal, and outputting it to the half-band filter; The third truncation module is used to calculate the bit width of the half-band filter output data according to the bit width of the second output signal, and truncate the bit width of the half-band filter output data, and use the truncation signal as the output signal of the digital filter.

9. The digital filter output truncation device based on multiple decimation rates as claimed in claim 8, characterized in that: The first truncation module comprises: A first acquisition submodule, used to acquire the bit width of current input data and parameters of a CIC filter, wherein the parameters of the CIC filter include a decimation factor, a delay factor, and an order; A first calculation submodule, used for calculating the bit width of the CIC filter output data according to the bit width of the current input data and the parameters of the CIC filter; A first interception submodule is used to divide the data output by the CIC filter into high-order bits and low-order bits, and intercept the number of bits corresponding to the set interception data bit width from the high-order bits to the low-order bits; The first output submodule is used to output the first output signal obtained after truncation to the compensation filter.

10. A method for optimizing a digital filter with multiple decimation rates, characterized in that: The bit width of the output data of the digital filter with multiple decimation rates is truncated by using the digital filter output truncation method based on multiple decimation rates as claimed in any one of claims 1 to 7.

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