Bus circuit and electronic equipment

Abstract

The invention discloses a bus circuit and electronic equipment. The bus circuit comprises a power interface, a power control circuit, a non-polar carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit and a port. According to the invention, the power supply signal and the non-polar carrier communication signal can be transmitted to other equipment at the same time in a bus mode, so that the cost is effectively saved. In addition, the first anti-interference circuit is used for isolating the non-polar carrier wave signal, so that distortion of the non-polar carrier wave communication signal is avoided; the second anti-interference circuit is used for isolating the power supply signal, thereby preventing the power supply of the bus from entering the low-voltage communication chip to damage the communication circuit.

Description

Technical Field

[0001] The present application relates to the field of power line carriers, and in particular to a bus circuit and electronic equipment. Background Art

[0002] Bus technology products are suitable for large-area control such as building intelligence and community intelligence. The main feature of bus technology is that all equipment communication and control are based on one bus. It is a fully distributed intelligent control network technology. Its product modules have two-way communication capabilities, interoperability, and interchangeability, and its control components can be programmed.

[0003] Generally, the devices on the bus work in master-slave mode. The communication and power supply between the master and slave devices require four lines, which significantly increases the construction difficulty, construction cost and equipment cost. In addition, the waveform on the communication transmission line has strict requirements on the number of pulses. An occasional interference may cause communication data errors or data loss, and in severe cases, communication may be impossible. Summary of the invention

[0004] The embodiments of the present application provide a bus circuit and an electronic device to solve the influence of interference signals in the bus circuit on non-polarity carrier communication signals.

[0005] In a first aspect, an embodiment of the present application provides a bus circuit, the bus circuit comprising: a power interface, a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port, wherein:

[0006] The non-polar carrier communication circuit includes: a first input end, a first transmission end, and a second transmission end; the first anti-interference circuit includes: a second input end, a third input end, a first output end, and a second output end; the second anti-interference circuit includes: a fourth input end, a fifth input end, a third output end, and a fourth output end; the port includes: a first terminal and a second terminal, wherein,

[0007] One end of the positive bus is connected to the power interface, the other end of the positive bus is connected to the second input end of the first anti-interference circuit, the first output end of the first anti-interference circuit is respectively connected to the first terminal of the port and the third output end of the second anti-interference circuit, and the fourth input end of the second anti-interference circuit is connected to the first transmission end of the non-polarity carrier communication circuit; one end of the negative bus is grounded via the power control circuit, the other end of the negative bus is connected to the third input end of the first anti-interference circuit, the second output end of the first anti-interference circuit is respectively connected to the second terminal of the port and the fourth output end of the second anti-interference circuit, and the fifth input end of the second anti-interference circuit is connected to the second transmission end of the non-polarity carrier communication circuit;

[0008] The power interface is used to receive a power signal;

[0009] The power control circuit is used to control the on and off of the bus circuit according to the received first control signal;

[0010] The first input end of the non-polarity carrier communication circuit is used to receive a logic level signal, the first transmission end of the non-polarity carrier communication circuit is used to output a first non-polarity carrier communication signal, and the second transmission end of the non-polarity carrier communication circuit is used to output a second non-polarity carrier communication signal;

[0011] The first anti-interference circuit is used to isolate the first non-polarity carrier communication signal and the second non-polarity carrier communication signal output by the non-polarity carrier communication circuit, and input the power signal in the positive bus into the first terminal of the port and the power signal in the negative bus into the second terminal of the port;

[0012] The second anti-interference circuit is used to isolate the power supply signal, and load the received first non-polarity carrier communication signal into the positive bus containing the power supply signal, and load the received second non-polarity carrier communication signal into the negative bus containing the power supply signal.

[0013] In a second aspect, an embodiment of the present application provides an electronic device, including: the bus circuit described above.

[0014] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:

[0015] The present application can use the bus to transmit the power signal and the non-polarity carrier communication signal to other devices at the same time, effectively saving the cost of the equipment. In addition, the present application also uses the first anti-interference circuit to isolate the non-polarity carrier signal to avoid distortion of the non-polarity carrier communication signal; and uses the second anti-interference circuit to isolate the power signal to avoid the power signal of the bus from entering the non-polarity carrier communication circuit and causing damage to the communication circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 An application scenario diagram of a bus circuit provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the internal structure of a bus circuit provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the internal structure of another bus circuit provided in an embodiment of the present application;

[0023] Description of the drawings: 00-power interface, 01-port, 02-RS485 non-polarity carrier communication chip. DETAILED DESCRIPTION

[0024] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0025] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0026] See also Figure 1 The application scenario diagram of a bus circuit provided by the present application is shown in FIG. The application scenario includes a master device, N slave devices (N is an integer greater than 1), and a bus. The master device includes the bus circuit provided by the present application ( Figure 1 The bus includes: a positive bus and a negative bus. The specific bus is a technology that combines the power supply line and the signal line into one relative to the four-wire system (two power supply lines and two communication lines), thereby realizing a technology that shares one bus for power supply and communication.

[0027] Optionally, the bus in the embodiment of the present application is a two-core bus. The two-core bus can realize, for example, power supply and communication between the indoor unit of the air conditioner and the wire controller.

[0028] specific Figure 1 The two communicating parties in the communication are the master device and the slave device. A master device can be connected to a maximum of multiple slave devices. The master device refers to the device that controls the bus, such as the line controller of the air conditioner, which can send control information to control the operation of the slave device. The slave device refers to the device that receives and processes the control information of the master device, such as the indoor unit and sensor of the air conditioner, which can perform specific tasks issued by the master device. The specific master device can send a query or write command to the slave device, and then the slave device passively receives the command and feeds back the corresponding data result or executes the write command according to the function code and register number. For example, the indoor unit in the air conditioner can receive and execute the instructions issued by the line controller.

[0029] Next, combine Figure 1 The bus circuit provided in the embodiment of the present application is introduced with the help of an application scenario diagram.

[0030] like Figure 2 The schematic diagram of a bus circuit provided by the present application is shown in FIG. The bus circuit may include: a power interface 00 , a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port 01 .

[0031] The non-polar carrier communication circuit may include: a first input terminal Input1, a first transmission terminal I / O1, and a second transmission terminal I / O2; the first anti-interference circuit may include: a second input terminal Input2, a third input terminal Input3, a first output terminal Out1, and a second output terminal Out2; the second anti-interference circuit may include: a fourth input terminal Input4, a fifth input terminal Input5, a third output terminal Out3, and a fourth output terminal Out4; and the port 01 may include: a first terminal 1 and a second terminal 2. One end of the positive bus is connected to the power interface 00, and the other end of the positive bus is connected to the second input terminal Input2 of the first anti-interference circuit; the first output terminal Out1 of the first anti-interference circuit is respectively connected to the first terminal 1 of the port 01 and the third output terminal Out3 of the second anti-interference circuit; and the fourth input terminal Input4 of the second anti-interference circuit is connected to the first transmission terminal I / O1 of the non-polar carrier communication circuit. One end of the negative bus is grounded via the power control circuit, the other end of the negative bus is connected to the third input terminal Input3 of the first anti-interference circuit, the second output terminal Out2 of the first anti-interference circuit is respectively connected to the second terminal 2 of port 01 and the fourth output terminal Out4 of the second anti-interference circuit, and the fifth input terminal Input5 of the second anti-interference circuit is connected to the second transmission terminal I / O2 of the non-polarity carrier communication circuit.

[0032] Among them, the power interface 00 is used to receive the power signal. The power control circuit is used to control the conduction and shutdown of the bus circuit according to the received first control signal. The first input terminal Input1 of the polarity-free carrier communication circuit is used to receive the logic level signal, the first transmission terminal I / O1 of the polarity-free carrier communication circuit is used to output the first polarity-free carrier communication signal, and the second transmission terminal I / O2 of the polarity-free carrier communication circuit is used to output the second polarity-free carrier communication signal. The first anti-interference circuit is used to isolate the first polarity-free carrier communication signal and the second polarity-free carrier communication signal output by the polarity-free carrier communication circuit, and input the power signal in the positive bus to the first terminal 1 of port 01 and the power signal in the negative bus to the second terminal 2 of port 01. The second anti-interference circuit is used to isolate the power signal, and load the received first polarity-free carrier communication signal into the positive bus containing the power signal, and load the received second polarity-free carrier communication signal into the negative bus containing the power signal. Specifically, the port 01 in the embodiment of the present application can interconnect the master device containing the bus circuit with multiple external slave devices. The non-polarity carrier circuit in the master device can transmit the carrier signal without distinguishing its polarity. That is to say, in the related art, the transmission end of the communication circuit of the master device usually needs to distinguish polarity, for example, I / O1 can only transmit positive signals and I / O2 can only transmit negative signals. In the embodiment of the present application, both transmission ends of the non-polarity carrier circuit can transmit positive or negative signals. As long as the polarities of the signals transmitted by the two transmission ends are opposite, normal communication between the master and slave devices can be achieved through the bus and port 01.

[0033] Optionally, the non-polarity carrier circuit in the embodiment of the present application can realize modulation and demodulation functions by setting on-off keying, that is, modulating the communication data onto the power line to realize power transmission and data communication on the bus at the same time, thereby significantly reducing system costs. In addition, on-off keying is not affected by signal polarity, eliminating the risk of equipment failure caused by incorrect connection of the output terminal.

[0034] Optionally, the embodiment of the present application may also digitally isolate the digital signal before the on-off keying receives it, so as to eliminate the bit error caused by the pulse loss that may occur during the pulse modulation process.

[0035] Optionally, the power signal in the embodiment of the present application may be a 24V DC power signal. Furthermore, the bus circuit in the embodiment of the present application may also include: a power polarity detection circuit. The input end of the power polarity detection circuit is connected to the negative bus, and the output end of the power polarity detection circuit is connected to the positive bus, which can be used to detect the positive and negative poles of the DC power supply connected to the power interface.

[0036] It can be understood that the purpose of setting a power polarity detection circuit between the positive bus and the negative bus in the embodiment of the present application is to prevent the DC power supply from being reversely connected to the power interface, that is, the positive pole of the DC power supply is connected to the negative end of the power interface, and the negative pole of the DC power supply is connected to the positive end of the power interface.

[0037] See also Figure 3 The schematic diagram of the internal structure of the bus circuit shown. The power polarity detection circuit in the embodiment of the present application can use an optocoupler circuit IC1 to detect whether there is a reverse power supply in the bus. For example, the optocoupler circuit IC1 is reversely connected between the positive bus and the negative bus, that is, the input terminal 1 of the optocoupler circuit is connected to the negative bus, and the output terminal 2 of the optocoupler circuit is connected to the positive bus through resistors R1 and R2 connected in parallel. In this way, when the DC power supply DC is positively connected to the power interface, the optocoupler circuit is not turned on and does not emit light, but when the DC power supply DC is reversely connected to the power interface, the optocoupler circuit will be turned on and emit light, so that the reverse connection detection of the DC power supply can be realized, and the user is prompted that there is a reverse connection problem of the DC power supply in the bus circuit, the master and slave devices cannot be powered normally, and the circuit board may be burned in serious cases. In addition, the output terminal 3 of the optocoupler circuit is respectively connected to resistors R4 and R6, the other end of the resistor R4 is connected to the second voltage source V2, and the bus circuit power supply status signal POC_STA can be obtained through the line at the other end of the resistor R6. When POC_STA outputs a high level, it indicates that the optocoupler circuit is turned on and the power supply in the bus circuit is reversed. When POC_STA outputs a low level, it indicates that the optocoupler circuit is disconnected and the power supply in the bus circuit is positively connected. The output terminal 4 of the optocoupler circuit is grounded. Optionally, the second voltage source V2 in the embodiment of the present application is +3.3V.

[0038] Optionally, the power polarity detection circuit in the embodiment of the present application can also use a buzzer alarm, which is reversely connected between the positive bus and the negative pole. In this way, once the DC power supply is reversely connected in the power interface, the buzzer alarm can send an alarm signal to prompt the user that there is a reverse connection problem with the DC power supply in the bus circuit.

[0039] Optionally, the embodiment of the present application may also use text, images, or symbols to minimize the risk of reverse connection of the DC power supply.

[0040] Optionally, if there are too many slave devices on the bus circuit, the master device may not be able to provide sufficient power using a single DC power supply, and therefore a DC power supply needs to be added to the master device. However, in the embodiment of the present application, the bus circuit can still use only one power polarity detection circuit to detect the polarity of the current in the positive bus and the negative bus. For example, when any one of the DC power supplies in the positive bus and the negative bus is reversely connected, the optocoupler will turn on and emit light, thereby realizing reverse real-time protection for multiple power supplies.

[0041] Therefore, the embodiment of the present application solves the problem that when the equipment in the related technology may have multiple communication protocols such as residential and building control standards (Konnex, KNX), the power supply signal and communication signal in the master device can be transmitted to the slave device together by using the corresponding DC carrier communication method. During the transmission process, only the polarity of the connected DC power supply needs to be considered without considering the polarity of the carrier communication circuit. Accordingly, the problem of the master and slave devices not being able to work normally due to incorrect wiring of the carrier communication circuit is avoided.

[0042] Optionally, the power signal in the embodiment of the present application may also use a low-frequency AC power supply. Optionally, the first anti-interference circuit in the embodiment of the present application may include: a common mode winding. The common mode winding may include: a first winding and a second winding. The first winding may include: a third terminal and a fourth terminal, and the second winding may include: a fifth terminal and a sixth terminal. The third terminal and the fifth terminal are terminals of the same name.

[0043] Among them, the other end of the positive bus is connected to the fifth terminal of the second winding, and the sixth terminal of the second winding is connected to the third output terminal of the second anti-interference circuit and the first terminal of the port; the other end of the negative bus is connected to the fourth terminal of the first winding, and the third terminal of the first winding is connected to the fourth output terminal of the second anti-interference circuit and the second terminal of the port.

[0044] Furthermore, in the embodiment of the present application, the two inductors of the common-mode winding can adopt EE-shaped magnetic cores, polycarbonate PC materials, with the same-name ends at both ends, and all wound in a forward manner, which can not only double the inductance but also effectively simplify the routing in the circuit.

[0045] See also Figure 3 The common-mode winding L in the embodiment of the present application includes four terminals, wherein the two ends of one inductor are terminal 1 and terminal 2 respectively, and the two terminals of the other inductor are terminal 3 and terminal 4 respectively, terminal 1 and terminal 3 are terminals of the same name, and there are two capacitors C2 and C3 connected in parallel between terminal 2 and terminal 3 for suppressing electromagnetic interference and stabilizing voltage, terminal 1 in the common-mode winding L is connected to terminal 2 in port 01 through a negative bus, and terminal 4 in the common-mode winding L is connected to terminal 1 in port 01 through a positive bus.

[0046] Specifically, the working principle of the common mode winding is: since the third terminal and the fifth terminal of the same-name end of the common mode winding in the embodiment of the present application are respectively located at different ends of the two windings, when there is an AC signal in the two coils, the magnetic flux in the magnetic ring is superimposed on each other, so that there is a considerable inductance, which will inhibit the AC signal, and when the DC current flows through the two coils, the magnetic flux in the magnetic ring cancels each other, and there is almost no inductance, so the DC current can pass without attenuation. Therefore, the common mode winding can effectively suppress the carrier communication signal in the bus circuit without affecting the DC power supply signal transmitted in the bus circuit.

[0047] See also Figure 3 Optionally, in the embodiment of the present application, a resistor R20 may be connected in series between the common mode winding L and the terminal 2 of the port 01. The resistor is used to avoid the circuit in the bus circuit being too large and to balance the current when there are multiple hosts supplying power to the slaves.

[0048] It can be understood that when the power signal in the embodiment of the present application adopts a low-frequency AC power signal, the relevant parameters of the common-mode winding can be adjusted so that the low-frequency AC power signal can pass through, but the high-frequency non-polarity carrier communication signal in the non-polarity carrier element circuit needs to be isolated to prevent the non-polarity carrier communication signal from being distorted.

[0049] Optionally, the non-polarity carrier communication circuit in the embodiment of the present application may include: a non-polarity carrier communication chip, and the transmission end of the non-polarity carrier communication chip may include: a first pin A and a second pin B; the first pin of the non-polarity carrier communication chip is connected to the fourth input end of the second anti-interference circuit. The second pin of the non-polarity carrier communication chip is connected to the fifth input end of the second anti-interference circuit.

[0050] See also Figure 3 The non-polarity carrier communication circuit in the embodiment of the present application may use an RS485 non-polarity carrier communication chip 02. The chip 02 may include: pin RO, pin Pin FS, pin DI, pin GND, pin A, pin B, and pin VCC. Among them, pin RO is the digital signal output terminal 485_RX, enable pin It is the mode selection terminal, that is, the transmission / reception mode selection. When the enable terminal 485_EN inputs a low level, the chip is in the reception mode, and when the input is a high level, the chip is in the transmission mode. Pin FS is used to select the carrier frequency, and the frequency can be selected using the grounded resistor R17. Pin DI is the digital signal input terminal 485_TX, pin GND is grounded, pin A is the first transmission terminal, pin B is the second transmission terminal, and pin VCC is connected to the third voltage source V3 (for example, 3.3V-5V power supply). The chip 02 works in half-duplex communication mode, that is, only one node on the bus can be in the transmission state at the same time, and the other nodes are in the receiving state.

[0051] Optionally, a resistor R14 is provided between the pin RO of the RS485 non-polar carrier communication chip and the UART serial port of the MCU, and a grounding capacitor C8 is provided between the resistor R14 and the UART serial port of the MCU. A grounding resistor R16 is provided between the UART serial port of the MCU, a resistor R18 is provided between the pin DI and the UART serial port, and a capacitor C6 is provided between the third voltage source and the ground.

[0052] Specifically, the signal input terminal 485_TX, signal output terminal 485_RX, and enable terminal 485_EN of the RS485 non-polarity carrier communication chip are connected to the universal asynchronous receiver / transmitter UART serial port of the microcontroller unit (MCU) to solve the need to change the protocol of carrier communications such as home bus and KNX through the MCU, as well as the physical connection and level logic communication between the RS485 non-polarity carrier communication core.

[0053] It is understandable that when the master device sends a control signal to the slave device, the RS485 non-polarity carrier communication chip can be used to convert the received logic level signal TTL into the first non-polarity carrier communication signal and the second non-polarity carrier communication signal. Among them, the input terminal 485-TX of the chip is not affected by the polarity of pin A and pin B, but the amplitude change of the input signal is checked by the data comparator in the chip, thereby outputting the corresponding first non-polarity carrier communication signal and the second non-polarity carrier communication signal.

[0054] Optionally, when the slave device sends feedback information to the master device, the first pin A and the second pin B of the RS485 non-polar carrier communication chip in the embodiment of the present application can receive the feedback information sent by the slave device, and after further processing the feedback information, output the logic level signal TTL to the MCU of the master device through the output terminal 485-RX of the chip.

[0055] Optionally, the second anti-interference circuit in the embodiment of the present application may include: a first capacitor and a second capacitor. One end of the first capacitor is connected to the first pin of the non-polar carrier communication chip, and the other end of the first capacitor is respectively connected to the first transmission end of the first anti-interference circuit and the first terminal of the port. One end of the second capacitor is connected to the second pin of the non-polar carrier communication chip, and the other end of the second capacitor is respectively connected to the second transmission end of the first anti-interference circuit and the second terminal of the port.

[0056] Optionally, the first capacitor and the second capacitor used in the second anti-interference circuit in the embodiment of the present application can be selected as high-frequency capacitors with a frequency of more than several thousand Hertz to effectively filter out the power supply signal in the bus and the DC signal of the pin VCC that may be carried in the first non-polarity carrier signal and the second non-polarity carrier signal output by the transmission end of the non-polarity carrier communication chip.

[0057] See also Figure 3 In the embodiment of the present application, the pin A of the RS485 non-polar carrier communication chip can be connected to one end of the coupling capacitor C7 via the resettable fuse F2, and the other end of the coupling capacitor C7 is connected to the terminal 1 in the port 01 via the positive bus. The pin B of the RS485 non-polar carrier communication chip can be connected to one end of the coupling capacitor C5 via the resettable fuse F1, and the other end of the second capacitor C5 is connected to the terminal 2 in the port 01 via the negative bus.

[0058] Optionally, the power control circuit in the embodiment of the present application may include: a first triode, a second triode, a field effect transistor, and a first voltage source. The base of the first triode receives the first control signal, the emitter of the first triode is grounded, the collector of the first triode is connected to the base of the second triode, the emitter of the second triode is connected to the first voltage source, the collector of the second triode is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, and the source of the field effect transistor is grounded.

[0059] See also Figure 3 . In the embodiment of the present application, the first transistor Q3 of the power control circuit can use an NPN transistor, and the second transistor Q1 can use a PNP transistor to control the field effect MOS tube Q5. The base of Q3 can be controlled by the pin of the MCU. When the base of Q3 is at a low level, Q3 is in the cut-off state, the base of Q1 is at a high level, Q1 is in the cut-off state, the gate of the MOS tube Q5 is at a low level, and the MOS tube is not turned on. When the pin of the MCU outputs a high level to the base of Q3, Q3 is turned on, the base of Q1 is at a low level, Q1 is turned on, the gate of the MOS tube is at a high level of the first voltage source V1, and the MOS tube Q5 is turned on, that is, the bus circuit is turned on.

[0060] Optionally, the first voltage source V1 in the embodiment of the present application is 12V.

[0061] Optionally, the IO pin of the MCU can control the base of the transistor Q3, and Q3 can be a common transistor or a DT type transistor. A resistor can be added between the base of the transistor Q3 and the ground, a pull-down resistor can be added between the base and the emitter of the transistor Q3, and a pull-down resistor can also be added between the base and the emitter of the transistor Q1, so as to omit the external resistor for circuit discharge.

[0062] See also Figure 3 A voltage regulator Z1 can be set between the gate and source of the MOS tube Q5 to stabilize the voltage between the two, and a transient voltage suppression diode TVS1 can be set between the source and drain of the MOS tube Q5 to protect it from overvoltage. The source of the MOS tube Q5 is connected to the current detection resistor R9 and the resistor network (R10, R11, R12, R13) respectively, and the other end of the resistor network is grounded. The other end of the resistor R9 is connected to the analog-to-digital conversion ADC sampling end of the MCU, and the capacitor C4 is connected in parallel between R9 and the ground GND.

[0063] Furthermore, the power control circuit in the embodiment of the present application may also include: an overcurrent detection unit; the overcurrent detection unit is connected to the other end of the negative bus; the overcurrent detection unit is used to detect the current value in the negative bus; when the current value in the negative bus is greater than the current threshold, the first transistor is controlled to be turned off through the first control signal to shut down the bus circuit.

[0064] See also Figure 3 The overcurrent detection unit in the embodiment of the present application may use a resistor R9, and after collecting a voltage signal at the POC_AD terminal, the current value in the bus circuit is calculated using the formula U=I×R.

[0065] Specifically, the power control circuit in the embodiment of the present application can realize the following functions:

[0066] 1. Overcurrent protection: Overcurrent detection of the bus circuit is achieved by setting an overcurrent detection resistor in the power control circuit;

[0067] Assuming that the maximum current of the bus circuit is 0.5A during normal operation, and the resistor used to measure the overvoltage protection is 1.2Ω, the overcurrent protection voltage can be set to 0.5A*1.2=0.6V through software, that is, the corresponding ADC sampling value in the circuit is 0.6V. Delay 5S to make the first control signal low level for line protection, and control the first control signal to high level after 10S of protection to detect the current in the bus circuit again. If the sampling voltage is less than 0.6V, the first control signal can be kept at a high level to power the bus circuit normally;

[0068] 2. Short circuit protection: achieved by detecting the current in the bus;

[0069] For example, assuming that the short-circuit current threshold is 1A, when the current in the bus is greater than or equal to 1A, the second transistor Q1 can be turned off by directly turning off the first transistor Q3 through hardware (for example, setting a short-circuit protection button outside the master device), so that the bus circuit stops running;

[0070] 3. Bus circuit reverse voltage protection:

[0071] When STATUS=1 (the first control signal is at a high level), it indicates that there is no voltage in the bus or there is a positive voltage and the power supply can be normal;

[0072] When STATUS=0 (the first control signal is at a low level), it indicates that a reverse voltage exists in the bus and the bus circuit needs to be shut down.

[0073] Optionally, the power control circuit of the bus circuit in the embodiment of the present application may include: a first transistor, a second transistor, a push-pull circuit, a field effect transistor, and a first voltage source.

[0074] Among them, the push-pull circuit may include: a sixth input terminal, a seventh input terminal, and an output terminal; the base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the collector of the second transistor is connected to the sixth input terminal of the push-pull circuit, the output terminal of the push-pull circuit is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, the source of the field effect transistor is grounded, and the first voltage source is respectively connected to the emitter of the second transistor and the seventh input terminal of the push-pull circuit.

[0075] Understandably, Figure 3 When the second transistor Q1 in is turned off, it is in a high configuration (i.e., open circuit state), which means Figure 3 The gate of the MOS tube Q5 cannot be guaranteed to be turned off reliably, that is, the voltage at the gate end cannot be guaranteed to be 0.

[0076] Therefore, the embodiment of the present application adopts a push-pull circuit to control the MOS tube Q5, and outputs high and low level control signals to the sixth input terminal of the push-pull circuit through the conduction and shutdown of the second transistor Q1, and then controls the conduction and shutdown of the MOS tube Q5 through the push-pull circuit to control the reliable conduction and shutdown of the MOS tube.

[0077] Optionally, the push-pull circuit in the embodiments of the present application may include: a third triode and a fourth triode; the bases of the third triode and the fourth triode are both connected to the collector of the second triode, the collector of the third triode is connected to the first voltage source, the collector of the fourth triode is grounded, and the emitters of the third triode and the fourth triode are both connected to the gate of the field effect transistor.

[0078] See Figure 4 The schematic diagram of the internal structure of the bus circuit shown. The push-pull circuit may include: an NPN-type triode Q2 and a PNP-type triode Q4. The bases of the triode Q2 and the triode Q4 are both connected to the collector of the PNP-type triode Q1, the collector of the triode Q2 is connected to the first voltage source, the collector of the triode Q4 is grounded, and the emitters of the triode Q2 and the triode Q4 are both connected to the gate of the MOS transistor Q5.

[0079] It can be understood that when a high-level signal is input to the POC_EN terminal, the base of the triode Q3 is at a high level, the triode Q3 conducts, making the base of the triode Q1 at a low level, the triode Q1 conducts, making the bases of the triodes Q2 and Q4 in the push-pull circuit at a high level, the triode Q2 conducts, the triode Q4 cuts off, the gate of the MOS transistor Q5 is at a high level, and the MOS transistor Q5 conducts.

[0080] When a low-level signal is input to the POC_EN terminal, the base of the triode Q3 is at a low level, the triode Q3 cuts off, making the base of the triode Q1 at a high level, the triode Q1 cuts off. Since the bases of the triodes Q2 and Q4 in the push-pull circuit are grounded at a low level, the triode Q2 cuts off, the triode Q4 conducts, making the output terminal of the push-pull circuit grounded, and the gate of the MOS transistor Q5 is at a low level, which can ensure that the MOS transistor Q5 is reliably turned off.

[0081] Further, the non-polar carrier communication circuit in the embodiments of the present application may further include: a first anti-interference module, and the first anti-interference module includes: an eighth input terminal, a ninth input terminal, a fifth output terminal, and a sixth output terminal. The eighth input terminal of the first anti-interference module is connected to the first pin of the non-polar carrier communication chip, the ninth input terminal of the first anti-interference module is connected to the second pin of the non-polar carrier communication chip, the fifth output terminal of the first anti-interference module is connected to one end of the first capacitor, and the sixth output terminal of the first anti-interference module is connected to one end of the second capacitor; the first anti-interference module is used to isolate the surge signal generated by lightning.

[0082] Optionally, the first anti-interference module in the embodiments of the present application may adopt an isolation transformer.

[0083] Furthermore, the bus circuit in the embodiment of the present application can isolate the first non-polarity carrier signal and the second non-polarity carrier signal through an isolation transformer based on the push-pull circuit, and the output side of the isolation transformer is respectively connected to the first coupling capacitor and the second coupling capacitor.

[0084] See also Figure 4 The schematic diagram of the bus circuit is shown. Pin A and pin B of the non-polar carrier chip 02 are connected to one end of the transient voltage suppressor TVS2 and the transient voltage suppressor TVS3 respectively, and the other end of TVS2 and TVS3 is grounded. R15 (resistance 100-120Ω) is connected between pin A and pin B, and pin A and pin B are connected to one end of two self-recovery fuses F1 and F2 respectively. The other end of F1 and F2 is connected to pin 1 and pin 4 of the isolation transformer T1, and pin 2 and pin 3 of the isolation transformer T1 are short-circuited and grounded through a capacitor. Pin 6 and pin 7 on the output side of the isolation transformer are grounded through a capacitor, and pin 5 and pin 8 of the isolation transformer T1 are connected to one end of capacitors C5 and C7, and the other end of C5 and C7 is connected to port 01.

[0085] Furthermore, the non-polarity carrier communication circuit in the embodiment of the present application also includes: a second anti-interference module, the second anti-interference module includes: a tenth input terminal, a seventh output terminal, and an eighth output terminal; the tenth input terminal of the second anti-interference module receives a second control signal, the seventh output terminal of the second anti-interference module is connected to the first pin of the non-polarity carrier communication chip, and the eighth output terminal of the second anti-interference module is connected to the second pin of the non-polarity carrier communication chip.

[0086] Among them, the second control signal is used to control the operation of the second anti-interference module. When the distance between the bus circuit and the device connected to the port is greater than the distance threshold, the second control signal is at a high level, and the second anti-interference module works; when the distance between the bus circuit and the device connected to the port is less than or equal to the distance threshold, the second control signal is at a low level, and the second anti-interference module stops working; the second anti-interference module is used to isolate the reflected voltage generated between the bus circuit and the device connected to the port.

[0087] Optionally, the second anti-interference module in the embodiment of the present application may adopt a solid-state relay.

[0088] It is understandable that when the line distance between the master and slave devices is too long, there may be interference from the reflected voltage on the line, thereby disrupting the transmitted waveform carrier signal. Therefore, when the line between the master and slave devices exceeds the threshold, a high level can be input to the input end of the second anti-interference module, and when it does not exceed the threshold, a low level is input.

[0089] See also Figure 6The internal structure diagram of the bus circuit is shown. Pin 1 of the solid-state relay IC2 is connected to pin A of the RS485 non-polar carrier communication chip via resistor R15, pin 2 of the solid-state relay IC2 is connected to pin B of the RS485 non-polar carrier communication chip, pin 3 of the solid-state relay IC2 is connected to the power supply VCC1 via resistor R19, and pin 4 of the solid-state relay IC2 is the second control signal input terminal. Assuming that the distance threshold is 50 meters, when the distance between the master and slave devices is greater than 50 meters, the second control signal is high level, and the solid-state relay IC2 works. When the distance between the master and slave devices is less than or equal to 50 meters, the second control signal is low level, and the solid-state relay IC2 stops working.

[0090] The embodiments described above are merely preferred embodiments of the present application and are not intended to limit the scope of the present application. Without departing from the design spirit of the present application, various modifications and improvements made to the technical solutions of the present application by ordinary technicians in this field should fall within the protection scope determined by the claims of the present application.

Claims

1. A bus circuit, It is characterized in that The bus circuit includes: a power interface, a power control circuit, a polarity-free carrier communication circuit, a positive bus, a negative bus, a first anti-interference circuit, a second anti-interference circuit, and a port, wherein: The non-polar carrier communication circuit includes: a first input end, a first transmission end, and a second transmission end; the first anti-interference circuit includes: a second input end, a third input end, a first output end, and a second output end; the second anti-interference circuit includes: a fourth input end, a fifth input end, a third output end, and a fourth output end; the port includes: a first terminal and a second terminal, wherein, One end of the positive bus is connected to the power interface, the other end of the positive bus is connected to the second input end of the first anti-interference circuit, the first output end of the first anti-interference circuit is respectively connected to the first terminal of the port and the third output end of the second anti-interference circuit, and the fourth input end of the second anti-interference circuit is connected to the first transmission end of the non-polarity carrier communication circuit; one end of the negative bus is grounded via the power control circuit, the other end of the negative bus is connected to the third input end of the first anti-interference circuit, the second output end of the first anti-interference circuit is respectively connected to the second terminal of the port and the fourth output end of the second anti-interference circuit, and the fifth input end of the second anti-interference circuit is connected to the second transmission end of the non-polarity carrier communication circuit; The power interface is used to receive a power signal; The power control circuit is used to control the on and off of the bus circuit according to the received first control signal; The first input end of the non-polarity carrier communication circuit is used to receive a logic level signal, the first transmission end of the non-polarity carrier communication circuit is used to output a first non-polarity carrier communication signal, and the second transmission end of the non-polarity carrier communication circuit is used to output a second non-polarity carrier communication signal; The first anti-interference circuit is used to isolate the first non-polarity carrier communication signal and the second non-polarity carrier communication signal output by the non-polarity carrier communication circuit, and input the power signal in the positive bus into the first terminal of the port and the power signal in the negative bus into the second terminal of the port; The second anti-interference circuit is used to isolate the power supply signal, and load the received first non-polarity carrier communication signal into the positive bus containing the power supply signal, and load the received second non-polarity carrier communication signal into the negative bus containing the power supply signal.

2. The bus circuit according to claim 1, It is characterized in that The bus circuit also includes: a power polarity detection circuit; The input end of the power polarity detection circuit is connected to the negative bus, and the output end of the power polarity detection circuit is connected to the positive bus; The power polarity detection circuit is used to detect the positive and negative poles of the DC power supply connected to the power interface.

3. The bus circuit according to claim 1, It is characterized in that The first anti-interference circuit comprises: a common mode winding, the common mode winding comprises: a first winding and a second winding, the first winding comprises: a third terminal and a fourth terminal, the second winding comprises: a fifth terminal and a sixth terminal, wherein the third terminal and the fifth terminal are terminals of the same name; The other end of the positive bus is connected to the fifth terminal of the second winding, and the sixth terminal of the second winding is connected to the fifth output terminal, the third output terminal of the second anti-interference circuit and the first terminal of the port; the other end of the negative bus is connected to the fourth terminal of the first winding, and the third terminal of the first winding is connected to the sixth output terminal, the fourth output terminal of the second anti-interference circuit and the second terminal of the port.

4. The bus circuit according to claim 1, It is characterized in that The non-polarity carrier communication circuit comprises: a non-polarity carrier communication chip, and the transmission end of the non-polarity carrier communication chip comprises: a first pin and a second pin; The first pin of the non-polarity carrier communication chip is connected to the fourth input terminal of the second anti-interference circuit; The second pin of the non-polarity carrier communication chip is connected to the fifth input terminal of the second anti-interference circuit.

5. The bus circuit according to claim 4, It is characterized in that The second anti-interference circuit includes: a first capacitor and a second capacitor; One end of the first capacitor is connected to the first pin of the non-polar carrier communication chip, and the other end of the first capacitor is connected to the first transmission end of the first anti-interference circuit and the first terminal of the port respectively; One end of the second capacitor is connected to the second pin of the non-polar carrier communication chip, and the other end of the second capacitor is respectively connected to the second transmission end of the first anti-interference circuit and the second terminal of the port.

6. The bus circuit according to claim 1, It is characterized in that The power control circuit comprises: a first triode, a second triode, a field effect transistor, and a first voltage source; The base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the emitter of the second transistor is connected to the first voltage source, the collector of the second transistor is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, and the source of the field effect transistor is grounded.

7. The bus circuit according to claim 1, It is characterized in that The power control circuit includes: a first triode, a second triode, a push-pull circuit, a field effect transistor, and a first voltage source; wherein the push-pull circuit includes: a sixth input terminal, a seventh input terminal, and an output terminal; The base of the first transistor receives the first control signal, the emitter of the first transistor is grounded, the collector of the first transistor is connected to the base of the second transistor, the collector of the second transistor is connected to the sixth input terminal of the push-pull circuit, the output terminal of the push-pull circuit is connected to the gate of the field effect transistor, one end of the negative bus is connected to the drain of the field effect transistor, the source of the field effect transistor is grounded, and the first voltage source is respectively connected to the emitter of the second transistor and the seventh input terminal of the push-pull circuit.

8. The bus circuit according to claim 7, It is characterized in that The push-pull circuit comprises: a third triode and a fourth triode; The base of the third transistor and the base of the fourth transistor are both connected to the collector of the second transistor, the collector of the third transistor is connected to the first voltage source, the collector of the fourth transistor is grounded, and the emitter of the third transistor and the emitter of the fourth transistor are both connected to the gate of the field effect transistor.

9. The bus circuit according to claim 5, It is characterized in that The non-polarity carrier communication circuit further includes: a first anti-interference module, the first anti-interference module including: an eighth input terminal, a ninth input terminal, a fifth output terminal, and a sixth output terminal; The eighth input end of the first anti-interference module is connected to the first pin of the non-polar carrier communication chip, the ninth input end of the first anti-interference module is connected to the second pin of the non-polar carrier communication chip, the fifth output end of the first anti-interference module is connected to one end of the first capacitor, and the sixth output end of the first anti-interference module is connected to one end of the second capacitor; The first anti-interference module is used to isolate surge signals generated by lightning.

10. The bus circuit according to claim 5 or 9, It is characterized in that The non-polarity carrier communication circuit further includes: a second anti-interference module, the second anti-interference module includes: a tenth input terminal, a seventh output terminal, and an eighth output terminal; The tenth input terminal of the second anti-interference module receives the second control signal, the seventh output terminal of the second anti-interference module is connected to the first pin of the non-polarity carrier communication chip, and the eighth output terminal of the second anti-interference module is connected to the second pin of the non-polarity carrier communication chip; Wherein, the second control signal is used to control the operation of the second anti-interference module. When the distance between the bus circuit and the device connected to the port is greater than the distance threshold, when the second control signal is at a high level, the second anti-interference module works; when the distance between the bus circuit and the device connected to the port is less than or equal to the distance threshold, when the second control signal is at a low level, the second anti-interference module stops working; The second anti-interference module is used to isolate the reflected voltage generated between the bus circuit and the device connected to the port.

11. The bus circuit according to claim 6, It is characterized in that The power supply control circuit further includes: an overcurrent detection unit; the overcurrent detection unit is connected to the other end of the negative bus; The overcurrent detection unit is used to detect the current value in the negative bus; When the current value in the negative bus is greater than the current threshold, the first transistor is controlled to be turned off by the first control signal, so that the bus circuit is turned off.

12. An electronic device, It is characterized in that include: A bus circuit as claimed in any one of claims 1 to 11.

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