Signal sending method, electronic equipment and communication system

Abstract

The invention provides a signal sending method, electronic equipment and a communication system. The signal sending method comprises the steps that a sending end sends a DQ redundant code and a DQS preamble to a receiving end in a preamble period, the DQ redundant code is configured to have a specific code pattern so that a DQ signal can track jitter of the DQS signal, and the specific code pattern comprises the fact that the lowest two bits of the DQ redundant code are the same as the lowest two bits of the DQS preamble; and the transmitting end transmits the DQ signal and the DQS signal to the receiving end during the data transmission period. The signal sending method provided by the invention can reduce the time sequence loss.

Description

Technical Field

[0001] The present application belongs to the field of communication technology and relates to a signal sending method, and in particular to a signal sending method, an electronic device and a communication system. Background Art

[0002] In a source clock synchronous transmission system, the transmitting end sends a sampling clock signal and a data signal to the receiving end at the same time, and the receiving end samples the data signal using the received sampling clock signal. The source clock synchronous transmission system can provide highly accurate clock synchronization, thereby ensuring accurate sampling and transmission of data. However, the inventors have found in actual applications that there is often timing loss at the receiving end of the source clock synchronous transmission system, which can cause a difference in time between the data received by the receiving end and the expected data, which can cause data loss or erroneous reception in severe cases, affecting the reliability of communication. Summary of the invention

[0003] Embodiments of the present application provide a signal transmission method, an electronic device, and a communication system for reducing the timing loss of a source clock synchronous transmission system.

[0004] In a first aspect, an embodiment of the present application provides a signal sending method, the signal sending method comprising: during a preamble period, a transmitting end sends a DQ redundant code and a DQS preamble code to a receiving end, wherein the DQ redundant code is configured to have a specific code pattern so that the DQ signal can track the jitter of the DQS signal, and the specific code pattern includes the lowest two bits of the DQ redundant code being the same as the lowest two bits of the DQS preamble code; during data transmission, the transmitting end sends the DQ signal and the DQS signal to the receiving end.

[0005] In an implementation of the first aspect, the channel between the transmitting end and the receiving end is a linear time-invariant channel, the jitter of the DQ signal includes basic jitter corresponding to a basic code pattern and additional jitter corresponding to other code patterns, and the DQ redundant code is configured to have the specific code pattern through a register in the transmitting end to reduce the basic jitter difference and the additional jitter difference between the DQ signal and the DQS signal.

[0006] In an implementation manner of the first aspect, the code patterns of the DQ redundant code and the DQS preamble code are stored in a register, and the signal sending method further includes: acquiring the code patterns of the DQ redundant code and the DQS preamble code from the register.

[0007] In an implementation manner of the first aspect, the lowest n bits of the DQ redundancy code are configured to be the same as the lowest n bits of the DQS preamble code, where n is a positive integer greater than 2.

[0008] In an implementation manner of the first aspect, a code type of the DQS preamble code is 00001010, and the lowest two bits of the DQ redundant code are 10.

[0009] In an implementation manner of the first aspect, a code type of the DQS preamble code is 00001010, and a code type of the DQ redundant code is 00001010 or 00010010.

[0010] In an implementation manner of the first aspect, the signal sending method is applied to a source clock synchronous transmission system.

[0011] In a second aspect, an embodiment of the present application provides an electronic device, comprising: a memory storing a computer program; and a processor communicatively connected to the memory, for executing any of the signal sending methods described in the first aspect of the embodiment of the present application when the computer program is called.

[0012] In a third aspect, an embodiment of the present application provides a communication system, comprising: a transmitting end, used to send a signal to a receiving end using the signal sending method described in any one of the first aspects of the embodiments of the present application; and a receiving end, used to receive the signal sent by the transmitting end.

[0013] In the signal sending method provided in the embodiment of the present application, the DQ redundant code is configured to have a specific code type, that is, at least the two lowest bits of the DQ redundant code are made the same as the two lowest bits of the DQS preamble code, so that the DQ signal can track the jitter of the DQS signal, thereby reducing the jitter difference between the DQ signal and the DQS signal, and reducing the timing loss at the receiving end. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A Shown is an architectural diagram of a DDR memory subsystem in an embodiment of the present application.

[0015] Figure 1B The waveform diagram shows the communication between the transmitter and receiver using source clock synchronous transmission.

[0016] Figure 1C Display as Figure 1B The jitter difference between the DQS signal and the DQ signal in the .

[0017] Figure 1D Displays the waveforms of the DQS and DQ signals.

[0018] Figure 2 Shown is a flowchart of a signal sending method provided in an embodiment of the present application.

[0019] Figure 3 Shown is a waveform diagram of the DQS signal and the DQ signal in an embodiment of the present application.

[0020] Figure 4A Shown is a waveform diagram of the DQS signal and the DQ signal in an embodiment of the present application.

[0021] Figure 4B Shown is a waveform diagram of the DQS signal and the DQ signal in an embodiment of the present application.

[0022] Figure 4C It shows the jitter difference between the DQS signal and the DQ signal in the embodiment of the present application.

[0023] Figure 5A Shown is a waveform diagram of the DQS signal and the DQ signal in an embodiment of the present application.

[0024] Figure 5B Shown is a waveform diagram of the DQS signal and the DQ signal in an embodiment of the present application.

[0025] Figure 5C It shows the jitter difference between the DQS signal and the DQ signal in the embodiment of the present application.

[0026] Figure 6 Shown is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0028] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0029] One application scenario of the source clock synchronous transmission system is a DDR (Double Data Rate) memory subsystem. Figure 1A The following is an architectural diagram of the DDR memory subsystem. Figure 1A As shown, the DDR memory subsystem includes a memory controller and a storage module.

[0030] The storage module includes a plurality of storage devices, each of which may include one or more memory particles. In some embodiments, the storage module may be a storage module that complies with the JEDEC double rate synchronous dynamic random access memory (SDRAM) standard, such as JEDEC DDR1, DDR2, DDR3, DDR4, DDR5 and other double rate memory standards. In addition, the storage module may also be an internal memory that complies with other standards or protocols, such as SDRAM or RAMBUS internal memory, or a memory that complies with future memory standards or protocols. In some embodiments, the storage module may include a volatile memory (e.g., a dynamic random access memory), a non-volatile memory (flash memory, such as NAND or NOR flash memory), or a combination of the two. In other embodiments, the storage module may also be a new type of memory manufactured using different production processes, including but not limited to: magnetoresistive memory, phase change memory, resistive memory, semi-floating gate memory, or any other type of memory.

[0031] The memory controller is used to coordinate and manage the reading and writing of memory data. Its main functions include timing control, data scheduling, address generation, and data buffering. The memory controller includes a clock cache chip and multiple data cache chips.

[0032] The function of the clock buffer chip is to generate and maintain accurate clock signals to ensure that memory operations and data transmission are performed at the right time. The clock signal is used to synchronize the operation of various components in the entire DDR memory subsystem. The clock buffer chip is coupled between the main controller and the storage module, and it can receive the DCK signal from the main controller. The DCK signal is a double data rate clock signal, for example, a clock signal used to transmit command and address information from the main controller to the clock buffer chip. The clock buffer chip generates a QCK signal (storage clock signal) and a BCK signal (data buffer clock signal) according to the DCK signal. The QCK signal and the BCK signal are transmitted to the storage module and the data buffer chip respectively to synchronize the components of each module.

[0033] The data cache chip is used to cache and manage data to ensure efficient execution of memory operations. The data cache chip has storage capacity and can temporarily store data read from the memory so that the data can be provided to other components more quickly. This method helps to reduce memory access latency and improve the response speed of the system. The data cache chip can exchange data between the main controller and the corresponding storage device. Among them, the communication between the data cache chip and the storage device, and the communication between the data cache chip and the main controller can be carried out in the form of source clock synchronous transmission. Taking the communication between the data cache chip and the main controller as an example, the sending end (such as the main controller) will use the DQS signal as a sampling clock signal, and send it together with the DQ signal (data signal) to the receiving end (such as the data cache chip), and the receiving end can use the received DQS signal to sample the DQ signal. The communication between the data cache chip and the storage device is similar to this. The sending end will use the MDQS signal as a sampling clock signal and send it together with the MDQ signal as a data signal to the receiving end, and the receiving end will use the received MDQS signal to sample the MDQ signal.

[0034] The main controller, data cache chip and storage device also include registers, and the main controller, data cache chip and storage device can configure the DQS (or MDQS) preamble code and the DQ (or MDQ) redundant code through their respective registers. The DQS preamble code and the DQ redundant code will be described in detail below.

[0035] Figure 1B The waveform diagram shows that a transmitter and a receiver communicate using source clock synchronous transmission. The transmitter can be Figure 1A Any one of the main controller, data buffer chip and storage device in the system. Correspondingly, when the sending end is the main controller or storage device, the receiving end is the data buffer chip; when the sending end is the data buffer chip, the receiving end is the main controller or storage device. For the convenience of explanation, the following will take the sending end as the main controller and the receiving end as the data buffer chip as an example. Figure 1B As shown, the main controller does not send data to the data cache chip during the idle period. During the preamble period, the main controller sends the DQS preamble code and the DQ redundant code to the data cache chip. Among them, the DQS preamble code is used during the calibration work (i.e. Figure 1B The DQS signal during the data transmission period in the DQS preamble period is the DQ redundancy code. It should be noted that Figure 1B The schematic diagram takes the DQS leading code pattern as 00001010 and the DQ redundant code pattern as 111111111 as an example. During data transmission, the main controller simultaneously sends the DQS signal and the DQ signal to the data cache chip, and the data cache chip samples the DQ signal according to the received DQS signal.

[0036] Due to the characteristics of the burst read data mode of the DQ interface, the DQS signal needs a period of time to stabilize. During the stabilization process, the DQS signal will have jitter. Figure 1B It can be seen that there is a large jitter difference between the DQS signal and the DQ signal. In a source clock synchronous transmission system, the jitter of the DQS signal itself may have a small impact on the timing, while the jitter difference between DQS and DQ has a greater impact on the timing.

[0037] Figure 1C Indicated Figure 1B The jitter difference between the DQS signal and the DQ signal in the Figure 1C As shown in the figure, in the first few code elements, the jitter difference between the DQ signal and the DQS signal is very large, and the jitter difference can last for more than 30 code elements before disappearing. The jitter difference between the DQ signal and the DQS signal will make the timing margin worse, causing timing loss, thus affecting the correctness of the data sampled by the receiving end.

[0038] In addition, the code types of the DQ redundant code and the DQS preamble code are different, and the jitter difference between the DQ signal and the DQS signal is also different. Figure 1D As shown, in some embodiments, the code pattern of the DQ redundant code may be 11111111, and the code pattern of the DQS preamble code may be 00001010. At this time, the channel responses of the DQ signal and the DQS signal are similar. During the preamble period, the code pattern of the DQ redundant code and the code pattern of the DQS preamble code are less consistent, resulting in a large difference in the inter-symbol interference of the DQ signal and the DQS signal, and thus a large difference in the jitter of the DQ signal and the DQS signal.

[0039] Based on the above content, an embodiment of the present application provides a signal transmission method. In the signal transmission method, by configuring the DQ redundant code to have a specific code pattern, the DQ signal can track the jitter of the DQS signal, thereby reducing the jitter difference between the DQ signal and the DQS signal, and reducing the timing loss of the receiving end.

[0040] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.

[0041] Figure 2 The flowchart of the signal sending method provided by the embodiment of the present application is shown. The signal sending method is applied to the sending end of the source clock synchronous transmission system. Figure 2 As shown, the signal sending method includes:

[0042] S21, during the preamble period, the transmitting end sends the DQ redundant code and the DQS preamble code to the receiving end. The DQ redundant code is configured to have a specific code pattern so that the DQ signal can track the jitter of the DQS signal. In some implementations, the specific code pattern includes the lowest two bits of the DQ redundant code being the same as the lowest two bits of the DQS preamble code. For example, when the lowest two bits of the DQS preamble code are 10, the lowest two bits of the DQ redundant code are also configured to be 10, but the embodiments of the present application are not limited to this. Since the lowest two bits of the DQ redundant code are configured to be the same as the lowest two bits of the DQS preamble code, the channel response of the DQ signal and the DQS signal are similar, and the inter-code interference of the DQ signal and the DQS signal is also similar, thereby reducing the jitter difference between the DQ signal and the DQS signal.

[0043] In some implementations, the code pattern of the DQ redundant code may be configured through a register in the transmitting end so that the DQ redundant code has the above-mentioned specific code pattern.

[0044] S22, during data transmission, the transmitting end sends a DQ signal and a DQS signal to the receiving end.

[0045] In some implementations, the transmitter sends the DQ signal and the DQS signal synchronously, and the receiver uses the rising and falling edges of the DQS signal to sample the DQ data. In order to achieve accurate sampling, the receiver's sampling of the DQ data should meet the requirements of the sampling setup time (Setup Time) and hold time (Hold Time). Figure 3 It is shown as an example diagram of the DQS signal and the DQ signal in the embodiment of the present application. Among them, the setup time refers to the time interval before the sampling moment when the DQ signal must be stable and maintained at an appropriate level. The hold time refers to the time interval after the sampling moment when the DQ signal must be maintained at an appropriate level. When the DQ signal remains unchanged, if the DQS signal causes the sampling moment to be advanced due to jitter, that is, the DQS signal shifts forward, the setup time will be reduced; if the DQS signal causes the sampling moment to be delayed due to jitter, that is, the DQS signal shifts backward, the hold time will be reduced, and both situations may cause sampling errors. In the embodiment of the present application, by configuring the DQ redundant code to have a specific code type, the DQ signal can track the jitter of the DQS signal. Specifically, when the DQS signal shifts forward due to jitter, the DQ signal also shifts forward, and the setup time and hold time remain basically unchanged. When the DQS signal shifts backward due to jitter, the DQ signal also shifts backward, and the setup time and hold time remain basically unchanged. Therefore, the signal sending method provided in the embodiment of the present application can reduce the possibility of sampling errors and reduce the timing loss of the received signal.

[0046] In some implementations, the channel between the transmitting end and the receiving end is a linear time-invariant channel. According to the superposition principle of the linear time-invariant channel, the jitter of the DQ signal includes a basic jitter corresponding to the basic code pattern and an additional jitter corresponding to other code patterns. The basic code pattern is, for example, a 1010 code pattern, and the other code patterns are any code patterns other than 1010. The DQ redundant code can be configured to have a specific code pattern through a register in the transmitting end to reduce the basic jitter difference and the additional jitter difference between the DQ signal and the DQS signal.

[0047] In some implementations, the lowest n bits of the DQ redundant code are configured to be the same as the lowest n bits of the DQS preamble code, where n is a positive integer greater than 2 and less than or equal to m, where m is the total number of bits of the DQ redundant code. That is, on the basis that the lowest two bits are the same, the more bits of the DQS preamble code and the DQ redundant code are the same, the more similar the code patterns of the two are, and the smaller the jitter difference between the two is.

[0048] See also Figure 4A In some implementations, the code pattern of the DQS preamble is 00001010, the code pattern of the DQ redundant code is configured as 00001010, and the channel responses of the DQ signal and the DQS signal are similar. Figure 4B The waveforms of the DQ and DQS signals in these implementations are shown as follows. Figure 4C The jitter difference between the DQ signal and the DQS signal in these implementations is shown. During the preamble period, the pattern of the DQ redundant code and the DQS preamble code are consistent. Since the DQ signal and the DQS signal are subject to similar inter-symbol interference, the jitter difference between the DQ signal and the DQS signal can be reduced, reducing timing loss.

[0049] See also Figure 5A In some implementations, the code pattern of the DQS preamble code is 00001010, the code pattern of the DQ redundant code is 00010010, and the channel responses of the DQ signal and the DQS signal are similar. Figure 5B The waveforms of the DQ and DQS signals in these implementations are shown as follows. Figure 5C The jitter difference between the DQ signal and the DQS signal in these implementations is shown. During the preamble period, the code patterns of the DQ redundant code and the DQS preamble are very similar. Since the DQ signal and the DQS signal are subject to similar inter-symbol interference, the jitter difference between the DQ signal and the DQS signal can be reduced, thereby reducing timing loss.

[0050] It should be noted that the code types of the DQ redundant code and the DQS preamble code in the above implementation are only several feasible methods of the embodiments of the present application, but the embodiments of the present application are not limited thereto.

[0051] The protection scope of the signal sending method provided by the embodiment of the present application is not limited to the execution order of the steps listed in this embodiment. All solutions implemented by adding, reducing or replacing steps in the prior art based on the principles of the present application are included in the protection scope of the present application.

[0052] An embodiment of the present application also provides an electronic device. Figure 6 The structure diagram of the electronic device 600 in one embodiment of the present application is shown. Figure 6 As shown, in this embodiment, the electronic device 600 includes a memory 610 and a processor 620 .

[0053] The memory 610 is used to store computer programs. In some possible implementations, the memory 610 may include: ROM, RAM, a disk, a USB flash drive, a memory card, or an optical disk, etc., various media that can store program codes.

[0054] In the embodiment of the present application, the memory 610 may include a computer system readable medium in the form of a volatile memory, such as a RAM and / or a cache memory. The electronic device 600 may further include other removable / non-removable, volatile / non-volatile computer system storage media. The memory 610 may include at least one program product, which has a set (e.g., at least one) of program modules, which are configured to perform the functions of the various embodiments of the present application.

[0055] The processor 620 is connected to the memory 610 and is used to execute the computer program stored in the memory 610 so that the electronic device 600 executes the signal sending method provided in the embodiment of the present application.

[0056] In some embodiments, the processor 620 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc. In other embodiments, the processor 620 may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0057] In some possible implementations, the electronic device 600 provided in the embodiment of the present application may further include a display 630. The display 630 is communicatively connected to the memory 610 and the processor 620, and is used to display a graphical user interface (GUI) related to the signal transmission method.

[0058] In the embodiment of the present application, the display 630 may include a display screen (display panel). In some implementations, the display panel may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc. In addition, the display 630 may also be a touch panel (touch screen, touch screen), and the touch panel may include a display screen and a touch-sensitive surface. When the touch-sensitive surface detects a touch operation on or near it, it is transmitted to the processor 620 to determine the type of touch event, and then the processor 620 provides a corresponding visual output on the display device according to the type of touch event.

[0059] The embodiment of the present application also provides a communication system, which is a source clock synchronous transmission system. The communication system provided by the embodiment of the present application includes a transmitting end and a receiving end. The transmitting end and the receiving end are connected at least by a DQ line and a DQS line. The transmitting end is used to send a DQ signal and a DQS signal to the receiving end using the signal sending method provided by the embodiment of the present application. The receiving end is used to receive the DQ signal and the DQS signal sent by the transmitting end, and use the DQS signal to sample the DQ signal.

[0060] In summary, in the signal sending method provided in the embodiment of the present application, the DQS preamble code and the DQ redundant code are configured to have a specific code type, so that the DQ signal can track the jitter of the DQS signal, thereby reducing the jitter difference between the DQ signal and the DQS signal, and reducing the timing loss at the receiving end. In addition, the embodiment of the present application also provides some code types of DQ redundant codes and DQS preamble codes with better performance. When these DQ redundant codes and DQS preamble codes are used, the jitter difference between the DQS signal and the DQ signal can be better reduced, the timing margin of the received signal can be increased, and the timing loss can be improved. Therefore, the embodiment of the present application effectively overcomes the various defects in the prior art and has a high industrial value.

[0061] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A signal sending method, It is characterized in that The signal sending method comprises: During the preamble period, the transmitting end transmits a DQ redundant code and a DQS preamble code to the receiving end, wherein the DQ redundant code is configured to have a specific code pattern so that the DQ signal can track the jitter of the DQS signal, and the specific code pattern includes that the lowest two bits of the DQ redundant code are the same as the lowest two bits of the DQS preamble code; During data transmission, the transmitting end sends the DQ signal and the DQS signal to the receiving end.

2. The signal transmission method according to claim 1, It is characterized in that The channel between the transmitting end and the receiving end is a linear time-invariant channel, the jitter of the DQ signal includes basic jitter corresponding to a basic code pattern and additional jitter corresponding to other code patterns, and the DQ redundant code is configured to have the specific code pattern through a register in the transmitting end to reduce the basic jitter difference and the additional jitter difference between the DQ signal and the DQS signal.

3. The signal transmission method according to claim 1, It is characterized in that The code patterns of the DQ redundant code and the DQS preamble code are stored in a register, and the signal sending method further includes: acquiring the code patterns of the DQ redundant code and the DQS preamble code from the register.

4. The signal transmission method according to claim 1, It is characterized in that The lowest n bits of the DQ redundant code are configured to be the same as the lowest n bits of the DQS preamble code, where n is a positive integer greater than 2.

5. The signal transmission method according to claim 1, It is characterized in that The code type of the DQS preamble code is 00001010, and the lowest two bits of the DQ redundant code are 10.

6. The signal transmission method according to claim 5, It is characterized in that The code type of the DQS preamble code is 00001010, and the code type of the DQ redundant code is 00001010 or 00010010.

7. The signal transmission method according to claim 1, It is characterized in that The signal sending method is applied to a source clock synchronous transmission system.

8. An electronic device, It is characterized in that The electronic device comprises: A memory storing a computer program; A processor is communicatively connected to the memory, and executes the signal sending method according to any one of claims 1 to 7 when calling the computer program.

9. A communication system, It is characterized in that The communication system comprises: A transmitting end, configured to send a signal to a receiving end using the signal sending method according to any one of claims 1 to 7; The receiving end is used to receive the signal sent by the sending end.

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