Display device and method for manufacturing display device

Abstract

The invention provides a display device and a method of manufacturing the same. The display device includes a substrate including a first pad electrode and a second pad electrode; a bank defining a first opening through which at least a portion of the first pad electrode and at least a portion of the second pad electrode are exposed; an inter-electrode planarization layer between the first pad electrode and the second pad electrode; a first reflective electrode extending from the bank to the inter-electrode planarization layer along the first pad electrode; a second reflective electrode extending from the bank to the inter-electrode planarization layer along the second pad electrode; an organic pattern layer in the first opening; a light emitting element having a first contact electrode and a second contact electrode on a top surface thereof; a via layer covering the light emitting element and defining a contact hole; a first lead over the via layer and electrically connecting the first contact electrode and the first reflective electrode; and a second lead over the via layer and electrically connecting the second contact electrode and the second reflective electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0162921 filed in the Korean Intellectual Property Office on November 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0004] As multimedia develops, display devices are becoming more and more important. In response to this, various types of display devices such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs) are being used.

[0005] The device for displaying an image of the display device includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element. For example, a light-emitting diode (LED) includes an organic light-emitting diode (OLED) using an organic material as a light-emitting material, an inorganic light-emitting diode using an inorganic material as a light-emitting material, and the like. Summary of the invention

[0006] Aspects of embodiments of the present disclosure provide a display device and a method of manufacturing the same, which can solve the problem of residues that may occur between pad electrodes when forming a reflective electrode.

[0007] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0008] According to one or more embodiments, a display device includes: a substrate on which a first pad electrode and a second pad electrode are positioned; a dam defining a first opening above the substrate and exposing at least a portion of the first pad electrode and at least a portion of the second pad electrode through the first opening; an inter-electrode planarization layer between the first pad electrode and the second pad electrode; a first reflective electrode extending from the dam along the first pad electrode to the inter-electrode planarization layer; a second reflective electrode extending from the dam along the second pad electrode to the inter-electrode planarization layer; an organic pattern layer in the first opening; a light-emitting element above the organic pattern layer and having a first contact electrode and a second contact electrode on a top surface of the light-emitting element; a through-hole layer covering the light-emitting element and defining a contact hole; a first lead above the through-hole layer and electrically connecting the first contact electrode and the first reflective electrode; and a second lead above the through-hole layer and electrically connecting the second contact electrode and the second reflective electrode.

[0009] The inter-electrode planarization layer and the bank may have the same thickness.

[0010] The inter-electrode planarization layer and the bank may include the same material.

[0011] The inter-electrode planarization layer and the bank may include a light blocking material.

[0012] The first pad electrode and the second pad electrode may be spaced apart from each other on the same plane, and may protrude outward from the light emitting element in a plan view.

[0013] The inter-electrode planarization layer may have the same height as the first pad electrode and the second pad electrode.

[0014] A height of the inter-electrode planarization layer may be greater than heights of the first pad electrode and the second pad electrode.

[0015] A top surface of the inter-electrode planarization layer may contact the organic pattern layer, wherein a roughness of the top surface of the inter-electrode planarization layer is greater than a roughness of another surface of the inter-electrode planarization layer.

[0016] The light emitting element may include a second semiconductor layer, an active layer, a first semiconductor layer, an element insulating layer, and a third semiconductor layer contacting the organic pattern layer, wherein the element insulating layer surrounds the third semiconductor layer, the second semiconductor layer, the active layer, the side surfaces of the first semiconductor layer, and the top surface of the light emitting element, and defines a second opening and a third opening, wherein the first contact electrode is electrically connected to the first semiconductor layer through the second opening, and wherein the second contact electrode is electrically connected to the second semiconductor layer through the third opening.

[0017] The width of the organic pattern layer may be greater than the width of the light emitting element.

[0018] The organic pattern layer may overlap the inter-electrode planarizing layer, not overlap the bank, and directly contact the inter-electrode planarizing layer.

[0019] The display device may further include: a partition wall over the via layer, the first lead, and the second lead and defining a light emitting region; and a wavelength conversion layer in the light emitting region and filling the contact hole in the via layer.

[0020] The display device may further include a capping layer and a color filter layer sequentially over the wavelength conversion layer and the partition wall.

[0021] According to one or more embodiments, a method for manufacturing a display device includes: providing a substrate on which a first pad electrode and a second pad electrode are positioned; forming a dam over the substrate, the dam defining a first opening exposing at least a portion of the first pad electrode and at least a portion of the second pad electrode; forming an inter-electrode planarization layer over the substrate between the first pad electrode and the second pad electrode; forming a first reflective electrode extending from the dam to the inter-electrode planarization layer along the first pad electrode; forming a second reflective electrode extending from the dam to the inter-electrode planarization layer along the second pad electrode; applying an organic pattern material layer in the first opening; placing a light-emitting element on the organic pattern material layer; curing the organic pattern material layer to form an organic pattern layer, and bonding the light-emitting element to the organic pattern layer; forming a through-hole layer covering the light-emitting element and defining a contact hole; forming a first lead over the through-hole layer to electrically connect the first contact electrode and the first reflective electrode; and forming a second lead over the through-hole layer to electrically connect the second contact electrode and the second reflective electrode.

[0022] The forming of the bank and the forming of the inter-electrode planarization layer may include: coating an organic material layer over the substrate; and forming the bank and the inter-electrode planarization layer by etching the organic material layer using a mask.

[0023] The organic material layer may include a light blocking material.

[0024] Coating the organic material layer may include applying the organic material layer to the same thickness as the first pad electrode and the second pad electrode.

[0025] The method may further include performing a plasma descum process or an ashing process on a top surface of the bank and a top surface of the inter-electrode planarization layer to increase roughness of the top surface of the bank and the top surface of the inter-electrode planarization layer.

[0026] The light-emitting element may include a third semiconductor layer, a second semiconductor layer, an active layer and a first semiconductor layer stacked in sequence, wherein the light-emitting element includes an element insulation layer, wherein the element insulation layer surrounds the third semiconductor layer, the second semiconductor layer, the active layer, the side surfaces of the first semiconductor layer and the top surface of the light-emitting element, and defines a second opening and a third opening, wherein the first contact electrode is electrically connected to the first semiconductor layer through the second opening, and wherein the second contact electrode is electrically connected to the second semiconductor layer through the third opening.

[0027] The method may also include: forming a partition wall above the through-hole layer, the first lead and the second lead, and defining a light-emitting area; forming a wavelength conversion layer in the light-emitting area; and forming a capping layer and a color filter layer sequentially arranged above the partition wall and the wavelength conversion layer.

[0028] The display device according to one or more embodiments can solve the problem of residue that may occur between pad electrodes when forming a reflective electrode, and has a degree of freedom in selecting an etching chemical solution. Light leakage to the bottom of a light emitting element can be reduced or prevented.

[0029] However, the effects of the present disclosure are not limited to the aforementioned aspects, and various other aspects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0031] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments.

[0032] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0033] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more other embodiments.

[0034] Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments.

[0035] Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted.

[0036] Figure 8 It is a reference Figure 7 An enlarged view of the described light-emitting element.

[0037] Fig. 9is a schematic diagram showing a reference according to one or more other embodiments Figure 6 An enlarged view of the first light emitting region is depicted.

[0038] Fig.10 is a schematic diagram showing a reference according to one or more other embodiments Figure 6 An enlarged view of the first light emitting region is depicted.

[0039] Figures 11 to 26 is a diagram illustrating a method of manufacturing a display device according to one or more embodiments.

[0040] Fig. 27 is a diagram schematically showing a virtual reality device including a display device according to one or more embodiments;

[0041] Fig.28 is a diagram schematically showing a smart device including a display device according to one or more embodiments;

[0042] Fig.29 is a diagram schematically showing a vehicle including a display device according to one or more embodiments; and

[0043] Fig.30 is a diagram schematically showing a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0044] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for fully understanding the various aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0045] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and substitutions within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0046] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0047] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, differences from the shapes shown in the drawings due to, for example, manufacturing techniques and / or tolerances should be expected. In addition, the specific structural or functional descriptions disclosed herein are only exemplified for the purpose of describing the embodiments according to the concept of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers or regions shown, but should include deviations in shapes caused by, for example, manufacturing.

[0048] For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted region to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0049] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the elements described as being "below", "below" or "below" other elements or features will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first portion is described as being arranged "on" a second portion, this means that the first portion is arranged at the upper or lower side of the second portion, and is not limited to the upper side of the second portion based on the direction of gravity.

[0050] In addition, the phrase "in a plan view" means when the object portion is observed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross section taken by vertically cutting the object portion is observed from the side. The term "overlap" or "overlapped" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separated from" or "separated from" or "offset from" and any other suitable equivalents as will be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "facing" may mean that the first object may be directly opposite or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0051] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly coupled or directly connected or indirectly coupled or indirectly coupled as well as integrally coupled or integrally coupled or non-integrally coupled or non-integrally coupled. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, expressions of connection indicate electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component or directly on another component without intermediate components.

[0052] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the situation that the part is "directly under" another part, but also the situation that there is another part between the part and the other part. At the same time, other expressions describing the relationship between components such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0053] For the purposes of this disclosure, when expressions such as "at least one of" or "any one of" or "one or more of" are located after a list of elements, they modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, when expressions such as "at least one of...", "a plurality of", "one of..." and other prepositional phrases are located after / before a list of elements, they modify the entire list of elements and do not modify the individual elements in the list.

[0054] It will be understood that although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are used only to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer or first section described below can be referred to as the second element, second component, second area, second layer or second section. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used herein to distinguish elements of different categories or groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0055] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0056] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, as used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well. It will also be understood that the terms "comprises", "comprising", "have", "having", "includes" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0057] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or can be performed in the reverse order of the described order.

[0058] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms and not as terms of degree, and are intended to allow for the inherent deviations of measured or calculated values ​​that will be recognized by those of ordinary skill in the art. For example, "substantially" may include a range of +5% / -5% of the corresponding value. In view of the measurement discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the value and mean within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0060] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0061] refer to Figure 1 The display device 10 is a device for displaying a video or a still image, for example, a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC), and a display screen for various products such as a television, a notebook computer, a monitor, a billboard, and an Internet of Things (IOT) device.

[0062] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED). In the following, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, in the following, a micro light-emitting diode is referred to as a light-emitting element.

[0063] The display device 10 includes a display panel 100 , a display driving circuit 250 , and a circuit board 300 .

[0064] The display panel 100 may be formed as a plane having a rectangular shape with a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a curvature (e.g., a predetermined curvature), or may be formed at a right angle. The plane shape of the display panel 100 is not limited to a rectangle, and may be formed in other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 is formed at the left and right end portions, and may include a curved portion having a constant curvature or a varying curvature. In addition, the display panel 100 may be formed to be flexible, such as being formed to be able to be bent, curved, folded, or curled.

[0065] The display panel 100 may include a main area MA and a sub area SBA.

[0066] The main area MA may include a display area DA that displays an image and a non-display area NDA that is a peripheral area of ​​the display area DA. The display area DA may include a plurality of pixels that display an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0067] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The sub-region SBA is shown as being unfolded, but the sub-region SBA may be bent, and in this case, may be located on the bottom surface (e.g., below) of the display panel 100. When the sub-region SBA is bent, it may overlap the main region MA in the third direction DR3 that is the thickness direction of the display panel 100. The display driving circuit 250 may be located in the sub-region SBA.

[0068] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0069] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Thus, the circuit board 300 may be electrically connected to the display panel 100 and electrically connected to the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip on a film.

[0070] Figure 2 and Figure 3 is a plan view showing a display device according to one or more embodiments. Figure 3 It is shown that the sub-area SBA is bent.

[0071] refer to Figure 2 and Figure 3 , the display panel 100 may include a main area MA and a sub-area SBA.

[0072] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

[0073] The non-display area NDA may be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged to surround the display area DA (e.g., in a plan view). The non-display area NDA may be an edge area of ​​the display panel 100.

[0074] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 is located on one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 is located on the other side (e.g., the right side) of the display panel 100. However, the present disclosure is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal from the display driving circuit 250, may generate a scan signal according to the scan control signal, and may output the scan signal to the scan line.

[0075] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be less than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be less than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be located at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap with the main region MA in the third direction DR3.

[0076] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0077] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0078] The pad area PA is an area where the pad PD and the display driving circuit 250 are located. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may contact the bending area BA.

[0079] The bending area BA is a bent area. When the bending area BA is bent, the pad area PA may be located below the connection area CA and below the main area MA. The bending area BA may be located between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0080] Figure 4 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more embodiments.

[0081] refer to Figure 4 According to one or more embodiments, the first subpixel SPX1 may be connected to the scan lines GWL, GIL, GCL, and GBL, the emission line EL, and the data line DL. For example, the first subpixel SPX1 may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EL, and the data line DL.

[0082] The first subpixel SPX1 according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1 and a first light emitting element LE1. The switching element may include first, second, third, fourth, fifth, and sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0083] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0084] The first light emitting element LE1 may be a micro light emitting diode. The first light emitting element LE1 emits light according to the driving current. The amount of light emitted from the first light emitting element LE1 may be proportional to the driving current. The anode electrode of the first light emitting element LE1 may be connected to the first electrode of the fourth transistor ST4 and to the second electrode of the sixth transistor ST6, and the cathode electrode of the first light emitting element LE1 may be connected to the second power line VSL to which the second power voltage is applied.

[0085] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode may be connected to the first power line VDL.

[0086] like Figure 4 As shown in , the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may all be formed as p-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may be formed of polysilicon or an oxide semiconductor.

[0087] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. Because the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, when a scan signal or an emission signal of a gate low voltage is applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission line EL, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0088] Figure 5 is a circuit diagram illustrating a first sub-pixel of a display panel according to one or more other embodiments.

[0089] refer to Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of p-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as n-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as n-type MOSFETs may be formed of an oxide semiconductor. In this case, transistors formed of polysilicon and transistors formed of oxide semiconductors may be arranged in different layers.

[0090] Because the first transistor ST1 and the third transistor ST3 are formed as n-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal having a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as p-type MOSFETs, and thus can be turned on when a scan signal having a gate low voltage and an emission signal are applied to the write scan line GWL, the bias scan line GBL, and the emission line EL, respectively.

[0091] Optionally, Figure 4 The fourth transistor ST4 in the embodiment may be formed by an n-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an n-type MOSFET, when a bias scan signal of a gate high voltage is applied to the bias scan line GBL, the fourth transistor ST4 may be turned on.

[0092] Alternatively, in one or more embodiments, the first transistor ST1 , the second transistor ST2 , the third transistor ST3 , the fourth transistor ST4 , the fifth transistor ST5 , and the sixth transistor ST6 and the driving transistor DT may all be formed as n-type MOSFETs.

[0093] Meanwhile, the circuit diagram of the second sub-pixel and the third sub-pixel according to one or more embodiments is combined with Figure 4 and Figure 5 The circuit diagram of the first sub-pixel SPX1 described is substantially the same, and thus a description thereof will be omitted.

[0094] Figure 6 is a schematic cross-sectional view of a display device according to one or more embodiments. Figure 7 is schematically shown with reference to Figure 6 An enlarged view of the first light emitting region is depicted. Figure 8 It is a reference Figure 7 An enlarged view of the described light-emitting element.

[0095] refer to Figure 6 and Figure 8 , the display device 10 may include a substrate 110 , a light emitting element portion LEP, a wavelength controller 200 , and a color filter layer CFL.

[0096] The substrate 110 may be an insulating substrate. The substrate 110 may include a transparent material. For example, the substrate 110 may include a transparent insulating material such as glass, quartz, etc. The substrate 110 may be a rigid substrate. However, the substrate 110 is not limited thereto and may include a plastic such as polyimide, etc. In addition, the substrate 110 may have a flexible property that allows it to bend, bend, fold, or curl. A plurality of light emitting areas EA1, EA2, and EA3 and a non-emitting area NEA may be defined on the substrate 110.

[0097] The switching elements T1, T2, and T3 may be located on the substrate 110. In one or more embodiments, the first switching element T1 may be located in the first light emitting area EA1 of the substrate 110, the second switching element T2 may be located in the second light emitting area EA2, and the third switching element T3 may be located in the third light emitting area EA3. However, the present disclosure is not limited thereto, and in other embodiments, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be located in the non-emission area NEA.

[0098] In one or more embodiments, the first switching element T1, the second switching element T2, and the third switching element T3 may each be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In one or more embodiments, there may be a plurality of signal lines (e.g., gate lines, data lines, power lines, etc.) further located on the substrate 110 to transmit signals to each switching element.

[0099] Each of the switching elements T1 , T2 , and T3 may include a semiconductor layer 65 , a gate electrode 75 , a source electrode 85 a , and a drain electrode 85 b .

[0100] For example, the buffer layer 60 may be located on the substrate 110. The buffer layer 60 may cover the front side of the substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be a single layer or a double layer of silicon nitride, silicon oxide, or silicon oxynitride.

[0101] The semiconductor layer 65 may be located on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, and T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In one example, the oxide semiconductor may include, for example, a binary compound (AB) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z In one or more embodiments, the semiconductor layer 65 may include indium tin zinc oxide (IGZO).

[0102] The gate insulating layer 70 may be located on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound, a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In one or more embodiments, the gate insulating layer 70 may include silicon oxide.

[0103] The gate electrode 75 may be located on the gate insulating layer 70. The gate electrode 75 may overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, In 2 O 3 The gate electrode 75 may be formed of a metal oxide or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) or nickel (Ni). For example, the gate electrode 75 may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0104] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be located on the gate electrode 75. The first interlayer insulating layer 80 may be directly located on the gate electrode 75, and the second interlayer insulating layer 82 may be directly located on the first interlayer insulating layer 80. The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may each include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, zinc oxide, etc. However, it is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the lower step. Two interlayer insulating layers (the first interlayer insulating layer 80 and the second interlayer insulating layer 82) are shown and described, but the present disclosure is not limited thereto, and only one interlayer insulating layer may be located.

[0105] The source electrode 85a and the drain electrode 85b may be located on the first interlayer insulating layer 80. The source electrode 85a and the drain electrode 85b may be connected to the semiconductor layer 65 through corresponding contact holes penetrating the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70. The source electrode 85a and the drain electrode 85b may include a semiconductor material such as ITO, IZO, ITZO, In 2 O 3 The source electrode 85a and the drain electrode 85b may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg) and / or nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be formed of a Cu / Ti double layer in which an upper layer of copper is stacked on a lower layer of titanium, but is not limited thereto.

[0106] The first planarization layer 120 may be located on the first switching element T1, on the second switching element T2, and on the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic-based resin, an epoxy-based resin, an imide-based resin, an ester-based resin, etc. In one or more embodiments, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0107] The pixel connection electrode 123 may be located on the first planarization layer 120. The pixel connection electrode 123 corresponds to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 123 may connect the pixel electrode to the above-mentioned switching elements T1, T2, and T3. The pixel connection electrode 123 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0108] A protective layer 125 may be formed on the first planarization layer 120 and the pixel connection electrode 123. The protective layer 125 may be formed of an inorganic film such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The protective layer 125 may be omitted.

[0109] The second planarization layer 130 may be located on the protection layer 125. The second planarization layer 130 flattens a lower height difference, and may include the same material as the first planarization layer 120 described above.

[0110] The light emitting element part LEP may be located on the second planarization layer 130. The light emitting element part LEP may include a first pad electrode APD, a second pad electrode CPD, an inter-electrode planarization layer PFL, a reflective electrode SCT, a bank PDL, an organic pattern layer BOL, a plurality of light emitting elements LE, a via layer VIA, and a lead LDL.

[0111] The first pad electrode APD may be provided with a first power supply voltage as a low potential voltage. For example, the first pad electrode APD may be a cathode electrode, but is not limited thereto. The second pad electrode CPD may be directly connected to the pixel connection electrode 123 through a contact hole penetrating the second planarization layer 130, and may be electrically connected to each of the switching elements T1, T2, and T3 through the pixel connection electrode 123. The second pad electrode CPD may be an anode electrode. The first pad electrode APD and the second pad electrode CPD may be formed as a single layer or multiple layers of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and alloys thereof. In some embodiments, the first pad electrode APD and the second pad electrode CPD may have a two-layer structure of Ti / Al or a three-layer structure of Ti / Al / Ti.

[0112] The first pad electrode APD and the second pad electrode CPD may be arranged to be spaced apart from each other on the same plane, and may be arranged to protrude outward from the light emitting element LE. The first pad electrode APD and the second pad electrode CPD may be arranged to be spaced apart by a first separation distance D1. The first separation distance D1 may be about 4 μm to about 6 μm. The height H1 of the first pad electrode APD and the second pad electrode CPD may be about to about

[0113] The inter-electrode planarization layer PFL may be located (eg, in a plan view) between the first pad electrode APD and the second pad electrode CPD. Figure 7 As shown in , the width D2 of the inter-electrode planarization layer PFL (e.g., in a plan view) may be the same as the first separation distance D1 between the first pad electrode APD and the second pad electrode CPD. Therefore, the width D2 of the inter-electrode planarization layer PFL may be about 4 μm to 6 μm. The height (e.g., thickness) H2 of the inter-electrode planarization layer PFL may be the same as the height (e.g., thickness) H1 of the first pad electrode APD and the second pad electrode CPD. The height H2 of the inter-electrode planarization layer PFL may be about to about Meanwhile, the height H2 of the inter-electrode planarization layer PFL may be the same as the height (eg, thickness) H3 of the bank PDL. Therefore, the height H3 of the bank PDL may be approximately to about

[0114] The inter-electrode planarization layer PFL may overlap the light emitting element LE in the thickness direction.

[0115] The inter-electrode planarization layer PFL is formed of an organic film such as an acrylic-based resin, an epoxy-based resin, a phenol-based resin, a polyamide-based resin, a polyimide-based resin, etc. The inter-electrode planarization layer PFL may further include a light blocking material, and the light blocking material may include a dye or a pigment having a light blocking property.

[0116] The embankment PDL may be located on the second planarization layer 130, the first pad electrode APD, and the second pad electrode CPD. The embankment PDL is not formed to cover both the first pad electrode APD and the second pad electrode CPD. The embankment PDL may include / define an opening to expose at least a portion of the first pad electrode APD and at least a portion of the second pad electrode CPD through the opening. The embankment PDL may cover the edges of the first pad electrode APD and the second pad electrode CPD. The embankment PDL may include an inclined portion overlapping the edges of the first pad electrode APD and the second pad electrode CPD and having a slope (e.g., a predetermined slope), and may also include a flat portion extending from the inclined portion and having a flat plane.

[0117] The bank PDL may be formed in a spaced-apart region between a pair of adjacent first and second pad electrodes APD and CPD formed on the second planarization layer 130 .

[0118] The bank PDL may be formed of the same material as the inter-electrode planarization layer PFL. The bank PDL may be formed of an organic film such as an acrylic-based resin, an epoxy-based resin, a phenolic-based resin, a polyamide-based resin, a polyimide-based resin, etc. The inter-electrode planarization layer PFL may further include a light blocking material, which may include a dye or pigment having a shielding property.

[0119] The reflective electrode SCT may be located on the bank PDL, the first pad electrode APD, and the second pad electrode CPD. The reflective electrode SCT may include a first reflective electrode SCT1 and a second reflective electrode SCT2. For example, the first reflective electrode SCT1 is located on the first pad electrode APD, and the first pad electrode APD and the first reflective electrode SCT1 are electrically connected to each other because they are formed of a conductive material. The second reflective electrode SCT2 is located on the second pad electrode CPD, and the second pad electrode CPD and the second reflective electrode SCT2 are electrically connected to each other because they are formed of a conductive material. The first reflective electrode SCT1 and the second reflective electrode SCT2 are arranged to be spaced apart from each other, and each end of the first reflective electrode SCT1 and the second reflective electrode SCT2 may be located on the top surface of the bank PDL along the bank PDL. One end of each of the first reflective electrode SCT1 and the second reflective electrode SCT2 may be located on a planar portion of the bank PDL. Therefore, the reflective electrode SCT may have a step caused by the bank PDL. The other ends of the first reflective electrode SCT1 and the second reflective electrode SCT2 may be located on the inter-electrode planarization layer PFL. The other ends of the first reflective electrode SCT1 and the second reflective electrode SCT2 may be spaced apart from each other on the inter-electrode planarization layer PFL.

[0120] The reflective electrode SCT may include a metal material having a high reflectivity to light. For example, the reflective electrode SCT may include aluminum or silver, or may be an alloy of aluminum or silver. The reflective electrode SCT may be formed as a single layer, but may also be formed as a multilayer. For example, the reflective electrode SCT may be formed of a multilayer structure of ITO / Ag / ITO. The ITO / Ag / ITO of the reflective electrode SCT may be formed to be approximately / about / about The thickness may be, but not limited to, .

[0121] The organic pattern layer BOL may be located in the opening of the bank PDL. The organic pattern layer BOL may be located on the reflective electrode SCT and the inter-electrode planarization layer PFL. The organic pattern layer BOL may overlap at least a portion of the first pad electrode APD and at least a portion of the second pad electrode CPD.

[0122] The organic pattern layer BOL may be positioned in each emission area EA1, EA2, and EA3 in an island pattern shape. For example, the organic pattern layer BOL located in each emission area EA1, EA2, and EA3 may be arranged to be spaced apart from the organic pattern layer BOL located in the adjacent emission areas EA1, EA2, and EA3.

[0123] The thickness of the plurality of organic pattern layers BOL may be the same as or thicker than the thickness of the bank PDL. For example, the thickness of the organic pattern layer BOL may be about 1.5 μm to about 2.1 μm, but is not limited thereto. The width W of the organic pattern layer BOL may be about 1.5 μm to about 2.1 μm. BOL It can be formed to be larger than the width W of the light emitting element LE. LE Wide, but not limited to this.

[0124] The organic pattern layer BOL may include an organic material. For example, the organic material may be, but is not limited to, a photosensitive organic insulating material. In addition, the organic material may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin. The organic pattern layer BOL may be formed by various methods such as an organic imprinting method, an inkjet printing method, an electrospraying method, or a stamping method.

[0125] In a high-resolution display panel, such as the display device 10 in one or more embodiments, it is difficult to replace the organic pattern layer BOL with an anisotropic conductive film (ACF).

[0126] The light emitting element LE may be located on the organic pattern layer BOL. The light emitting element LE may be an inorganic light emitting element made of an inorganic material such as GaN.

[0127] The light emitting element LE may be located in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3. The light emitting element LE is a lateral light emitting element, so that the length of the first direction DR1, the length of the second direction DR2, and the length of the third direction DR3 may each be from several micrometers to hundreds of micrometers. For example, the light emitting element LE may be about 10 μm×25 μm, but is not limited thereto. The thickness of the light emitting element LE may be about 5.5 μm, but is not limited thereto.

[0128] refer to Figure 8The light emitting element LE may be a light emitting structure including a third semiconductor layer SEM3, a second semiconductor layer SEM2, an active layer MQW, a first semiconductor layer SEM1, a transparent conductive layer TCO, a first contact electrode CTE1, and a second contact electrode CTE2.

[0129] The third semiconductor layer SEM3 may include an undoped semiconductor and may be a material that is not doped to n-type or p-type. In one or more embodiments, the material of the third semiconductor layer SEM3 may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0130] The second semiconductor layer SEM2 may be located on the third semiconductor layer SEM3. The second semiconductor layer SEM2 may be doped with a second conductive dopant such as Si, Ge, Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be about 500 nm to about 1 μm.

[0131] The active layer MQW may be located on the second semiconductor layer SEM2. The active layer MQW may emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength range of about 450 nm to about 495 nm, that is, light in a blue wavelength band.

[0132] The active layer MQW may include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. The thickness of the well layer may be about 1 nm to about 4 nm, and the thickness of the barrier layer may be about 3 nm to about 10 nm.

[0133] Alternatively, the active layer MQW may have a structure in which a semiconductor material having a high band gap energy and a semiconductor material having a low band gap energy are alternately stacked with each other, and may include other group III to group V semiconductor materials according to the wavelength range of the emitted light. The light emitted from the active layer MQW is not limited to the first light (light in the blue wavelength band), and in some cases the second light (light in the green wavelength band) or the third light (light in the red wavelength band) may be emitted. The thickness of the active layer MQW may be about 10 nm to about 25 nm.

[0134] The first semiconductor layer SEM1 may be doped with a first conductive dopant such as Mg, Zn, Ca, Se, or Ba. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The first semiconductor layer SEM1 may have a thickness of about 30 nm to about 200 nm.

[0135] In one or more other embodiments, a superlattice layer may be further included between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for alleviating stress between the second semiconductor layer SEM2 and the active layer MQW. The superlattice layer may be formed of InGaN or GaN. In addition, an electron blocking layer may be further included between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer that reduces or prevents the possibility of too many electrons flowing into the active layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be about 10 nm to about 50 nm. The electron blocking layer may be omitted.

[0136] The transparent conductive layer TCO may be located on the lower surface of the first semiconductor layer SEM1. The transparent conductive layer TCO may be in direct contact with the first semiconductor layer SEM1. The transparent conductive layer TCO may be formed to be transparent to emit light. The transparent conductive layer TCO may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO). The transparent conductive layer TCO may be omitted.

[0137] The element insulating layer INSO may surround the side surfaces of the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1 and the transparent conductive layer TCO and the top surface of the transparent conductive layer TCO. The element insulating layer INSO has or is defined with two openings. For example, the element insulating layer INSO includes a first opening OP-L1 and a second opening OP-L2. The element insulating layer INSO may include a silicon compound, a metal oxide, and the like. For example, the element insulating layer INSO may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, and the like.

[0138] The first contact electrode CTE1 and the second contact electrode CTE2 are respectively located on the two openings. For example, the first contact electrode CTE1 may be located on the first opening OP-L1 and may contact the first semiconductor layer SEM1. The second contact electrode CTE2 may be located on the second opening OP-L2 and may contact the second semiconductor layer SEM2. To this end, the second opening OP-L2 may expose the second semiconductor layer SEM2. The second opening OP-L2 may have a diameter wider than the first opening OP-L1.

[0139] The element insulating layer INSO may cover side surfaces of the recesses defined by the second openings OP-L2 or defining the second openings OP-L2.

[0140] Since the first and second contact electrodes CTE1 and CTE2 are located on the top surface of the light emitting element LE, they may be transparent electrodes. For example, the first and second contact electrodes CTE1 and CTE2 may be formed of transparent conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0141] refer to Figure 7 The via layer VIA may support the lead LDL connecting the first contact electrode CTE1 and the second contact electrode CTE2 to the first reflective electrode SCT1 and the second reflective electrode SCT2, respectively, and flatten the step formed by the light emitting element LE. The via layer VIA may include an organic insulating material. For example, the via layer VIA may include an acrylic-based resin, an epoxy-based resin, an imide-based resin, an ester-based resin, etc. The lead LDL may include a first lead LDL1 and a second lead LDL2. The via layer VIA may be formed to be higher than the height of the light emitting element LE, but is not limited thereto.

[0142] refer to Figure 7 , the via layer VIA may include or define a plurality of contact holes. For example, the via layer VIA may include a first contact hole CH1 for connecting the first contact electrode CTE1 and the first lead LDL1, a second contact hole CH2 for connecting the first lead LDL1 to the first reflective electrode SCT1, a third contact hole CH3 for connecting the second contact electrode CTE2 to the second lead LDL2, and a fourth contact hole CH4 for connecting the second lead LDL2 to the second reflective electrode SCT2.

[0143] refer to Figure 6 , the wavelength controller 200 may be located on the light emitting element part LEP.

[0144] The wavelength controller 200 may include a partition wall PW and a wavelength conversion layer QDL.

[0145] The partition wall PW is arranged to extend in the first direction DR1 and in the second direction DR2 and may be formed in a lattice pattern throughout the display area DA. In addition, the partition wall PW may not overlap the plurality of light emitting areas EA1, EA2, and EA3 and may overlap the non-emission area NEA.

[0146] The partition wall PW may be used to provide space for the wavelength conversion layer QDL to be formed. The partition wall PW may have a relatively large thickness to provide space for the wavelength conversion layer QDL to be formed. For example, the partition wall PW may include an organic insulating material so that the partition wall PW may be made thick. The organic insulating material may include, for example, an epoxy-based resin, an acrylic-based resin, a cardo-based resin, an imide-based resin, and the like.

[0147] In one or more embodiments, the partition wall PW may block the transmission of light in the non-emitting area NEA. The partition wall PW may also include a light blocking material, and may include a dye or pigment having a light blocking property. For example, the partition wall PW may be a black matrix. External light incident from outside the display device 10 may cause the problem of distorting the color gamut of the wavelength controller 200. The partition wall PW including the light blocking material is located in the wavelength controller 200 so that at least a portion of the external light is absorbed by the light blocking material. Therefore, the color distortion caused by the reflection of external light can be reduced. In addition, the partition wall PW including the light blocking material can reduce or prevent light from intruding between adjacent light emitting areas and causing color mixing, thereby further improving the color reproduction rate.

[0148] The wavelength conversion layer QDL can convert or shift the peak wavelength of the incident light into another corresponding peak wavelength of light, and can emit the light. The wavelength conversion layer QDL can convert the blue first light emitted from the light emitting element LE into red second light or green third light, or can transmit the blue first light as it is.

[0149] The wavelength conversion layer QDL may be located in each of the light emitting areas EA1, EA2, and EA3 divided by the partition wall PW, and may be spaced apart from each other. That is, the wavelength conversion layer QDL may be formed into an island pattern spaced apart from each other. The wavelength conversion layer QDL may overlap the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively. In one or more embodiments, the wavelength conversion layer QDL may completely overlap the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, respectively.

[0150] The wavelength conversion layer QDL includes a first wavelength conversion pattern WCL1 overlapping the first light emitting area EA1 , a second wavelength conversion pattern WCL2 overlapping the second light emitting area EA2 , and a light transmitting pattern TPL overlapping the third light emitting area EA3 .

[0151] The first wavelength conversion pattern WCL1 may overlap the first light emitting area EA1. The first wavelength conversion pattern WCL1 may convert or shift the peak wavelength of the incident light into light of another corresponding peak wavelength and may emit the light. In one or more embodiments, the first wavelength conversion pattern WCL1 may convert the blue first light emitted from the light emitting element LE of the first light emitting area EA1 into a second light which is red light having a single peak wavelength in the range of about 610 nm to about 650 nm and emit the second light.

[0152] The first wavelength conversion pattern WCL1 may include a first base resin BRS1, first wavelength conversion particles WCP1, and scatterers SCP. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a cardo-based resin, or an imide-based resin.

[0153] The first wavelength conversion particle WCP1 may convert the first light incident from the light emitting element LE into the second light. For example, the first wavelength conversion particle WCP1 may convert the light in the blue wavelength band into the light in the red wavelength band. The first wavelength conversion particle WCP1 may be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot may be a particle material that emits light of a corresponding color when an electron transitions from a conduction band to a valence band.

[0154] Quantum dots can be semiconductor nanocrystal materials. Depending on the quantum dot composition and size, the quantum dot can have a corresponding band gap to absorb light and can emit light with a unique wavelength. Examples of semiconductor nanocrystals of quantum dots include group IV element and compound nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof.

[0155] The II-VI compound is a binary compound selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS or a mixture thereof; a binary compound selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnP, CdZnS, CdZnSe, CdZnS ... A ternary compound selected from the group consisting of CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS or a mixture thereof; and / or a quaternary compound selected from the group consisting of CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe or a mixture thereof.

[0156] The III-V compound is a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or a mixture thereof; a ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb or a mixture thereof; and / or a quaternary compound selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb or a mixture thereof.

[0157] The IV-VI compound may be selected from the group consisting of binary compounds, ternary compounds and / or quaternary compounds, wherein the binary compound is selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe or a mixture thereof, the ternary compound is selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe or a mixture thereof, and the quaternary compound is selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe or a mixture thereof. The IV group element may be selected from the group consisting of Si, Ge or a mixture thereof. The IV group compound may be a binary compound selected from the group consisting of SiC, SiGe or a mixture thereof.

[0158] The binary, ternary or quaternary compound may be present in a particle at a uniform concentration, or may be present in the same particle at a partially different concentration distribution. The quantum dot may also have a core-shell structure in which one quantum dot surrounds another quantum dot. The interface of the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0159] In one or more embodiments, the quantum dot may have a core-shell structure comprising a core comprising a nanocrystal as described above and a shell surrounding the core. The shell of the quantum dot may be used as a protective layer to reduce or prevent chemical denaturation of the core, thereby maintaining semiconductor properties, and / or as a charge layer to impart electrophoretic properties to the quantum dot. The shell may be monolayer or multilayer. Examples of shells for quantum dots include metal or nonmetal oxides, semiconductor compounds, or combinations thereof.

[0160] For example, metal or nonmetal oxides can be formed by using materials such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 , NiO or binary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 、CoMn2 O 4 The ternary compound is exemplified, but the present disclosure is not limited thereto.

[0161] In addition, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but is not limited thereto.

[0162] The second wavelength conversion pattern WCL2 may overlap the second light emitting area EA2. The second wavelength conversion pattern WCL2 may emit light by converting or shifting the peak wavelength of the incident light into light of another corresponding peak wavelength. In one or more embodiments, the second wavelength conversion pattern WCL2 converts the blue first light emitted from the light emitting element LE of the second light emitting area EA2 into a green third light having a peak wavelength in the range of about 510 nm to about 550 nm, and may emit the green third light.

[0163] The second wavelength conversion pattern WCL2 may include a second base resin BRS2, ​​and may include second wavelength conversion particles WCP2 and scatterers SCP dispersed in the second base resin BRS2.

[0164] The second base resin BRS2 may be made of a material having high light transmittance, may be made of the same material as the first base resin BRS1, or may include at least one of the materials exemplified as constituent materials of the first base resin BRS1.

[0165] The second wavelength conversion particles WCP2 can convert or shift the peak wavelength of the incident light into another corresponding peak wavelength. In one or more embodiments, the second wavelength conversion particles WCP2 can convert the blue first light provided from the light emitting element LE into a green third light having a peak wavelength in the range of about 510nm to about 550nm, and can emit the green third light. Examples of the second wavelength conversion particles WCP2 include quantum dots, quantum rods, or phosphors. A more thorough description of the second wavelength conversion particles WCP2 is substantially the same or similar to those described above in the description of the first wavelength conversion particles WCP1, and will be omitted.

[0166] The light-transmitting pattern TPL may be arranged to overlap the third light-emitting area EA3. The light-transmitting pattern TPL may transmit incident light. The light-transmitting pattern TPL may directly transmit the blue first light emitted from the light-emitting element LE located in the third light-emitting area EA3. The light-transmitting pattern TPL may include a third base resin BRS3 and a scatterer SCP dispersed in the third base resin BRS3. Since the third base resin BRS3 is substantially the same as or similar to the above-mentioned first base resin BRS1, its description will be omitted.

[0167] The wavelength controller 200 may further include a capping layer CAP. The capping layer CAP may be located on the wavelength conversion layer QDL and the partition wall PW. The capping layer CAP may include an inorganic material. For example, the capping layer CAP may include at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxide. Meanwhile, the accompanying drawings show that the capping layer CAP is formed as a single layer, but the present disclosure is not limited thereto. For example, the capping layer CAP may be formed by alternating multiple layers of inorganic layers including at least one of the materials that the capping layer CAP may include. The thickness of the capping layer CAP may range from about 0.05 μm to about 2 μm, but is not limited thereto.

[0168] Meanwhile, a color filter layer CFL may be positioned on the wavelength controller 200. The color filter layer CFL may include a first overcoat layer OC1, a first color filter CF1, a second color filter CF2, a third color filter CF3, and a second overcoat layer OC2.

[0169] The first overcoat layer OC1 may be located on the wavelength controller 200. The first overcoat layer OC1 may be located directly on the capping layer CAP of the wavelength controller 200. The first overcoat layer OC1 may be located entirely above the display area DA and may have a flat surface. The first overcoat layer OC1 may flatten a step formed by the lower wavelength controller 200 to facilitate formation of the color filter layer CFL.

[0170] The first overcoat layer OC1 may include a light-transmitting organic material. For example, the first overcoat layer OC1 may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0171] First, second, and third color filters CF1, CF2, and CF3 may be located on the first overcoat layer OC1. The first color filter CF1 may be located in the first emission area EA1, the second color filter CF2 may be located in the second emission area EA2, and the third color filter CF3 may be located in the third emission area EA3.

[0172] The first color filter CF1, the second color filter CF2, and the third color filter CF3 may include a colorant such as a dye or a pigment that absorbs wavelengths other than the wavelengths of the corresponding colors. The first color filter CF1 may selectively transmit the second light (e.g., red light), and may block or absorb the first light (e.g., blue light) and the third light (e.g., green light). The second color filter CF2 may selectively transmit the third light (e.g., green light), and may block or absorb the first light (e.g., blue light) and the second light (e.g., red light). The third color filter CF3 may selectively transmit the first light (e.g., blue light), and may block or absorb the second light (e.g., red light) and the third light (e.g., green light). For example, the first color filter CF1 may be a red color filter, the second color filter CF2 may be a green color filter, and the third color filter CF3 may be a blue color filter.

[0173] In one or more embodiments, the light incident on the first color filter CF1 may be light converted into the second light in the first wavelength conversion pattern WCL1, the light incident on the second color filter CF2 may be light converted into the third light in the second wavelength conversion pattern WCL2, and the light incident on the third color filter CF3 may be the first light transmitted through the light-transmitting pattern TPL. As a result, the second light transmitted through the first color filter CF1, the third light transmitted through the second color filter CF2, and the first light transmitted through the third color filter CF3 may be emitted to the top of the substrate 110 to achieve full color.

[0174] The first color filter CF1, the second color filter CF2, and the third color filter CF3 can absorb a portion of light entering from the outside of the display device 10 to reduce reflected light caused by the external light. Therefore, the first color filter CF1, the second color filter CF2, and the third color filter CF3 can reduce or prevent color distortion caused by reflection of external light.

[0175] The plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be (for example, respectively) larger than the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3. For example, the first color filter CF1 may be larger than the plane area of ​​the first light-emitting region EA1. The second color filter CF2 may be larger than the plane area of ​​the second light-emitting region EA2. The third color filter CF3 may be larger than the plane area of ​​the third light-emitting region EA3. However, the present disclosure is not limited thereto, and the plane area of ​​each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be (for example, respectively) equal to the plane area of ​​each of the plurality of light-emitting regions EA1, EA2, and EA3.

[0176] The second overcoat layer OC2 may be located in the color filter layer CFL. The second overcoat layer OC2 may be located directly on the color filter layer CFL. The second overcoat layer OC2 may be located entirely in the display area DA and may have a flat surface. The second overcoat layer OC2 may flatten a step formed by the color filter layer CFL therebelow. The second overcoat layer OC2 may include a light-transmitting organic material and may be substantially the same as or similar to the first overcoat layer OC1 described above.

[0177] The display device 10 according to one or more embodiments may reduce or prevent the possibility that the first reflective electrode SCT1 and the second reflective electrode SCT2 are connected by forming an inter-electrode planarization layer PFL between the first pad electrode APD and the second pad electrode CPD.

[0178] In addition, by forming the inter-electrode planarization layer PFL including a light blocking material between the first pad electrode APD and the second pad electrode CPD, it is possible to block light from traveling to the light emitting element LE.

[0179] Furthermore, by forming the inter-electrode planarization layer PFL including a light blocking material between the first pad electrode APD and the second pad electrode CPD, it is possible to block the advancement of light toward the light emitting element LE.

[0180] In addition, the residue problem that may occur between the pad electrodes during wet etching can be solved to ensure the separation distance between the first reflective electrode SCT1 and the second reflective electrode SCT2. In addition, the first pad electrode APD and the second pad electrode CPD are less likely to be exposed to the etching solution, so there is no risk of Ag residue. In addition, there is a degree of freedom in the selection of the etchant. For reference, if the first pad electrode APD and the second pad electrode CPD contain aluminum, there may be a problem that if aluminum is exposed to the etchant, Ag residue may be caused on the surface due to the galvanic phenomenon.

[0181] Fig. 9 is a schematic diagram showing a reference according to one or more other embodiments Figure 6 An enlarged view of the first light emitting region is depicted.

[0182] refer to Fig. 9 , one or more embodiments corresponding to Figure 7 One or more embodiments may be different in that the inter-electrode planarization layer PFL protrudes above the top surfaces of the first pad electrode APD and the second pad electrode CPD. Hereinafter, descriptions overlapping with the above will be omitted, and the differences will be described.

[0183] The first pad electrode APD and the second pad electrode CPD are arranged to be spaced apart from each other. The first pad electrode APD and the second pad electrode CPD may be arranged to be spaced apart by a first separation distance D1. The first separation distance D1 may be about 4 μm to about 6 μm. The height H1 of the first pad electrode APD and the second pad electrode CPD may be about to about

[0184] The inter-electrode planarization layer PFL may be located between the first pad electrode APD and the second pad electrode CPD. The inter-electrode planarization layer PFL may fill the space between the first pad electrode APD and the second pad electrode CPD. The lower width D2 of the inter-electrode planarization layer PFL (e.g., the width of the lower portion of the inter-electrode planarization layer PFL) may be equal to the first separation distance D1 between the first pad electrode APD and the second pad electrode CPD. The height (e.g., thickness) H2 of the inter-electrode planarization layer PFL may be higher than the height (thickness) H1 of the first pad electrode APD and the second pad electrode CPD. The height H2 of the inter-electrode planarization layer PFL may be approximately to about Meanwhile, the height H2 of the inter-electrode planarization layer PFL may be equal to the height (eg, thickness) H3 of the bank PDL. Therefore, the height H3 of the bank PDL may be approximately to about

[0185] The inter-electrode planarization layer PFL may cover at least a portion of the first pad electrode APD and at least a portion of the second pad electrode CPD. The first reflective electrode SCT1 may cover a portion of the inter-electrode planarization layer PFL, a portion of the first pad electrode APD, and a portion of the bank PDL. The second reflective electrode SCT2 may cover a portion of the inter-electrode planarization layer PFL, a portion of the second pad electrode CPD, and a portion of the bank PDL. The first reflective electrode SCT1 and the second reflective electrode SCT2 are arranged to be spaced apart from each other on the inter-electrode planarization layer PFL.

[0186] The organic pattern layer BOL may be located on the reflective electrode SCT and on the inter-electrode planarization layer PFL located in the opening of the bank PDL.

[0187] and Figure 7 Compared with the inter-electrode planarization layer PFL, Fig. 9The inter-electrode planarization layer PFL is formed to be higher (e.g., thicker) than a height H1 of the first pad electrode APD and the second pad electrode CPD, so that the inter-electrode planarization layer PFL can protrude above the first pad electrode APD and the second pad electrode CPD. In this way, when the inter-electrode planarization layer PFL protrudes above the first pad electrode APD and the second pad electrode CPD, the contact surface with the organic pattern layer BOL becomes wider, and adhesion between the organic pattern layer BOL and the underlying layer can be improved.

[0188] Fig.10 is a schematic diagram showing a reference according to one or more other embodiments Figure 6 An enlarged view of the first light emitting region is depicted.

[0189] refer to Fig.10 , which corresponds to Fig. 9 One or more embodiments of the present invention are different in that the roughness of the top surfaces of the inter-electrode planarization layer PFL and the bank PDL is increased to make the contact surface with the organic pattern layer BOL wider. Hereinafter, the description overlapping with the above content will be omitted, and the difference will be described.

[0190] In such Fig. 9 After forming the inter-electrode planarization layer PFL and the bank PDL as shown in , a plasma pretreatment (descum) process or an ashing process may be added. These processes may increase the surface roughness of the top surfaces of the PFL and PDL, resulting in a larger contact area with the organic pattern layer BOL. The inter-electrode planarization layer PFL and the bank PDL may have a roughness of the top surface greater than that of the bottom surface.

[0191] Figures 11 to 26 is a diagram illustrating a method of manufacturing a display device according to one or more embodiments.

[0192] Figures 11 to 26 The cross-sectional views each show the structure of each layer of the display device 10 in the order of formation. Figures 11 to 26 It mainly shows that it can roughly correspond to Figure 7 FIG. 1 is a cross-sectional view of a manufacturing process of a light emitting element portion LEP. In addition, the following will focus on the first light emitting area EA1 of the display device 10.

[0193] First, refer to Figures 11 to 16 , a plurality of light emitting elements LE are formed on the base substrate BSUB.

[0194] For example, a base substrate BSUB is prepared. The base substrate BSUB may be sapphire (Al 2 O 3) substrate or a silicon wafer including silicon. However, the present disclosure is not limited thereto, and in one or more embodiments, a case where the base substrate BSUB is a sapphire substrate will be described as an example.

[0195] A plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L are formed on a base substrate BSUB. A plurality of semiconductor material layers grown by an epitaxial method can be formed by growing seed crystals. Methods for forming semiconductor material layers include electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal organic chemical vapor deposition (MOCVD), etc., and are preferably formed by metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto.

[0196] The precursor material(s) used to form the plurality of semiconductor material layers are not particularly limited to the range that can be conventionally selected for forming the target material. In one example, the precursor material may be a metal precursor including an alkyl group such as a methyl or ethyl group. For example, it may be a precursor such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), triethyl phosphate ((C 2 H 5 ) 3 PO 4 ) compounds, but not limited thereto.

[0197] For example, a third semiconductor material layer SEM3L is formed on the base substrate BSUB. Although the drawings show a third semiconductor material layer SEM3L that is further stacked, the present disclosure is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer SEM3L may reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer SEM3L may include an undoped semiconductor that may be an n-type or p-type undoped material. In one or more embodiments, the third semiconductor material layer SEM3L may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, or InN, but is not limited thereto.

[0198] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L by using the above method.

[0199] Then, a transparent conductive material layer TCOL is formed on the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. The transparent conductive material layer TCOL may cover all of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L. The transparent conductive material layer TCOL may be formed of a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0200] Next, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, SEM1L and the transparent conductive material layer TCOL are etched.

[0201] For example, a plurality of first mask patterns MP1 are formed on the transparent conductive material layer TCOL. The first mask pattern MP1 may be a hard mask including an inorganic material or a photoresist mask including an organic material. The first mask pattern MP1 reduces or prevents etching of the lower plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the transparent conductive material layer TCOL. Then, the plurality of first mask patterns MP1 are used as masks to etch (first etching) a portion of the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the transparent conductive material layer TCOL.

[0202] like Fig.12 As shown in , on the base substrate BSUB, the plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the transparent conductive material layer TCOL not overlapping with the first mask pattern MP1 may be etched and removed, and the unetched portions overlapping with the first mask pattern MP1 may be formed into a plurality of light emitting elements LE.

[0203] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the reflective material layer may be etched by conventional methods. For example, the process of etching the plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L and the transparent conductive material layer TCOL may be performed by a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method. In the case of a dry etching method, anisotropic etching that may be applicable to vertical etching is possible. When the above etching method is used, the etchant may be Cl 2 or 2 However, the present disclosure is not limited thereto.

[0204] The plurality of semiconductor material layers SEM3L, SEM2L, MQWL and SEM1L and the transparent conductive material layer TCOL overlapping the first mask pattern MP1 are formed into a plurality of light emitting elements LE without being etched. Thus, a plurality of light emitting elements LE including the third semiconductor layer SEM3, the second semiconductor layer SEM2, the active layer MQW, the first semiconductor layer SEM1 and the transparent conductive layer TCO are formed.

[0205] Next, refer to Fig.13 , an opening exposing the second semiconductor layer SEM2 is formed on the transparent conductive layer TCO by an etching process. As described above, the etching process may be a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc.

[0206] refer to Fig.14 and Fig.15 , an insulating material layer INSL having / defining a plurality of openings OP1 and OP2 may be formed on the base substrate BSUB on which the light emitting element LE is formed.

[0207] For example, the insulating material layer INSL may be formed on the outer surfaces of the plurality of light emitting elements LE. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB such that the insulating material layer INSL is formed not only on the light emitting elements LE but also on the top surface of the base substrate BSUB exposed by the light emitting elements LE.

[0208] Next, a second etching may be performed to partially remove the insulating material layer INSL, thereby forming a light emitting element LE including the element insulating layer INSO.

[0209] For example, a second etching process may be performed in which the insulating material layer INSL is partially removed so that the insulating material layer INSL exposes the top surface of the light emitting element LE but surrounds the side of the light emitting element LE. For example, in this process, the insulating material layer INSL may define a first opening OP1 by removing at least a portion of the top surface of the transparent conductive layer TCO of the light emitting element LE. In addition, the insulating material layer INSL may define a second opening OP2 by removing at least a portion of the second semiconductor layer SEM2 of the light emitting element LE. The process of partially removing the insulating material layer INSL may be performed by an etching process using a mask.

[0210] Next, refer to Fig.16 , the light emitting element LE may be formed by forming the first contact electrode CTE1 and the second contact electrode CTE2 on the light emitting element LE.

[0211] For example, the first contact electrode CTE1 and the second contact electrode CTE2 are formed by stacking a contact electrode material layer on the base substrate BSUB. Then, the contact electrode material layer is etched by an etching process to form the first contact electrode CTE1 covering the first opening OP1 of the light emitting element LE, and to form the second contact electrode CTE2 covering the second opening OP2. The contact electrode material layer may be formed of a transparent conductive material. For example, the contact electrode material layer may be a transparent conductive oxide such as indium tin oxide (ITO) and indium zinc oxide (IZO). The first contact electrode CTE1 may be electrically connected to the first semiconductor layer SEM1 through the first opening OP1, and the second contact electrode CTE2 may be electrically connected to the second semiconductor layer SEM2 through the second opening OP2.

[0212] Next, refer to Fig.17 Attach the support film SPF1 to Fig.16 A plurality of light emitting elements LE are fabricated on a base substrate BSUB.

[0213] For example, the support film SPF1 is attached on the plurality of light emitting elements LE. The support film SPF1 may be aligned on the plurality of light emitting elements LE and may be attached to the first contact electrode CTE1 and the second contact electrode CTE2 of the plurality of light emitting elements LE. The plurality of light emitting elements LE may be arranged in large quantities and may be attached to the support film SPF1 without being detached.

[0214] The supporting film SPF1 may be composed of a supporting layer S2 and an adhesive layer S1 located on the supporting layer S2. The supporting layer S2 may be made of a transparent, mechanically stable material that allows light to pass through. For example, the supporting layer S2 may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesive layer S1 may include an adhesive material for bonding the light-emitting element LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet (UV) or heat is applied, and thus the adhesive layer S1 is appropriately separated from the light-emitting element LE.

[0215] Next, the base substrate BSUB is irradiated with the first laser (first laser) to separate the light emitting element LE from the base substrate BSUB. The base substrate BSUB is separated from each third semiconductor layer SEM3 of the plurality of light emitting elements LE.

[0216] The process of separating the base substrate BSUB may be performed by a laser lift-off (LLO) process. The laser lift-off process uses laser. KrF excimer laser (wavelength of about 248 nm) may be used as a light source. The energy density of the excimer laser may be about 550 mJ / cm 2About 950mJ / cm 2 The incident area can be irradiated within a range of about 50 × 50 μm 2 About 1×1cm 2 By irradiating the base substrate BSUB with laser, the base substrate BSUB can be separated from the light emitting element LE.

[0217] At the same time, for the sake of explanation, Figures 18 to 21 as well as Fig.23 A plan view corresponding to the cross-sectional view is shown.

[0218] First, refer to Fig.18 , prepare substrate 110. As shown in reference Figure 6 As described, the second planarization layer 130, the first pad electrode APD, and the second pad electrode CPD may be positioned on the substrate 110. The first pad electrode APD and the second pad electrode CPD may be arranged to be spaced apart from each other.

[0219] Afterwards, refer to Fig.19 , a bank PDL and an inter-electrode planarization layer PFL may be formed on the second planarization layer 130. For example, an organic material layer including a light blocking material is applied to the entire substrate on which the first pad electrode APD and the second pad electrode CPD are formed. The organic material layer may have the same thickness as the first pad electrode APD and the second pad electrode CPD. For example, the organic material layer may be applied to about to about In another variation, the organic material layer may be applied to about to about The organic material layer may then be etched using a mask etching process to form a dam PDL and an inter-electrode planarization layer PFL. The dam PDL may expose at least a portion of the first pad electrode APD and at least a portion of the second pad electrode CPD. The dam PDL and the inter-electrode planarization layer PFL may be connected to each other.

[0220] Then, refer to Fig. 20 , forming the first reflective electrode SCT1 and the second reflective electrode SCT2 on the bank PDL, the first pad electrode APD and the second pad electrode CPD. For example, the reflective electrode material layer may cover the bank PDL, the first pad electrode APD, the inter-electrode planarization layer PFL and the second pad electrode CPD. Thereafter, a photoresist pattern is formed to cover at least a portion of the reflective electrode material layer. The photoresist pattern may be applied to about to about Then, wet etching may be performed using an etching chemical solution. The reflective electrode material layer in the region where the photoresist pattern is not located is removed to form a first reflective electrode SCT1 and a second reflective electrode SCT2 spaced apart from each other.

[0221] Meanwhile, when the reflective electrode material layer is applied without forming the inter-electrode planarizing layer PFL on the second planarizing layer 130 and wet etching is performed by an etching solution, the reflective electrode material layer located in the gap between the first pad electrode APD and the second pad electrode CPD may not be cleanly etched. Therefore, there may be a possibility that a short circuit may occur between the first pad electrode APD and the second pad electrode CPD.

[0222] On the other hand, when the inter-electrode planarization layer PFL is formed between the first pad electrode APD and the second pad electrode CPD, as in one or more embodiments, the reflective electrode material layer can be cleanly etched between the first pad electrode APD and the second pad electrode CPD. Therefore, the possibility of a short circuit between the first pad electrode APD and the second pad electrode CPD can be reduced or prevented.

[0223] Then, refer to Fig.21 and Fig.23 , the plurality of light emitting elements LE arranged on the support film SPF1 are transferred onto the second planarization layer 130 .

[0224] For example, an organic pattern layer BOL is formed within an opening defined by the bank PDL. At this stage, the organic pattern layer BOL is not cured and is in a fluid state, and may be referred to as a temporary adhesive layer.

[0225] Next, the support film SPF1 is aligned on the substrate 110. The third semiconductor layer SEM3 of the light emitting element LE is aligned on the support film SPF1 to be located on the organic pattern layer BOL. The light emitting element LE is positioned so that the first contact electrode CTE1 and the second contact electrode CTE2 face the top. The first contact electrode CTE1 may be positioned close to the first pad electrode APD, and the second contact electrode CTE2 may be positioned close to the second pad electrode CPD.

[0226] Then, the substrate 110 and the supporting film SPF1 are bonded together. For example, the third semiconductor layer SEM3 of the light emitting element LE on the supporting film SPF1 may contact the organic pattern layer BOL. Next, the organic pattern layer BOL is cured by applying heat and pressure to the organic pattern layer BOL. Therefore, the light emitting element LE is bonded to the organic pattern layer BOL by curing the organic pattern layer BOL. The heat and pressure required in the process of bonding the organic pattern layer BOL are lower than the heat and pressure required in the eutectic bonding process. For example, while the eutectic bonding process is a relatively high temperature process of about 200 degrees Celsius to about 400 degrees Celsius, the organic material curing process may be a relatively low temperature process of about 80 degrees Celsius to about 200 degrees Celsius. Therefore, compared with the eutectic bonding process, the light emitting element LE can be bonded to the substrate 110 at relatively low temperature and pressure.

[0227] Thereafter, the supporting film SPF1 is separated from the plurality of light emitting elements LE. After ultraviolet rays or heat are applied to the supporting film SPF1 to reduce the adhesive strength of the adhesive layer S1 of the supporting film SPF1, the supporting film SPF1 may be physically or naturally separated from the plurality of light emitting elements LE.

[0228] Next, refer to Fig.24 , a via layer VIA having a plurality of contact holes CH1 , CH2 , CH3 , and CH4 may be formed.

[0229] The via layer VIA may be formed to be higher than the light emitting element LE. The via layer VIA may be formed so that the entire light emitting element LE is covered. The via layer VIA may be applied using a solution process such as spin coating or inkjet printing.

[0230] Next, a plurality of contact holes CH1 , CH2 , CH3 , and CH4 may be formed in the via layer VIA through an etching process using a mask.

[0231] The first contact hole CH1 exposes the first contact electrode CTE1, the second contact hole CH2 exposes the first reflective electrode SCT1, the third contact hole CH3 exposes the second contact electrode CTE2, and the fourth contact hole CH4 exposes the second reflective electrode SCT2.

[0232] Next, refer to Fig.25 , a first lead line LDL1 and a second lead line LDL2 are formed on the via layer VIA.

[0233] For example, a lead material layer may be applied on the through hole layer VIA, and the lead material layers may be spaced apart from each other by an etching process using a mask to form a first lead LDL1 and a second lead LDL2. The first lead LDL1 is formed along the first contact hole CH1 and the second contact hole CH2, and the second lead LDL2 is formed along the third contact hole CH3 and the fourth contact hole CH4. Therefore, the first lead LDL1 contacts the first contact electrode CTE1 exposed by the first contact hole CH1, and contacts the first reflective electrode SCT1 exposed by the second contact hole CH2. In addition, the second lead LDL2 contacts the second contact electrode CTE2 exposed by the third contact hole CH3, and contacts the second reflective electrode SCT2 exposed by the fourth contact hole CH4. Therefore, the first contact electrode CTE1 is electrically connected to the first pad electrode APD, and the second contact electrode CTE2 is electrically connected to the second pad electrode CPD.

[0234] Next, refer to Fig.26 , an organic material is applied onto the via layer VIA and patterned to form a partition wall PW.

[0235] An organic material is applied on the via layer VIA and patterned to form a partition wall PW. A plurality of openings may be formed to correspond to the first light emitting area EA1. In one or more embodiments, other openings corresponding to other light emitting areas are also formed.

[0236] Fig. 27 is a diagram illustrating a virtual reality device including a display device according to one or more embodiments. Fig. 27 A virtual reality device 1 is shown in which a display device 10 according to one or more embodiments is used.

[0237] refer to Fig. 27 The virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left eye lens 10a, a right eye lens 10b, a support frame 20, left legs 30a and right legs 30b, a reflective member 40, and a display device housing 50.

[0238] Fig. 27 The virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be mounted on the head without including the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Fig. 27 , and can be applied in various forms and in various electronic devices.

[0239] The display device housing 50 can receive the display device 10 and the reflective member 40. The image displayed on the display device 10 can be reflected from the reflective member 40 and provided to the user's right eye through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10 through the right eye.

[0240] Fig. 27 The display device housing 50 is shown to be located at the right end of the support frame 20. However, one or more embodiments of the present disclosure are not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, the image displayed on the display device 10 may be reflected from the reflective member 40 and provided to the user's left eye via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10 via the left eye. As another example, the display device housing 50 may be located at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10 via both the left eye and the right eye.

[0241] Fig.28 is a diagram illustrating a smart device including a display device according to one or more embodiments.

[0242] refer to Fig.28 The display device 10 according to one or more embodiments may be applied to a smart watch 2 which is one of smart devices.

[0243] Fig.29 is a diagram illustrating a vehicle including a display device according to one or more embodiments. Fig.29 A vehicle using a display device according to one or more embodiments is shown.

[0244] refer to Fig.29 The display devices 10_a, 10_b, and 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, may be applied to a central instrument panel of a vehicle, or may be applied to a CID (Central Information Display) located on a dashboard of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display that replaces each of the side mirrors of the vehicle.

[0245] Fig.30 is a diagram illustrating a transparent display device including a display device according to one or more embodiments.

[0246] refer to Fig.30, the display device according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device may not only view the image IM displayed on the display device 10, but may also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, the substrate 110 of the display device 10 may include a light-transmitting portion through which light may be transmitted, or may be made of a material through which light may be transmitted.

[0247] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only and not for a limiting purpose.

Claims

1. A display device, comprising: a substrate on which a first pad electrode and a second pad electrode are positioned; a bank defining a first opening over the substrate and exposing at least a portion of the first pad electrode and at least a portion of the second pad electrode through the first opening; an inter-electrode planarization layer, between the first pad electrode and the second pad electrode; a first reflective electrode extending from the bank to the inter-electrode planarization layer along the first pad electrode; a second reflective electrode extending from the bank to the inter-electrode planarization layer along the second pad electrode; an organic pattern layer in the first opening; a light emitting element, above the organic pattern layer, and having a first contact electrode and a second contact electrode on a top surface of the light emitting element; a through-hole layer covering the light-emitting element and defining a contact hole; a first lead, which is above the through-hole layer and electrically connects the first contact electrode and the first reflective electrode; as well as A second lead is above the via layer and electrically connects the second contact electrode and the second reflective electrode.

2. The display device according to claim 1, wherein: The inter-electrode planarization layer and the bank have the same thickness.

3. The display device according to claim 2, wherein: The inter-electrode planarization layer and the bank include the same material.

4. The display device according to claim 3, wherein: The inter-electrode planarization layer and the bank include a light blocking material.

5. The display device according to claim 2, wherein: The first pad electrode and the second pad electrode are spaced apart from each other on the same plane and protrude outward from the light emitting element in a plan view.

6. The display device according to claim 2, wherein: The inter-electrode planarization layer has the same height as the first pad electrode and the second pad electrode.

7. The display device according to claim 2, wherein: A height of the inter-electrode planarization layer is greater than a height of the first pad electrode and the second pad electrode.

8. The display device according to claim 7, wherein: A top surface of the inter-electrode planarization layer contacts the organic pattern layer, and The roughness of the top surface of the inter-electrode planarization layer is greater than the roughness of another surface of the inter-electrode planarization layer.

9. The display device according to claim 1, wherein: The light emitting element includes a second semiconductor layer, an active layer, a first semiconductor layer, an element insulating layer and a third semiconductor layer contacting the organic pattern layer. The element insulating layer surrounds the third semiconductor layer, the second semiconductor layer, the side surfaces of the active layer and the first semiconductor layer and the top surface of the light emitting element, and defines a second opening and a third opening. wherein the first contact electrode is electrically connected to the first semiconductor layer through the second opening, and The second contact electrode is electrically connected to the second semiconductor layer through the third opening.

10. The display device according to claim 1, wherein: The width of the organic pattern layer is greater than the width of the light emitting element.

11. The display device according to claim 10, wherein: The organic pattern layer overlaps the inter-electrode planarization layer, does not overlap the bank, and directly contacts the inter-electrode planarization layer.

12. The display device according to claim 1, further comprising: a partition wall over the via layer, the first lead, and the second lead and defining a light emitting area; as well as A wavelength conversion layer is in the light emitting region and fills the contact hole in the via layer. 13 . The display device of claim 12 , further comprising a capping layer and a color filter layer sequentially over the wavelength conversion layer and the partition wall.

14. A method for manufacturing a display device, comprising: providing a substrate on which a first pad electrode and a second pad electrode are positioned; forming a bank over the substrate, the bank defining a first opening exposing at least a portion of the first pad electrode and at least a portion of the second pad electrode; forming an inter-electrode planarization layer above the substrate between the first pad electrode and the second pad electrode; forming a first reflective electrode extending from the bank to the inter-electrode planarization layer along the first pad electrode; forming a second reflective electrode extending from the bank to the inter-electrode planarization layer along the second pad electrode; applying an organic pattern material layer in the first opening; placing a light emitting element on the organic pattern material layer; curing the organic pattern material layer to form an organic pattern layer, and bonding the light emitting element to the organic pattern layer; forming a through-hole layer covering the light-emitting element and defining a contact hole; forming a first lead over the through-hole layer to electrically connect a first contact electrode on a top surface of the light-emitting element and the first reflective electrode; as well as A second wiring is formed over the via layer to electrically connect a second contact electrode on a top surface of the light emitting element and the second reflective electrode.

15. The method according to claim 14, wherein: Forming the bank and forming the inter-electrode planarization layer comprises: coating a layer of organic material over the substrate; and The organic material layer is etched by using a mask to form the bank and the inter-electrode planarization layer.

16. The method according to claim 15, wherein: The organic material layer includes a light blocking material.

17. The method according to claim 15, wherein: Coating the organic material layer includes applying the organic material layer to the same thickness as the first pad electrode and the second pad electrode.

18. The method according to claim 15, further comprising performing a plasma pretreatment process or an ashing process on a top surface of the bank and a top surface of the inter-electrode planarization layer to increase roughness of the top surface of the bank and the top surface of the inter-electrode planarization layer.

19. The method according to claim 14, wherein: The light emitting element comprises a third semiconductor layer, a second semiconductor layer, an active layer and a first semiconductor layer stacked in sequence, Wherein, the light emitting element further comprises an element insulating layer, The element insulating layer surrounds the third semiconductor layer, the second semiconductor layer, the side surfaces of the active layer and the first semiconductor layer and the top surface of the light emitting element, and defines a second opening and a third opening. wherein the first contact electrode is electrically connected to the first semiconductor layer through the second opening, and The second contact electrode is electrically connected to the second semiconductor layer through the third opening.

20. The method of claim 14, further comprising: a partition wall formed over the via layer, the first lead, and the second lead and defining a light emitting area; forming a wavelength conversion layer in the light emitting region; as well as A capping layer and a color filter layer are formed which are sequentially disposed over the partition wall and the wavelength conversion layer.

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