Display device

Abstract

The invention relates to a display device. The display device includes: a substrate; a pixel electrode and a common electrode spaced apart from each other on the substrate; an organic pattern layer between the pixel electrode and the common electrode; a light emitting element over the organic pattern layer and including a first contact electrode and a second contact electrode over a top surface of the light emitting element; an organic layer in a region other than a region in which the light emitting element is positioned, and having a first electrode opening and a second electrode opening; a first conductive wall in the first electrode opening and electrically connected to the pixel electrode; and a second conductive wall in the second electrode opening and electrically connected to the common electrode; and a first connection electrode and a second connection electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0162936 filed in the Korean Intellectual Property Office on November 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, a light-emitting display, etc. The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element (OLED) as a light-emitting element and a micro light-emitting display device including a micro light-emitting diode element (hereinafter, referred to as a micro light-emitting element) as a light-emitting element.

[0005] In particular, as display devices become smaller and thinner, inorganic light emitting elements are widely used as light emitting devices.

[0006] Generally, a light-emitting element using an inorganic material is grown on a growth substrate, and the grown light-emitting element is separated from the growth substrate and transferred to a transistor substrate. At this time, the light-emitting element can be bonded to the pixel electrode and the common electrode of the substrate using a connecting electrode. If the connecting electrode is excessively bent during the bonding process, disconnection of the connecting electrode may occur, resulting in the light-emitting element not emitting light. Summary of the invention

[0007] Aspects of embodiments of the present disclosure provide a display device and a method of manufacturing the same which can reduce or prevent a situation where a non-emitting light emitting element is caused by disconnection of a connection electrode.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] According to one or more embodiments, a display device includes: a substrate; a pixel electrode and a common electrode, which are spaced apart from each other on the substrate; an organic pattern layer, between the pixel electrode and the common electrode; a light-emitting element, which is above the organic pattern layer and includes a first contact electrode and a second contact electrode on a top surface of the light-emitting element; an organic layer, which is located in an area other than an area where the light-emitting element is positioned and has a first electrode opening and a second electrode opening; a first conductive wall, which is in the first electrode opening and is electrically connected to the pixel electrode; a second conductive wall, which is in the second electrode opening and is electrically connected to the common electrode; and a first connection electrode and a second connection electrode, the first connection electrode being connected to the first contact electrode and the first conductive wall of the light-emitting element, and the second connection electrode being connected to the second contact electrode and the second conductive wall of the light-emitting element.

[0010] The display device also includes: a dam covering edges of the pixel electrode and the common electrode and in an area other than an area where the organic pattern layer is positioned; a first auxiliary electrode extending from the pixel electrode to above a top surface of the dam; and a second auxiliary electrode extending from the common electrode to above the top surface of the dam, wherein the first electrode opening exposes the first auxiliary electrode, and wherein the second electrode opening exposes the second auxiliary electrode.

[0011] The first conductive wall contacts the first auxiliary electrode through the first electrode opening, and the second conductive wall contacts the second auxiliary electrode through the second electrode opening.

[0012] The first conductive wall and the second conductive wall include a light blocking material.

[0013] The first conductive wall overlaps with a first side of the light emitting element, and the first side of the light emitting element completely overlaps with the first conductive wall, wherein the second conductive wall overlaps with a second side of the light emitting element, and the second side of the light emitting element completely overlaps with the second conductive wall, and wherein the first side and the second side are parallel to each other.

[0014] The width of the first conductive wall is greater than the width of the first side of the light emitting element, and wherein the width of the second conductive wall is greater than the width of the second side of the light emitting element.

[0015] The first conductive wall overlaps a third side of the light emitting element and is spaced apart from the second conductive wall, wherein the second conductive wall overlaps a fourth side of the light emitting element and is spaced apart from the first conductive wall, and wherein the third side is substantially perpendicular to the first side and parallel to the fourth side.

[0016] The display device also includes: a third conductive wall overlapping the third side of the light emitting element and spaced apart from the first conductive wall and the second conductive wall, and a fourth conductive wall overlapping the fourth side of the light emitting element and spaced apart from the first conductive wall and the second conductive wall, wherein the third side of the light emitting element completely overlaps with the third conductive wall, wherein the fourth side of the light emitting element completely overlaps with the fourth conductive wall, and wherein the third side is substantially perpendicular to the first side and parallel to the fourth side.

[0017] The light-emitting element also includes a third semiconductor layer (undoped semiconductor layer), a second semiconductor layer, an active layer, a first semiconductor layer and a protective layer (protective film), wherein the third semiconductor layer is in contact with the organic pattern layer, and wherein the protective layer is on the entire surface of the light-emitting element except the bottom of the light-emitting element, and defines an opening on the top surface of the light-emitting element that exposes the first contact electrode and the second contact electrode.

[0018] The pixel electrode and the common electrode include an opaque metal material, and wherein the first connection electrode and the second connection electrode include a transparent conductive oxide.

[0019] The width of the organic pattern layer is greater than the width of the light emitting element.

[0020] The display device further includes a light blocking layer on the first connection electrode and the second connection electrode, overlapping the bank and defining a light emitting region; and a light conversion layer or a light transmission layer in a space defined by the light blocking layer.

[0021] The display device further includes a capping layer, an overcoat layer, and a color filter layer sequentially over the light conversion layer and the light blocking layer.

[0022] However, aspects of the present disclosure are not limited to the aforementioned effects, and various other aspects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0024] Figure 2 is a layout diagram illustrating a display device according to one or more embodiments.

[0025] Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0026] Figure 4 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0027] Figure 5 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0028] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0029] Figure 7 It is shown in detail Figure 6 FIG. 1 is a diagram showing an example layout of area A. FIG.

[0030] Figure 8 is shown with Figure 6 2 is a cross-sectional view of an example of a cross section of a display panel corresponding to lines I1 - I1 ′, I2 - I2 ′, and I4 - I4 ′.

[0031] Fig. 9 yes Figure 8 An enlarged view of the connection structure of the light emitting element LE of the first sub-pixel SPX1.

[0032] Fig.10 It is shown Fig. 9 A plan view of a light-emitting element, a conductive wall, a pixel electrode, a common electrode and a connecting electrode.

[0033] Fig.11 yes Fig.10 One or more other embodiments of the present invention.

[0034] Fig.12 yes Fig.10 One or more other embodiments of the present invention.

[0035] Fig.13 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments.

[0036] Figures 14 to 22 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments.

[0037] Fig.23 A virtual reality device including a display device according to one or more embodiments is shown.

[0038] Fig.24 A smart device including a display device according to one or more embodiments is shown.

[0039] Fig.25 A vehicle including a display device according to one or more embodiments is shown.

[0040] Fig.26 A transparent display device including the display device according to one or more embodiments is shown. DETAILED DESCRIPTION

[0041] By referring to the detailed description and drawings of the embodiments, it is easier to understand the aspects of the embodiments of the present disclosure and the methods for realizing them. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments or unnecessary processes, elements and techniques for fully understanding the aspects of the present disclosure by those of ordinary skill in the art can be omitted. Unless otherwise stated, in the entire drawings and written descriptions, the same reference numerals, characters or combinations thereof represent the same elements, and therefore, their repeated descriptions can be omitted.

[0042] The embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The present disclosure encompasses all modifications, equivalents and / or substitutions within the scope of the present disclosure's ideas and techniques. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in its entirety, and various interlocks and drives are technically possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0043] In the drawings, the relative sizes of elements, layers, and / or regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0044] One or more embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. Therefore, variations in the shape of the figures due to, for example, manufacturing techniques and / or tolerances should be expected. In addition, the specific structural or functional descriptions disclosed herein are merely exemplary for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, and / or regions shown, but should include deviations in shapes caused by, for example, manufacturing.

[0045] For example, an implanted region illustrated as a rectangle will, typically, have rounded and / or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted region to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0046] For ease of explanation, spatial relative terms such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc. may be used herein to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or in operation. For example, if the device in the drawings is turned over, the elements described as "below", "below" or "below" other elements or features will be oriented "above" other elements and / or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this means that the first part is arranged at the upper or lower side of the second part based on the direction of gravity, without being limited to its upper side.

[0047] In addition, the phrase "in a plan view" means when viewing the object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object can be above or below the second object, or on one side of the second object, and vice versa. In addition, the term "overlap" may include stacking, facing (face) or facing (facing), extending on ..., covering or partially covering or any other suitable term as will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable equivalent such as "spaced apart from ... " or "separated from ... " or "offset from ... " and as will be appreciated and understood by a person of ordinary skill in the art. The term "face (face)" and "facing (facing)" may mean that the first object may be directly opposite or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other, but still facing each other.

[0048] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it may be directly formed on, directly on, directly connected to, or directly coupled to, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to, such that one or more intervening elements, layers, regions, or components may be present. Furthermore, this may collectively mean directly coupled or coupled or indirectly coupled or indirect coupled or indirect coupled as well as integrally coupled or integrally coupled or non-integrally coupled or non-integrally coupled. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or directly electrically coupled to the other layer, region, and / or component, and / or there may be intervening layers, regions, and / or components. However, "directly connected / directly coupled" or "directly on" means that one component is directly connected or directly coupled to another component or directly on another component without intervening components.

[0049] In addition, in the present disclosure, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "under" another part, this not only includes the situation that the part is "directly under" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to...", can be interpreted similarly. It will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0050] For the purposes of this disclosure, when expressions such as "at least one of" or "any one of" or "one or more of" are located after a list of elements, the entire list of elements is modified and the individual elements in the list are not modified. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, and XZ) and / or any variation thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, expressions such as "A and / or B" can include A, B, or A and B. Similarly, when expressions such as "at least one of", "a plurality of", "one of", and other prepositional phrases are located before / after a list of elements, the entire list of elements is modified and the individual elements in the list are not modified.

[0051] It will be understood that although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or advantage, and are only used to distinguish an element, member, component, area, region, layer, section and / or part from another element, member, component, area, region, layer, section and / or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, first component, first area, first layer and / or first section described below may be referred to as the second element, second component, second area, second layer and / or second section. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish elements of different categories or sets. For the sake of simplicity, the terms "first", "second", etc. may respectively represent "first category (or first set)", "second category (or second set)", etc.

[0052] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0053] The terms used herein are only used for the purpose of describing the embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises", "comprising", "have", "having", "includes" and / or "including" when used in the present disclosure specify the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0054] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously, or in an order opposite to the described order.

[0055] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to allow for inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the value and means within an acceptable range of deviations of the particular value determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0056] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the present disclosure, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0057] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0058] Figure 1 is a perspective view showing a display device according to one or more other embodiments.

[0059] refer to Figure 1The display device 10 is a device for displaying video and / or still images, such as a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, and an ultra mobile PC (UMPC), and a display screen for various products such as a television, a notebook computer, a monitor, a billboard, and / or an Internet of Things (IOT) device.

[0060] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode (OLED), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using a micro light-emitting diode or a nano light-emitting diode (micro-LED or nano-LED). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, in the following, a micro light-emitting diode is referred to as a light-emitting element.

[0061] The display device 10 includes a display panel 100 , a display driving circuit 250 , a circuit board 300 , and a power supply circuit 500 .

[0062] The display panel 100 may be formed as a plane having a rectangular shape with a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be formed at a right angle. The planar shape of the display panel 100 is not limited to a rectangle, and may be formed in other polygonal shapes, a circular shape, or an elliptical shape. The display panel 100 may be formed to be flat, but is not limited thereto. For example, the display panel 100 is formed at the left and right end portions, and may include a curved portion having a constant curvature or a changing curvature. In addition, the display panel 100 may be formed to be flexible, such as being formed to be able to be bent, curved, folded, and / or curled.

[0063] The display panel 100 may include a main area MA and a sub area SBA.

[0064] The main area MA may include a display area DA displaying an image and a non-display area NDA which is a peripheral area of ​​the display area DA and is around the display area DA along an edge or periphery of the display area DA. The display area DA may include a plurality of pixels displaying an image. For example, a pixel may include a first sub-pixel emitting a first light, a second sub-pixel emitting a second light, and a third sub-pixel emitting a third light.

[0065] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. Figure 1 The sub-region SBA is shown as being expanded, but the sub-region SBA may be bent, and in this case, may be located on the bottom surface of the display panel 100. When the sub-region SBA is bent, it may overlap the main region MA in the third direction DR3 which is the thickness direction of the display panel 100. The display driving circuit 250 may be located in the sub-region SBA.

[0066] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0067] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Therefore, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF).

[0068] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. The power supply circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 using a COF method.

[0069] Figure 2 is a layout diagram illustrating a display device according to one or more embodiments. Figure 2 The sub-area SBA is shown unfolded without bending.

[0070] refer to Figure 2 , the display panel 100 may include a main area MA and a sub-area SBA.

[0071] The main area MA may include a display area DA displaying an image and a non-display area NDA as a peripheral area of ​​the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed in the center of the main area MA.

[0072] The display area DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub-pixels SPX. The pixel PX may be defined as a sub-pixel group that is a minimum unit capable of expressing a white grayscale.

[0073] The non-display area NDA may be placed adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., arranged to surround the display area DA). The non-display area NDA may be an edge area of ​​the display panel 100.

[0074] The first scan driver SDC1 and the second scan driver SDC2 may be located in the non-display area NDA. The first scan driver SDC1 is located on one side (e.g., the left side) of the display panel 100, and the second scan driver SDC2 is located on the other side (e.g., the right side) of the display panel 100. However, it is not limited thereto. Each of the first scan driver SDC1 and the second scan driver SDC2 may be electrically connected to the display driving circuit 250 through a scan fan-out line. Each of the first scan driver SDC1 and the second scan driver SDC2 may receive a scan control signal from the display driving circuit 250, generate scan signals according to the scan control signal, and output them to the scan lines.

[0075] The sub-region SBA may protrude from one side of the main region MA in the second direction DR2. The length of the sub-region SBA in the second direction DR2 may be smaller than the length of the main region MA in the second direction DR2. The length of the sub-region SBA in the first direction DR1 may be smaller than the length of the main region MA in the first direction DR1, or may be substantially equal to the length of the main region MA in the first direction DR1. The sub-region SBA may be curved and may be located at a lower portion of the display panel 100. In this case, the sub-region SBA may overlap with the main region MA in the third direction DR3.

[0076] The sub-area SBA may include a connection area CA, a pad area PA, and a bending area BA.

[0077] The connection area CA is an area protruding from one side of the main area MA in the second direction DR2. One side of the connection area CA may contact the non-display area NDA of the main area MA, and the other side of the connection area CA may contact the bending area BA.

[0078] The pad area PA is an area where the pad PD and the display driving circuit 250 are located. The display driving circuit 250 may be attached to the driving pad of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be attached to the pad PD of the pad area PA using a conductive adhesive member such as an anisotropic conductive film. One side of the pad area PA may be in contact with the bending area BA.

[0079] The bending area BA is a bent area. When the bending area BA is bent, the pad area PA may be located below the connection area CA and below the main area MA (e.g., in the thickness direction). The bending area BA may be located between the connection area CA and the pad area PA. One side of the bending area BA may contact the connection area CA, and the other side of the bending area BA may contact the pad area PA.

[0080] The non-display power line NVSL may be disposed in the non-display area NDA, the connection area CA, the bending area BA, and the pad area PA.

[0081] The non-display power line NVSL may be arranged on four sides of the display area DA in the non-display area NDA. The non-display power line NVSL may be arranged around at least three sides of the display area DA (e.g., around at least three sides of the display area DA). For example, the non-display power line NVSL may be around the left side, upper side, and lower side of the display area DA (e.g., around the left side, upper side, and lower side of the display area DA), and may be arranged on at least a portion of the lower side. In addition, the non-display power line NVSL may be arranged outside the first scan driver SDC1 and outside the second scan driver SDC2. For example, the non-display power line NVSL may be arranged on the left side of the first scan driver SDC1 and on the right side of the second scan driver SDC2. Optionally, the non-display power line NVSL may overlap with the first scan driver SDC1 and the second scan driver SDC2.

[0082] The non-display power line NVSL may be disposed at left and right edges of the connection area CA and the bending area BA. The non-display power line NVSL may be connected to pads PD adjacent to one side edge and pads PD adjacent to another side edge from among pads PD in the pad area PA.

[0083] Figure 3 is a block diagram illustrating a display device according to one or more embodiments.

[0084] refer to Figure 3 The display area DA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission lines EL, and a plurality of data lines DL. Each of the plurality of pixels PX includes a plurality of sub-pixels SPX.

[0085] A plurality of pixels PX may be arranged in a matrix form in a first direction DR1 and a second direction DR2. For example, a plurality of pixels PX may be arranged along rows and columns of a matrix along the first direction DR1 and the second direction DR2. A plurality of scan lines SL and a plurality of emission lines EL may extend in the first direction DR1 and be arranged along the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and be arranged along the first direction DR1. The plurality of scan lines SL may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0086] Each of the plurality of sub-pixels SPX may be connected to a write scan line GWL from among a plurality of write scan lines GWL, a control scan line GCL from among a plurality of control scan lines GCL, an initialization scan line GIL from among a plurality of initialization scan lines GIL, a bias scan line GBL from among a plurality of bias scan lines GBL, an emission line EL from among a plurality of emission lines EL, and a data line DL from among a plurality of data lines DL. Each of the plurality of sub-pixels SPX may be supplied with a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and may emit light from the light emitting element according to the data voltage.

[0087] The non-display area NDA includes a first scan driver SDC1 , a second scan driver SDC2 , and a display driving circuit 250 .

[0088] Each of the first scan driver SDC1 and the second scan driver SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emitting signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emitting signal output unit 615 may receive a scan timing control signal SCS from the timing control circuit 251. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 251, and output them to the write scan line GWL in sequence. The control scan signal output unit 612 may generate a control scan signal according to the scan timing control signal SCS, and output the control scan signal to the control scan line GCL in sequence. The initialization scan signal output unit 613 may generate an initialization scan signal according to the scan timing control signal SCS, and output the initialization scan signal to the initialization scan line GIL in sequence. The bias scan signal output unit 614 can generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL. The light emission signal output unit 615 can generate a light emission control signal according to the scan timing control signal SCS, and sequentially output the light emission control signal to the emission line EL.

[0089] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit 252 .

[0090] The data driving circuit 252 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixel SPX is selected by the write scan signal of the first scan driver SDC1 and the second scan driver SDC2, and the data voltage may be provided to the selected sub-pixel SPX.

[0091] The timing control circuit 251 may receive digital video data DATA and a timing signal from an external source. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS to control the display panel 100 according to the timing signal. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driver SDC1 and the second scan driver SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0092] The power supply circuit 500 can generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 can generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT and can provide the first driving voltage VDD, the second driving voltage VSS, and the third driving voltage VINT to the display panel 100.

[0093] Figure 4 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0094] refer to Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to the scan lines GWL, GIL, GCL and GBL, the emission line EL and the data line DL. For example, the sub-pixel SPX may be connected to the write scan line GWL, the initialization scan line GIL, the control scan line GCL, the bias scan line GBL, the emission line EL and the data line DL.

[0095] The subpixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1 and a light emitting element LE. The switching element includes first, second, third, fourth, fifth, and sixth transistors ST1, ST2, ST3, ST4, ST5, and ST6.

[0096] The driving transistor DT includes a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Ids (hereinafter, referred to as a "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0097] The light emitting element LE may be a micro light emitting diode.

[0098] The light emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light emitting element LE may be proportional to the driving current Ids. The anode electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to the second power line VSL to which the second power voltage is applied. The parasitic capacitor Cel may be formed between the anode electrode and the cathode electrode of the light emitting element LE.

[0099] The capacitor C1 is formed between the gate electrode of the driving transistor DT and the first power line VDL to which the first power voltage is applied. The first power voltage may be at a higher level than the second power voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first power line VDL.

[0100] like Figure 4As shown in , the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may all be formed as P-type metal oxide semiconductor field effect transistors (MOSFETs). In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6 and the driving transistor DT may be formed of polysilicon.

[0101] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission line EL. Because the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, when a scan signal of a gate low voltage and a low voltage emission signal are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission line EL, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 may be turned on. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0102] For example, the first transistor ST1 may be connected between the second electrode and the gate electrode of the driving transistor DT. The second transistor ST2 may be connected between the data line DL and the first electrode of the driving transistor DT. The third transistor ST3 may be connected between the initialization voltage line VIL and the gate electrode of the driving transistor DT. The fourth transistor ST4 may be connected between the initialization voltage line VIL and the light emitting element LE. The fifth transistor ST5 may be connected between the first power line VDL and the first electrode of the driving transistor DT. The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the light emitting element LE.

[0103] Figure 5 is an equivalent circuit diagram illustrating a sub-pixel according to one or more embodiments.

[0104] refer to Figure 5, the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as N-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as N-type MOSFETs may be formed of an oxide semiconductor. In this case, transistors formed of polysilicon and transistors formed of oxide semiconductors may be arranged in different layers.

[0105] Because the first transistor ST1 and the third transistor ST3 are formed as N-type MOSFETs, the first transistor ST1 can be turned on when a control scan signal with a gate high voltage is applied to the control scan line GCL, and the third transistor ST3 can be turned on when an initialization scan signal is applied to the initialization scan line GIL. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, so when a scan signal with a gate low voltage and an emission signal with a low voltage are applied to the write scan line GWL, the bias scan line GBL, and the emission line EL, respectively, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 can be turned on.

[0106] Optionally, Figure 4 The fourth transistor ST4 in the embodiment may be formed by an N-type MOSFET. In this case, the active layer of each fourth transistor ST4 may be formed by an oxide semiconductor. When the fourth transistor ST4 is formed by an N-type MOSFET, when a bias scan signal of a gate high voltage is applied to the bias scan line GBL, the fourth transistor ST4 may be turned on.

[0107] In one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may all be formed as N-type MOSFETs. In this case, an active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT may be formed of an oxide semiconductor.

[0108] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments. Figure 7 It is shown in detail Figure 6 FIG. 1 is a diagram showing an example layout of area A. FIG.

[0109] refer to Figure 6 and Figure 7 , each of the plurality of pixels PX in the display area DA may include a first sub-pixel SPX1 , a second sub-pixel SPX2 , a third sub-pixel SPX3 , and a fourth sub-pixel SPX4 .

[0110] A plurality of pixels PX may be arranged in a matrix form. Each of the plurality of pixels PX located in N (N is a positive integer) rows may be arranged in the order of a first sub-pixel SPX1, a second sub-pixel SPX2, a third sub-pixel SPX3, and a fourth sub-pixel SPX4 along a first direction DR1. In each of the plurality of pixels PX arranged in an N+1 row, the first sub-pixel SPX1, the fourth sub-pixel SPX4, the third sub-pixel SPX3, and the second sub-pixel SPX2 may be arranged in the order of a first sub-pixel SPX1, a fourth sub-pixel SPX4, a third sub-pixel SPX3, and a second sub-pixel SPX2 along a first direction DR1.

[0111] The first subpixel SPX1 and the third subpixel SPX3 may emit the first light, the second subpixel SPX2 may emit the second light, and the fourth subpixel SPX4 may emit the third light. Here, the first light may be light in a green wavelength band, the second light may be light in a red wavelength band, and the third light may be light in a blue wavelength band. For example, the blue wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band from approximately 370 μm to approximately 460 μm, the green wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band from approximately 480 μm to approximately 560 μm, and the red wavelength band may indicate that the main peak wavelength of the light is included in a wavelength band from approximately 600 μm to approximately 750 μm. When the first subpixel SPX1 and the third subpixel SPX3 emit the first light, they have the advantage of compensating the light with a lower luminous efficiency.

[0112] In the above example, the first subpixel SPX1 and the third subpixel SPX3 emit the same light, but the present disclosure is not limited thereto. For example, the first subpixel SPX1 may emit the first light, the second subpixel SPX2 may emit the second light, the third subpixel SPX3 may emit the third light, and the fourth subpixel SPX4 may emit the fourth light. In this case, the fourth light may be light in a monochromatic wavelength band different from the first to third lights or white light as a mixture of the first to third lights.

[0113] However, the arrangement and number of sub-pixels of each of the plurality of pixels PX according to an embodiment of the present disclosure and the emission wavelength band of the sub-pixels are not limited to those described above. For example, each of the plurality of pixels PX may include three sub-pixels arranged in a strip shape. In this case, each of the plurality of pixels PX may include a first sub-pixel emitting a second light, a second sub-pixel emitting a first light, and a third sub-pixel emitting a third light. In each of the plurality of pixels PX, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged sequentially along the first direction DR1.

[0114] Each of the first to fourth sub-pixels SPX1 to SPX4 may include a bank 190 having an opening OA, a pixel electrode PXE, a common electrode CE, a light emitting element LE, an organic pattern layer BOL, and a conductive layer COL.

[0115] The opening OA is formed by the dike ( Figure 8 190) in the figure, and may be defined as a region in which the light emitting element LE is located in each of the first to fourth sub-pixels SPX1 to SPX4.

[0116] The pixel electrode PXE and the common electrode CE are spaced apart from each other. A portion of the pixel electrode PXE may be located in a first portion of the opening OA, and the rest of the pixel electrode PXE may be located in an area other than the opening OA. A portion of the common electrode CE may be located in a second portion of the opening OA, and the rest of the common electrode CE may be located in an area other than the opening OA. At least a portion of the pixel electrode PXE and the common electrode CE may overlap with the light emitting element LE in a thickness direction, but is not limited thereto. The pixel electrode PXE and the common electrode CE may include an opaque metal material.

[0117] The organic pattern layer BOL may overlap the pixel electrode PXE and the common electrode CE in the opening OA. The organic pattern layer BOL is used to temporarily fix or adhere the light emitting element LE during the process of transferring the light emitting element LE to the display panel 100. That is, the organic pattern layer BOL may be a film for temporarily adhering the light emitting element LE to the pixel electrode PXE and the common electrode CE in the opening OA.

[0118] The light emitting element LE may have a rectangular planar shape. The light emitting element LE includes a first contact electrode CTE1 (see Fig. 9 ) and the second contact electrode CTE2 located on the other side (see Fig. 9 ). The first contact electrode CTE1 and the second contact electrode CTE2 may be spaced apart from each other in the second direction DR2.

[0119] The light emitting element LE may completely overlap the organic pattern layer BOL. A first portion of the light emitting element LE may overlap the pixel electrode PXE, and a second portion of the light emitting element LE may overlap the common electrode CE.

[0120] The conductive layer COL may include a conductive layer formed by a third organic layer ( Figure 8 The first conductive wall COL1 and the second conductive wall COL2 are formed by filling the region divided in 191) with a conductive material.

[0121] The conductive layer COL overlaps the bank 190 and does not overlap the light emitting element LE.

[0122] The first conductive wall COL1 is used to pass through the first connecting electrode BE1 (for example, see Fig. 9 ) electrically connects the first contact electrode CTE1 of the light emitting element LE and the pixel electrode PXE.

[0123] The second conductive wall COL2 is used to pass through the second connecting electrode BE2 (for example, see Fig. 9 ) electrically connects the second contact electrode CTE2 of the light emitting element LE and the common electrode CE.

[0124] In one or more embodiments, the first conductive wall COL1 may partially overlap at least a first side of the light emitting element LE. In one or more embodiments, the first side of the light emitting element LE may completely overlap with the first conductive wall COL1. For example, the length of the first conductive wall COL1 in the first direction DR1 may be longer than the length of the light emitting element LE in the first direction DR1.

[0125] In one or more embodiments, the second conductive wall COL2 may partially overlap at least the second side of the light emitting element LE. In one or more embodiments, the second side of the light emitting element LE may completely overlap the second conductive wall COL2. For example, the length of the second conductive wall COL2 in the first direction DR1 may be longer than the length of the light emitting element LE in the first direction DR1. Here, the first side and the second side may be sides facing each other.

[0126] One end of the common electrode CE may be connected to a second power line ( Figure 4 and Figure 5 Each of the second power supply lines VSL may be electrically connected to Figure 2 The non-display power line NVSL shown in FIG. 1 is located in the non-display area NDA.

[0127] The connection hole CT may be a hole in which the pixel electrode PXE is connected to the fourth source connection electrode ( Figure 8 The fourth source connection electrode ( Figure 8SBE4 in the first thin film transistor ( Figure 8 The connection hole CT may overlap with the pixel electrode PXE.

[0128] Figure 8 is shown with Figure 6 2 is a cross-sectional view of an example of a cross section of a display panel corresponding to lines I1 - I1 ′, I2 - I2 ′, and I4 - I4 ′. Fig. 9 yes Figure 8 An enlarged view of the connection structure of the light emitting element LE of the first sub-pixel SPX1. Fig.10 It is shown Fig. 9 A plan view of a light-emitting element, a conductive wall, a pixel electrode, a common electrode and a connecting electrode. Fig.11 yes Fig.10 One or more other embodiments of the present invention, and Fig.12 yes Fig.10 One or more other embodiments of the present invention.

[0129] refer to Figures 8 to 10 The substrate SUB may be made of an insulating material such as glass, a polymer resin, etc. If the substrate SUB is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin.

[0130] The barrier film BR may be provided on the substrate SUB. The barrier film BR is a membrane for protecting the transistors of the thin film transistor layer TFTL and the light emitting element layer EML from moisture penetration through the substrate SUB susceptible to moisture penetration. The barrier film BR may be composed of a plurality of inorganic films stacked alternately. For example, the barrier film BR may be formed as a multilayer of alternating inorganic films of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0131] The first thin film transistor TFT1 may be disposed on the barrier film BR. The first thin film transistor TFT1 may be Figure 4 The fourth transistor ST4 or the sixth transistor ST6 shown in FIG. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1.

[0132] The first active layer ACT1 of the first thin film transistor TFT1 may be located on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polycrystalline silicon, single crystalline silicon, low temperature polycrystalline silicon, and / or amorphous silicon.

[0133] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region overlapping with the first gate electrode G1 in a third direction DR3 that is a thickness direction of the substrate SUB. The first source region S1 may be located on one side of the first channel region CHA1, and the first drain region D1 may be located on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which a silicon semiconductor is doped with ions to make it conductive.

[0134] The first gate insulating film 131 may be located on the first channel region CHA1, the first source region S1, the first drain region D1 and the barrier film BR of the first thin film transistor TFT1. The first gate insulating film 131 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer).

[0135] The first gate metal layer GTL1 may be located on the first gate insulating film 131. The first gate metal layer GTL1 may include a first gate electrode G1 of the first thin film transistor TFT1 and a first capacitor electrode CAE1. The first gate electrode G1 may overlap the first active layer ACT1 in the third direction DR3. Figure 7 , the first gate electrode G1 and the first capacitor electrode CAE1 are shown to be spaced apart from each other, but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0136] The second gate insulating film 132 may be on the first gate electrode G1 of the first thin film transistor TFT1, the first capacitor electrode CAE1, and the first gate insulating film 131. The second gate insulating film 132 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0137] The second gate metal layer GTL2 may be located on the second gate insulating film 132. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may overlap the first capacitor electrode CAE1 in the third direction DR3. Since the second gate insulating film 132 has a suitable dielectric constant (eg, a predetermined dielectric constant), the capacitor ( Figure 5The first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating film 132 between the first capacitor electrode CAE1 and the second capacitor electrode CAE2 may be formed. The second gate metal layer GTL2 may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof.

[0138] The first interlayer insulating film 141 may be located on the second capacitor electrode CAE2 and the second gate insulating film 132. The first interlayer insulating film 141 may be formed of an inorganic film such as a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0139] The second thin film transistor TFT2 may be located on the first interlayer insulating film 141. The second thin film transistor TFT2 may be Figure 5 The first transistor ST1 or the third transistor ST3 shown in FIG. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0140] The second active layer ACT2 of the second thin film transistor TFT2 may be located on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)) and / or IGTO (indium (In), gallium (Ga), tin (Sn), and / or oxygen (O)).

[0141] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region overlapping with the second gate electrode G2 in the third direction DR3. The second source region S2 may be located on one side of the second channel region CHA2, and the second drain region D2 may be located on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that do not overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions in which the oxide semiconductor is doped with ions to make it conductive.

[0142] The third gate insulating film 133 may be on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating film 141. The third gate insulating film 133 may be formed of an inorganic film such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0143] The third gate metal layer GTL3 may be located on the third gate insulating film 133. The third gate metal layer GTL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may overlap the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and / or an alloy thereof.

[0144] The second interlayer insulating film 142 may be on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating film 133. The second interlayer insulating film 142 may be formed of an inorganic film such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and / or aluminum oxide.

[0145] The first data metal layer DTL1 may be located on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source connection hole PCT1 penetrating the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection hole BCT1 penetrating the second interlayer insulating film 142 and the third gate insulating film 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection hole BCT2 penetrating the second interlayer insulating film 142 and the third gate insulating film 133. The first data metal layer DTL1 may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or alloys thereof. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and / or a third layer made of titanium (Ti).

[0146] The first organic layer 160 may flatten a step caused by the first thin film transistor TFT1 and the second thin film transistor TFT2 on the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2 and the second interlayer insulating film 142. The first organic layer 160 may be formed of an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0147] The second data metal layer DTL2 may be located on the first organic layer 160. The second data metal layer DTL2 may include a fourth source connection electrode SBE4 and a second power line VSL (see FIG. 1 ). Figure 4 ). The fourth source connection electrode SBE4 may be connected to the first source connection electrode SBE3 through the second pixel connection hole PCT2 penetrating the first organic layer 160. The second data metal layer DTL2 may be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof. For example, the second data metal layer DTL2 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and / or a third layer made of titanium (Ti).

[0148] The second organic layer 180 may be located on the fourth source connection electrode SBE4 and the first organic layer 160. The second organic layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0149] The light emitting element layer EML may be located on the second organic layer 180. The light emitting element layer EML may include a pixel electrode PXE, a bank 190, a light emitting element LE, a common electrode CE, an organic pattern layer BOL, a first conductive wall COL1, and a second conductive wall COL2. In addition, the light emitting element layer EML may further include a first auxiliary electrode SCT1, a second auxiliary electrode SCT2, a first connection electrode BE1, and a second connection electrode BE2.

[0150] The pixel electrode PXE and the common electrode CE may be positioned on the second organic layer 180. The pixel electrode PXE and the common electrode CE may be spaced apart from each other.

[0151] The pixel electrode layer PXL may include a pixel electrode PXE and a common electrode CE, which are respectively located. The pixel electrode PXE may be referred to as an anode electrode, and the common electrode CE may be referred to as a cathode electrode.

[0152] The pixel electrode PXE may be connected to the fourth source connection electrode SBE4 through the connection hole CT penetrating the second organic layer 180. The pixel electrode PXE may be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, a voltage controlled by the first thin film transistor TFT1 may be applied to the pixel electrode PXE.

[0153] The common electrode CE may be connected to adjacent sub-pixels in common. One end of the common electrode CE may be connected to a second power line ( Figure 4 or Figure 5Therefore, the second driving voltage VSS may be applied to the common electrode CE.

[0154] When the pixel electrode layer PXL is made of a highly reflective metal material, the light emitted from the active layer MQW of the light emitting element LE and traveling in the downward direction of the light emitting element LE can be reflected from the pixel electrode PXE and the common electrode CE, and can travel in the upward direction of the light emitting element LE. Therefore, because the light loss from the light emitting element LE can be reduced, the light efficiency of the light emitting element LE can be improved. For example, the pixel electrode layer PXL can be formed as a single layer or multiple layers of one of molybdenum (Mo), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) and / or alloys thereof. In particular, the pixel electrode layer PXL can be a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), a two-layer structure of titanium (Ti) / copper (Cu) and / or a three-layer structure of titanium (Ti) / copper (Cu) / aluminum (Al), but the present disclosure is not limited thereto.

[0155] The bank 190 may be located on the second organic layer 180. The bank 190 is not formed on the entire surface of the second organic layer 180, and may include an opening OA to expose at least a portion of the pixel electrode PXE and the common electrode CE. For example, the bank 190 may be formed to cover the edges of the pixel electrode PXE and the common electrode CE. The opening OA may be a region separated by the bank 190. The opening OA may be a region in which the pixel electrode PXE, the common electrode CE, and the second organic layer 180 are exposed and in which the bank 190 is not located.

[0156] The bank 190 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The bank 190 may include a light blocking material to reduce or prevent the possibility that light from the light emitting element LE of one sub-pixel travels to an adjacent sub-pixel. For example, the bank 190 may include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0157] The first auxiliary electrode SCT1 may extend along the side of the bank 190 on the pixel electrode PXE, and may be located on the top surface of the bank 190. The second auxiliary electrode SCT2 may be located on the common electrode CE, extend along the side of the bank 190, and may be located on the top surface of the bank 190. The first auxiliary electrode SCT1 and the second auxiliary electrode SCT2 may be spaced apart from each other.

[0158] The first auxiliary electrode SCT1 and the second auxiliary electrode SCT2 may be formed as a single layer or a multilayer of one of molybdenum (Mo), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof. The first auxiliary electrode SCT1 and the second auxiliary electrode SCT2 may be made of a highly reflective metal material such as aluminum (Al).

[0159] The organic pattern layer BOL may be located on the pixel electrode PXE and the common electrode CE in each of the sub-pixels SPX1, SPX2, SPX3, and SPX4. The organic pattern layer BOL is used to temporarily fix or adhere the light emitting element LE during the process of transferring the light emitting element LE to the display panel 100. That is, the organic pattern layer BOL may be a film for temporarily adhering the light emitting element LE to the pixel electrode PXE and the common electrode CE. Because the greater thickness of the organic pattern layer BOL promotes temporary adhesion (Temporary Tack), the height of the opening OA in which the organic pattern layer BOL is accommodated or the thickness of the embankment 190 may be about 0.5 μm or more. The height of the opening OA may be greater than the thickness of the organic pattern layer BOL. The thickness of the organic pattern layer BOL may be greater than the thickness of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0160] The organic pattern layer BOL may contact the bottom surface of the light emitting element LE. In addition, the organic pattern layer BOL may contact at least a portion of each side of the light emitting element LE.

[0161] The area (or width) of the organic pattern layer BOL may be greater than the area (or width) of the light emitting element LE. The area of ​​the organic pattern layer BOL may be greater than the area of ​​the first connection electrode BE1 and the area of ​​the second connection electrode BE2.

[0162] The organic pattern layer BOL may be a photosensitive organic layer such as a photoresist. Alternatively, the organic pattern layer BOL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0163] Furthermore, when the plurality of light emitting elements LE are bonded by eutectic bonding in which the plurality of light emitting elements LE are bonded to the bonding electrode located on each of the plurality of pixel electrodes PXE by heat and pressure, the bonding electrode of each of the plurality of light emitting elements LE and the bonding electrode of each of the plurality of pixel electrodes PXE must be precisely aligned, and therefore any misalignment may result in a malfunction in which the light emitting element LE does not light up. In contrast, in the present disclosure, each of the plurality of light emitting elements LE only needs to be located on the organic pattern layer BOL for pseudo-adhesion in the opening OA defined by the bank 190, which has an advantage that the accuracy of alignment is not required when bonding is performed by eutectic bonding.

[0164] Furthermore, in the case of eutectic bonding, heat and pressure are required to bond the bonding electrode of each of the plurality of light emitting elements LE and the bonding electrode of each of the pixel electrodes PXE, but the light emitting element LE may be tilted or damaged by the heat and pressure. In contrast, in the present disclosure, heat and pressure are not required, which has the advantage that the light emitting element LE is not tilted or damaged by the heat and pressure. In each of the sub-pixels SPX1, SPX2, SPX3, and SPX4, the light emitting element LE may be located on the organic pattern layer BOL. Figure 8 and Fig. 9 As shown in , the light emitting element LE is exemplified as a lateral type micro LED in which both the first contact electrode CTE1 and the second contact electrode CTE2 are located on the top surface of the light emitting element LE.

[0165] Each of the plurality of light emitting elements LE may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light emitting elements LE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of tens to hundreds of micrometers. For example, each of the plurality of light emitting elements LE may have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of approximately 100 μm or less.

[0166] The plurality of light emitting elements LE may be formed by growing on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The plurality of light emitting elements LE may be directly transferred from the semiconductor substrate to the organic pattern layer BOL of the display panel 100. Alternatively, the plurality of light emitting elements LE may be transferred to the organic pattern of the display panel 100 by an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as polydimethylsiloxane (PDMS) or silicon as a transfer substrate.

[0167] Each of the plurality of light emitting elements LE includes a first contact electrode CTE1, a second contact electrode CTE2, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and an undoped semiconductor layer USEM.

[0168] The undoped semiconductor layer USEM may be located on the organic pattern layer BOL. The undoped semiconductor layer USEM may be formed as a semiconductor layer not doped with an N-type dopant or a P-type dopant (i.e., an undoped semiconductor layer). For example, the undoped semiconductor layer USEM may be one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN that are not doped with a dopant. For example, the undoped semiconductor layer USEM may be GaN that is not doped with a dopant.

[0169] The second semiconductor layer SEM2 may be located on the undoped semiconductor layer USEM. The second semiconductor layer SEM2 may be doped with a second conductive dopant such as Si, Ge, Sn, Se, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with N-type Si. The thickness of the second semiconductor layer SEM2 may be approximately 500 nm to approximately 1 μm. The second semiconductor layer SEM2 may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness.

[0170] The active layer MQW may be located on the second semiconductor layer SEM2. For example, the active layer MQW may be located on the first portion of the second semiconductor layer SEM2. The active layer MQW may include a material having a single quantum well structure or a multiple quantum well structure. When the active layer MQW includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer may be formed of InGaN, and the barrier layer may be formed of GaN and / or AlGaN, but is not limited thereto. Alternatively, the active layer MQW may have a structure in which semiconductor materials having high band gap energy and semiconductor materials having low band gap energy are alternately stacked with each other, and may include other III- to V-group semiconductor materials according to the wavelength range of the emitted light.

[0171] When the active layer MQW includes InGaN, the color of the emitted light may vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer MQW may shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer MQW may shift to the blue wavelength band. For example, the content of indium (In) in the active layer MQW of the light emitting element LE that emits the third light (light in the blue wavelength band) may be approximately 10 wt % to approximately 20 wt %.

[0172] The first semiconductor layer SEM1 may be located on the active layer MQW. The first semiconductor layer SEM1 may be one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN doped with a P-type dopant such as Mg, Zn, Ca, Ba, etc. For example, the first semiconductor layer SEM1 may be p-GaN doped with P-type Mg.

[0173] The first contact electrode CTE1 and the second contact electrode CTE2 are respectively located on the two openings. For example, the first contact electrode CTE1 may be located on the opening OP-L1 exposing the first semiconductor layer SEM1 and may contact the first semiconductor layer SEM1. The second contact electrode CTE2 may be located on the opening OP-L2 exposing the second semiconductor layer SEM2 and may contact the second semiconductor layer SEM2.

[0174] The electron blocking layer may be located between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be a layer that inhibits or prevents too many electrons from flowing into the active layer MQW. For example, the electron blocking layer may be AlGaN and / or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0175] The superlattice layer may be located between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN and / or GaN. The superlattice layer may be omitted.

[0176] In one or more embodiments, the light emitting element LE may further include a protective film INS0 to protect the outer surface. The protective film INS0 may be located on the side surface of the first semiconductor layer SEM1, the side surface of the active layer MQW, and the side surface of the second semiconductor layer SEM2. The protective film INS0 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer). The protective film INS0 may be on the entire surface of the light emitting element LE except for the bottom of the light emitting element LE, and may define an opening exposing the first contact electrode CTE1 and the second contact electrode CTE2 on the top surface of the light emitting element LE.

[0177] The third organic layer 191 covers the first auxiliary electrode SCT1, the second auxiliary electrode SCT2, and the bank 190 to flatten the light emitting element LE, and may be formed to a desired height (e.g., a predetermined height). For example, the third organic layer 191 may be formed at a desired height (e.g., a predetermined height) so that at least a portion of the light emitting element LE (such as the first contact electrode CTE1 and the second contact electrode CTE2) may protrude above the third organic layer 191. That is, the height of the third organic layer 191 may be less than the height of the light emitting element LE.

[0178] The third organic layer 191 may include a first electrode opening OA1 penetrating the third organic layer 191 to expose the first auxiliary electrode SCT1 and a second electrode opening OA2 penetrating the third organic layer 191 to expose the second auxiliary electrode SCT2 .

[0179] The first electrode opening OA1 may partially overlap at least a first side of the light emitting element LE. The first side of the light emitting element LE may completely overlap the first electrode opening OA1. For example, the length of the first electrode opening OA1 in the first direction DR1 may be longer than the length of the light emitting element LE in the first direction DR1.

[0180] The second electrode opening OA2 may partially overlap at least the second side of the light emitting element LE. The second side of the light emitting element LE may completely overlap the second electrode opening OA2. For example, the length of the second electrode opening OA2 in the first direction DR1 may be longer than the length of the light emitting element LE in the first direction DR1.

[0181] refer to Figures 8 to 10 , the first conductive wall COL1 is formed by filling the first electrode opening OA1 with a conductive material. Therefore, the first conductive wall COL1 may partially overlap at least the first side of the light emitting element LE. The first side of the light emitting element LE may completely overlap the first conductive wall COL1. For example, the length (width) of the first conductive wall COL1 in the first direction DR1 may be longer than the length (width) of the light emitting element LE (e.g., the first side of the light emitting element LE) in the first direction DR1.

[0182] The first conductive wall COL1 may be in contact with the first auxiliary electrode SCT1 on the top surface of the bank 190. That is, the first conductive wall COL1 may be electrically connected to the pixel electrode PXE through the first auxiliary electrode SCT1 on the top surface of the bank 190. To this end, the first conductive wall COL1 may be connected to the first auxiliary electrode SCT1 connected to the pixel electrode PXE and the first connection electrode BE1 connected to the first contact electrode CTE1 of the light emitting element LE. The first conductive wall COL1 may overlap at least a portion of the first auxiliary electrode SCT1 and at least a portion of the first connection electrode BE1.

[0183] The second conductive wall COL2 is formed by filling the second electrode opening OA2 with a conductive material. Therefore, the second conductive wall COL2 may partially overlap at least the second side of the light emitting element LE. The second side of the light emitting element LE may completely overlap with the second conductive wall COL2. For example, the length (width) of the second conductive wall COL2 in the first direction DR1 may be longer than the length (width) of the light emitting element LE (e.g., the second side of the light emitting element LE) in the first direction DR1.

[0184] The second conductive wall COL2 may be in contact with the second auxiliary electrode SCT2 on the top surface of the bank 190. That is, the second conductive wall COL2 may be electrically connected to the common electrode CE through the second auxiliary electrode SCT2 on the top surface of the bank 190. To this end, the second conductive wall COL2 may be connected to the second auxiliary electrode SCT2 connected to the common electrode CE and the second connection electrode BE2 connected to the second contact electrode CTE2 of the light emitting element LE. The second conductive wall COL2 may overlap at least a portion of the second auxiliary electrode SCT2 and at least a portion of the second connection electrode BE2.

[0185] The area of ​​the pixel electrode PXE may be greater than that of the first link electrode BE1. The area of ​​the common electrode CE within the sub-pixel SPX may be greater than that of the second link electrode BE2.

[0186] The first connection electrode BE1 connects the first contact electrode CTE1 of the light emitting element LE and the first conductive wall COL1. The first connection electrode BE1 may be located on the top and side surfaces of the first contact electrode CTE1 and on the top surface of the first semiconductor layer SEM1. The first connection electrode BE1 extends from the top and side surfaces of the first contact electrode CTE1 and the top surface of the first semiconductor layer SEM1 to the top surface of the first conductive wall COL1.

[0187] The first conductive wall COL1 may be electrically connected to the first contact electrode CTE1 of the light emitting element LE through the first connection electrode BE1 on the top surface of the bank 190. Thus, the first contact electrode CTE1, the first connection electrode BE1, the first conductive wall COL1, the first auxiliary electrode SCT1 and the pixel electrode PXE may be electrically connected.

[0188] The second connection electrode BE2 connects the second contact electrode CTE2 of the light emitting element LE to the second conductive wall COL2. The second connection electrode BE2 may be located on the top surface and the side surface of the second contact electrode CTE2. The second connection electrode BE2 extends from the top surface and the side surface of the second contact electrode CTE2 to the top surface of the second conductive wall COL2. The first connection electrode BE1 and the second connection electrode BE2 may include a transparent conductive oxide.

[0189] The second conductive wall COL2 may be electrically connected to the second contact electrode CTE2 of the light emitting element LE through the second connection electrode BE2 on the top surface of the bank 190. Thus, the second contact electrode CTE2, the second connection electrode BE2, the second conductive wall COL2, the second auxiliary electrode SCT2 and the common electrode CE may be electrically connected.

[0190] The first and second conductive walls COL1 and COL2 may include a conductive material and may further include a light blocking material. The light blocking material may include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0191] In one or more embodiments, the light blocking material may be omitted. When the first and second conductive walls COL1 and COL2 include the light blocking material, light emitted from the light emitting element LE toward the first and second conductive walls COL1 and COL2 may be blocked, thereby reducing light mixing between pixels.

[0192] The first and second connection electrodes BE1 and BE2 may include a transparent metal material (TCO) such as indium tin oxide (ITO) and / or indium zinc oxide (IZO) that may transmit light.

[0193] Fig.10 The first conductive wall COL1 and the second conductive wall COL2 are shown to be arranged to overlap with the first side and the second side of the light emitting element LE, but the present disclosure is not limited thereto. In an embodiment, the first side and the second side of the light emitting element LE may be parallel to each other. For example, Fig.11 As shown in FIG, the first conductive wall COL1 overlaps the first side and the third side adjacent to the first side of the light emitting element LE, and the second conductive wall COL2 may be arranged to overlap the second side and the fourth side adjacent to the second side of the light emitting element LE.

[0194] refer to Fig.11 , the first side of the light emitting element LE and the third side adjacent to the first side completely overlap with the first conductive wall COL1. In one or more embodiments, the first conductive wall COL1 partially overlaps with the first side of the light emitting element LE and the third side adjacent to the first side. The third side and the fourth side may be opposite to each other. The first side and the third side may be perpendicular to each other, the third side may be parallel to the fourth side, and the second side and the fourth side may be perpendicular to each other.

[0195] The second side and the fourth side adjacent to the second side of the light emitting element LE completely overlap the second conductive wall COL2. In one or more embodiments, the second conductive wall COL2 partially overlaps the second side and the fourth side adjacent to the second side of the light emitting element LE.

[0196] like Fig.11As shown in , when the first conductive wall COL1 and the second conductive wall COL2 overlap with the first to fourth sides of the light emitting element LE, most of the light emitted from the light emitting element LE to that side can be blocked, thereby more effectively preventing or reducing mixing with light from other pixels.

[0197] like Fig.12 As shown in , the first conductive wall COL1 and the second conductive wall COL2 overlapping the first side and the second side of the light emitting element LE may be spaced apart from the third conductive wall COL3 and the fourth conductive wall COL4 located on the third side and the fourth side of the light emitting element LE, respectively. Fig.12 , the third and fourth conductive walls COL3 and COL4 are shown as being located within the opening OA, but are not limited thereto and may be located on the bank 190. In an embodiment, the third side of the light emitting element LE may be substantially perpendicular to the first side of the light emitting element LE and substantially parallel to the fourth side of the light emitting element LE.

[0198] For example, returning a reference Figure 8 , the light blocking layer BM may be located on the bank 190. The light blocking layer BM may overlap the bank 190, and may not overlap the plurality of light emitting elements LE.

[0199] The light blocking layer BM may include a first light blocking layer BM1 and a second light blocking layer BM2 stacked in sequence. The length of the first light blocking layer BM1 in the first direction DR1 or the length of the second light blocking layer BM2 in the first direction DR1 or the length of the second light blocking layer BM2 in the second direction DR2. The height of the first light blocking layer BM1 may be greater than the height of the second light blocking layer BM2. The first light blocking layer BM1 and the second light blocking layer BM2 may be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. The first light blocking layer BM1 and the second light blocking layer BM2 may include a light blocking material to reduce or prevent light from a light emitting element LE of one sub-pixel from traveling to an adjacent sub-pixel. For example, the first light blocking layer BM1 and the second light blocking layer BM2 may include an inorganic black pigment or an organic black pigment such as carbon black. The light blocking layer BM may define a light emitting region of the light emitting element LE.

[0200] The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be located on the light emitting element layer EML. The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be located in an area separated by the light blocking layer BM. For example, the first light conversion layer QDL1 may be located on the first capping layer CAP1 in the first sub-pixel SPX1 and the third sub-pixel SPX3, the second light conversion layer QDL2 may be located on the first capping layer CAP1 in the second sub-pixel SPX2, and the light transmission layer TPL may be located on the first capping layer CAP1 in the fourth sub-pixel SPX4.

[0201] The first light conversion layer QDL1 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a first light (e.g., light in a green wavelength band). The first light conversion layer QDL1 may include a first base resin BRS1 and first wavelength conversion particles WCP1. The first base resin BRS1 may include a light-transmitting organic material. For example, the first base resin BRS1 may include an epoxy-based resin, an acrylic-based resin, a carbon-based resin, and / or an imide-based resin. The first wavelength conversion particles WCP1 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a first light (e.g., light in a green wavelength band). The first wavelength conversion particles WCP1 may be quantum dots (QD), quantum rods, fluorescent materials, and / or phosphorescent materials. The first light conversion layer QDL1 may also include a material such as titanium dioxide (TiO 2 ) light diffuser.

[0202] The second light conversion layer QDL2 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a second light (e.g., light in a red wavelength band). The second light conversion layer QDL2 may include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 may include a light-transmitting organic material. For example, the second base resin BRS2 may include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The second wavelength conversion particles WCP2 may convert a portion of the third light (e.g., light in a blue wavelength band) incident from the light emitting element LE into a second light (e.g., light in a red wavelength band). The second wavelength conversion particles WCP2 may be quantum dots (QD), quantum rods, fluorescent materials, and / or phosphorescent materials. The second light conversion layer QDL2 may also include a material such as titanium dioxide (TiO 2 ) light diffuser.

[0203] The light-transmitting layer TPL may include a light-transmitting organic material. For example, the light-transmitting layer TPL may include epoxy resin, acrylic resin, cardo resin, and / or imide resin.

[0204] In one or more embodiments of the present disclosure, a third light conversion layer may be positioned without positioning the light transmission layer TPL. In this case, the third light conversion layer may include a material different from that of the first light conversion layer QDL1 and the second light conversion layer QDL2. For example, the first light conversion layer QDL1 may include quantum dots that convert light in a blue wavelength band into light in a green wavelength band, the second light conversion layer QDL2 may include quantum dots that convert light in a blue wavelength band into light in a red wavelength band, and the third light conversion layer may include a blue phosphor. In addition, each of the first light conversion layer QDL1, the second light conversion layer QDL2, and the third light conversion layer may include quantum dots and a material such as titanium dioxide (TiO 2 ) light diffusing agent. In this case, the titanium dioxide (TiO 2 ) particles may be greater than the titanium dioxide (TiO 2 ) particles or the amount of titanium dioxide (TiO 2 )The number of particles.

[0205] The first capping layer CAP1 may be located between the light emitting element layer EML and the first light conversion layer QDL1, between the light emitting element layer EML and the second light conversion layer QDL2, between the light emitting element layer EML and the light transmission layer TPL, between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light transmission layer TPL. The first capping layer CAP1 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer). The first capping layer CAP1 may be located on the top surface of the light blocking layer BM.

[0206] The reflective layer RF may be located between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light transmission layer TPL. The reflective layer RF may be located on the first capping layer CAP1 positioned on the side of the first light blocking layer BM1 and the side of the second light blocking layer BM2. The reflective layer RF is used to reflect light traveling in a lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL.

[0207] The reflective layer RF may include a highly reflective metal material such as aluminum (Al). The thickness of the reflective layer RF may be approximately 0.1 μm.

[0208] Optionally, the reflective layer RF may include M (M is an integer of 2 or more) pairs of first and second layers having different refractive indices to serve as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer).

[0209] In one embodiment, a capping layer (eg, a second capping layer CAP2), a coating layer (eg, Figure 8 ) and a color filter layer (eg, including a fourth organic layer 192 shown in FIG. Figure 8 The first color filter CF1, the second color filter CF2, and the third color filter CF3 described in the foregoing). The second capping layer CAP2 may be located on the first capping layer CAP1, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL. The second capping layer CAP2 may be formed of an inorganic film (e.g., a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer).

[0210] Because the first capping layer CAP1 and the second capping layer CAP2 are used to protect the first wavelength conversion particles WCP1 in the first light conversion layer QDL1 and the second wavelength conversion particles WCP2 in the second light conversion layer QDL2 from moisture and / or oxygen, the first light conversion layer QDL1, the second light conversion layer QDL2 and the light transmission layer TPL can be encapsulated by the first capping layer CAP1 and the second capping layer CAP2.

[0211] In addition, the first capping layer CAP1 and the second capping layer CAP2 may be formed of a low refractive index material having a lower refractive index than the fourth organic layer 192. In this case, total reflection of light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 in the first capping layer CAP1 and the second capping layer CAP2 may be prevented or minimized. Therefore, the light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 may be focused on the top of the first light conversion layer QDL1 or the second light conversion layer QDL2. For example, the refractive index of at least one of the first capping layer CAP1 and the second capping layer CAP2 may be approximately 1.1 to approximately 1.5, and the refractive index of each of the first base resin BRS1 of the first light conversion layer QDL1, the second base resin BRS2 of the second light conversion layer QDL2, and the light transmission layer TPL may be approximately 1.5 to approximately 2.0.

[0212] Alternatively, the fourth organic layer 192 may also be formed of a low refractive index material, in which case the light converted by the first light conversion layer QDL1 or the second light conversion layer QDL2 may be prevented, reduced, or minimized from being transmitted by the fourth organic layer 192. Therefore, the light converted in the first light conversion layer QDL1 or the second light conversion layer QDL2 may be focused on the top of the first light conversion layer QDL1 or the second light conversion layer QDL2.

[0213] The fourth organic layer 192 may be located on the second capping layer CAP2. The fourth organic layer 192 may be formed of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0214] When the light emitting element LE of the first sub-pixel SPX1, the light emitting element LE of the second sub-pixel SPX2, and the light emitting element LE of the third sub-pixel SPX3 emit light in the blue wavelength band, the first light conversion layer QDL1 and the second light conversion layer QDL2 are required for wavelength conversion. However, the present disclosure is not limited thereto, and when the light emitting element LE of the first sub-pixel SPX1 emits light of a first color, and the light emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light emitting element LE of the third sub-pixel SPX3 emits light of a third color, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmission layer TPL may be omitted.

[0215] Optionally, when the light emitting element LE of the first subpixel SPX1 emits light of a first color, the light emitting element LE of the second subpixel SPX2 emits light of a second color, and the light emitting element LE of the third subpixel SPX3 emits light of a third color, the first light conversion layer QDL1 and the second light conversion layer QDL may include phosphor particles instead of wavelength conversion particles to improve color purity.

[0216] A plurality of color filters CF1, CF2, and CF3 may be positioned on the fourth organic layer 192. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0217] The first color filter CF1 located in the first subpixel SPX1 and the third subpixel SPX3 transmits the first light (e.g., light in the green wavelength band), and absorbs or blocks the third light (e.g., light in the blue wavelength band). Therefore, the first color filter CF1 can transmit the first light (e.g., light in the green wavelength band) converted by the first light conversion layer QDL1 from the third light (e.g., light in the blue wavelength band) emitted by the light emitting element LE, and absorb and / or block the third light (e.g., light in the blue wavelength band) not converted by the first light conversion layer QDL1. Therefore, the first subpixel SPX1 can emit the first light (e.g., light in the green wavelength band).

[0218] The second color filter CF2 located in the second sub-pixel SPX2 can transmit the second light (e.g., light in the red wavelength band) and absorb or block the third light (e.g., light in the blue wavelength band). Therefore, the second color filter CF2 can transmit the second light (e.g., light in the red wavelength band) converted by the second light conversion layer QDL2 from the third light (e.g., light in the blue wavelength band) emitted by the light-emitting element LE, and absorb and / or block the third light (e.g., light in the blue wavelength band) not converted by the second light conversion layer QDL2. Therefore, the second sub-pixel SPX2 can emit the second light (e.g., light in the red wavelength band).

[0219] The third color filter CF3 located in the fourth subpixel SPX4 can transmit the third light (e.g., light in the blue wavelength band). Therefore, the third color filter CF3 can transmit the third light (e.g., light in the blue wavelength band) emitted by the light emitting element LE through the light transmission layer TPL. Therefore, the fourth subpixel SPX4 can emit the third light (e.g., light in the blue wavelength band).

[0220] The area where the first, second, and third color filters CF1, CF2, and CF3 overlap may serve as a light blocking area.The area where the first, second, and third color filters CF1, CF2, and CF3 overlap may overlap the bank 190 and the light blocking layer BM.

[0221] A fifth organic layer 193 for planarization may be positioned on the plurality of color filters CF1, CF2, and CF3. The fifth organic layer 193 may be formed of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

[0222] refer to Figure 8 and Fig. 9 When the light emitting element LE, the pixel electrode PXE and the common electrode CE are electrically connected, the connection electrodes BE1 and BE2 are not located in the connection holes that directly expose the pixel electrode PXE and the common electrode CE, but the connection holes are formed with a conductive material. Therefore, the possibility of disconnection of the connection electrodes BE1 and BE2 can be reduced or prevented, thereby reducing or preventing the light emitting element LE from not emitting light.

[0223] In one or more embodiments, the third subpixel SPX3 may be formed substantially the same as the first subpixel SPX1. Therefore, a description of the third subpixel SPX3 is omitted.

[0224] Fig.13 is a flowchart illustrating a method of manufacturing a display device according to one or more embodiments. Figures 14 to 22 is a cross-sectional view illustrating a method of manufacturing a display device according to one or more embodiments. Figures 14 to 22 Shown is a reference Fig. 9 An example of a cross-sectional view of a display device is described.

[0225] First, if Fig.14 As shown in FIG. , a plurality of light emitting elements LE ( Fig.13 , or step S110 in the above process.

[0226] A plurality of light emitting elements LE are positioned on an adhesive layer located on a light emitting element substrate ESUB. The plurality of light emitting elements LE are adhered and fixed to the adhesive layer. The light emitting element substrate ESUB may include a material that allows light to be transmitted. For example, the light emitting element substrate ESUB may include a first supporting layer and an adhesive layer. The first supporting layer may include a transparent polymer such as polyimide, polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesive layer may include an adhesive material for bonding the plurality of light emitting elements LE. For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc.

[0227] A plurality of light emitting elements LE grown on a semiconductor substrate can be transferred to a light emitting element substrate ESUB. A known method can be used as a transfer method.

[0228] Second, a pixel electrode PXE, a common electrode CE and a bank 190 are formed on the substrate using a mask. Fig.13 , or step S120 in the above procedure.

[0229] Here, the substrate may include Figure 8 The thin film transistor layer TFTL is described. The second organic layer 180 may be positioned on the thin film transistor layer TFTL.

[0230] Therefore, reference Fig.15 and Fig.16 , a pixel electrode PXE and a common electrode CE are formed on the second organic layer 180 using a photolithography process, and then a bank 190 is formed. Each of the pixel electrodes PXE is located at a corresponding connection hole ( Figure 8 CT) in the middle, and a common electrode CE spaced apart from the pixel electrode PXE is formed.

[0231] Thereafter, a bank 190 having an opening OA exposing at least a portion of the pixel electrode PXE and the common electrode CE is formed.

[0232] Third, reference Fig.17 , a first auxiliary electrode SCT1 and a second auxiliary electrode SCT2 are formed by a photolithography process ( Fig.13 , or step S130 in the above procedure.

[0233] The first auxiliary electrode SCT1 is formed to extend from the pixel electrode PXE to the top surface of the bank 190. The first auxiliary electrode SCT1 is in direct contact with the pixel electrode PXE.

[0234] The second auxiliary electrode SCT2 is formed to extend from the common electrode CE to the top surface of the bank 190. The second auxiliary electrode SCT2 is in direct contact with the common electrode CE.

[0235] Fourth, if Fig.18 and Fig.19 As shown in FIG. 1 , an organic pattern layer BOL is formed on the pixel electrode PXE and the common electrode CE in the opening OA, and the light emitting element LE on the light emitting element substrate ESUB is fixed to the organic pattern layer BOL ( Fig.13 , or step S140 in the above procedure.

[0236] First, the organic pattern layer BOL may be a temporary adhesive layer and / or a temporary fixing layer for temporarily fixing or adhering the plurality of light emitting elements LE for a process of transferring the plurality of light emitting elements LE to the display panel 100. The thickness of the organic pattern layer BOL may be less than the height of the opening OA or the thickness of the bank 190.

[0237] The organic pattern layer BOL may be a photosensitive organic layer such as a photoresist. Alternatively, the organic pattern layer BOL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, or the like.

[0238] Then, a plurality of light emitting elements LE on the light emitting element substrate ESUB are fixed to the organic pattern layer BOL.

[0239] For example, a stamp may be used to fix a plurality of light emitting elements LE on a light emitting element substrate ESUB to an organic pattern layer BOL. Here, a stamp including an adhesive layer having high adhesion compared to the adhesive layer of the light emitting element substrate ESUB may detach the plurality of light emitting elements LE from the adhesive layer. Each of the plurality of light emitting elements LE detached from the light emitting element substrate ESUB and transferred to the stamp may be temporarily fixed by being embedded in the organic pattern layer BOL. At this time, a portion of each of the plurality of light emitting elements LE may be temporarily fixed by being embedded in the organic pattern layer BOL. For example, an undoped semiconductor layer USEM of each of the plurality of light emitting elements LE may be embedded and fixed in the organic pattern layer BOL.

[0240] When the organic pattern layer BOL is a photosensitive organic layer such as a photoresist, after curing (e.g., soft baking) the organic pattern layer BOL at a first temperature, at least a portion of each of the plurality of light emitting elements LE may be inserted into the organic pattern layer BOL, and then the organic pattern layer BOL may be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the present disclosure is not limited thereto. In the process of curing the organic pattern layer BOL at the first temperature, because the first temperature is low enough to not completely cure the organic pattern layer BOL, the organic pattern layer BOL is fluid, which allows the organic pattern layer BOL to spread throughout the opening OA. In addition, the process of completely curing the organic pattern layer BOL at the second temperature may be performed for approximately 30 minutes.

[0241] Alternatively, since at least a portion of the light emitting element LE may be inserted and embedded in the organic pattern layer BOL, the organic pattern layer BOL remains between the bottom surface of the light emitting element LE and the pixel electrode PXE and between the bottom surface of the light emitting element LE and the common electrode CE.

[0242] Alternatively, if the organic pattern layer BOL has a large fluidity, the organic pattern layer BOL may be pushed to the edge of the opening OA by the light emitting element LE, in which case the organic pattern layer BOL may be removed between the lower side of the light emitting element LE and the pixel electrode PXE and between the lower side of the light emitting element LE and the common electrode CE, or the organic pattern layer BOL may be positioned at a very small height. That is, the organic pattern layer BOL may not be located between the bottom surface of the light emitting element LE and the pixel electrode PXE and / or between the bottom surface of the light emitting element LE and the common electrode CE, and / or may be located at a very small height.

[0243] Alternatively, if the fluidity of the organic pattern layer BOL is low or the organic pattern layer BOL is hard, the depth of the light emitting element LE inserted or embedded in the organic pattern layer BOL may be very small, or the light emitting element LE may not be inserted or embedded in the organic pattern layer BOL but may be placed on the organic pattern layer BOL.

[0244] Then, by applying heat to the adhesive layer of the stamp to reduce the adhesiveness of the adhesive layer, the stamp can be separated from the plurality of light emitting elements LE.

[0245] Fifth, if Fig. 20 and Fig.21 As shown in FIG. 1 , a third organic layer 191, a first conductive wall COL1 and a second conductive wall COL2 are formed. Fig.13 , or step S150 in the above process.

[0246] First, a third organic layer 191 having a first electrode opening OA1 and a second electrode opening OA2 is formed. The third organic layer 191 may be formed to cover the bank 190, the first auxiliary electrode SCT1, and the second auxiliary electrode SCT2. The third organic layer 191 may be formed to planarize a step caused by the light emitting element LE, but to expose at least a portion of the light emitting element LE, for example, to expose the first contact electrode CTE1 and the second contact electrode CTE2.

[0247] The first electrode opening OA1 may be formed to overlap the bank 190 and completely penetrate the third organic layer 191 to expose a portion of the first auxiliary electrode SCT1. The second electrode opening OA2 may be formed to overlap the bank 190 and completely penetrate the third organic layer 191 to expose a portion of the second auxiliary electrode SCT2.

[0248] As reference Figures 9 and 10 As described, the first electrode opening OA1 and the second electrode opening OA2 may be formed to overlap one surface of the light emitting element LE. The first surface and the second surface opposite to the first surface of the light emitting element LE completely overlap the first electrode opening OA1 and the second electrode opening OA2, respectively.

[0249] Subsequently, the first electrode opening OA1 and the second electrode opening OA2 may be filled with a filling material including a conductive material to form a first conductive wall COL1 and a second conductive wall COL2. The filling material may include a light blocking material. For example, the light blocking material may include an inorganic black pigment such as carbon black and / or an organic black pigment. The light blocking material may be omitted, but when the first conductive wall COL1 and the second conductive wall COL2 are formed of a filling material including a light blocking material, it is beneficial to prevent light from a light emitting element LE of one sub-pixel from traveling to an adjacent sub-pixel.

[0250] Sixth, if Fig. 22 As shown in FIG. 1 , a first connection electrode BE1 and a second connection electrode BE2 are formed using a photolithography process. Fig.13 , or step S160 in the above procedure.

[0251] The first connection electrode BE1 connects the first contact electrode CTE1 of the light emitting element LE and the first conductive wall COL1. The second connection electrode BE2 connects the second contact electrode CTE2 of the light emitting element LE and the common electrode CE.

[0252] Then, the light blocking layer BM and the fourth organic layer 192 are sequentially formed.

[0253] A first light blocking layer BM1 of the light blocking layer BM may be formed on the bank 190 , and a second light blocking layer BM2 of the light blocking layer BM may be formed on the first light blocking layer BM1 .

[0254] exist Figure 8 , it is shown that the length of the bottom surface of the second light blocking layer BM2 in the first direction DR1 is shorter than the length of the top surface of the first light blocking layer BM1 in the first direction DR1, thereby forming a step extending to the side of the first light blocking layer BM1, a portion of the top surface of the first light blocking layer BM1, and the side of the second light blocking layer BM2, but the present disclosure is not limited thereto. For example, the length of the bottom surface of the second light blocking layer BM2 in the first direction DR1 is substantially the same as the length of the top surface of the first light blocking layer BM1 in the first direction DR1, so that the side of the first light blocking layer BM1 and the side of the second light blocking layer BM2 can be connected without the above step. Optionally, the length of the bottom surface of the second light blocking layer BM2 in the first direction DR1 is substantially the same as the length of the top surface of the first light blocking layer BM1 in the first direction DR1, but the angle at which the side of the first light blocking layer BM1 is inclined relative to the bottom side of the first light blocking layer BM1 and the angle at which the side of the second light blocking layer BM2 is inclined relative to the bottom side of the second light blocking layer BM2 may be different. When the step is reduced or eliminated, the occurrence of uneven light reflection such as light leakage due to diffuse reflection of light can be reduced, prevented or minimized.

[0255] The fourth organic layer 192 may be formed to cover the light emitting element LE in a region partitioned by the light blocking layer BM.

[0256] Then, if Figure 8 As shown in the figure, a first light conversion layer QDL1, a second light conversion layer QDL2 and a light transmitting layer TPL are formed on the fourth organic layer 192, and color filters CF1, CF2 and CF3 are formed on the first light conversion layer QDL1, the second light conversion layer QDL2 and the light transmitting layer TPL in the area separated by the light blocking layer BM.

[0257] First, the first capping layer CAP1 covering the light emitting element layer EML and the light blocking layer BM is formed, and the reflective layer RF is formed on the first capping layer CAP1 on the side of the light blocking layer BM.

[0258] Then, in the area separated by the light blocking layer BM, a first light conversion layer QDL1 is formed in the area corresponding to the first subpixel SPX1, a second light conversion layer QDL2 is formed in the area corresponding to the second subpixel SPX2, and a light transmission layer TPL is formed in the area corresponding to the fourth subpixel SPX4.

[0259] Then, a second capping layer CAP2 is formed on the first capping layer CAP1 , the first light conversion layer QDL1 , the second light conversion layer QDL2 , and the light transmitting layer TPL, and a fourth organic layer 192 is formed on the second capping layer CAP2 .

[0260] Then, a plurality of color filters CF1 , CF2 , and CF3 are formed on the fourth organic layer 192 , and a fifth organic layer 193 is formed on the plurality of color filters CF1 , CF2 , and CF3 .

[0261] Fig.23 A virtual reality device 1 using a display device 10 - 1 according to one or more embodiments is shown.

[0262] refer to Fig.23 The virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10-1, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, left legs 30a and right legs 30b, a reflective member 40, and a display device housing 50.

[0263] Fig.23 The virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be mounted on the head of a user without including the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Fig.23 The examples shown in and can be applied in various forms and can be applied in various electronic devices.

[0264] The display device housing 50 can accommodate the display device 10-1 and the reflective member 40. The image displayed on the display device 10-1 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can watch the virtual reality image displayed on the display device 10-1 through the right eye.

[0265] Fig.23 The display device housing 50 is shown to be located at the right end of the support frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 may be located at the left end of the support frame 20. In this case, the image displayed on the display device 10-1 may be reflected from the reflective member 40 and provided to the user's left eye via the left eye lens 10a. Therefore, the user can view the virtual reality image displayed on the display device 10-1 via the left eye. As another example, the display device housing 50 may be located at each of the left and right ends of the support frame 20. In this case, the user can view the virtual reality image displayed on the display device 10-1 via both the left eye and the right eye.

[0266] Fig.24 A smart device including a display device according to one or more embodiments is shown.

[0267] refer to Fig.24 The display device 10 - 2 according to one or more embodiments may be applied to a smart watch 2 which is one of smart devices.

[0268] Fig.25 A vehicle in which a display device according to one or more embodiments is used is shown.

[0269] refer to Fig.25 The display device 10_a, 10_b or 10_c according to one or more embodiments may be applied to a dashboard of a vehicle, to a central instrument panel of a vehicle, or to a central information display (CID) located on a dashboard of a vehicle, respectively. In addition, each of the display devices 10_d and 10_e according to one or more embodiments may be applied to each interior mirror display that replaces each of the side mirrors of the vehicle.

[0270] Fig.26 is an exemplary diagram showing a transparent display device including a display device according to one or more embodiments.

[0271] refer to Fig.26 , the display device 10-3 according to one or more embodiments may be applied to a transparent display device. The transparent display device may transmit light therethrough while displaying an image IM thereon. Therefore, a user located in front of the transparent display device may not only view the image IM displayed on the display device 10, but may also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 8 The substrate SUB of the display device 10 shown in FIG. 1 may include a light-transmitting portion through which light is transmitted, or may be made of a material through which light is transmitted.

[0272] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles and scope of the present disclosure. Therefore, the embodiments of the present disclosure are used in a general and descriptive sense only and not for a limiting purpose.

[0273] However, the aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the claims (and functional equivalents of the claims should be included therein).

Claims

1. A display device, comprising: substrate; a pixel electrode and a common electrode spaced apart from each other on the substrate; an organic pattern layer, between the pixel electrode and the common electrode; a light emitting element over the organic pattern layer and including a first contact electrode and a second contact electrode on a top surface of the light emitting element; an organic layer located in a region other than a region where the light emitting element is located and having a first electrode opening and a second electrode opening; a first conductive wall in the first electrode opening and electrically connected to the pixel electrode; a second conductive wall in the second electrode opening and electrically connected to the common electrode; as well as A first connection electrode and a second connection electrode, the first connection electrode being connected to the first contact electrode of the light emitting element and the first conductive wall, and the second connection electrode being connected to the second contact electrode of the light emitting element and the second conductive wall.

2. The display device according to claim 1, further comprising: a bank covering edges of the pixel electrode and the common electrode and in an area except an area where the organic pattern layer is located; a first auxiliary electrode extending from the pixel electrode to above the top surface of the bank; as well as a second auxiliary electrode extending from the common electrode to above the top surface of the bank, wherein the first electrode opening exposes the first auxiliary electrode, and The second electrode opening exposes the second auxiliary electrode.

3. The display device according to claim 2, wherein: The first conductive wall contacts the first auxiliary electrode through the first electrode opening, and The second conductive wall contacts the second auxiliary electrode through the second electrode opening.

4. The display device according to claim 3, wherein: The first conductive wall and the second conductive wall include a light blocking material.

5. The display device according to claim 4, wherein: The first conductive wall overlaps with a first side of the light emitting element, and the first side of the light emitting element completely overlaps with the first conductive wall, wherein the second conductive wall overlaps with the second side of the light emitting element, and the second side of the light emitting element completely overlaps with the second conductive wall, and Wherein, the first side and the second side are parallel to each other.

6. The display device according to claim 5, wherein: The width of the first conductive wall is greater than the width of the first side of the light emitting element, and Wherein, the width of the second conductive wall is greater than the width of the second side of the light emitting element.

7. The display device according to claim 5, wherein: The first conductive wall overlaps with the third side of the light emitting element and is spaced apart from the second conductive wall, wherein the second conductive wall overlaps with the fourth side of the light emitting element and is spaced apart from the first conductive wall, and The third side is perpendicular to the first side and parallel to the fourth side.

8. The display device according to claim 5, further comprising: a third conductive wall overlapping a third side of the light emitting element and spaced apart from the first conductive wall and the second conductive wall; as well as a fourth conductive wall overlapping a fourth side of the light emitting element and spaced apart from the first conductive wall and the second conductive wall, wherein the third side of the light emitting element completely overlaps with the third conductive wall, wherein the fourth side of the light emitting element completely overlaps with the fourth conductive wall, and The third side is perpendicular to the first side and parallel to the fourth side.

9. The display device according to claim 1, wherein: The light emitting element further includes a third semiconductor layer, a second semiconductor layer, an active layer, a first semiconductor layer and a protective layer. Wherein, the third semiconductor layer is in contact with the organic pattern layer, and The protective layer is on the entire surface of the light emitting element except for the bottom of the light emitting element, and defines an opening on the top surface of the light emitting element that exposes the first contact electrode and the second contact electrode.

10. The display device according to claim 1, wherein: The pixel electrode and the common electrode include an opaque metal material, and Wherein, the first connecting electrode and the second connecting electrode include transparent conductive oxide.

11. The display device according to claim 1, wherein: The width of the organic pattern layer is greater than the width of the light emitting element.

12. The display device according to claim 2, further comprising: a light blocking layer, on the first connection electrode and the second connection electrode, overlapping the bank and defining a light emitting area of ​​the light emitting element; as well as A light conversion layer or a light transmission layer is in the space defined by the light blocking layer. 13 . The display device of claim 12 , further comprising a capping layer, an overcoat layer, and a color filter layer sequentially over the light conversion layer and the light blocking layer.

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