Display device and method of manufacturing same

Abstract

The invention provides a display device and a method of manufacturing the same. The display device may include a substrate including a display area and a peripheral area outside the display area; a pixel circuit layer disposed in the display area on the substrate and including a thin film transistor and a plurality of insulating layers; a light emitting element layer disposed on the substrate in the display area and including a light emitting element electrically connected to the thin film transistor; an encapsulation layer disposed on the light emitting element layer; and a pattern portion disposed on the substrate in a portion of the peripheral region. The upper surface of the pattern portion may have an uneven structure.

Description

Technical Field

[0001] Embodiments relate to a display device and a method of manufacturing the display device. Background Art

[0002] The display device may be manufactured (or provided) by a process including forming a light emitting element layer and a pixel circuit layer including a thin film transistor, etc. on a substrate, etc. A protective film, etc. may be used to protect the light emitting element layer during the sequential manufacturing process of the display device.

[0003] Since the demand for display devices having various shapes has increased and there are limitations on protecting display devices of various shapes using a protective film due to limitations in processing the various shapes of display devices, methods for effectively protecting display devices during a manufacturing process of the display devices are being studied. Summary of the invention

[0004] The embodiment provides a display device having improved reliability.

[0005] Embodiments also provide a method of manufacturing a display device having improved reliability.

[0006] Additional features of example embodiments will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of example embodiments.

[0007] The display device according to the embodiment may include: a substrate including a display area and a peripheral area outside the display area; a pixel circuit layer provided in the display area, on the substrate and including a thin film transistor and a plurality of insulating layers; a light emitting element layer provided in the display area, on the substrate and including a light emitting element electrically connected to the thin film transistor; an encapsulation layer provided on the light emitting element layer; and a pattern portion provided in a portion of the peripheral area, on the substrate. The upper surface of the pattern portion may have an uneven structure.

[0008] In an embodiment, the pattern portion may include a plurality of protrusions spaced apart from each other and grooves defining the plurality of protrusions.

[0009] In an embodiment, a distance between adjacent protrusions among the plurality of protrusions may be in a range of about 10 μm to about 50 μm.

[0010] In an embodiment, each of the plurality of protrusions may have a rectangular shape in a cross-sectional view.

[0011] In an embodiment, each of the plurality of protrusions may have an inverted tapered shape in a cross-sectional view.

[0012] In an embodiment, a bottom surface of the groove may have an insulating property.

[0013] In an embodiment, the light emitting element may include a pixel electrode, an emission layer and a common electrode. The common electrode may extend from the display area to the peripheral area. In the peripheral area, a portion of the pattern portion may overlap a portion of the common electrode.

[0014] In an embodiment, in a region where the portion of the pattern portion overlaps the portion of the common electrode, a bottom surface of the groove may be spaced apart from an upper surface of the common electrode in an upward direction.

[0015] In an embodiment, the encapsulation layer may include a first inorganic encapsulation layer disposed on the light emitting element layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer, the first inorganic encapsulation layer, and the second inorganic encapsulation layer may extend from the display area to the peripheral area. At least the uppermost layer of the at least one insulating layer may define a groove of the pattern portion in the peripheral area.

[0016] In an embodiment, the pattern portion may be disposed to correspond to a corner portion of the display area.

[0017] In an embodiment, the substrate may further include a pad area located at least on one side of the display area. The peripheral area may include a first peripheral area between the display area and the pad area and a second peripheral area spaced apart from the pad area. The pattern portion may be disposed in the second peripheral area of ​​the peripheral area.

[0018] In an embodiment, the pattern portion may be close to an edge of the substrate.

[0019] In an embodiment, the pattern portion may be continuously disposed from a first virtual line to a second virtual line. The first virtual line may be spaced apart from the display area in an outward direction and may be located in the peripheral area. The second virtual line may be located at an edge of the substrate.

[0020] In an embodiment, the display device may further include a first dam portion disposed in the peripheral region, on the substrate, spaced apart from the display region in an outward direction, and surrounding the display region. The pattern portion may overlap the first dam portion.

[0021] In an embodiment, the display device may further include a crack prevention portion disposed in the peripheral region, on the substrate, and spaced apart from the first dam portion in an outward direction. The pattern portion may further overlap the crack prevention portion.

[0022] In an embodiment, the display device may further include a second dam portion disposed in the peripheral region, on the substrate, and spaced apart from the crack prevention portion in an outward direction. The pattern portion may further overlap the second dam portion.

[0023] In an embodiment, the display device may further include an anti-reflection member disposed on the encapsulation layer.

[0024] The method for manufacturing a display device may include: forming a pixel circuit layer, a light emitting element layer, and an encapsulation layer on a mother substrate including a plurality of unit areas; forming a pattern portion in a peripheral area of ​​each of the plurality of unit areas; forming a protective layer by providing a protective layer resin on the encapsulation layer and the pattern portion of each of the plurality of unit areas; obtaining a plurality of display panels by cutting along a cutting line, the cutting line being defined along an edge of each of the plurality of unit areas; and removing the protective layer from each of the plurality of display panels. Each of the plurality of unit areas may include a display area and a peripheral area outside the display area. The upper surface of the pattern portion may have an uneven structure.

[0025] In an embodiment, at least one insulating layer among the plurality of insulating layers included in the pixel circuit layer and the at least one inorganic encapsulation layer included in the encapsulation layer may extend from the display area to the peripheral area. The formation of the pattern portion may include forming a plurality of protrusions and grooves defining the plurality of protrusions by partially etching the at least one insulating layer in the peripheral area.

[0026] In an embodiment, the forming of the protective layer may include curing the protective layer resin by exposing the provided protective layer resin to ultraviolet light.

[0027] In an embodiment, the forming of the protection layer may include providing the protection layer resin such that an edge of the protection layer resin is located on the pattern portion.

[0028] In an embodiment, the method may further include providing an anti-reflection member on each of the plurality of display panels from which the protective layer has been removed.

[0029] The embodiments of the present disclosure support preventing a protective layer formed on a display panel and later removed during a manufacturing process of a display device from remaining on the display panel or reducing the amount of the protective layer remaining on the display panel. Accordingly, the reliability of the display device can be improved.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the embodiments of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of example aspects supported by the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments supported by the disclosure and together with the description serve to explain example aspects supported by the disclosure.

[0032] Figure 1 is a perspective view showing a display device according to an embodiment.

[0033] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0034] Figure 3 It is shown that the Figure 1 A plan view of an example of a display panel in a display device.

[0035] Figure 4 It is shown that the Figure 1 A plan view of another example of a display panel in a display device.

[0036] Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II'.

[0037] Figure 6 It is shown along Figure 3 A cross-sectional view of the example taken along line III-III'.

[0038] Figure 7 It is shown Figure 6 A perspective view of an example of area "A".

[0039] Figure 8 It is shown Figure 6 A perspective view of another example of area "A".

[0040] Fig. 9 It is shown along Figure 3 A cross-sectional view of another example taken along line III-III'.

[0041] Fig.10 It is shown along Figure 3 A cross-sectional view of yet another example taken along line III-III'.

[0042] Fig.11 and Fig.12 is a cross-sectional view showing a display panel according to an embodiment.

[0043] Fig.13 and Fig.14 is a cross-sectional view showing a display panel according to an embodiment.

[0044] Figures 15 to 21 is a diagram illustrating a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0045] The exemplary aspects of the present disclosure will now be more fully described below with reference to the accompanying drawings in which various embodiments are shown. However, the exemplary aspects supported by the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, the exemplary embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the exemplary aspects of the present disclosure to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0046] It will be understood that when an element is referred to as being associated with another element (e.g., being "on" another element), the element can be directly on the other element or intervening elements can exist between the element and the other element. Conversely, when an element is referred to as being associated with another element (e.g., being "directly on" another element), there are no intervening elements present.

[0047] It will be understood that although the terms "first", "second", and "third", etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, the first element, component, region, layer, or portion discussed below may be referred to as a second element, component, region, layer, or portion without departing from the teachings herein.

[0048] The terms used in this article are only used for the purpose of describing specific embodiments, and are not intended to be restrictive. As used in this article, "one", "the (described)" and "at least one" do not represent the limitation of quantity, and are intended to include both the singular and the plural, unless the context clearly indicates otherwise. For example, "element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as being limited to "one". "Or" means "and / or". As used in this article, reference numerals can indicate single elements or multiple elements. For example, the reference numerals marking the elements in the singular form in the drawings can be used to reference multiple single elements mentioned above in the text of the specification.

[0049] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that when used in this specification, the terms "include" and / or "comprise" or "contain" and / or "have" indicate the presence of the described features, regions, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, parts and / or groups thereof.

[0050] In addition, relative terms such as, for example, "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the accompanying drawings, relative terms are intended to include different orientations of the device. For example, if the device in one of the accompanying drawings is turned over, the element described as being on the "lower" side of the other element will then be oriented on the "upper" side of the other element. Therefore, depending on the specific orientation of the accompanying drawings, the term "lower" may include both "lower" and "upper" orientations. Similarly, if the device in one of the accompanying drawings is turned over, the element described as being "below" or "below" of the other element will then be oriented "above" the other element. Therefore, the term "below" or "below" may include both upper and lower orientations.

[0051] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] As used herein, the term "substantially" means approximately or virtually. The term "substantially equal" means approximately or virtually equal. The term "substantially the same" means approximately or virtually the same. The term "substantially perpendicular" means approximately or virtually perpendicular. The term "substantially parallel" means approximately or virtually parallel.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the present disclosure, and unless explicitly defined as such in this article, these terms will not be interpreted in an idealized or overly formal sense.

[0054] In this article, embodiments are described with reference to cross-sectional views that are schematic diagrams of example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances should be expected. Therefore, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but should include deviations in shapes, for example, caused by manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the current claims.

[0055] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0056] Figure 1 is a perspective view showing a display device 10 according to the embodiment.

[0057] refer to Figure 1 In an embodiment, the display device 10 may have a display surface defined by a first direction DR1 and a second direction DR2 crossing the first direction DR1. The display device 10 may display an image in a third direction DR3 through the display surface. The third direction DR3 may be substantially parallel to the normal direction of the display surface. The display surface may correspond to the front surface (or upper surface) of the display device 10.

[0058] The display device 10 may include a display area DA and a peripheral area PA. An image may be displayed in the display area DA.

[0059] The peripheral area PA may be located around the display area DA. The peripheral area PA may be located outside the display area DA. For example, in a plan view, the peripheral area PA may surround the display area DA.

[0060] The display device 10 may include a display panel 100 and an anti-reflection member 200. A plurality of pixels for generating an image may be disposed in a display area DA of the display panel 100.

[0061] Each of the pixels may include a pixel circuit and a light emitting element. The pixel circuit may include at least one thin film transistor and at least one capacitor. The thin film transistor may generate a drive current, and the generated drive current may be provided to the light emitting element. The light emitting element may emit light based on the drive current. For example, the light emitting element may include an organic light emitting diode, an inorganic light emitting diode, or a quantum dot light emitting diode, etc. An image may be generated by combining the light emitted from each of the pixels.

[0062] The anti-reflection member 200 may be disposed on the display panel 100. The anti-reflection member 200 may reduce reflectivity with respect to external light incident to the anti-reflection member 200 from the outside of the display device 10. In other words, the anti-reflection member 200 may reduce reflectivity of the display device 10 to external light. The anti-reflection member 200 may include a polarizer, a retarder, a destructive interference structure, a plurality of color filters, or the like.

[0063] In an embodiment, a cover window (not shown) may be provided on the anti-reflection member 200. The cover window may be transparent.

[0064] Figure 2 It is along Figure 1 A cross-sectional view taken along line II'.

[0065] In the following, reference will be made to Figure 1 and Figure 2 The display area DA of the display device 10 is described in detail.

[0066] refer to Figure 1 and Figure 2 In an embodiment, the display panel 100 may include a substrate 110, a pixel circuit layer PCL, a light emitting element layer EDL, and an encapsulation layer 140. The pixel circuit layer PCL may include a pixel circuit PC and a plurality of insulating layers 120, 132, 134, and 136. The pixel circuit PC may include at least one thin film transistor TR and at least one capacitor (not shown). The light emitting element layer EDL may include a light emitting element ED and a pixel defining layer 138. The light emitting element ED may include a pixel electrode AE, an emission layer EL, and a common electrode CE. The pixel circuit PC and the light emitting element ED may form a pixel PX. The anti-reflection member 200 may be disposed on the encapsulation layer 140.

[0067] The substrate 110 may be an insulating substrate including or made of a transparent material or an opaque material. In an embodiment, the substrate 110 may be a rigid substrate including a material such as, for example, glass or quartz. In another embodiment, the substrate 110 may be a flexible substrate including plastic. Similar to the display device 10, the substrate 110 may also include a display area DA and a peripheral area PA outside the display area DA.

[0068] The buffer layer 120 may be disposed on the substrate 110. The buffer layer 120 may prevent or reduce impurities such as, for example, oxygen or moisture from penetrating through the substrate 110 to the upper portion of the substrate 110. The buffer layer 120 may include an inorganic material. In an embodiment, for example, the buffer layer 120 may include silicon oxide (SiO2). x O y ), silicon nitride (Si x N y ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbonitride (SiC x N y ), aluminum oxide (Al x O y ), aluminum nitride (Al x N y ), Tantalum Oxide (Ta x O y ), Hafnium Oxide (Hf x O y )、Zirconium oxide (Zr x O y) or titanium oxide (Ti x O y ) etc. These materials may be used alone or in combination. The buffer layer 120 may have a single layer structure or a multi-layer structure including a plurality of insulating layers.

[0069] The thin film transistor TR may be disposed on the buffer layer 120. The thin film transistor TR may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0070] The active layer ACT may be disposed on the buffer layer 120. The active layer ACT may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, or the like. In an embodiment, for example, the oxide semiconductor may include at least one of an oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon or polycrystalline silicon, or the like. The active layer ACT may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0071] The gate insulating layer 132 may be disposed on the active layer ACT. The gate insulating layer 132 may cover the active layer ACT on the buffer layer 120. The gate insulating layer 132 may include an inorganic insulating material.

[0072] The gate electrode GE may be disposed on the gate insulating layer 132. The gate electrode GE may overlap with the channel region of the active layer ACT. The gate electrode GE may include a conductive material such as, for example, a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. In an embodiment, for example, the gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum, an alloy containing silver, an alloy containing copper, an alloy containing molybdenum, aluminum nitride (AlN), or the like. x N y ), tungsten nitride (W x N y ), titanium nitride (Ti x N y ), chromium nitride (Cr x N y ), Tantalum Nitride (Ta x N y ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (Zn x O y)、Indium Tin Oxide ("ITO")、Tin Oxide (Sn x O y ), indium oxide (In x O y ), gallium oxide (Ga x O y ) or indium zinc oxide ("IZO"), etc. These materials may be used alone or in combination thereof. The gate electrode GE may have a single-layer structure or a multi-layer structure including a plurality of conductive layers.

[0073] The interlayer insulating layer 134 may be disposed on the gate electrode GE. The interlayer insulating layer 134 may cover the gate electrode GE on the gate insulating layer 132. The interlayer insulating layer 134 may include an inorganic insulating material.

[0074] The source electrode SE and the drain electrode DE may be disposed on the interlayer insulating layer 134. The source electrode SE and the drain electrode DE may be connected to the source region and the drain region of the active layer ACT, respectively. Each of the source electrode SE and the drain electrode DE may include a conductive material.

[0075] The through hole insulating layer 136 may be disposed on the source electrode SE and the drain electrode DE. The through hole insulating layer 136 may include an organic insulating material. In an embodiment, for example, the through hole insulating layer 136 may include a photoresist, a polyacrylic resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, or an epoxy resin, etc. These materials may be used alone or in combination.

[0076] Figure 2 It is shown that the pixel circuit layer PCL includes four insulating layers and three conductive layers, but this is an example and the embodiment is not limited thereto. For example, the pixel circuit layer PCL may include five or more insulating layers and four or more conductive layers.

[0077] The pixel electrode AE ​​may be disposed on the through-hole insulating layer 136. The pixel electrode AE ​​may include a conductive material. The pixel electrode AE ​​may have a single-layer structure or a multi-layer structure including a plurality of conductive layers. The pixel electrode AE ​​may be connected to the drain electrode DE through a contact hole defined or formed in the through-hole insulating layer 136. Accordingly, the pixel electrode AE ​​may be electrically connected to the thin film transistor TR.

[0078] The pixel defining layer 138 may be disposed on the pixel electrode AE. The pixel defining layer 138 may cover an edge portion of the pixel electrode AE, and the pixel defining layer 138 may define a pixel opening exposing a central portion of the pixel electrode AE. The pixel defining layer 138 may include an organic insulating material.

[0079] The emission layer EL may be disposed on the pixel electrode AE. The emission layer EL may be disposed in a pixel opening of the pixel defining layer 138. In some embodiments, the emission layer EL may include at least one of an organic light emitting material and a quantum dot.

[0080] In an embodiment, the organic light emitting material may include a low molecular weight organic compound or a high molecular weight organic compound. Examples of low molecular weight organic compounds may include copper phthalocyanine, N,N'-diphenylbenzidine or tris-(8-hydroxyquinoline) aluminum, etc. Examples of high molecular weight organic compounds may include poly(3,4-ethylenedioxythiophene), polyaniline, poly(p-phenylene vinylene) or polyfluorene, etc. These materials may be used alone or in combination.

[0081] In an embodiment, the quantum dot may include a core comprising a II-VI compound, a III-V compound, a IV-VI compound, a IV element, and / or a IV compound. In an embodiment, the quantum dot may have a core-shell structure including a core and a shell surrounding the core. The shell may be used as a protective layer for preventing the core from being chemically denatured to maintain semiconductor properties, and the shell may be used as a charging layer for imparting electrophoretic properties to the quantum dot.

[0082] The common electrode CE may be disposed on the emission layer EL. The common electrode CE may also be disposed on the pixel defining layer 138. The common electrode CE may include a conductive material. The pixel electrode AE, the emission layer EL, and the common electrode CE may form a light emitting element ED. The light emitting element ED may further include various functional layers (e.g., a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer, etc.) disposed between the pixel electrode AE ​​and the emission layer EL or between the emission layer EL and the common electrode CE.

[0083] The encapsulation layer 140 may be disposed on the common electrode CE. The encapsulation layer 140 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 142 disposed on the common electrode CE, an organic encapsulation layer 144 disposed on the first inorganic encapsulation layer 142, and a second inorganic encapsulation layer 146 disposed on the organic encapsulation layer 144. The organic encapsulation layer 144 may be disposed throughout the entire display area DA. In some aspects, although not shown in the drawings, the display panel 100 may further include various functional layers (e.g., a touch sensing layer, a color filter layer, or a light collection layer, etc.) disposed on the encapsulation layer 140.

[0084] The anti-reflection member 200 may be disposed on the display panel 100. The anti-reflection member 200 may be disposed on the encapsulation layer 140. The anti-reflection member 200 may be disposed on the second inorganic encapsulation layer 146. For example, the anti-reflection member 200 may be attached to the display panel 100 by an adhesive member. The adhesive member may include an optically clear adhesive ("OCA"), a pressure sensitive adhesive ("PSA"), a photocurable resin, a thermosetting resin, or the like.

[0085] Figure 3 It is shown that the Figure 1 FIG. 1 is a plan view of an example of a display panel 100 in a display device 10 of FIG. 1 .

[0086] refer to Figure 1 and Figure 3 , the display panel 100 may include a display area DA, a peripheral area PA, and a pad area PDA. A plurality of pixels PX may be disposed in the display area DA. For example, the pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2.

[0087] The peripheral area PA may be located outside the display area DA. For example, in a plan view, the peripheral area PA may surround the display area DA.

[0088] The pad area PDA may be located at least on one side of the display area DA. The pad area PDA may be spaced apart from the display area DA. A pad unit PD electrically connected to a driver (e.g., a data driver or a scan driver, etc.) (not shown) may be provided in the pad area PDA. The driver may provide various drive signals (e.g., a drive voltage, a gate signal, a data signal, etc.) for driving the pixel PX to the display area DA. Figure 3 It is shown that the pad area PDA is located only on one side of the display area DA, but this is an example and the embodiment is not limited thereto. For example, the pad area PDA may be additionally located in other areas outside the display area DA.

[0089] The peripheral area PA may include a first peripheral area PA1 and a second peripheral area PA2. The first peripheral area PA1 may be an area located between the display area DA and the pad area PDA. The second peripheral area PA2 may be located outside the display area DA and may be spaced apart from the pad area PDA. For example, the second peripheral area PA2 may refer to a remaining portion of the peripheral area PA surrounding the display area DA that is different from the first peripheral area PA1 between the display area DA and the pad area PDA. Specifically, in Figure 3 In the embodiment, the first peripheral area PA1 may be an area adjacent to the lower side of the display area DA, and the second peripheral area PA2 may be an area adjacent to the left, upper, and right sides of the display area DA.

[0090] The display panel 100 may include a pattern portion PP disposed in the peripheral area PA. The pattern portion PP may be a structure whose upper surface has an uneven structure (or a concave-convex structure). Fig.21 ), the pattern portion PP supports relatively easy removal of the protective layer PT. The removal of the pattern portion PP and the protective layer PT will be described in detail later.

[0091] The pattern portion PP may be disposed in a portion of the peripheral area PA. In an embodiment, the pattern portion PP may be disposed in the second peripheral area PA2 of the peripheral area PA. For example, the pattern portion PP may be disposed only in the second peripheral area PA2 of the peripheral area PA except the first peripheral area PA1.

[0092] In an embodiment, Figure 3 As shown in FIG. 1 , the pattern portion PP may be disposed in a portion of the second peripheral area PA2 corresponding to a corner portion of the display area DA. For example, the pattern portion PP may be disposed only in a portion of the second peripheral area PA2 corresponding to a corner portion of the display area DA. In an example, the pattern portion PP may be disposed to be adjacent to two corner portions ( Figure 3 However, this is an example and the embodiment is not limited thereto, and the pattern portion PP may be disposed to correspond to at least one of the four corner portions of the display area DA.

[0093] Figure 4 It is shown that the Figure 1 FIG. 1 is a plan view of another example of a display panel 100 in a display device 10 of FIG. 1 .

[0094] refer to Figure 4 In an embodiment, the pattern portion PP may be substantially completely disposed in the second peripheral area PA2 corresponding to the edge of the display area DA. For example, the pattern portion PP may be disposed to correspond to the left edge, the upper edge, and the right edge of the edge of the display area DA that are not adjacent to the pad area PDA.

[0095] Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II'. Figure 6 It is shown along Figure 3 A cross-sectional view of the example taken along line III-III'.

[0096] In the following, reference will be made to Figure 5 and Figure 6 The peripheral area PA of the display panel 100 is described in detail.

[0097] For example, Figure 5 An example of a portion of the second peripheral area PA2 where the pattern portion PP is not provided is shown, and Figure 6 An example of a portion of the second peripheral area PA2 where the pattern portion PP is disposed is shown. Figure 5 A portion of the second peripheral area PA2 where the pattern portion PP is not disposed is described.

[0098] refer to Figure 3 and Figure 5 , the display panel 100 may further include a power transmission line 150 , a first dam portion 162 , a second dam portion 164 , and a crack prevention portion 172 disposed in the peripheral area PA.

[0099] refer to Figure 2 At least one insulating layer among the insulating layer included in the pixel circuit layer PCL and the inorganic encapsulation layer included in the encapsulation layer 140 described above may extend from the display area DA to the peripheral area PA including the second peripheral area PA2. In other words, at least one insulating layer among the buffer layer 120, the gate insulating layer 132, the interlayer insulating layer 134, the through-hole insulating layer 136, the first inorganic encapsulation layer 142, and the second inorganic encapsulation layer 146 may extend from the display area DA to the peripheral area PA. For example, Figure 5 As shown in FIG. 1 , the buffer layer 120, the first inorganic encapsulation layer 142, and the second inorganic encapsulation layer 146 may extend to the edge 110e of the substrate 110, and the gate insulating layer 132 and the interlayer insulating layer 134 may extend to the crack prevention portion 172 between the display area DA and the edge 110e of the substrate 110. However, this is an example and the embodiment is not limited thereto, and the arrangement structure of the insulating layer in the peripheral area PA may be modified variously.

[0100] The power transmission line 150 may be disposed in the peripheral area PA on the substrate 110. For example, the power transmission line 150 may be disposed in the second peripheral area PA2 on the substrate 110. The power transmission line 150 may be spaced apart from the display area DA in an outward direction.

[0101] In the embodiments, reference Figure 2 The common electrode CE described as included in the light emitting element layer EDL may extend from the display area DA to the second peripheral area PA2. For example, the common electrode CE may extend to the crack prevention portion 172. The portion of the common electrode CE extending to the second peripheral area PA2 may be electrically connected to the power line 150. Accordingly, the common electrode CE may receive a low power supply voltage ("ELVSS") from the power line 150.

[0102] The first dam portion 162 may be disposed in the peripheral area PA on the substrate 110. The first dam portion 162 may be disposed in the first peripheral area PA1 and the second peripheral area PA2 on the substrate 110. For example, in a plan view, the first dam portion 162 may be spaced apart from the display area DA in an outward direction, and the first dam portion 162 may have a shape that substantially completely surrounds the display area DA. In some embodiments, the first dam portion 162 may be discontinuous in some portions.

[0103] The second dam portion 164 may be disposed in the peripheral area PA on the substrate 110. The second dam portion 164 may be disposed in the first peripheral area PA1 and the second peripheral area PA2 on the substrate 110. For example, in a plan view, the second dam portion 164 may be spaced apart from the first dam portion 162 in an outward direction, and the second dam portion 164 may have a shape that substantially completely surrounds the first dam portion 162. In some embodiments, the second dam portion 164 may be discontinuous in some portions.

[0104] Each of the first dam portion 162 and the second dam portion 164 may have a multilayer structure including a plurality of layers. Figure 5 As shown in , the first dam portion 162 may include a first layer 162a and a second layer 162b, and the second dam portion 164 may include a first layer 164a, a second layer 164b, and a third layer 164c. For example, the first layer 162a of the first dam portion 162 and the first layer 164a of the second dam portion 164 may be formed substantially simultaneously with the through-hole insulating layer 136 of the display area DA. The second layer 162b of the first dam portion 162 and the second layer 164b of the second dam portion 164 may be formed substantially simultaneously with the pixel defining layer 138 of the display area DA. The third layer 164c of the second dam portion 164 may be formed substantially simultaneously with the spacer (not shown) of the display area DA. However, this is an example, and embodiments are not limited thereto.

[0105] The first and second dam portions 162 and 164 may prevent the organic encapsulation layer 144 disposed in the display area DA and encapsulating the light emitting element layer EDL from overflowing. For example, the first and second dam portions 162 and 164 may prevent the organic encapsulation layer 144 from overflowing to an unintended portion of the display panel 100 during formation of the organic encapsulation layer 144.

[0106] The crack prevention portion 172 may be disposed in the peripheral area PA on the substrate 110. For example, the crack prevention portion 172 may be disposed in the first peripheral area PA1 and the second peripheral area PA2 on the substrate 110. For example, in a plan view, the crack prevention portion 172 may be spaced apart from the second dam portion 164 in an outward direction, and the crack prevention portion 172 may have a shape that substantially completely surrounds the second dam portion 164. In some embodiments, the crack prevention portion 172 may be discontinuous in some portions.

[0107] The crack prevention portion 172 may include at least one inorganic insulating layer. The crack prevention portion 172 may be spaced apart in an outward direction from at least one insulating layer extending to the peripheral area PA including the second peripheral area PA2 among the inorganic insulating layers included in the pixel circuit layer PCL. Figure 5 As shown in , the gate insulating layer 132 and the interlayer insulating layer 134 may extend from the display area DA to the peripheral area PA. The crack prevention portion 172 may be spaced apart from the gate insulating layer 132 and the interlayer insulating layer 134 extending to the peripheral area PA in an outward direction. For example, the crack prevention portion 172 may be formed by partially removing the gate insulating layer 132 and the interlayer insulating layer 134. That is, the first layer 172a of the crack prevention portion 172 may be formed substantially simultaneously with the gate insulating layer 132, and the second layer 172b of the crack prevention portion 172 may be formed substantially simultaneously with the interlayer insulating layer 134. For example, as shown in FIG. Figure 5 As shown in FIG. 1 , a plurality of crack prevention portions 172 may be provided.

[0108] In an embodiment, a capping layer 174 may be disposed on the crack prevention portion 172. The capping layer 174 may cover the crack prevention portion 172, and the capping layer 174 may fill the transfer prevention groove formed at least one side of the crack prevention portion 172. The capping layer 174 may include an organic insulating material. For example, the capping layer 174 may be formed substantially simultaneously with the through hole insulating layer 136 of the display area DA.

[0109] In an embodiment, the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 may extend from the display area DA to the peripheral area PA including the second peripheral area PA2. For example, the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 may extend to the edge 110e of the substrate 110. In the peripheral area PA, the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 may cover the common electrode CE, the first dam portion 162, the second dam portion 164, and the covering layer 174.

[0110] In some embodiments, Figure 5The second inorganic encapsulation layer 146 is shown to be the uppermost layer of the display panel 100 in the second peripheral area PA2, but this is an example and the embodiment is not limited thereto. For example, in at least a portion of the second peripheral area PA2, the second inorganic encapsulation layer 146 may be omitted, and another insulating layer disposed under the second inorganic encapsulation layer 146 may be the uppermost layer (refer to Fig.11 In another example, in at least a portion of the second peripheral area PA2, another insulating layer (eg, a touch insulating layer (not shown) or the like) disposed above the second inorganic encapsulation layer 146 may be the uppermost layer.

[0111] Next, we will refer to Figure 6 A portion of the second peripheral area PA2 where the pattern portion PP is disposed is described.

[0112] refer to Figure 3 and Figure 6 , the pattern part PP of the display panel 100 may be disposed in a portion of the second peripheral area PA2 on the substrate 110. The pattern part PP may be a structure having an uneven structure on an upper surface thereof.

[0113] The pattern portion PP may be formed by partially removing at least one insulating layer extending to the second peripheral area PA2. In other words, the upper portion of the insulating structure located in the second peripheral area PA2 and including at least one insulating layer may be partially removed, and a portion of the insulating structure having an uneven structure by partially removing the upper surface thereof may be defined as the pattern portion PP. For example, Figure 6 It is shown that a portion of an upper portion of the insulating structure including the first and second inorganic encapsulation layers 142 and 146 is removed to form the pattern portion PP in the second peripheral area PA2 , but this is an example and the embodiment is not limited thereto.

[0114] Figure 7 It is shown Figure 6 A perspective view of an example of area "A".

[0115] refer to Figure 6 and Figure 7, the pattern portion PP may have a plurality of protrusions PRT spaced apart from each other and a groove GV defining the protrusion PRT. For example, the protrusion PRT may be arranged so that the protrusion PRT is spaced apart from each other along the first direction DR1 and the second direction DR2. The groove GV may define the protrusion PRT. That is, in a plan view, the groove GV may surround each of the protrusions PRT. For example, a space from which a portion of the upper portion of the insulating structure located in the second peripheral area PA2 is removed may be defined as the groove GV, and the remaining portion of the upper portion of the insulating structure that is not removed may be defined as the protrusion PRT. At least the uppermost layer (e.g., the second inorganic encapsulation layer 146) of the plurality of insulating layers included in the pixel circuit layer PCL and at least one insulating layer extending to the second peripheral area PA2 among the inorganic encapsulation layers included in the encapsulation layer 140 may define a groove GV in the second peripheral area PA2.

[0116] Regarding the protective layer PT (refer to Fig.21 ), the pattern portion PP supports relatively easy removal of the protective layer PT. For example, the protective layer PT can be formed by providing a protective layer resin on the display panel 100 through an inkjet printing process or the like and curing the provided protective layer resin. The protective layer resin may be provided on the display panel 100 so that an edge of the protective layer resin is located on the pattern portion PP. In this case, since the pattern portion PP includes protrusions PRT spaced apart from each other, the contact angle of the protective layer resin may be increased. That is, compared to a comparative example in which the pattern portion PP is not formed, the protective layer PT according to one or more embodiments of the present disclosure may be formed to have a relatively thick edge portion, and therefore, the protective layer PT may be easily removed from the display panel 100. Accordingly, embodiments of the present disclosure support preventing the protective layer PT from remaining on the display panel 100 or reducing the amount of the protective layer PT remaining on the display panel 100, and the reliability of the display device 10 may be improved.

[0117] In an embodiment, the distance D between adjacent protrusions PRT may be in the range of about 10 μm to about 50 μm. If the distance D between adjacent protrusions PRT is less than about 10 μm, the effect of increasing the contact angle of the protective layer resin may not be achieved. If the distance D between adjacent protrusions PRT is greater than about 50 μm, the effect of increasing the contact angle of the protective layer resin may be reduced. Accordingly, the distance D between adjacent protrusions PRT may be in the range of about 10 μm to about 50 μm. Preferably, for example, the distance D between adjacent protrusions PRT may be in the range of about 25 μm to about 50 μm.

[0118] In an embodiment, Figure 7As shown in , each of the protrusions PRT may have a rectangular shape in a cross-sectional view. For example, a portion of an upper portion of the insulating structure located in the second peripheral area PA2 may be removed by a dry etching process. In this case, each of the protrusions PRT may have a substantially rectangular shape in a cross-sectional view.

[0119] Figure 8 It is shown Figure 6 A perspective view of another example of area "A".

[0120] refer to Figure 8 In an embodiment, each of the protrusions PRT may have an inverted tapered shape in a cross-sectional view in which the upper side is larger than the lower side (for example, the upper side is wider than the lower side in the first direction DR1 and / or the second direction DR2). That is, the groove GV may have an undercut shape in a cross-sectional view. In an example in which each of the protrusions PRT has an inverted tapered shape in a cross-sectional view, the effect of increasing the contact angle of the protective layer resin can be further improved. For example, by appropriately adjusting the conditions of the dry etching process, each of the protrusions PRT can be formed to have an inverted tapered shape in a cross-sectional view. In another example, a portion of the upper portion of the insulating structure located in the second peripheral area PA2 can be removed by a wet etching process.

[0121] Reference again Figure 6 and Figure 7 , the embodiments of the present disclosure support different determination or setting of the thickness T of each of the protrusions PRT. The thickness T of the protrusion PRT may be defined as the distance between the upper surface of the protrusion PRT and the bottom surface of the groove GV. That is, the thickness T of the protrusion PRT may be equal to the depth of the groove GV. Accordingly, for example, in the case where a portion of the upper portion of the insulating structure located in the second peripheral area PA2 is removed, the insulating structure may not expose the conductive layer (e.g., Figure 6 common electrode CE).

[0122] That is, in the second peripheral area PA2, even if a portion of an upper portion of the insulating structure is removed to form the pattern portion PP, the conductive layer may be disposed under the pattern portion PP and covered by the pattern portion PP.

[0123] The bottom surface of the groove GV may have an insulating property. In other words, the bottom surface of the groove GV may be a portion of the insulating layer extending to the second peripheral area PA2. Figure 6 As shown in FIG. 1 , the bottom surface of the groove GV may be a portion of the first inorganic encapsulation layer 142 extending to the second peripheral area PA2 , but this is an example and the embodiment is not limited thereto.

[0124] The pattern portion PP may overlap at least one conductive layer disposed in the second peripheral area PA2 in the third direction DR3. Figure 6 As shown in , a portion of the pattern portion PP may overlap with a portion of the common electrode CE located in the second peripheral area PA2 in the third direction DR3. In the region where the above-mentioned portion of the pattern portion PP overlaps with the above-mentioned portion of the common electrode CE, the bottom surface of the groove GV may be spaced apart from the upper surface of the common electrode CE in the third direction DR3 which is an upward direction. That is, the common electrode CE may be covered by the pattern portion PP. Accordingly, the pattern portion PP may prevent or reduce impurities such as, for example, oxygen or moisture from penetrating into the common electrode CE.

[0125] In an embodiment, Figure 6 As shown in , the thickness of each of the protrusions PRT may be greater than the thickness of the second inorganic encapsulation layer 146, and the thickness of each of the protrusions PRT may be less than the sum of the thickness of the first inorganic encapsulation layer 142 and the thickness of the second inorganic encapsulation layer 146. In this case, the bottom surface of the groove GV may be a portion of the first inorganic encapsulation layer 142 extending to the second peripheral area PA2.

[0126] Fig. 9 It is shown along Figure 3 A cross-sectional view of another example taken along line III-III'.

[0127] In another embodiment, if Fig. 9 As shown in , the thickness of each of the protrusions PRT may be smaller than the thickness of the second inorganic encapsulation layer 146. In this case, the bottom surface of the groove GV may be a portion of the second inorganic encapsulation layer 146 extending to the second peripheral area PA2.

[0128] However, Figure 6 and Fig. 9 The thickness of each of the protrusion PRTs shown in is an example, and the embodiment is not limited thereto. As described herein, the thickness of each of the protrusion PRTs may be modified differently within a certain range so that the pattern portion PP does not expose the conductive layer that may be disposed under the pattern portion PP.

[0129] Reference again Figure 3 and Figure 6 , the first virtual line VL1 and the second virtual line VL2 may be defined in the second peripheral area PA2 of the display panel 100 .

[0130] The first virtual line VL1 may be spaced apart from the display area DA in an outward direction. For example, the first virtual line VL1 may be adjacent to a corner portion of the display area DA and may have a “┌” shape in a plan view.

[0131] The second virtual line VL2 may be spaced apart from the first virtual line VL1 in an outward direction. For example, the second virtual line VL2 may be adjacent to a corner portion of the substrate 110 and may have a “┌” shape in a plan view.

[0132] The pattern portion PP may be continuously disposed from the first virtual line VL1 to the second virtual line VL2 defined in the second peripheral area PA2. In other words, a space where a portion of the upper portion of the insulating structure overlapping the area between the first virtual line VL1 and the second virtual line VL2 is removed by an etching process may be defined as a groove GV, and a remaining portion of the upper portion of the insulating structure that is not removed may be defined as a protrusion PRT.

[0133] In an embodiment, Figure 6 As shown in , the first virtual line VL1 may be located between the display area DA and the first dam portion 162. The second virtual line VL2 may be spaced apart from the crack prevention portion 172 in an outward direction. In this case, the pattern portion PP may overlap the first dam portion 162, the second dam portion 164, the crack prevention portion 172, and the cover layer 174. The upper surfaces of at least some of the protrusions PRT may have different levels. Depending on the position, the bottom surface of the groove GV may have different levels.

[0134] In an embodiment, although not shown in the drawings, the first virtual line VL1 may be located between the second dam portion 164 and the crack prevention portion 172. The second virtual line VL2 may be spaced apart from the crack prevention portion 172 in an outward direction. In this case, the pattern portion PP may overlap the crack prevention portion 172 and the cover layer 174, and may not overlap the first dam portion 162 and the second dam portion 164. The upper surfaces of at least some of the protrusions PRT may have different levels. That is, for example, the respective upper surfaces of at least some of the protrusions PRT may have different heights compared to each other. Depending on the position, the bottom surface of the groove GV may have different levels. For example, some portions of the bottom surface of the groove GV may be substantially uneven relative to each other.

[0135] In an embodiment, although not shown in the drawings, the first virtual line VL1 may be spaced apart from the crack prevention portion 172 in an outward direction. The second virtual line VL2 may be spaced apart from the first virtual line VL1 in an outward direction. In this case, the pattern portion PP may not overlap the first dam portion 162, the second dam portion 164, the crack prevention portion 172, and the cover layer 174. The upper surfaces of the protrusions PRT may have substantially the same horizontal height. That is, for example, the respective upper surfaces of the protrusions PRT may have the same height compared to each other. The bottom surface of the groove GV may have a substantially constant horizontal height. For example, the bottom surface of the groove GV may be substantially flat.

[0136] In an embodiment, Figure 6 As shown in , the second virtual line VL2 may be located at the edge 110e of the substrate 110. In this case, the pattern portion PP may be close to the edge 110e of the substrate 110. In some aspects, as Figure 6 As shown in FIG. 1 , the pattern portion PP may overlap with the edge 110 e of the substrate 110 .

[0137] Fig.10 It is shown along Figure 3 A cross-sectional view of yet another example taken along line III-III'.

[0138] In an embodiment, Fig.10 As shown in FIG. 1 , the second virtual line VL2 may be spaced apart from the edge 110 e of the substrate 110 in the inward direction. In this case, the pattern portion PP may be spaced apart from the edge 110 e of the substrate 110 in the inward direction.

[0139] Fig.11 and Fig.12 is a cross-sectional view showing a display panel 100 b according to an embodiment.

[0140] In the following, we will focus on the reference Figure 6 and Figure 7 The display panel 100 is described differently. Fig.11 and Fig.12 The display panel 100 b is shown in FIG. 1 , and any repeated detailed description of elements that are the same as or similar to elements described herein may be omitted or simplified.

[0141] Fig.11 Can be used with Figure 5 corresponding, and Fig.12 Can be used with Figure 6 For example, Fig.11 A portion of the second peripheral area PA2 where the pattern portion PP is not disposed may be shown, and Fig.12 A portion of the second peripheral area PA2 where the pattern portion PP is disposed may be shown.

[0142] refer to Fig.11, at least one insulating layer among the insulating layer included in the pixel circuit layer PCL and the inorganic encapsulation layer included in the encapsulation layer 140 may extend from the display area DA to the peripheral area PA including the second peripheral area PA2. For example, the buffer layer 120 may extend to the edge 110e of the substrate 110, and the gate insulating layer 132, the interlayer insulating layer 134, the first inorganic encapsulation layer 142, and the second inorganic encapsulation layer 146 may extend to the anti-crack portion 172 between the display area DA and the edge 110e of the substrate 110. For example, the covering layer 174 may cover the edge of the gate insulating layer 132 and the edge of the interlayer insulating layer 134. The edge of the first inorganic encapsulation layer 142 and the edge of the second inorganic encapsulation layer 146 may be disposed on the covering layer 174. A portion of the upper surface of the covering layer 174 may be exposed and may not be covered by the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146.

[0143] refer to Fig.12 , the pattern portion PP may be disposed in a portion of the second peripheral area PA2 on the substrate 110. The pattern portion PP may be a structure having an uneven structure on an upper surface thereof.

[0144] The pattern portion PP may be formed by partially removing (e.g., etching) at least one insulating layer extending to the second peripheral area PA2. In other words, an upper portion of an insulating structure located in the second peripheral area PA2 and including at least one insulating layer may be partially removed, and a portion of the insulating structure having an uneven structure by partially removing its upper surface may be defined as the pattern portion PP.

[0145] The space where a portion of the upper portion of the insulating structure located in the second peripheral area PA2 is removed can be defined as a groove GV, and the remaining portion of the upper portion of the insulating structure that is not removed can be defined as a protrusion PRT. For example, depending on the position, a portion of the upper portion of the different insulating layers can be removed to define the groove GV. For example, at least some of the protrusions PRT may include different insulating layers. For example, depending on the position, the bottom surface of the groove GV may be a portion of each of the different insulating layers.

[0146] In a region between the first virtual line VL1 and edges of the first and second inorganic encapsulating layers 142 and 146 , corresponding portions of upper portions of the first and second inorganic encapsulating layers 142 and 146 may be removed to define a groove GV. A bottom surface of the groove GV may be a portion of the first inorganic encapsulating layer 142 .

[0147] In a region between the edges of the first and second inorganic encapsulating layers 142 and 146 and the outer edge of the cover layer 174 , a portion of an upper portion of the cover layer 174 may be removed to define a groove GV. A bottom surface of the groove GV may be a portion of the cover layer 174 .

[0148] In a region between an outer edge of the capping layer 174 and the second virtual line VL2 , a portion of an upper portion of the buffer layer 120 may be removed to define a groove GV. A bottom surface of the groove GV may be a portion of the buffer layer 120 .

[0149] Fig.13 and Fig.14 is a cross-sectional view showing a display panel 100 c according to an embodiment.

[0150] In the following, we will focus on the reference Figure 6 and Figure 7 The display panel 100 is described differently. Fig.13 and Fig.14 The display panel 100c is shown in FIG. 1 , and any repeated detailed description of elements that are the same as or similar to elements described herein may be omitted or simplified.

[0151] Fig.13 Can be used with Figure 5 corresponding, and Fig.14 Can be used with Figure 6 For example, Fig.13 A portion of the second peripheral area PA2 where the pattern portion PP is not disposed may be shown, and Fig.14 A portion of the second peripheral area PA2 where the pattern portion PP is disposed may be shown.

[0152] refer to Fig.13 and Fig.14 , the display panel 100c may further include a third dam portion 180 disposed in the second peripheral area PA2.

[0153] The third dam portion 180 may be disposed in the second peripheral area PA2 on the substrate 110. The third dam portion 180 may be spaced apart from the crack prevention portion 172 in an outward direction. The third dam portion 180 may be disposed adjacent to the edge 110e of the substrate 110. For example, the third dam portion 180 may be formed substantially simultaneously with the through-hole insulating layer 136 or the pixel defining layer 138 of the display area DA. The third dam portion 180 may prevent the protective layer resin from overflowing.

[0154] In an embodiment, the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 may cover the third dam portion 180. In another embodiment, the first inorganic encapsulation layer 142 and the second inorganic encapsulation layer 146 may extend to the inner side surface of the third dam portion 180 (eg, may extend until Fig.13 and Fig.14 The third dam portion 180 may not be covered.

[0155] The second virtual line VL2 may be defined to be spaced apart from the third dam portion 180 in an outward direction. In this case, the pattern portion PP may overlap the third dam portion 180. That is, the pattern portion PP having the protrusion PRT and the groove GV may also be disposed on the third dam portion 180. Accordingly, the protective layer PT (refer to Fig.21 ) can be easily removed from the display panel 100c.

[0156] Figures 15 to 21 is a view showing a method of manufacturing the display device 10 according to the embodiment.

[0157] In the following, reference will be made to Figures 15 to 21 To describe the manufacturing reference Figures 1 to 14 The method of the display device 10 is described, and any repeated detailed description of elements that are the same as or similar to elements described herein may be omitted or simplified.

[0158] Fig.15 is a plan view showing a mother substrate 110 p on which a plurality of preliminary display panels 100 p are formed. Fig.15 Each of the preliminary display panels 100p shown in FIG. Figures 1 to 14 The described display panels 100 , 100 b , and 100 c correspond to one of them. Figures 16 to 21 2 is a cross-sectional view showing a process from forming the protective layer PT on each of the preliminary display panels 100 p to removing the protective layer PT. Figures 16 to 21 Each of these can be combined with Fig.15 It corresponds to the cross-sectional view taken along line IV-IV'.

[0159] refer to Figures 15 to 21 First, the method may include forming a plurality of preliminary display panels 100p on a mother substrate 110p. The mother substrate 110p may include a plurality of unit areas CA spaced apart from each other. Each of the unit areas CA may include a display area DA, a peripheral area PA (not shown) located outside the display area DA, and a pad area PDA (not shown) located outside the display area DA. The peripheral area PA may include a first peripheral area PA1 (not shown) between the display area DA and the pad area PDA, and a second peripheral area PA2 other than the first peripheral area PA1. The preliminary display panels 100p may be formed in the unit areas CA and on the mother substrate 110p, respectively.

[0160] The method may include forming in the display area DA included in each of the cell areas CA Figure 5The method may include forming a pixel circuit layer PCL, a light emitting element layer EDL and an encapsulation layer 140. The organic encapsulation layer 144 included in the encapsulation layer 140 may be provided throughout the entire display area DA. Figure 5 The transmission line 150, the first dam portion 162, the second dam portion 164, and the crack prevention portion 172. The insulating layer included in the pixel circuit layer PCL and at least one insulating layer among the at least one inorganic encapsulation layer included in the encapsulation layer 140 may extend from the display area DA to the peripheral area PA including the second peripheral area PA2.

[0161] Subsequently, the method may include forming a pattern portion PP having an upper surface with an uneven structure in the second peripheral area PA2 included in each of the cell areas CA. The pattern portion PP may have a protrusion PRT and a groove GV defining the protrusion PRT.

[0162] The method may include forming a pattern portion PP by partially removing (e.g., etching) an insulating structure including at least one insulating layer in the second peripheral area PA2. In other words, in the second peripheral area PA2, a portion of the insulating structure having an uneven structure by partially removing an upper surface thereof may be defined as a pattern portion PP. For example, a space where a portion of an upper portion of the insulating structure is removed may be defined as a groove GV, and a remaining portion of the upper portion of the insulating structure that is not removed may be defined as a protrusion PRT.

[0163] In each of the unit areas CA, the pixel circuit layer PCL, the light emitting element layer EDL, the encapsulation layer 140, the power transmission line 150, the first dam portion 162, the second dam portion 164, the crack prevention portion 172 and the pattern portion PP formed on the mother substrate 110p may constitute each of the preliminary display panels 100p.

[0164] Subsequently, the method may include forming a protective layer PT in each of the cell areas CA. Fig.17 As shown in , the method may include providing a protective layer resin P-PT in each of the cell areas CA. The protective layer resin P-PT may be provided on the encapsulation layer 140 and the pattern portion PP formed in each of the cell areas CA.

[0165] The method may include providing a protective layer resin P-PT in a liquid form in each of the unit areas CA. For example, the method may include providing the protective layer resin P-PT by an inkjet printing process or a coating process, etc. In an example, the protective layer resin P-PT may include an acrylic resin, but this is an example and the embodiment is not limited thereto. The protective layer resin P-PT may be provided to cover the entire organic encapsulation layer 144.

[0166] like Fig.18 As shown in , the protective layer resin P-PT may be provided so that an edge P-PTe of the protective layer resin P-PT is located on the pattern portion PP. In some aspects, providing the protective layer resin P-PT so that the edge P-PTe is located on the pattern portion PP having an uneven structure on its upper surface supports increasing the contact angle θ of the protective layer resin P-PT. The contact angle θ of the protective layer resin P-PT may be defined as the angle between the upper surface of the protrusion PRT that contacts the edge P-PTe and the tangent of the edge P-PTe. For example, the contact angle θ of the protective layer resin P-PT may be greater than or equal to approximately 90°. Compared to a comparative example in which the pattern portion PP is not formed, the protective layer resin P-PT may be formed to have a relatively thick edge portion.

[0167] In an area where the pattern portion PP is not set, an edge P-PTe of the protective layer resin P-PT may be located on the upper surface of at least one insulating layer extending to the peripheral area PA, or an edge P-PTe of the protective layer resin P-PT may be located on the upper surface of the mother substrate 110p.

[0168] Then, if Fig.17 and Fig.19 As shown in , the method may include curing the protective layer resin P-PT to form the protective layer PT. For example, the method may include emitting ultraviolet light UV from the top of the protective layer resin P-PT toward the protective layer resin P-PT to expose the protective layer resin P-PT to the ultraviolet light UV. The protective layer PT may be formed by curing the protective layer resin P-PT with the ultraviolet light UV.

[0169] Then, if Fig.19 and Fig. 20 As shown in , the method may include cutting with respect to each of the unit areas CA of the mother substrate 110p to obtain the display panel 100. The cutting line CTL may be defined along the edge of each of the unit areas CA. The protective layer PT may protect various structures such as, for example, pixel circuits, light-emitting elements, and wiring formed on the mother substrate 110p in the unit area CA during the cutting process. Each of the preliminary display panels 100p separated by the cutting process may be a display panel 100. Immediately after the cutting process, the protective layer PT may remain on each of the display panels 100.

[0170] Then, if Fig.21 As shown in , the method may include removing the protective layer PT from each display panel 100 after cutting. For example, the method may include removing the protective layer PT using a separation device (not shown). In an example, the separation device may be a cutter including an edge portion inserted between the upper surface of the pattern portion PP and the lower surface of the protective layer PT, but this is an example and the embodiment is not limited thereto.

[0171] As described herein, providing a protective layer resin P-PT so that an edge P-PTe is located on a pattern portion PP having an uneven structure on its upper surface supports increasing the contact angle θ of the protective layer resin P-PT. The protective layer PT can be formed by curing the protective layer resin P-PT. That is, compared to a comparative example in which the pattern portion PP is not formed, the protective layer PT can be formed to have a relatively thick edge portion, and thus the protective layer PT can be easily removed from the display panel 100. Accordingly, embodiments of the present disclosure support preventing the protective layer PT from remaining on the display panel 100 or reducing the amount of the protective layer PT remaining on the display panel 100, and can improve the reliability of the display device 10.

[0172] The method may include providing an anti-reflection member ( Figure 1 The display panel 100, the anti-reflection member and the cover window may constitute the display device 10.

[0173] Although embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this specification. Accordingly, the exemplary aspects of the present disclosure are not limited to such embodiments, but are limited to the broader scope of the claims and various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display device, comprising: A substrate including a display area and a peripheral area outside the display area; A pixel circuit layer, which is disposed in the display area and on the substrate and includes a thin film transistor and a plurality of insulating layers; a light emitting element layer, disposed in the display area, on the substrate and comprising a light emitting element electrically connected to the thin film transistor; An encapsulation layer, disposed on the light-emitting element layer; as well as A pattern portion is disposed in a portion of the peripheral region and on the substrate, wherein an upper surface of the pattern portion has an uneven structure.

2. The display device according to claim 1, wherein: The pattern portion includes a plurality of protrusions spaced apart from each other and grooves defining the plurality of protrusions.

3. The display device according to claim 2, wherein: A distance between adjacent protrusions among the plurality of protrusions is in a range of 10 μm to 50 μm.

4. The display device according to claim 2, wherein: Each of the plurality of protrusions has a rectangular shape in a cross-sectional view.

5. The display device according to claim 2, wherein: Each of the plurality of protrusions has an inverted tapered shape in a cross-sectional view.

6. The display device according to claim 2, wherein: A bottom surface of the groove has insulating properties.

7. The display device according to claim 2, wherein The light emitting element comprises a pixel electrode, an emission layer and a common electrode. The common electrode extends from the display area to the peripheral area, and In the peripheral area, a portion of the pattern portion overlaps a portion of the common electrode.

8. The display device according to claim 7, wherein: In a region where the portion of the pattern portion overlaps the portion of the common electrode, a bottom surface of the groove is spaced apart from an upper surface of the common electrode in an upward direction.

9. The display device according to claim 2, wherein The encapsulation layer includes a first inorganic encapsulation layer disposed on the light emitting element layer, an organic encapsulation layer disposed on the first inorganic encapsulation layer, and a second inorganic encapsulation layer disposed on the organic encapsulation layer. At least one insulating layer among the plurality of insulating layers included in the pixel circuit layer, the first inorganic encapsulation layer, and the second inorganic encapsulation layer extends from the display area to the peripheral area, and At least an uppermost layer of the at least one insulating layer defines the groove of the pattern portion in the peripheral region.

10. The display device according to claim 1, wherein: The pattern portion is disposed to correspond to a corner portion of the display area.

11. The display device according to claim 1, wherein The substrate further includes a pad area located on at least one side of the display area, The peripheral area includes a first peripheral area between the display area and the pad area and a second peripheral area spaced apart from the pad area, and The pattern portion is disposed in the second peripheral region of the peripheral region.

12. The display device according to claim 1, wherein: The pattern portion is close to an edge of the substrate.

13. The display device according to claim 1, wherein The pattern portion is continuously arranged from the first virtual line to the second virtual line, The first virtual line is spaced apart from the display area in an outward direction and is located in the peripheral area, and The second virtual line is located at an edge of the substrate.

14. The display device according to claim 1, further comprising: a first dam portion disposed in the peripheral region, on the substrate, spaced apart from the display region in an outward direction and surrounding the display region, Wherein, the pattern portion overlaps with the first dam portion.

15. The display device according to claim 14, further comprising: a crack prevention portion disposed in the peripheral region, on the substrate and spaced apart from the first dam portion in the outward direction, Wherein, the pattern portion further overlaps with the anti-cracking portion.

16. The display device according to claim 15, further comprising: a second dam portion disposed in the peripheral region, on the substrate and spaced apart from the crack prevention portion in the outward direction, Wherein, the pattern portion further overlaps with the second dam portion.

17. The display device according to any one of claims 1 to 16, further comprising: The anti-reflection member is disposed on the packaging layer.

18. A method for manufacturing a display device, the method comprising: forming a pixel circuit layer, a light emitting element layer and a packaging layer on a mother substrate including a plurality of unit areas, wherein each of the plurality of unit areas includes a display area and a peripheral area outside the display area; forming a pattern portion in the peripheral region of each of the plurality of unit regions, wherein an upper surface of the pattern portion has an uneven structure; forming a protective layer by providing a protective layer resin on the encapsulation layer and the pattern portion of each of the plurality of unit regions; obtaining a plurality of display panels by cutting along cutting lines defined along edges of each of the plurality of unit areas; and The protection layer is removed from each of the plurality of display panels.

19. The method according to claim 18, wherein At least one insulating layer among a plurality of insulating layers included in the pixel circuit layer and at least one inorganic encapsulation layer included in the encapsulation layer extends from the display area to the peripheral area, and The forming of the pattern portion includes forming a plurality of protrusions and grooves defining the plurality of protrusions by partially etching the at least one insulating layer in the peripheral region.

20. The method according to claim 18, wherein: The forming of the protective layer includes curing the protective layer resin by exposing the provided protective layer resin to ultraviolet light.

21. The method according to claim 18, wherein: The forming of the protective layer includes providing the protective layer resin so that an edge of the protective layer resin is located on the pattern portion.

22. The method according to any one of claims 18 to 21, further comprising: An anti-reflection member is provided on each of the plurality of display panels from which the protective layer has been removed.

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