Display device

Abstract

The invention relates to a display device. A display device according to one embodiment includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, each including a semiconductor layer, a gate electrode disposed on the semiconductor layer, and a first electrode and a second electrode disposed on the gate electrode, a connection between the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor is different from a connection between the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0161904, filed on November 21, 2023, the entire contents of which are incorporated herein by reference for all purposes. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device having an oxide thin - film transistor with improved reliability. Background art

[0004] With the development of the information society, various demands for display devices for displaying images are increasing, and various types of display devices are utilized, such as liquid crystal display (LCD) devices and organic light - emitting diode (OLED) display devices.

[0005] A display device includes a plurality of pixels and a plurality of switching elements for driving and controlling the pixels. The switching elements can be formed of thin - film transistors, and thin - film transistors are widely applied to both pixels and integrated circuits. Recently, various studies and developments have been conducted to improve the performance and reliability of thin - film transistors. Summary of the invention

[0006] Embodiments of the present specification are directed to providing a display device to which a connection structure between thin - film transistors is applied in consideration of the characteristics of each of the thin - film transistors in pixels.

[0007] Embodiments of the present specification are directed to minimizing fluctuations in threshold voltage by implementing a connection between a transistor sensitive to fluctuations in threshold voltage and an adjacent transistor through a separate conductive layer different from a semiconductor layer.

[0008] Embodiments of the present specification are directed to minimizing fluctuations in threshold voltage by implementing a connection between a transistor sensitive to fluctuations in threshold voltage and an adjacent transistor through a line located on a conductive layer having excellent hydrogen - trapping ability.

[0009] Embodiments of the present specification are directed to providing a display device that can reduce the number of contact holes required for connecting transistors and simplify the process by implementing a connection between transistors that are relatively insensitive to fluctuations in threshold voltage.

[0010] The object of the present specification is not limited to the above - mentioned object, and other technical objects can be inferred from the following embodiments.

[0011] To achieve the purpose, a display device according to one embodiment includes a first thin film transistor, a second thin film transistor and a third thin film transistor, each thin film transistor including a semiconductor layer, a gate electrode arranged on the semiconductor layer, and a first electrode and a second electrode arranged on the gate electrode, wherein a connection between the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor is different from a connection between the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

[0012] To achieve the purpose, a display device according to another embodiment includes a first thin film transistor, a second thin film transistor and a third thin film transistor, each thin film transistor including a semiconductor layer, a gate electrode arranged on the semiconductor layer, and a first electrode and a second electrode arranged on the gate electrode, wherein the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor are connected through a first connecting line, the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor are connected through a second connecting line, and the reflectivity of the first connecting line is lower than the reflectivity of the second connecting line.

[0013] Details of other implementations are included in the detailed description and accompanying drawings.

[0014] In the display device according to the embodiment, the fluctuation of the threshold voltage may be minimized by realizing the connection between the transistor sensitive to the fluctuation of the threshold voltage and the adjacent transistor through a separate conductive layer different from the semiconductor layer.

[0015] In addition, in the display device according to the embodiment, fluctuation of the threshold voltage can be minimized by implementing a transistor sensitive to fluctuation of the threshold voltage and a wire on a conductive layer having excellent hydrogen collection capability for connection between the transistor and an adjacent transistor.

[0016] In addition, in the display device according to the embodiment, the connection between transistors that is relatively insensitive to fluctuations in threshold voltage can be realized through a line located coplanar with the semiconductor layer of the transistor to reduce the number of contact holes required for connection between transistors and simplify the process.

[0017] In addition, in the display device according to the embodiment, by implementing a transistor and an adjacent transistor that are sensitive to fluctuations in threshold voltage through a line located on a conductive layer having excellent hydrogen capture capability, defects of the transistor can be minimized and the life of the transistor can be increased, thereby realizing a low-power display device.

[0018] However, effects obtainable from the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art to which the present specification belongs from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional view of the display device according to the first embodiment.

[0020] Figure 2 is a cross-sectional view of a display device according to a second embodiment.

[0021] Figure 3 is a cross-sectional view of a display device according to a third embodiment.

[0022] Figure 4 is a cross-sectional view of a display device according to a fourth embodiment.

[0023] Figure 5 is a pixel circuit diagram of a display device according to a fifth embodiment.

[0024] Figure 6 is based on Figure 5 A cross-sectional view of a display device.

[0025] Figure 7 is based on Figure 6 sectional view of a modified example of the display device. DETAILED DESCRIPTION

[0026] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0027] The same reference numerals indicate the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the components may be exaggerated. For the convenience of description, the proportions of the components shown in the drawings are different from the actual proportions, and therefore are not limited to the proportions shown in the drawings.

[0028] In the specification, when a first component (or region, layer, portion, etc.) is described as being “on,” “connected” or “coupled to” a second component, this means that the first component may be directly connected / coupled to the second component or a third component may be disposed between the first and second components.

[0029] The term "and / or" includes all one or more combinations that can be defined by the associated configurations.

[0030] Terms such as first and second can be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another component. For example, without departing from the scope of the embodiments, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0031] Terms such as "below ...", "at the lower side of ...", "above ...", and "at the upper side of ..." are used to describe the relationship between the components shown in the drawings. These terms are relative concepts and are described relative to the directions marked in the drawings. For example, as long as "immediately" or "directly" is not used, one or more other parts can be located between two parts. Spatially relative terms "below or below ...", "at the lower part of ...", "above ...", "at the upper part of ...", etc. can be used to easily describe the correlation of one element or component with another element or component as shown in the figure. Spatially relative terms should be understood as terms that include different directions of elements in use or operation in addition to the directions shown in the drawings. For example, in the case of flipping the elements shown in the drawings, an element described as being disposed "below" or "below" another element can be disposed "above" another element. Therefore, the exemplary term "below" can include both downward and upward directions.

[0032] It should be understood that terms such as “include” or “have” are intended to specify the presence of the features, numbers, steps, operations, components, parts, or a combination thereof described in the specification, and do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or a combination thereof.

[0033] The features of various embodiments of this specification may be coupled or combined in part or in whole, and various technical intercommunications and drives are possible, and the embodiments may be implemented independently of each other or together in an associated relationship.

[0034] Hereinafter, the display device of the present specification will be described with reference to the following drawings and embodiments.

[0035] Figure 1 is a cross-sectional view of the display device according to the first embodiment.

[0036] Reference Figure 1 According to the present embodiment, the display device may include: a substrate 110; a buffer layer 121 arranged on the substrate 110; a first insulating layer 122 arranged on the buffer layer 121; a first conductive layer 130 arranged on the first insulating layer 122; a second insulating layer 123 arranged on the first conductive layer 130; a third insulating layer 124 arranged on the second insulating layer 123; a second conductive layer 140 arranged on the third insulating layer 124; a fourth insulating layer 125 arranged on the second conductive layer 140; a semiconductor layer arranged on the fourth insulating layer 125; a gate insulating layer 126 arranged on the semiconductor layer; a third conductive layer 150 arranged on the gate insulating layer 126; an interlayer insulating layer 127 arranged on the third conductive layer 150; and a fourth conductive layer 160 arranged on the interlayer insulating layer 127.

[0037] The substrate 110 may support each layer disposed thereon. The substrate 110 may be made of an insulating material such as a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP) or a combination thereof. The substrate 110 may be a flexible substrate capable of bending, folding, curling, etc. An example of a material forming a flexible substrate may be polyimide (PI), but is not limited thereto. The substrate 110 may be a rigid substrate made of glass, quartz, etc.

[0038] The buffer layer 121 may be disposed on the substrate 110. The buffer layer 121 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. The buffer layer 121 may prevent diffusion of impurity ions and prevent penetration of moisture or external air. Unlike shown, the buffer layer 121 may include a plurality of layers. In other words, the buffer layer 121 may be formed by layers of silicon nitride (SiNx) and silicon oxide (SiOx) alternately stacked at least once.

[0039] The first insulating layer 122 may be disposed on the buffer layer 121. The first insulating layer 122 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the first insulating layer 122 may include a plurality of layers. That is, the first insulating layer 122 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once.

[0040] The first conductive layer 130 may be disposed on the first insulating layer 122. The first conductive layer 130 may include a metal material. For example, the first conductive layer 130 may include a metal material having a low reflectivity. For example, the first conductive layer 130 may include an opaque metal material. For example, the first conductive layer 130 may include one or more selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The first conductive layer 130 may include a light blocking layer, but is not limited thereto.

[0041] The second insulating layer 123 may be disposed on the first conductive layer 130. The second insulating layer 123 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the second insulating layer 123 may include a plurality of layers. That is, the second insulating layer 123 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. For example, the second insulating layer 123 may perform an interlayer insulating function of insulating the first conductive layer 130 from the second conductive layer 140 to be described below.

[0042] The third insulating layer 124 may be disposed on the second insulating layer 123. The third insulating layer 124 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the third insulating layer 124 may include a plurality of layers. That is, the third insulating layer 124 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. For example, the third insulating layer 124 may perform an interlayer insulating function of insulating the first conductive layer 130 from the second conductive layer 140 to be described below.

[0043] The second conductive layer 140 may be disposed on the third insulating layer 124. The second conductive layer 140 may include a light blocking layer 141. For example, the light blocking layer 141 may overlap the semiconductor layers ACT1 and ACT2 of the first thin film transistor T1 and the second thin film transistor T2, which will be described below. The light blocking layer 141 may be disposed to overlap the semiconductor layers ACT1 and ACT2 of the first thin film transistor T1 and the second thin film transistor T2, thereby blocking light from traveling to the semiconductor layers ACT1 and ACT2 at the bottom. Although Figure 1 The width of the light blocking layer 141 is shown to be the same as the width of the semiconductor layers ACT1 and ACT2, but the present disclosure is not limited thereto, and the width of the light blocking layer 141 may be greater than or less than the width of the semiconductor layers ACT1 and ACT2. For example, the second conductive layer 140 may include one or more selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). For example, the second conductive layer 140 may include at least titanium (Ti). For example, the second conductive layer 140 may include a metal having excellent hydrogen (H 2 ) capture capability. In this specification, when any composition has good hydrogen (H 2) capture capacity, this can mean that hydrogen (H 2 ) can penetrate the corresponding composition well. For example, titanium (Ti) can be a material with excellent hydrogen capture ability. For example, the hydrogen capture ability of the second conductive layer 140 can be better than the hydrogen capture ability of the first conductive layer 130. More specifically, good hydrogen capture ability means that the target composition is well infiltrated with hydrogen (H 2 ) is an exothermic reaction, and hydrogen (H 2 ) at the target composition with hydrogen (H 2 ) are not easily separated after being bonded therebetween. In one embodiment, since the second conductive layer 140 has better hydrogen capture capability than the first conductive layer 130 and the fourth conductive layer 160, the formation heat Δh of the second conductive layer 140 may be lower than the formation heat Δh of the first conductive layer 130. In addition, better hydrogen capture capability may mean that, in the case where the connecting electrode is formed of the corresponding conductive layer, the threshold voltage (Vth) of the thin film transistor electrically connected to the connecting electrode fluctuates less.

[0044] The fourth insulating layer 125 may be disposed on the second conductive layer 140. The fourth insulating layer 125 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the fourth insulating layer 125 may include a plurality of layers. That is, the fourth insulating layer 125 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. For example, the fourth insulating layer 125 may perform an interlayer insulating function of insulating the semiconductor layer to be described below from the second conductive layer 140.

[0045] The semiconductor layer may be disposed on the fourth insulating layer 125. The semiconductor layer may include a first semiconductor layer ACT1 of the first thin film transistor T1 and a second semiconductor layer ACT2 of the second thin film transistor T2. The semiconductor layers ACT1 and ACT2 may include oxides. The semiconductor layers ACT1 and ACT2 may be oxide semiconductor layers. The oxide semiconductor layer may have a lower light reflectivity than a semiconductor layer made of polycrystalline silicon. That is, the oxide semiconductor layer may have a higher light transmittance than a semiconductor layer made of polycrystalline silicon. The semiconductor layers ACT1 and ACT2 may each include a channel region, a first region, and a second region. The channel regions of the semiconductor layers ACT1 and ACT2 may overlap with the upper gate electrodes G1 and G2, respectively.

[0046] The oxide semiconductor may include, for example, a binary compound (ABx), a ternary compound (ABxCy), or a quaternary compound (ABxCyDz) containing indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), magnesium (Mg), etc. In one embodiment, the second semiconductor layer ACT2 may include ITZO (an oxide including indium, tin, and titanium) or IGZO (an oxide including indium, gallium, and tin).

[0047] The conductivity of the first and second regions of the semiconductor layers ACT1 and ACT2 may be higher than the conductivity of the channel region. To this end, the first and second regions of the semiconductor layers ACT1 and ACT2 may each be conductive.

[0048] The gate insulating layer 126 may be formed on the semiconductor layers ACT1 and ACT2. The gate insulating layer 126 may include an inorganic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the gate insulating layer 126 may include a plurality of layers. That is, the gate insulating layer 126 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. For example, the gate insulating layer 126 may be used to insulate the gate electrodes G1 and G2 and the semiconductor layers ACT1 and ACT2.

[0049] The third conductive layer 150 may be disposed on the gate insulating layer 126. The third conductive layer 150 may include a first gate electrode G1 of the first thin film transistor T1 and a second gate electrode G2 of the second thin film transistor T2. The gate electrodes G1 and G2 may overlap with the channel regions of the semiconductor layers ACT1 and ACT2 of the thin film transistors T1 and T2, respectively. For example, the third conductive layer 150 may include one or more selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu).

[0050] The interlayer insulating layer 127 may be disposed on the third conductive layer 150. The interlayer insulating layer 127 may include an inorganic material or an organic material. For example, the inorganic material may include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), but is not limited thereto. Unlike shown, the interlayer insulating layer 127 may include a plurality of layers. That is, the interlayer insulating layer 127 may be provided as a layer formed by alternately stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once. For example, the interlayer insulating layer 127 may be used to insulate the gate electrodes G1 and G2 and the fourth conductive layer 160 to be described below.

[0051] The fourth conductive layer 160 may be disposed on the interlayer insulating layer 127 .

[0052] The fourth conductive layer 160 may include a first source electrode SDa and a first drain electrode SDb of the first thin film transistor T1 , a second source electrode SDc and a second drain electrode SDd of the second thin film transistor T2 , and a connection line CNE.

[0053] The fourth conductive layer 160 may include at least any one of the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu). The fourth conductive layer 160 may be a single film made of the above-mentioned exemplary materials. The present disclosure is not limited thereto, and the fourth conductive layer 160 may be a stacked film. For example, the fourth conductive layer 160 may be formed as a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, Ti / Cu, etc.

[0054] The first source electrode SDa of the first thin film transistor T1 may be electrically connected to the first region of the first semiconductor layer ACT1 through a contact hole CT passing through the interlayer insulating layer 127 and the gate insulating layer 126 .

[0055] The first drain electrode SDb of the first thin film transistor T1 may be electrically connected to the second region of the first semiconductor layer ACT1 through a contact hole CT passing through the interlayer insulating layer 127 and the gate insulating layer 126 .

[0056] The second source electrode SDc of the second thin film transistor T2 may be electrically connected to the first region of the second semiconductor layer ACT2 through a contact hole CT passing through the interlayer insulating layer 127 and the gate insulating layer 126 .

[0057] The second drain electrode SDd of the second thin film transistor T2 may be electrically connected to the second region of the second semiconductor layer ACT2 through a contact hole CT passing through the interlayer insulating layer 127 and the gate insulating layer 126 .

[0058] The first thin film transistor T1 according to the first embodiment may include a channel region, a first electrode, a second electrode, and a first gate electrode G1. The channel region may be a region of the first semiconductor layer ACT1 that overlaps with the first gate electrode G1, the first electrode may be a region (or first region) that overlaps and contacts the first source electrode SDa or the first source electrode SDa on the first semiconductor layer ACT1, and the second electrode may be a region (or second region) that overlaps and contacts the first drain electrode SDb or the first drain electrode SDb on the first semiconductor layer ACT1. For example, the first thin film transistor T1 may include the first semiconductor layer ACT1, the first gate electrode G1, the first source electrode SDa, and the first drain electrode SDb.

[0059] The second thin film transistor T2 according to the first embodiment may include a channel region, a first electrode, a second electrode, and a second gate electrode G2. The channel region may be a region of the second semiconductor layer ACT2 that overlaps with the second gate electrode G2, the first electrode may be a region (or a first region) that overlaps and contacts the second source electrode SDc or the second source electrode SDc on the second semiconductor layer ACT2, and the second electrode may be a region (or a second region) that overlaps and contacts the second drain electrode SDd or the second drain electrode SDd on the second semiconductor layer ACT2. For example, the second thin film transistor T2 may include the second semiconductor layer ACT2, the second gate electrode G2, the second source electrode SDc, and the second drain electrode SDd.

[0060] According to the first embodiment, the first thin film transistor T1 and the second thin film transistor T2 may be electrically connected. The first thin film transistor T1 and the second thin film transistor T2 may be connected through a connection line CNE. According to the present embodiment, the connection line CNE may be provided in the fourth conductive layer 160. The connection line CNE may be provided between the first drain electrode SDb and the second drain electrode SDd, and the first drain electrode SDb and the second drain electrode SDd may be electrically connected through the connection line CNE. The first drain electrode SDb and the second drain electrode SDd may each be directly connected to the connection line CNE.

[0061] The display device according to the first embodiment shows that adjacent thin film transistors (in Figure 1 In the embodiment, the electrical connection between the first thin film transistor T1 and the second thin film transistor T2 can be performed through the connection line CNE located in the fourth conductive layer 160.

[0062] In the following, other embodiments will be described. Figures 2 to 4 The embodiment of FIG. 1 shows the electrical connection relationship between adjacent thin film transistors. Figures 2 to 4 The embodiments show that electrical connections between thin film transistors can be made in different ways.

[0063] Figure 2is a cross-sectional view of a display device according to a second embodiment.

[0064] according to Figure 2 The display device and the Figure 1 The display device of FIG. 1 is different in that the connection line CNE_1 is located in the semiconductor layer.

[0065] More specifically, in the case of the display device according to the second embodiment, the first drain electrode SDb (see Figure 1 ) and the second drain electrode SDd (see Figure 1 ). The second electrode of the first thin film transistor T1 of the display device according to the present embodiment may be a second region (region connected to the connection line CNE_1) located at one side of the channel region of the first semiconductor layer ACT1. In addition, the second electrode of the second thin film transistor T2 may be a second region (region connected to the connection line CNE_1) located at the other side of the channel region of the second semiconductor layer ACT2. The connection line CNE_1 may be coplanarly positioned with the first semiconductor layer ACT1 and the second semiconductor layer ACT2, and may include the same material as the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The connection line CNE_1 may be directly connected to the first semiconductor layer ACT1 and the second semiconductor layer ACT2. The connection line CNE_1 may be electrically connected to the first semiconductor layer ACT1 and the second semiconductor layer ACT2.

[0066] The connection line CNE_1 may be a conductive region, such as a first region and a second region of the thin film transistors T1 and T2 .

[0067] According to the display device according to the second embodiment, since the second region located at one side of the channel region of the first semiconductor layer ACT1 (the region connected to the connection line CNE_1) and the second region located at the other side of the channel region of the second semiconductor layer ACT2 (the region connected to the connection line CNE_1) are used as the second electrodes of the thin film transistors T1 and T2, respectively, the above-mentioned Figure 1 The first drain electrode SDb described in Figure 1 ) and the second drain electrode SDd (see Figure 1 ). In addition, since the contact hole CT connecting the first drain electrode SDb with the second region of the first semiconductor layer ACT1 and the contact hole CT connecting the second drain electrode SDd with the second region of the second semiconductor layer ACT2 can be omitted, the process can be simplified.

[0068] Figure 3 is a cross-sectional view of a display device according to a third embodiment.

[0069] Reference Figure 3 ,according to Figure 3 The display device and the Figure 1 The display device of FIG. 1 is different in that the connection line CNE_2 is located in the second conductive layer 140 .

[0070] More specifically, in the case of the display device according to the third embodiment, the first drain electrode SDb of the first thin film transistor T1 may be electrically connected to the connection line CNE_2 through the contact hole CT, and the second drain electrode SDd of the second thin film transistor T2 may be electrically connected to the connection line CNE_2 through the contact hole CT. The connection line CNE_2 may be positioned coplanar with the light blocking layer 141 and may include the same material as the light blocking layer 141.

[0071] According to the display device according to the third embodiment, since the connection line CNE_2 is located in the second conductive layer 140 , a sufficient space for disposing the connection line CNE_2 can be secured compared to the first embodiment in which the connection line CNE is located in the fourth conductive layer 160 .

[0072] In addition, since the reflectivity of the second conductive layer 140 is higher than that of the semiconductor layer, light can be prevented from entering and traveling inside the connection line CNE_2, thereby preventing the characteristics of the first and second thin film transistors from being changed by light and the reliability from being deteriorated.

[0073] In addition, as mentioned above Figure 1 As described in, since the second conductive layer 140 has better hydrogen capture capability than the first conductive layer 130 and the fourth conductive layer 160, when the first thin film transistor T1 and the second thin film transistor T2 are electrically connected by using the connecting line CNE_2 located in the second conductive layer 140, the fluctuation of the threshold voltage (Vth) of the first thin film transistor T1 and the second thin film transistor T2 can be minimized.

[0074] Figure 4 is a cross-sectional view of a display device according to a fourth embodiment.

[0075] Reference Figure 4 ,according to Figure 4 The display device and the Figure 3 The display device of FIG. 1 is different in that the connection line CNE_3 is located in the first conductive layer 130_1 .

[0076] More specifically, in the case of the display device according to the fourth embodiment, the first drain electrode SDb of the first thin film transistor T1 may be electrically connected to the connection line CNE_3 through the contact hole CT, and the second drain electrode SDd of the second thin film transistor T2 may be electrically connected to the connection line CNE_3 through the contact hole CT. The connection line CNE_3 may be located in the first conductive layer 130_1 and may include the same material as the first conductive layer 130_1.

[0077] According to the display device according to the fourth embodiment, since the connection line CNE_3 is located in the first conductive layer 130_1 , a sufficient space for disposing the connection line CNE_3 can be ensured compared to the first embodiment in which the connection line CNE is located in the fourth conductive layer 160 .

[0078] In addition, since the reflectivity of the first conductive layer 130 is higher than that of the semiconductor layer, light can be prevented from entering and traveling inside the connection line CNE_3, thereby preventing the characteristics of the first and second thin film transistors T1 and T2 from being changed by light and deteriorating their reliability.

[0079] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, from a plan view, the connection lines CNE, CNE_1, CNE_2, CNE_3 are on the substrate 110 and between the first thin film transistor T1 and the second thin film transistor T2. The connection lines electrically connect the first thin film transistor T1 and the second thin film transistor T2. In addition, the connection lines and the substrate 110 are spaced apart from each other by varying distances.

[0080] For example, in Figure 1 In the embodiment of the present invention, the connection line CNE and the substrate 110 are spaced apart from each other by a first distance D1. More specifically, the first distance D1 is defined by a distance between a bottom surface BS of the connection line CNE and a top surface TS of the substrate 110.

[0081] exist Figure 2 In the embodiment of the present invention, the connection line CNE_1 and the substrate 110 are spaced apart from each other by a second distance D2. More specifically, the second distance D2 is defined by a distance between a bottom surface BS of the connection line CNE_1 and a top surface TS of the substrate 110.

[0082] exist Figure 3 In the embodiment, the connection line CNE_2 and the substrate 110 are spaced apart from each other by a third distance D3. More specifically, the third distance D3 is defined by a distance between a bottom surface BS of the connection line CNE_2 and a top surface TS of the substrate 110.

[0083] exist Figure 4 In the embodiment, the connection line CNE_3 and the substrate 110 are spaced apart from each other by a fourth distance D4. More specifically, the fourth distance D4 is defined by a distance between a bottom surface BS of the connection line CNE_3 and a top surface TS of the substrate 110.

[0084] In some embodiments, the light emitting element EL is electrically connected to the first thin film transistor T1 and the second thin film transistor T2. Figure 5As shown, the light emitting element EL may be electrically connected to the thin film transistors T1 , T2 , T3 , T4 , T5 , and T6 .

[0085] like Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the semiconductor layers (eg, ACT1, ACT2) and the substrate 110 are spaced apart from each other by varying distances.

[0086] For example, in Figure 1 In FIG. 1 , the semiconductor layer ACT1 and the substrate 110 are spaced apart from each other by a distance D11. More specifically, the distance D11 is defined by the distance between the bottom surface BBS of the semiconductor layer ACT1 and the top surface TS of the substrate 110. As shown, the distances D11 and D1 are different from each other. Figure 1 In an embodiment, the distance D1 is greater than the distance D11.

[0087] exist Figure 2 In FIG. 1 , the semiconductor layer ACT1 and the substrate 110 are spaced apart from each other by a distance D22. More specifically, the distance D22 is defined by the distance between the bottom surface BBS of the semiconductor layer ACT1 and the top surface TS of the substrate 110. As shown, the distances D22 and D2 are different from each other. Figure 2 In the embodiment of the present invention, the distance D22 is greater than the distance D2. Here, both the semiconductor layer ACT1 and the connection line CNE_1 are on the same layer. That is, both the semiconductor layer ACT1 and the connection line CNE_1 are on the fourth insulating layer 125. However, the distance D2 is less than the distance D22, so that the bottom surface BS of the connection line CNE_1 is closer to the top surface TS of the substrate 110 than the bottom surface BBS of the semiconductor layer ACT1.

[0088] exist Figure 3 In FIG. 1 , the semiconductor layer ACT1 and the substrate 110 are spaced apart from each other by a distance D33. More specifically, the distance D33 is defined by the distance between the bottom surface BBS of the semiconductor layer ACT1 and the top surface TS of the substrate 110. As shown, the distances D33 and D3 are different from each other. Figure 3 In an embodiment, distance D33 is greater than distance D3.

[0089] exist Figure 4 In FIG. 1 , the semiconductor layer ACT1 and the substrate 110 are spaced apart from each other by a distance D44. More specifically, the distance D44 is defined by the distance between the bottom surface BBS of the semiconductor layer ACT1 and the top surface TS of the substrate 110. As shown, the distances D44 and D4 are different from each other. Figure 4 In an embodiment, distance D44 is greater than distance D4.

[0090] Hereinafter, a display device having a pixel circuit diagram with a 6T1C structure will be described (fifth embodiment). For ease of description, although the pixel of the display device according to the fifth embodiment is illustrated as 6T1C, the present disclosure is not limited thereto, and the pixel of the display device according to the fifth embodiment may have various pixel circuit diagrams, such as 3T1C, 6T2C, 7T1C, 7T2C, 8T1C, and 8T2C. That is, Figure 5 The pixel circuit diagram for description is shown exemplarily, and the present disclosure is not limited thereto, as long as the structure can control the light emission of the light emitting element EL by receiving the emission signal EM(n). For example, the pixel circuit may include an additional scanning signal, a switching thin film transistor connected to the additional scanning signal, and a switching thin film transistor to which an additional initialization voltage is applied, and the connection relationship of the switching element or the connection position of the capacitor may be set differently. In the following, for the convenience of description, the pixel circuit with Figure 5 A display device with a pixel circuit structure.

[0091] Figure 5 is a pixel circuit diagram of a display device according to a fifth embodiment. Figure 6 is based on Figure 5 A cross-sectional view of a display device.

[0092] Reference Figure 5 and Figure 6 , each of the plurality of pixels P may include first to sixth thin film transistors T1 to T6 , a capacitor CST, and a light emitting element EL connected to a pixel circuit.

[0093] The pixel circuit can drive the light emitting element EL by controlling the driving current flowing in the light emitting element EL. The pixel circuit may include a first thin film transistor T1 to a sixth thin film transistor T6 and a capacitor CST. Each of the thin film transistors T1 to T6 may include a first electrode, a second electrode and a gate electrode. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode.

[0094] Each of the thin film transistors T1 to T6 may be a p-type thin film transistor or an n-type thin film transistor. Figure 5 In the embodiment of FIG. 1 , all thin film transistors T1 to T6 are shown as n-type thin film transistors.

[0095] However, the present invention is not limited thereto, and according to an embodiment, some of the thin film transistors T1 to T6 may be formed as p-type thin film transistors.

[0096] In addition, the n-type thin film transistor may be an oxide thin film transistor, and the p-type thin film transistor may be a polysilicon thin film transistor.

[0097] Hereinafter, a case where all the thin film transistors T1 to T6 are n-type thin film transistors will be mainly described.

[0098] Therefore, the thin film transistors T1 to T6 are turned on by receiving the high voltage.

[0099] According to one example, the second thin film transistor T2 forming the pixel circuit can be used as a driving transistor, the third thin film transistor T3 can be used as a compensation transistor, the first thin film transistor can be used as a data supply transistor, the fourth thin film transistor T4 and the fifth thin film transistor T5 can be used as emission control transistors, and the sixth thin film transistor T6 can be used as an initialization transistor.

[0100] The light emitting element EL may include an anode and a cathode. The anode of the light emitting element EL may be connected to the second electrode of the fifth thin film transistor T5, and the cathode thereof may be connected to the low potential driving voltage EVSS.

[0101] The second thin film transistor T2 may include a first electrode connected to the second electrode of the fourth thin film transistor T4, a second electrode connected to the first electrode of the fifth thin film transistor T5, and a gate electrode connected to the second electrode of the third thin film transistor T3. The second thin film transistor T2 may provide a driving current to the light emitting element EL based on the data voltage stored in the capacitor CST.

[0102] The third thin film transistor T3 may include a first electrode connected to the second electrode of the fourth thin film transistor T4, a second electrode connected to the gate electrode of the second thin film transistor T2, and a gate electrode for receiving the first scan signal SCAN1(n). The third thin film transistor T3 may be turned on in response to the first scan signal SCAN1(n), and a diode is connected between the first electrode and the second electrode to sample a threshold voltage (Vth) of the second thin film transistor T2. The third thin film transistor T3 may be a compensation transistor.

[0103] The capacitor CST may be connected or formed between the second electrode of the third thin film transistor T3 (or the gate electrode of the second thin film transistor T2 ) and the anode of the light emitting element EL.

[0104] The first thin film transistor T1 may include a first electrode connected to the data line DL (or for receiving the data voltage DATA), a second electrode connected to the second electrode of the second thin film transistor T2 (or the first electrode of the fifth thin film transistor T5), and a gate electrode for receiving the second scan signal SCAN2 (n). The first thin film transistor T1 may be turned on in response to the second scan signal SCAN2 (n), and may transmit the data voltage DATA to the second electrode of the second thin film transistor T2 (or the first electrode of the fifth thin film transistor T5). The first thin film transistor T1 may be a data supply transistor.

[0105] The fourth thin film transistor T4 and the fifth thin film transistor T5 (or the first emission control transistor and the second emission control transistor) can be connected to the high potential voltage line VDDEL, connected between the high potential driving voltage EVDD and the light emitting element EL, and can form a current moving path, through which the driving current generated by the second thin film transistor T2 moves.

[0106] The fourth thin film transistor T4 may include a first electrode for receiving the high potential driving voltage EVDD, a second electrode connected to the first electrode of the second thin film transistor T2 (or the first electrode of the third thin film transistor T3 ), and a gate electrode for receiving the emission control signal EM(n).

[0107] The fifth thin film transistor T5 may include a first electrode connected to the second electrode of the second thin film transistor T2 (or the second electrode of the first thin film transistor T1), a second electrode connected to the second electrode of the sixth thin film transistor T6 (or the anode electrode of the light emitting element EL), and a gate electrode for receiving the emission control signal EM(n-1).

[0108] The fourth thin film transistor T4 and the fifth thin film transistor T5 may be turned on in response to the emission control signals EM(n) and EM(n-1), respectively, and in this case, a driving current may be supplied to the light emitting element EL, and the light emitting element EL may emit light having a brightness corresponding to the driving current. Figure 5 , the fourth thin film transistor T4 and the fifth thin film transistor T5 are shown to be turned on in response to the emission control signals EM(n) and EM(n-1), respectively, but are not limited thereto, and the fourth thin film transistor T4 and the fifth thin film transistor T5 may be turned on in response to the same emission control signal EM(n).

[0109] The sixth thin film transistor T6 may include a first electrode for receiving the initialization voltage VINI, a second electrode connected to the anode of the light emitting element EL, and a gate electrode for receiving the first scan signal SCAN1 (n).

[0110] The sixth thin film transistor T6 may be turned on in response to the first scan signal SCAN1(n) before the light emitting element EL emits light (or after the light emitting element EL emits light), and may initialize the anode (or pixel electrode) of the light emitting element EL using the initialization voltage VINI. The light emitting element EL may have a parasitic capacitor formed between the anode electrode and the cathode electrode. In addition, when the light emitting element EL emits light, the parasitic capacitor may be charged so that the anode of the light emitting element EL may have a specific voltage. Therefore, the amount of charge accumulated in the light emitting element EL may be initialized by applying the initialization voltage VINI to the anode of the light emitting element EL through the sixth thin film transistor T6.

[0111] Figure 6 The connection relationship between the sixth thin film transistor T6, the fifth thin film transistor T5 and the second thin film transistor T2 is shown. Figure 6 In the cross-sectional view of the display device according to the fifth embodiment shown in FIG. Figures 1 to 4 The sixth thin film transistor T6 may be used as an initialization transistor, the fifth thin film transistor T5 may be used as an emission control transistor, and the second thin film transistor T2 may be used as a driving transistor.

[0112] The second conductive layer 140 may include a light blocking layer 141 and a connection line CNE_2 under the semiconductor layers ACT6, ACT5, and ACT2 of the thin film transistors T6, T5, and T2. The light blocking layer 141 and the second connection line CNE_2 may include the same material.

[0113] The semiconductor layer may include a sixth semiconductor layer ACT6 of the sixth thin film transistor T6, a fifth semiconductor layer ACT5 of the fifth thin film transistor T5, a second semiconductor layer ACT2 of the second thin film transistor T2, and a first connection line CNE_1. The sixth semiconductor layer ACT6 may include a channel region ACT61, a first region ACT62 overlapping with and electrically connected to a source electrode SD6 to be described below, and a second region ACT63 electrically connected to and directly connected to the first connection line CNE_1. The fifth semiconductor layer ACT5 may include a channel region ACT51, a second region ACT53 electrically connected to and directly connected to the first connection line CNE_1, and a first region ACT52 overlapping with and electrically connected to a source electrode SD5 to be described below. The first region ACT52 may be electrically connected to the second connection line CNE_2 through the source electrode SD5. The second semiconductor layer ACT2 may include a channel region ACT21, a first region ACT22 overlapping with and electrically connected to a source electrode SD21 to be described below, and a second region ACT23 electrically connected to the second connection line CNE_2 and overlapping with and electrically connected to the drain electrode SD22. The second region ACT23 may be electrically connected to the second connection line CNE_2 through the drain electrode SD22.

[0114] The third conductive layer 150 may include a sixth gate electrode G6 of the sixth thin film transistor T6 , a fifth gate electrode G5 of the fifth thin film transistor T5 , and a second gate electrode G2 of the second thin film transistor T2 .

[0115] The fourth conductive layer 160 may include a source electrode SD6 of the sixth thin film transistor T6 , a source electrode SD5 of the fifth thin film transistor T5 , and a drain electrode SD22 and a source electrode SD21 of the second thin film transistor T2 .

[0116] at the same time, Figure 6 The structure above the fourth conductive layer 160 of the display device is also shown. Figure 6 The display device may further include: a planarization layer 128 disposed on the fourth conductive layer 160; a first electrode ANO disposed on the planarization layer 128; a bank layer 129 disposed on the first electrode ANO; an organic layer OL disposed on the upper surface of the first electrode ANO exposed by the bank layer 129; a second electrode CAT disposed on the organic layer OL; and an encapsulation layer 180 disposed on the second electrode CAT. Figure 6As shown, the planarization layer 128 disposed on the fourth conductive layer 160, the first electrode ANO disposed on the planarization layer 128, the bank layer 129 disposed on the first electrode ANO, the organic layer OL disposed on the upper surface of the first electrode ANO exposed by the bank layer 129, the second electrode CAT disposed on the organic layer OL, and the encapsulation layer 180 disposed on the second electrode CAT can also be applied according to Figures 1 to 4 The above-mentioned display device.

[0117] The planarization layer 128 may be disposed on the fourth conductive layer 160. The planarization layer 128 may include an organic material. The planarization layer 128 may be used to planarize the fourth conductive layer 160.

[0118] The first electrode ANO may be disposed on the planarization layer 128. The first electrode ANO may be used as an anode of the display device. A bank layer 129 may be provided to cover the edge of the first electrode ANO. The emission region may be defined by the bank layer 129. The bank layer 129 may expose the upper surface of the first electrode ANO. The first electrode ANO may be electrically connected to the second region ACT53 of the fifth semiconductor layer ACT5 of the fifth thin film transistor T5 through the 5-3 contact hole CT53. However, the present disclosure is not limited thereto, and the first electrode ANO may be electrically connected to the second region ACT63 of the sixth semiconductor layer ACT6 of the sixth thin film transistor T6 through the contact hole.

[0119] The organic layer OL may be disposed on the upper surface of the first electrode ANO exposed by the bank layer 129. Figure 6 1 and 2. It is shown that the organic layer OL is disposed only on the upper surface of the first electrode ANO exposed by the bank layer 129, but the present disclosure is not limited thereto, and the organic layer OL may be integrally formed in the entire pixel P (see FIG. 1). Figure 5 ).

[0120] The second electrode CAT is formed on the organic layer OL. The second electrode CAT may be used as a cathode of the display device. The second electrode CAT may be formed integrally in the entire pixel P (see Figure 5 ).

[0121] The first electrode ANO, the organic layer OL, and the second electrode CAT may form an organic light emitting element EL.

[0122] The encapsulation layer 180 is formed on the second electrode CAT to prevent external moisture from penetrating the organic layer OL. The encapsulation layer 180 may be made of an inorganic insulating material, or may be formed in a structure in which an inorganic insulating material and an organic insulating material are alternately stacked, but is not necessarily limited thereto. For example, the encapsulation layer 180 may include a first encapsulation layer 181 and a third encapsulation layer 183 including an inorganic insulating material, and a second encapsulation layer 182 including an organic insulating material between the first encapsulation layer 181 and the third encapsulation layer 183, but is not limited thereto.

[0123] The sixth thin film transistor T6 may include a sixth gate electrode G6, a first electrode, and a second electrode. The first electrode of the sixth thin film transistor T6 may be the first region ACT62 or the source electrode SD6. The second electrode of the sixth thin film transistor T6 may be the second region ACT63.

[0124] The fifth thin film transistor T5 may include a fifth gate electrode G5, a first electrode, and a second electrode. The first electrode of the fifth thin film transistor T5 may be the first region ACT52 or the source electrode SD5. The second electrode of the fifth thin film transistor T5 may be the second region ACT53.

[0125] The second thin film transistor T2 may include a second gate electrode G2 , a first electrode, and a second electrode.

[0126] The first electrode of the second thin film transistor T2 may be the first region ACT22 or the source electrode SD21 .

[0127] The second electrode of the second thin film transistor T2 may be the second region ACT23 or the drain electrode SD22 .

[0128] The source electrode SD6 of the sixth thin film transistor T6 may be electrically connected to the first region ACT62 through the sixth contact hole CT6 .

[0129] The source electrode SD5 of the fifth thin film transistor T5 may be electrically connected to the first area ACT52 through the 5-1 contact hole CT51 and electrically connected to the second connection line CNE_2 through the 5-2 contact hole CT52.

[0130] The source electrode SD21 of the second thin film transistor T2 may be electrically connected to the first area ACT22 through the 2-1 contact hole CT21, and the drain electrode SD22 may be electrically connected to the second area ACT23 through the 2-2 contact hole CT22 and to the second connection line CNE_2 through the 2-3 contact hole CT23.

[0131] According to the fifth embodiment, the electrical connection method between the sixth thin film transistor T6 and the fifth thin film transistor T5 may be different from the electrical connection method between the fifth thin film transistor T5 and the second thin film transistor T2. In this embodiment, the sixth thin film transistor T6 and the fifth thin film transistor T5 may be electrically connected through a first connection line CNE_1 located coplanar with the semiconductor layer, and the fifth thin film transistor T5 and the second thin film transistor T2 may be electrically connected through a second connection line CNE_2 located in the second conductive layer 140.

[0132] In the present embodiment, the second thin film transistor T2 and the third thin film transistor T3 may be sensitive to fluctuations in the threshold voltage (Vth). In the present specification, when some thin film transistors (e.g., T2 and T3) are sensitive to fluctuations in the threshold voltage (Vth) compared to other thin film transistors T1 and T4 to T6, this means that when fluctuations in the threshold voltage (Vth) from the initial setting threshold voltage (Vth) of the thin film transistors T2 and T3 are caused by light, temperature, hydrogen, etc., fluctuations in the brightness of the light emitting element EL are caused by the corresponding fluctuations, and the amplitude of the fluctuations is relatively large compared to the other thin film transistors T1 and T4 to T6. For example, while each of the thin film transistors T2 and T3 can have a change rate of the driving current Ioled of -3.44 to 13.68% and -6.09 to 8.26% respectively relative to the reference driving current at the threshold voltage (Vth) of -0.5 to 0.5V, the other thin film transistors T1 and T4 to T6 can have a change rate of the driving current Ioled of -0.08 to 0.23%, -0.09 to 0.05%, -0.45 to 0.01% and -0.6 to 1.29% respectively relative to the reference driving current at the threshold voltage (Vth) of -0.5 to 0.5V.

[0133] Therefore, in order to electrically connect the second thin film transistor T2 sensitive to fluctuations in threshold voltage (Vth) with the adjacent fifth thin film transistor T5, a second connection wire CNE_2 having a second conductive layer 140 with a higher reflectivity than the semiconductor layer may be applied. Therefore, a phenomenon in which light enters the connection wire CNE_2 and travels inside the connection wire CNE_2 may be prevented, thereby preventing the characteristics of the second thin film transistor T2 from being changed by light and preventing degradation of its reliability.

[0134] In addition, compared with the second thin film transistor T2 and the third thin film transistor T3, the first thin film transistor T1 and the fourth thin film transistor T4 to the sixth thin film transistor T6 may be less sensitive to fluctuations in the threshold voltage (Vth). Therefore, in the process of electrically connecting the sixth thin film transistor T6 and the fifth thin film transistor T5, in order to simplify the process rather than considering that the characteristics of the thin film transistors T5 and T6 are changed by light, it is more effective to reduce the contact holes between the source electrode / drain electrode and the semiconductor layers ACT6 and ACT5. The second electrode ACT63 of the sixth semiconductor layer ACT6 of the sixth thin film transistor T6 and the second electrode ACT53 of the fifth semiconductor layer ACT5 of the fifth thin film transistor T5 can be electrically connected by directly connecting to the first connection line CNE_1 positioned coplanarly.

[0135] In the present embodiment, the second thin film transistor T2 and the third thin film transistor T3 may be sensitive to fluctuations in the threshold voltage (Vth). Therefore, in order to electrically connect the second thin film transistor T2, which is sensitive to fluctuations in the threshold voltage (Vth), to the adjacent fifth thin film transistor T5, a second connection line CNE_2 having a second conductive layer 140 with a higher reflectivity than the semiconductor layer may be applied. Therefore, a phenomenon in which light enters the connection line CNE_2 and travels inside the connection line CNE_2 may be prevented, thereby preventing the characteristics of the second thin film transistor T2 from being changed by light and preventing degradation of its reliability.

[0136] Figure 7 is based on Figure 6 sectional view of a modified example of the display device.

[0137] Reference Figure 7 , modify the example and according to Figure 6 The embodiment is different from the embodiment in that the fifth thin film transistor T5 and the second thin film transistor T2 of the display device according to the present embodiment may be electrically connected through a third connection line CNE_3.

[0138] Since the above is already Figure 4 The third connection line CNE_3 is described in the connection line CNE_3 of FIG. 1 , and thus its detailed description will be omitted below. Figure 7 In an embodiment, the first conductive layer 130_1 may include a light blocking layer 131 and a connection line CNE_3 respectively located below the semiconductor layers ACT5 and ACT2 of the thin film transistors T5 and T2. That is, unlike the light blocking layer 141 of the sixth thin film transistor T6, in the fifth thin film transistor T5 and the second thin film transistor T2, the light blocking layer 131 may be disposed in the first conductive layer 130_1. The light blocking layer 131 and the third connection line CNE_3 may include the same material.

[0139] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs will be able to understand that the technical configuration described above of the present invention can be performed in other specific forms without changing its technical spirit or basic features. Therefore, it should be understood that the embodiments described above are illustrative in all aspects, rather than restrictive. In addition, the scope of the present invention is described by the claims to be described herein rather than by detailed description. In addition, the meaning and scope of the claims and all changes or modifications derived from equivalent concepts should be interpreted as being included within the scope of the present invention.

[0140] Description of Reference Numerals

[0141] 1: Display device

[0142] 200: Controller

[0143] 300: Gate driver

[0144] 310: Scan driver

[0145] 320: Transmit control signal driver

Claims

1. A display device, comprising a first thin film transistor, a second thin film transistor and a third thin film transistor, each thin film transistor comprising: Semiconductor layer, a gate electrode disposed on the semiconductor layer, and a first electrode and a second electrode, The connection between the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor is different from the connection between the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

2. The display device according to claim 1, wherein: The semiconductor layer of the first thin film transistor, the semiconductor layer of the second thin film transistor, and the semiconductor layer of the third thin film transistor each include an oxide.

3. The display device according to claim 1, wherein: The semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor are electrically connected through a connection line located coplanar with the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor.

4. The display device according to claim 3, wherein: The semiconductor layer of the first thin film transistor, the semiconductor layer of the second thin film transistor and the connection line include the same material.

5. The display device according to claim 3, wherein: A first scan signal is applied to a gate electrode of the first thin film transistor, an initialization voltage is applied to a first electrode of the first thin film transistor, and a second electrode of the first thin film transistor is electrically connected to a first electrode of the second thin film transistor.

6. The display device according to claim 5, wherein: The first thin film transistor is an initialization transistor.

7. The display device according to claim 3, wherein: An emission control signal is applied to a gate electrode of the second thin film transistor, a first electrode of the second thin film transistor is electrically connected to a second electrode of the first thin film transistor, and a second electrode of the second thin film transistor is electrically connected to a second electrode of the third thin film transistor.

8. The display device according to claim 7, wherein: The second thin film transistor is an emission control transistor.

9. The display device according to claim 1, wherein: The semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor are electrically connected through a connection line located at a layer different from the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

10. The display device according to claim 9, wherein: The connection line is disposed under the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

11. The display device according to claim 9, wherein: The semiconductor layer of the second thin film transistor and the connection line are electrically connected through the second electrode of the second thin film transistor, and the semiconductor layer of the third thin film transistor and the connection line are electrically connected to the second electrode of the third thin film transistor.

12. The display device according to claim 1, wherein: A first scan signal is applied to a gate electrode of the first thin film transistor, an initialization voltage is applied to a first electrode of the first thin film transistor, and a second electrode of the first thin film transistor is electrically connected to a first electrode of the second thin film transistor.

13. The display device according to claim 12, wherein: The first thin film transistor is an initialization transistor.

14. The display device according to claim 1, wherein: An emission control signal is applied to a gate electrode of the second thin film transistor, a first electrode of the second thin film transistor is electrically connected to a second electrode of the first thin film transistor, and a second electrode of the second thin film transistor is electrically connected to a second electrode of the third thin film transistor.

15. The display device according to claim 14, wherein: The second thin film transistor is an emission control transistor. 16 . The display device according to claim 1 , further comprising a capacitor provided between the second electrode of the first thin film transistor and the third thin film transistor.

17. The display device according to claim 16, wherein: A gate electrode of the third thin film transistor is electrically connected to the capacitor, a high potential voltage is applied to a first electrode of the third thin film transistor, and a second electrode of the third thin film transistor is electrically connected to a second electrode of the second thin film transistor.

18. The display device according to claim 17, wherein: The third thin film transistor is a driving transistor.

19. A display device, comprising a first thin film transistor, a second thin film transistor and a third thin film transistor, each thin film transistor comprising: Semiconductor layer, a gate electrode disposed on the semiconductor layer, and a first electrode and a second electrode, The semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor are connected via a first connecting line. The semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor are connected through a second connecting line, and The reflectivity of the first connecting line is lower than the reflectivity of the second connecting line.

20. The display device according to claim 19, wherein: The first connection line is positioned coplanar with the semiconductor layer of the first thin film transistor and the semiconductor layer of the second thin film transistor, and the second connection line is located below the semiconductor layer of the second thin film transistor and the semiconductor layer of the third thin film transistor.

21. A display device, comprising: substrate; a first thin film transistor on the substrate and a second thin film transistor adjacent to the first thin film transistor; A connecting line on the substrate and between the first thin film transistor and the second thin film transistor is viewed from a plan view, the connecting line electrically connecting the first thin film transistor and the second thin film transistor, and the connecting line and the substrate are spaced apart from each other by a first distance; a light emitting element electrically connected to at least one of the first thin film transistor and the second thin film transistor; Wherein, the first thin film transistor and the second thin film transistor each include: a semiconductor layer on the substrate, the semiconductor layer and the substrate being spaced apart from each other by a second distance, a gate electrode adjacent to the semiconductor layer, and a first electrode and a second electrode adjacent to the gate electrode, The second distance is different from the first distance.

22. The display device according to claim 21, wherein: The first distance is shorter than the second distance, so that the connection line is closer to the substrate than the semiconductor layer of the first thin film transistor or the second thin film transistor.

23. The display device according to claim 21, wherein: The connection line and semiconductor layers of the first and second thin film transistors are on the same layer.

24. The display device according to claim 21, further comprising: a light blocking layer overlapping with the semiconductor layer of the first thin film transistor or the second thin film transistor, Wherein, the connecting line is on the same layer as the light blocking layer.

25. The display device according to claim 24, wherein: From a plan view, the connecting line is spaced apart from the light blocking layer. Wherein, the light blocking layer and the connecting line are made of the same material.

26. The display device according to claim 21, further comprising: a light blocking layer overlapping with the semiconductor layer of the first thin film transistor or the second thin film transistor, Wherein, the connecting line is on a layer different from the light blocking layer.

27. The display device according to claim 26, wherein: The connection line is closer to the substrate than the light blocking layer.

28. The display device according to claim 26, wherein: The light blocking layer is closer to the substrate than the connecting line.

29. The display device according to claim 26, wherein: From a plan view, the connecting line is spaced apart from the light blocking layer. Wherein, the light blocking layer and the connecting line are made of different materials.

Images