Display device and head mounted display device including the same

Abstract

A display device and a head-mounted display device including the same are provided. The display device includes: a first single crystal semiconductor substrate in which a first transistor is positioned; and a second single-crystal semiconductor substrate on which the second transistor is positioned, the second single-crystal semiconductor substrate having a planar area larger than that of the first single-crystal semiconductor substrate, the second single-crystal semiconductor substrate being positioned above the first single-crystal semiconductor substrate, and a second single crystal semiconductor substrate including a display area in which a sub-pixel including a light emitting element is positioned, the second single crystal semiconductor substrate defining a first through hole in which a first conductive via electrically connected to the data line is positioned, and defining a second through hole in which a second conductive via electrically connected to the gate driving portion is positioned, the data lines are connected with the sub-pixels, and the gate driving parts are electrically connected with the sub-pixels.

Description

Technical Field

[0001] The present disclosure relates to a display device and a head mounted display (HMD) device including the display device. Background Art

[0002] A head mounted display (HMD) device can be worn on a user's head in the form of glasses or a helmet, and functions as a display device that forms an image at a short distance in front of the user's eyes. The HMD device can realize virtual reality (VR) or augmented reality (AR).

[0003] The HMD device uses a plurality of lenses to magnify an image displayed by a small display device. Therefore, the display device for the HMD device can appropriately provide a high-resolution image (e.g., an image with a resolution exceeding 3000 pixels per inch (PPI)). To achieve this, an organic light emitting diode (OLED) on silicon (OLEDoS) display device is being utilized as a high-resolution small-sized OLED display device. The OLEDoS display device is a device that displays an image using an OLED located on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) element is arranged. Summary of the invention

[0004] Aspects of the present disclosure provide an ultra-small display device including a plurality of different single-crystal semiconductor substrates and a head mounted display (HMD) device including the display device.

[0005] Aspects of the present disclosure also provide a display device capable of reducing or minimizing an area occupied by a through hole for connecting two different semiconductor substrates, and an HMD device including the display device.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to one or more disclosed embodiments, a display device includes: a first single crystal semiconductor substrate, on which a first transistor is positioned; and a second single crystal semiconductor substrate, on which a second transistor is positioned, having a planar area larger than a planar area of ​​the first single crystal semiconductor substrate, the second single crystal semiconductor substrate being located above the first single crystal semiconductor substrate, the second single crystal semiconductor substrate including a display area on which a sub-pixel including a light-emitting element is positioned, the second single crystal semiconductor substrate defining a first through hole in which a first conductive via electrically connected to a data line connected to the sub-pixel is positioned, and defining a second through hole in which a second conductive via electrically connected to a gate driving unit electrically connected to the sub-pixel is positioned.

[0008] The number of the first through holes may be greater than the number of the second through holes.

[0009] The number of the first through holes may be equal to the number of columns of the sub-pixels.

[0010] The display device may further include a circuit board over a pad located in a non-display region around the display region of the second single crystalline semiconductor substrate, wherein the second single crystalline semiconductor substrate defines a third through hole overlapping the pad.

[0011] The first through hole may overlap the circuit board in a thickness direction.

[0012] The third through hole may overlap the circuit board and the first single crystal semiconductor substrate.

[0013] The first through hole may not overlap with the pad.

[0014] The display device may further include: a circuit board on a bottom surface of the first single crystalline semiconductor substrate, wherein the first single crystalline semiconductor substrate defines a third through hole in which there exists a conductive via connected to the circuit board.

[0015] The display device may further include a driving circuit portion on the circuit board.

[0016] A width of the first single crystal semiconductor substrate in one direction may be greater than a width of the display region in the one direction.

[0017] The first through hole and the second through hole may be in a non-display area located around the display area in a plan view.

[0018] The data line can extend along a first direction over the second single crystal semiconductor substrate and be electrically connected to some of the first transistors, wherein the display device further includes: a scan line electrically connected to the gate driving unit and extending in a second direction intersecting the first direction over the second single crystal semiconductor substrate.

[0019] The first through holes may be arranged along the first direction parallel to the data lines.

[0020] The number of the first through holes may be equal to the number of the data lines.

[0021] The display device may further include: a connection wiring layer between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate and connected to the first conductive via and the second conductive via.

[0022] According to one or more disclosed embodiments, a head mounted display (HMD) device includes: a frame configured to be worn on a user's body and to correspond to the user's eyes; a display device in the frame; and a lens above the display device, wherein the display device includes: a first single crystal semiconductor substrate on which a first transistor is positioned; and a second single crystal semiconductor substrate above the first single crystal semiconductor substrate and on which a second transistor is positioned, wherein the second single crystal semiconductor substrate includes a display area on which a sub-pixel including a light emitting element is positioned, the second single crystal semiconductor substrate defines a first through hole in which a first conductive via electrically connected to a data line connected to the sub-pixel is positioned, and defines a second through hole in which a second conductive via electrically connected to a gate driving unit electrically connected to the sub-pixel is positioned, and wherein a planar area of ​​the first single crystal semiconductor substrate is smaller than a planar area of ​​the second single crystal semiconductor substrate.

[0023] The number of the first through holes may be equal to the number of columns of the sub-pixels.

[0024] A width of the first single crystal semiconductor substrate in one direction may be greater than a width of the display region in the one direction.

[0025] The first through hole and the second through hole may be in a non-display area located around the display area.

[0026] The HMD device may further include: a circuit board over the pad, the pad being in a non-display area around the display area of ​​the second single crystalline semiconductor substrate in a plan view, wherein the second single crystalline semiconductor substrate defines a third through hole overlapping the pad, and wherein the first through hole overlaps the circuit board in a thickness direction.

[0027] According to the foregoing and other embodiments of the present disclosure, a display includes two different single crystalline semiconductor substrates, and fabrication of the lower single crystalline semiconductor substrate allows for high throughput of each wafer substrate, potentially improving yield.

[0028] In addition, the circuit part can be distributed between two different single crystal semiconductor substrates, and the number of through holes connecting the circuit parts can be reduced or minimized. The display device can alleviate high integration density on a single crystal semiconductor substrate with a narrow area.

[0029] It should be noted that aspects of the present disclosure are not limited to those described above, and other aspects of the present disclosure will be apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which: Figure 1 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure; Figure 2 yes Figure 1 A plan view of an example of a driving portion; Figure 3 yes Figure 1 A plan view of an example of a display portion; Figure 4 It is shown that the Figure 3 A plan view of the arrangement of a plurality of wirings in a display portion; Figure 5 is a block diagram of a display device according to one or more embodiments of the present disclosure; Figure 6 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure; Figure 7 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure; Figure 8 is a bottom view of a display device according to one or more embodiments of the present disclosure; Fig. 9 is a cross-sectional view of a driving portion according to one or more embodiments of the present disclosure; Fig.10 is a plan view showing first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display portion according to one or more embodiments of the present disclosure; Fig.11 is a plan view showing first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display portion according to one or more other embodiments of the present disclosure; Fig.12 and Fig.13 is a cross-sectional view showing a portion of a display area and a non-display area of ​​a display portion according to one or more embodiments of the present disclosure; Fig.14 and Fig.15 is a cross-sectional view of a display device according to another embodiment of the present disclosure; Fig.16 is a cross-sectional view of a display device according to one or more other embodiments of the present disclosure; Fig.17 yes Fig.16 A bottom view of a display device; Fig.18 is a perspective view of an HMD device according to one or more embodiments of the present disclosure; Fig.19 yes Fig.18 An exploded perspective view of an HMD device; and Fig. 20is a perspective view of an HMD device according to one or more other embodiments of the present disclosure. DETAILED DESCRIPTION

[0031] Aspects of some embodiments of the present disclosure and methods for implementing some embodiments of the present disclosure may be more easily understood by referring to the detailed description and drawings of the embodiments. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey aspects of the present disclosure to those skilled in the art. Therefore, processes, elements, and techniques that are redundant, irrelevant or unrelated to the description of the embodiments, or are not necessary for a full understanding of aspects of the present disclosure for those of ordinary skill in the art may be omitted. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals, characters, or combinations thereof represent the same elements, and therefore, their repeated descriptions may be omitted.

[0032] The described embodiments may have various modifications and may be embodied in different forms, and should not be construed as being limited to the embodiments shown here. The use of "may", "may" or "may not" in describing an embodiment corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the conceptual and technical scope of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be partially combined with each other or all combined with each other, and various interlocks and drives are technically feasible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0033] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading is generally provided in the drawings to make the boundaries between adjacent elements clear. As such, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a specific material, material property, size, ratio, commonality between illustrated elements, and / or any other characteristic, attribute, property, etc. of an element.

[0034] Various embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments and / or intermediate structures. As such, variations in the illustrated shapes caused by, for example, manufacturing techniques and / or tolerances are anticipated. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the descriptions of specific structures or functions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the illustrated shapes of elements, layers, or regions, but will include deviations in shapes caused by, for example, manufacturing.

[0035] For example, an implanted region illustrated as a rectangle will, typically, have chamfered or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0036] For ease of explanation, spatial relative terms such as "under ...", "below ...", "lower", "lower side", "below ...", "above ...", "upper", "upper side", etc. may be used here to describe the relationship between an element or feature and another element or feature as shown in the drawings. It will be understood that in addition to the orientation depicted in the drawings, the spatial relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the element described as "under" "under" or "below" other elements or features will then be oriented to be "above" the other elements or features. Therefore, the example terms "under ..." and "under ..." can include both upper and lower orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used here should be interpreted accordingly. Similarly, when a first component (part) is described as being arranged "on" a second component (part), this means that the first component (part) is arranged on the upper or lower side of the second component (part), without being limited to its upper side based on the direction of gravity.

[0037] In addition, the phrase "in a plan view" means when the target portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section intercepted by vertically cutting the object portion is viewed from the side. The term "overlapping with..." or "overlapping" means that the first object can be above or below or on the side of the second object, and vice versa. In addition, the term "overlapping with..." can include stacking, facing or facing, extending on, covering or partially covering, or any other suitable term as will be appreciated and understood by those of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separate" or "biased" or "deviation" and any other suitable equivalents as will be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing" can mean that the first object can be directly or indirectly opposite to the second object. In the case where a third object is between the first object and the second object, the first object and the second object can be understood to be indirectly opposite to each other, but still facing each other.

[0038] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component may be directly formed on, directly on, directly connected to, or directly coupled to the other element, layer, region, or component, or indirectly formed on, indirectly on, indirectly connected to, or indirectly coupled to the other element, layer, region, or component, such that one or more intervening elements, layers, regions, or components may be present. Additionally, this may collectively mean directly coupled or indirectly coupled or directly connected or indirectly coupled as well as integrally coupled or non-integrally coupled or integrally connected or non-integrally connected. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or directly coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. One or more intermediate components may include switches, resistors, and / or capacitors, etc. When describing embodiments, unless explicitly described as being directly connected, the expression of connection indicates electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or directly coupled to another component, or is directly on another component, without intermediate components.

[0039] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upper direction, but includes forming the part on the side surface or in the lower direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this not only includes the case where the part is "directly below" the other part, but also includes the case where there is another part between the part and the other part. At the same time, other expressions describing the relationship between components, such as "between...", "directly between..." or "adjacent to..." and "directly adjacent to..." can be similarly interpreted. It will be understood that when an element or layer is referred to as "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0040] For the purposes of this disclosure, when expressions such as "at least one of..." or "any one of..." or "one or more of..." are located after a list of elements, the entire list of elements is modified without modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one of the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, any combination of two or more of X, Y, and Z (such as XYZ, XYY, YZ, and ZZ as examples), or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as “at least one of,” “a plurality of,” “one of,” and other prepositional phrases when preceding or following a list of elements modify the entire list of elements and do not modify the individual elements of the list.

[0041] It will be understood that, although the terms "first", "second", "third", etc. can be used here to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms do not correspond to a specific order, position or superiority, and are only used to distinguish an element, member, component, region, area, layer, section or part from another element, member, component, region, area, layer, section or part. Therefore, without departing from the scope of the present disclosure, the first element, first component, first region, first layer or first section described below can be referred to as the second element, second component, second region, second layer or second section. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used here to distinguish between elements of different categories or elements of different groups. For the sake of simplicity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0042] In the example, the x-axis, y-axis and / or z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the x-axis, y-axis and z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. The same applies to the first direction, the second direction and / or the third direction.

[0043] The terms used herein are only for the purpose of describing the embodiments and are not intended to be limitations of the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "a (kind / person)" are also intended to include plural forms, and the plural forms are also intended to include singular forms. It will also be understood that when the terms "comprise", "include", "have" and their variations are used in this specification, the descriptions indicate the presence of stated features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0044] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as approximate terms rather than as terms of degree, and are intended to account for the inherent deviations of measured or calculated values ​​that one of ordinary skill in the art will recognize. For example, "substantially" may include a range of + / - 5% of the corresponding value. "About" or "approximately" as used herein include the stated values ​​and mean: within the acceptable deviation range of the specific value as determined by one of ordinary skill in the art, taking into account the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0045] The electronic device or electronic apparatus according to the embodiments of the present disclosure described herein and / or any other related apparatus or component can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware to process data or digital signals. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on separate IC chips. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. The circuit hardware may include, for example, a general-purpose or dedicated central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device such as a field programmable gate array (FPGA) configured to execute instructions stored in a non-temporary storage medium in an application specific integrated circuit (ASIC).

[0046] In some embodiments, known structures and devices may be described in the accompanying drawings with respect to one or more functional blocks (e.g., block diagrams), units and / or modules to avoid making various embodiments unnecessarily obscure. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, optionally driven by firmware and / or software. In addition, each block, unit and / or module may be implemented by a combination of dedicated hardware, or dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and related circuits) that performs functions different from those of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, blocks, units and / or modules may be physically divided into two or more interacting separate blocks, units and / or modules. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense, unless clearly defined as such herein.

[0048] Figure 1 is an exploded perspective view of a display device according to one or more embodiments of the present disclosure.

[0049] Reference Figure 1 The display device 10 is a device that displays a video or a still image. The display device 10 can be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-book readers, portable multimedia players (PMPs), navigation systems, ultra-mobile PCs (UMPCs), etc. For example, the display device 10 can be applied as a display part of a television (TV), a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. In addition, the display device 10 can also be applied to a smart watch, a watch phone, or a head-mounted display (HMD) device for realizing virtual reality (VR) and augmented reality (AR).

[0050] The display device 10 may include a driving part 100, a display part 200, and a circuit board 300. The display device 10 may further include a protective layer 900 around the driving part 100.

[0051] The driving unit 100 may have a planar shape similar to a rectangle. For example, the driving unit 100 may have a planar shape similar to a rectangle having a side in a first direction DR1 and a side in a second direction DR2 intersecting the first direction DR1. The lengths of the side in the first direction DR1 and the side in the second direction DR2 of the driving unit 100 may be different. The corner where the side in the first direction DR1 and the side in the second direction DR2 of the driving unit 100 meet may be formed with a curvature (e.g., a predetermined curvature), or may be formed as a right angle. The planar shape of the driving unit 100 is not specifically limited, and the driving unit 100 may also be formed in a shape similar to a polygon, a circle, or an ellipse.

[0052] The display unit 200 may be located on the driving unit 100. In the display device 10, the driving unit 100 and the display unit 200 may be joined to each other. Unlike the driving unit 100, the display unit 200 may have a square-like shape. For example, the display unit 200 may have a planar shape similar to a square, and may have sides in the first direction DR1 and sides in the second direction DR2 of the same length. The planar shape of the display unit 200 is not specifically limited, and the display unit 200 may also be formed in a shape similar to a polygon, a circle, or an ellipse. The planar shape of the display device 10 may conform to the planar shape of the display unit 200, but the present disclosure is not limited thereto.

[0053] The display unit 200 may have a larger plane area than the drive unit 100. The drive unit 100 and the display unit 200 may include different substrates, and the different substrates may have different areas. Different elements may be formed in the drive unit 100 and the display unit 200, and may be formed separately on different substrates. The display device 10 may be manufactured by forming a plurality of elements having different sizes, line widths, and manufacturing processes on different substrates and then joining the plurality of elements, providing the advantages of improving product performance and yield rate. This will be described later with reference to other drawings.

[0054] The circuit board 300 may be electrically connected to a plurality of pads in a pad region of the display portion 200 using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 may be a flexible printed circuit board or a flexible film. Figure 1The circuit board 300 is shown to be unfolded, but the circuit board 300 may be bent. When the circuit board 300 is bent, one end of the circuit board 300 may be located on the bottom surface of the driving portion 100. The other end of the circuit board 300 may be connected to a pad in the pad area of ​​the display portion 200 using a conductive adhesive member. Alternatively, in other embodiments, the circuit board 300 may be attached to the bottom surface of the driving portion 100.

[0055] In one or more embodiments, the display device 10 may further include a heat dissipation layer that overlaps the driving portion 100 and the display portion 200 in the third direction DR3. The heat dissipation layer may be located on the bottom surface of the driving portion 100 and may dissipate heat generated from the driving portion 100 and the display portion 200. The heat dissipation layer may include a layer of a metal having high thermal conductivity (such as silver, copper, or aluminum) or graphite.

[0056] The protective layer 900 may surround the driving part 100 and may be located on the bottom surface of the display part 200. The protective layer 900 may reduce a step difference caused by a difference between the areas of the driving part 100 and the display part 200 and may also protect the driving part 100 and the display part 200.

[0057] Figure 2 yes Figure 1 A plan view of an example of a drive unit. Figure 3 yes Figure 1 A plan view of an example of a display portion. Figure 4 It is shown that the Figure 3 A plan view showing the arrangement of a plurality of wirings in a display portion.

[0058] Reference Figures 2 to 4 The driving part 100 of the display device 10 may include driving circuit elements of the display device 10. The driving part 100 may include a first single crystal semiconductor substrate 110, a driving circuit part 400 formed on the first single crystal semiconductor substrate 110, and a data driving part 700.

[0059] The first single crystal semiconductor substrate 110 may be a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon germanium (SiGe) substrate. A plurality of first transistors may be formed on the first single crystal semiconductor substrate 110 and may be electrically connected to form a driving circuit portion 400 and a data driving portion 700. The first transistor may be formed by a semiconductor process. For example, the first transistor may be formed as a complementary metal oxide semiconductor (CMOS) transistor.

[0060] The driving circuit part 400 may be shown as being located at an upper portion of the driving part 100, and the data driving part 700 and the first pad area PDA1 are located below the driving circuit part 400, but the present disclosure is not limited thereto. That is, the positions of the driving circuit part 400 and the data driving part 700 in the driving part 100 may vary according to the design structure of the plurality of circuit elements formed on the first single crystal semiconductor substrate 110.

[0061] The first pad area PDA1 may include a plurality of first pads PD1 positioned along the first direction DR1. The first pads PD1 may be electrically connected to the plurality of second pads PD2 of the display part 200, and may thereby be electrically connected to the circuit board 300. The first pads PD1 may transmit an electrical signal applied from the circuit board 300 to the driving circuit part 400, the gate driving parts 610 and 620, and the data driving part 700.

[0062] The display portion 200 may include a second single crystal semiconductor substrate 210 and a plurality of pixels PX and gate driving portions 610 and 620 formed on the second single crystal semiconductor substrate 210. The display portion 200 may include a display area DAA where the pixels PX are located and a non-display area NA around the display area DAA. The gate driving portions 610 and 620 and the second pad area PDA2 may be located in the non-display area NA.

[0063] The second single crystal semiconductor substrate 210 may be a Si substrate, a Ge substrate or a SiGe substrate. A plurality of second transistors may be formed on the second single crystal semiconductor substrate 210 and may be electrically connected to each other to form gate drive units 610 and 620 and a pixel circuit unit for lighting the pixel PX. The second transistor may be formed by a semiconductor process. For example, the second transistor may be formed as a CMOS transistor.

[0064] The display area DAA may include pixels PX including light-emitting elements. Each of the pixels PX may include three sub-pixels (e.g., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3). The three sub-pixels (e.g., a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3) may together form a pixel PX to display a color, but the present disclosure is not limited thereto. Optionally, each of the pixels PX may include more than three sub-pixels. A plurality of sub-pixels SP1, SP2, and SP3 may be arranged in a matrix form in a first direction DR1 and a second direction DR2. Figure 6 As shown in , each of the sub-pixels SP1, SP2, and SP3 may be electrically connected to a pixel circuit composed of a plurality of second transistors formed on a second single crystal semiconductor substrate 210. Each of the sub-pixels SP1, SP2, and SP3 includes a light emitting element, and the light emitting element may emit light in the display area DAA according to an electrical signal applied from the corresponding pixel circuit.

[0065] Some of the sub-pixels SP1, SP2, and SP3 located in the display area DAA of the display part 200 may overlap the driving part 100 in the thickness direction of the display device 10, and the other sub-pixels SP1, SP2, and SP3 may not overlap the driving part 100. The driving part 100 may have a smaller area than the display part 200 and may be adjacent to one side of the display part 200. Therefore, only some of the sub-pixels SP1, SP2, and SP3 may overlap the driving part 100 in the thickness direction.

[0066] A plurality of scan lines GL extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of data lines DL extending in the second direction DR2 and arranged in the first direction DR1 may be located in the display area DAA. Figure 5 , the scan lines GL may include different types of scan lines (e.g., a first scan line GWL, a second scan line GCL, and a third scan line GBL), and may further include emission control lines EL1 and EL2. The scan lines GL and the data lines DL may be connected to the sub-pixels SP1, SP2, and SP3 in the display area DAA. The scan lines GL may be electrically connected to the gate driving parts 610 and 620 of the display part 200, and the data lines DL may be electrically connected to the data driving part 700 of the driving part 100. The data lines DL may be electrically connected to the data driving part 700 of the driving part 100 through the first through holes TSV1.

[0067] Subpixels SP1, SP2, and SP3 may be electrically connected to scan lines GL and data lines DL. Subpixels SP1, SP2, and SP3 may receive data voltages from data lines DL according to scan signals from scan lines GL and may enable their light emitting elements to emit light according to the data voltages.

[0068] The non-display area NA may surround the display area DAA. The non-display area NA may be an area where no pixel PX is disposed so as not to emit light. The non-display area NA may include gate driving parts 610 and 620, a second pad area PDA2, and a plurality of through holes TSV1, TSV2, and TSV3.

[0069] The gate driving parts 610 and 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the second single crystal semiconductor substrate 210, and the emission driver 620 may include a plurality of emission transistors formed on the second single crystal semiconductor substrate 210. The scan transistors and the emission transistors may be formed by a semiconductor process. For example, the scan transistors and the emission transistors may be formed as CMOS transistors.

[0070] The scan driver 610 may be located at one side of the display area DAA (e.g., located at one side of the display area DAA in the first direction DR1, or at the left side of the display area DAA). The emission driver 620 may be located at the other side of the display area DAA (e.g., located at the other side of the display area DAA in the first direction DR1, such as at the right side of the display area DAA). The scan line GL may be electrically connected to the scan driver 610 or the emission driver 620. For example, the first scan line GWL, the second scan line GCL, and the third scan line GBL may be connected to the scan driver 610, and the emission control lines EL1 and EL2 may be connected to the emission driver 620.

[0071] The second pad area PDA2 may be positioned at one side of the display area DAA relative to the second direction DR2 (e.g., at the lower side of the display area DAA). A plurality of second pads PD2 may be positioned in the second pad area PDA2 and may be arranged in the first direction DR1. The second pad PD2 may be electrically connected to the first pad PD1 of the driving part 100, and the circuit board 300 may be attached to the second pad PD2. The second pad PD2 may be electrically connected to the circuit board 300, and may transmit an electrical signal applied from the circuit board 300 to the driving part 100.

[0072] The display device 10 may include through-holes TSV1, TSV2, and TSV3 forming paths for electrically connecting elements placed in the driving part 100 and elements located in the display part 200. The through-holes TSV1, TSV2, and TSV3 may penetrate the second single crystal semiconductor substrate 210 of the display part 200. The driving circuit part 400 and the data driving part 700 located in the driving part 100 may be electrically connected to the display part 200 and the circuit board 300 through connection lines located in the through-holes TSV1, TSV2, and TSV3.

[0073] The through holes TSV1 , TSV2 , and TSV3 may include a plurality of first through holes TSV1 , a plurality of second through holes TSV2 , and a plurality of third through holes TSV3 located in the non-display area NA.

[0074] The first through hole TSV1 may be located on one side of the display area DAA within the non-display area NA. For example, the first through hole TSV1 may be located on the lower side of the display area DAA (for example, in a plan view). In some embodiments, the first through hole TSV1 may be located in the second pad area PDA2 and may be arranged not to overlap with the second pad PD2. The first through hole TSV1 may be positioned to correspond to the data line DL located in the display area DAA. The number of the first through holes TSV1 may be equal to the number of data lines DL and the number of columns of sub-pixels SP1, SP2, and SP3 in the display area DAA. The data lines DL may correspond to the first through holes TSV1, respectively, and may be electrically connected to the connection lines within the first through holes TSV1. The sub-pixels SP1, SP2, and SP3 may receive data signals from the data lines DL connected to the drive unit 100 through the first through holes TSV1.

[0075] The second through holes TSV2 may be located in the gate driving parts 610 and 620 in the non-display area NA. Some of the second through holes TSV2 may overlap with the scan driver 610, and other second through holes TSV2 may overlap with the emission driver 620. A connection line connecting the gate driving parts 610 and 620 with the driving part 100 may be located in the second through holes TSV2, and a signal for driving the gate driving parts 610 and 620 may be applied to the connection line from the driving part 100. For example, the gate driving parts 610 and 620 may be connected to the connection line, which is connected to the driving circuit part 400 of the driving part 100 through the second through holes TSV2, and may receive a timing signal applied to the gate driving parts 610 and 620.

[0076] The third through holes TSV3 may be located in the non-display area NA to overlap the second pad PD2. The number of the third through holes TSV3 may be equal to the number of the second pads PD2. The second pad PD2 may be electrically connected to the first pad PD1 of the driving part 100 through a connection line located in the third through holes TSV3.

[0077] Figure 5 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0078] Reference Figure 5 The driving circuit unit 400 may include a timing control circuit. In addition, the driving circuit unit 400 may also include various circuits related to the operation of the display device 10 (such as a gamma circuit and a logic circuit). The driving circuit unit 400 may include a driving circuit transistor formed on the first single crystal semiconductor substrate 110.

[0079] The driving circuit section 400 may receive digital video data DATA and a timing signal from an external source. The timing control circuit may generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS according to the timing signal to control the display section 200. The timing control circuit may output the scan timing control signal SCS to the scan driver 610 of the gate driving sections 610 and 620, and output the emission timing control signal ECS to the emission driver 620 of the gate driving sections 610 and 620. The timing control circuit may output the digital video data DATA and the data timing control signal DCS to the data driving section 700.

[0080] The power supply unit may generate a plurality of panel driving voltages according to an external power voltage. For example, the power supply unit may generate a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage (or a third driving voltage) VINT, and may supply the first driving voltage VSS, the second driving voltage VDD, the reference voltage VREF, and the initialization voltage VINT to the pixel PX.

[0081] The pixel PX may be supplied with a scan timing control signal SCS, an emission timing control signal ECS, digital video data DATA, and a data timing control signal DCS from the driving circuit portion 400. The pixel PX may also be supplied with a first driving voltage VSS, a second driving voltage VDD, a reference voltage VREF, and an initialization voltage VINT from a power supply unit.

[0082] The gate driving parts 610 and 620 may include a scan driver 610 and an emission driver 620. The scan driver 610 may include a plurality of scan transistors formed on the second single crystal semiconductor substrate 210, and the emission driver 620 may include a plurality of emission transistors formed on the second single crystal semiconductor substrate 210. The scan transistors and the emission transistors may be formed by a semiconductor process. For example, the scan transistors and the emission transistors may be formed as CMOS transistors.

[0083] The scan driver 610 may include a first scan signal output portion 611, a second scan signal output portion 612, and a third scan signal output portion 613. The first scan signal output portion 611, the second scan signal output portion 612, and the third scan signal output portion 613 may receive a scan timing control signal SCS from the drive circuit portion 400. The first scan signal output portion 611 may generate a write scan signal according to the scan timing control signal SCS from the drive circuit portion 400, and may sequentially output the write scan signal to the first scan line GWL. The second scan signal output portion 612 may generate a control scan signal according to the scan timing control signal SCS, and may sequentially output the control scan signal to the second scan line GCL. The third scan signal output portion 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output the bias scan signal to the third scan line GBL.

[0084] The emission driver 620 may include a first emission signal output portion 621 and a second emission signal output portion 622. The first emission signal output portion 621 and the second emission signal output portion 622 may receive an emission timing control signal ECS from the driving circuit portion 400. The emission driver 620 may generate an emission control signal according to the emission timing control signal ECS, and may sequentially output the emission control signal to the first emission control line EL1 and the second emission control line EL2.

[0085] The data driving part 700 may receive the digital video data DATA and the data timing control signal DCS from the driving circuit part 400. The data driving part 700 may convert the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and may output the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by the write scan signal from the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0086] The pixels PX, the data lines DL, the scan lines GL, and the emission control lines EL1 and EL2 may be located in the display area DAA of the display portion 200. The scan lines GL may include a first scan line GWL, a second scan line GCL, and a third scan line GBL. The scan lines GL and the emission control lines EL1 and EL2 may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2. The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0087] Figure 6 is an equivalent circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0088] Reference Figure 6 , the sub-pixel SP1 may be connected to the first scan line GWL, the second scan line GCL, the third scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the sub-pixel SP1 may be connected to the first drive voltage line VSL to which a low potential voltage corresponding to the first drive voltage VSS is applied, the second drive voltage line VDL to which a high potential voltage corresponding to the second drive voltage VDD is applied, and the third drive voltage line VIL to which an initialization voltage corresponding to the third drive voltage VINT is applied. Therefore, the first drive voltage line VSL may be a low potential voltage line, the second drive voltage line VDL may be a high potential voltage line, and the third drive voltage line VIL may be an initialization voltage line. In this case, the first drive voltage VSS may be lower than the third drive voltage VINT, and the second drive voltage VDD may be higher than the third drive voltage VINT.

[0089] The sub-pixel SP1 includes a plurality of first to sixth transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0090] The light emitting element LE emits light according to the driving current flowing through the channel of the first transistor T1. The amount of light emitted by the light emitting element LE may be proportional to the driving current. The light emitting element LE may be located between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode, and the second electrode of the light emitting element LE may be a cathode. The light emitting element LE may be an organic light emitting diode (LED) including a first electrode, a second electrode, and an organic light emitting layer placed between the first electrode and the second electrode, but the present disclosure is not limited thereto. Alternatively, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor located between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode (micro-LED).

[0091] The first transistor T1 can be used as a driving transistor, which controls a source-drain current or a driving current flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to a first node N1, a source electrode connected to a drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0092] The second transistor T2 may be located between the first electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal from the first scan line GWL, connecting the first electrode of the first capacitor C1 to the data line DL. As a result, a data voltage from the data line DL may be applied to the first electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the first scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the first electrode of the first capacitor C1.

[0093] The third transistor T3 may be located between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the second scan line GCL, thereby connecting the first node N1 to the second node N2. Therefore, the gate electrode and the source electrode of the first transistor T1 are connected, thereby causing the first transistor T1 to operate as a diode. The third transistor T3 includes a gate electrode connected to the second scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0094] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal from the first emission control line EL1, thereby connecting the second node N2 to the third node N3. Therefore, the driving current from the first transistor T1 may be applied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0095] The fifth transistor T5 may be located between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scanning signal from the third scanning line GBL, thereby connecting the third node N3 to the third driving voltage line VIL. Therefore, the initialization voltage VINT from the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the third scanning line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0096] The sixth transistor T6 may be located between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal from the second emission control line EL2, thereby connecting the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, the second drive voltage VDD from the second drive voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0097] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes a first electrode connected to the drain electrode of the second transistor T2, and a second electrode connected to the first node N1.

[0098] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the second driving voltage line VDL.

[0099] The first node N1 is a junction of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the second electrode of the first capacitor C1, and the first electrode of the second capacitor C2. The second node N2 is a junction of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0100] The first to sixth transistors T1, T2, T3, T4, T5 and T6 may be MOSFETs. For example, the first to sixth transistors T1, T2, T3, T4, T5 and T6 may be P-type MOSFETs, but the present disclosure is not limited thereto. Alternatively, the first to sixth transistors T1, T2, T3, T4, T5 and T6 may be N-type MOSFETs. Alternatively, some of the first to sixth transistors T1, T2, T3, T4, T5 and T6 may be P-type MOSFETs, while the other transistors may be N-type MOSFETs.

[0101] Figure 6 The subpixel SP is shown to include six transistors (e.g., first to sixth transistors T1, T2, T3, T4, T5, and T6) and two capacitors (e.g., first capacitor C1 and second capacitor C2), but the present disclosure is not limited thereto. That is, the number of transistors and capacitors included in each subpixel SP is not specifically limited.

[0102] Figure 7 is a cross-sectional view of a display device according to one or more embodiments of the present disclosure, Figure 8 is a bottom view of a display device according to one or more embodiments of the present disclosure. Figure 7 1 shows the arrangement of routing wires RM1, RM2, and RM3 that electrically connect the display section 200 and the driving section 100, Figure 8 An arrangement of the first through-hole TSV1 and the second through-hole TSV2 viewed from the rear side of the display device 10 is shown.

[0103] Reference Figure 4 , Figure 7 and Figure 8 The display device 10 may include a driving portion 100 and a display portion 200, wherein the driving portion 100 includes a first single crystal semiconductor substrate 110 and a driving circuit layer 120 on the first single crystal semiconductor substrate 110, and the display portion 200 includes a second single crystal semiconductor substrate 210 and a pixel circuit portion 220 and a display element layer 230 on the second single crystal semiconductor substrate 210. The display device 10 may include two different single crystal semiconductor substrates (e.g., a first single crystal semiconductor substrate 110 and a second single crystal semiconductor substrate 210) stacked in a third direction DR3, and the third direction DR3 is a thickness direction of the display device 10.

[0104] The driving part 100 may include circuit elements suitable for emission of the light emitting element included in the display element layer 230 of the display part 200. As described above, the driving circuit layer 120 of the driving part 100 may include a driving circuit part 400 and a data driving part 700. Circuit elements (e.g., transistors and capacitors) forming the driving circuit part 400 and the data driving part 700 may be formed as CMOS transistors on the first single crystal semiconductor substrate 110.

[0105] The display section 200 may include a plurality of light emitting elements that emit light to display an image on the display device 10. The light emitting elements may be electrically connected to circuit elements formed in the driving section 100, and may thereby emit light. In addition, the display section 200 may include a pixel circuit section 220 that accommodates the gate driving sections 610 and 620, and circuit elements and wiring that form a pixel circuit electrically connected to the sub-pixels SP1, SP2, and SP3. The pixel circuit section 220 may include, for example, Figure 6 The pixel circuit unit 220 may further include the first to sixth transistors T1, T2, T3, T4, T5 and T6, the scanning transistors forming the gate driving units 610 and 620, the scanning lines GL and the data lines DL as circuit elements and wiring. Fig.12 The plurality of terminals DTD and GTD are connected to the through holes TSV1 , TSV2 , and TSV3 in the non-display area NA of the display part 200 .

[0106] The protective layer 900 may be located around the driving portion 100. The protective layer 900 may surround the driving portion 100 and may be located on the bottom surface of the display portion 200. The protective layer 900 may cover the driving portion 100 during the manufacture of the display device 10, and may fill the step difference between the driving portion 100 and the display portion 200. During the manufacture of the display device 10, when the first single crystal semiconductor substrate 110 is attached to the bottom surface of the second single crystal semiconductor substrate 210 having a different area from the first single crystal semiconductor substrate 110, the protective layer 900 may fill the step difference between the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210, and may allow further processing to be performed on the second single crystal semiconductor substrate 210.

[0107] In one or more embodiments, the thickness of the protective layer 900 may be greater than the thickness of the first single crystal semiconductor substrate 110. The protective layer 900 may have a thickness equal to or greater than the combined thickness of the first single crystal semiconductor substrate 110 and the driving circuit layer 120 on the first single crystal semiconductor substrate 110. Since the protective layer 900 is thicker than the driving part 100, a portion of the protective layer 900 may directly contact the bottom surface of the display part 200, and a portion of the protective layer 900 may directly contact the bottom surface of the driving part 100. Therefore, both the driving part 100 and the display part 200 may be completely covered by the protective layer 900 at the bottom surface of the display device 10.

[0108] In addition, the protective layer 900 may have the same plane area as the second single crystal semiconductor substrate 210, and the side of the protective layer 900 may be aligned with the side of the second single crystal semiconductor substrate 210. When the second single crystal semiconductor substrate 210 is separated from the wafer substrate during the manufacture of the display device 10, the protective layer 900 may be separated together with the second single crystal semiconductor substrate 210, and thus, the plane area of ​​the protective layer 900 may be the same as the plane area of ​​the second single crystal semiconductor substrate 210. Even if the display device 10 includes the first single crystal semiconductor substrate 110 and the second single crystal semiconductor substrate 210 having different plane areas, any local step difference may be compensated by the protective layer 900, ensuring structural stability.

[0109] The planar area of ​​the driving part 100 or the first single crystal semiconductor substrate 110 may be smaller than the planar area of ​​the display part 200 or the second single crystal semiconductor substrate 210. The transistors formed in the driving part 100 may be very small in size or line width because they are formed by a semiconductor microfabrication process. The driving part 100 may accommodate a large number of circuit elements with a high integration density, and may provide an advantage of reducing power consumption due to miniaturization of the circuit elements.

[0110] In addition, since the driving unit 100 includes only CMOS elements formed on the first single crystal semiconductor substrate 110 and no light-emitting elements, it may be sufficient to ensure space only for elements formed by a microfabrication process. It is still appropriate that the first single crystal semiconductor substrate 110 is smaller than the second single crystal semiconductor substrate 210, and therefore, since a considerable number of driving units 100 can be manufactured on a single wafer substrate, the yield rate can be improved. For example, since the manufacture of each driving unit 100 involves a high-cost semiconductor process, the improved yield rate can also save costs. In addition, a large number of light-emitting elements can be formed on the relatively large second single crystal semiconductor substrate 210, enabling a high-resolution display device to be realized.

[0111] The display device 10 may include a connection wiring layer 500 located between the second single crystal semiconductor substrate 210 of the display part 200 and the driving circuit layer 120 of the driving part 100. The connection wiring layer 500 may be located on the bottom surface of the second single crystal semiconductor substrate 210. The connection wiring layer 500 may include routing wirings RM1, RM2, and RM3. The routing wirings RM1, RM2, and RM3 may connect the pixel circuit part 220 of the display part 200 and the circuit board 300 to the driving part 100. The driving circuit layer 120 of the driving part 100 may be electrically connected to the display part 200 and the circuit board 300 through the routing wirings RM1, RM2, and RM3 of the connection wiring layer 500 to transmit an electrical signal for lighting.

[0112] The first routing wiring RM1 may be connected to the data line DL in the display part 200 and the data driving part 700 in the driving part 100. The first routing wiring RM1 may be located in the first through hole TSV1 formed in the second single crystal semiconductor substrate 210, and may include a data routing wiring GDL connecting the wiring layer 500. The first through hole TSV1 may be located in the non-display area NA of the display part 200, and may not overlap the driving part 100 in the thickness direction of the display device 10.

[0113] In one or more embodiments, the first through hole TSV1 may be located in the second pad area PDA2 of the non-display area NA of the display part 200, and may not overlap with the driving part 100 but overlap with the circuit board 300 in the thickness direction of the display device 10. Part of the first routing wiring RM1 may be located in the first through hole TSV1, and the data routing wiring GDL may be located in the connection wiring layer 500 to connect the first through hole TSV1 and the data driving part 700 that are not overlapped with the driving part 100. As described above, the display part 200 may have a larger plane area than the driving part 100, and the driving part 100 located on the back surface of the display part 200 may not overlap with the non-display area NA of part of the display part 200. Therefore, the driving part 100 may not overlap with the through holes TSV1, TSV2, and TSV3 located in the non-display area NA, and the routing wiring RM1, RM2, and RM3 may include wiring that connects the through holes TSV1, TSV2, and TSV3 to the driving part 100.

[0114] The number of first through holes TSV1 may be equal to the number of columns of sub-pixels SP1, SP2, and SP3 in the display area DAA. For example, if the sub-pixels SP1, SP2, and SP3 are arranged in the first direction DR1 and the second direction DR2 in the display area DAA, and the number of sub-pixel columns arranged in the first direction DR1 is 4000, the number of first through holes TSV1 may also be 4000. The first through holes TSV1 may correspond one-to-one to the columns of sub-pixels SP1, SP2, and SP3 arranged in the first direction DR1, and may also correspond one-to-one to the data lines DL and the first routing wiring RM1 arranged in the first direction DR1. One data line DL arranged in parallel to one sub-pixel column may be connected to the data driving part 700 through one first routing wiring RM1 located in one first through hole TSV1. The number of first routing wirings RM1 and the number of first through holes TSV1 may be equal to the number of sub-pixel columns and the number of data lines DL.

[0115] In addition, the data lines DL may extend in the second direction DR2 and may be connected to the corresponding first through holes TSV1 in the non-display area NA without bending to maintain substantially parallel alignment. The display device 10 may maintain uniform spacing between the data lines DL in both the display area DAA and the non-display area NA of the display unit 200, thereby eliminating the need for a fan-out structure in which the data lines DL are bent and narrowed in the non-display area NA. The spacing between the first through holes TSV1 and the spacing between the data routing wirings GDL may also be uniformly maintained similar to the spacing between the data lines DL. The driving unit 100 of the display device 10 may have a width that allows the data lines DL and the data routing wirings GDL to extend in parallel at intervals of equal distance. For example, the width of the driving unit 100 in the first direction DR1 may be greater than the width of the display area DAA in the first direction DR1. The display device 10 connects the data lines DL to the driving unit 100 through the first through holes TSV1 and arranges them in parallel without a fan-out structure, thereby reducing or minimizing interference between adjacent wirings.

[0116] The second routing wiring RM2 may be connected to the gate driving parts 610 and 620 located in the display part 200 and the driving circuit part 400 located in the driving part 100. The second routing wiring RM2 may be located in the second through hole TSV2 formed in the second single crystal semiconductor substrate 210, and may include a control routing wiring TCL connecting the wiring layer 500. The second through hole TSV2 may be located in the non-display area NA of the display part 200, and may not overlap with the driving part 100 and the circuit board 300 in the thickness direction of the display device 10. In some embodiments, the second through hole TSV2 may overlap with each of the scan driver 610 and the emission driver 620.

[0117] A portion of the second routing wiring RM2 may be located within the second through-via TSV2 , and the control routing wiring TCL may be located in the connection wiring layer 500 and may connect the second through-via TSV2 not overlapping the driving part 100 and the driving part 100 .

[0118] The gate driving parts 610 and 620 may be electrically connected to the driving circuit part 400 of the driving part 100 and may receive a timing control signal. Unlike the first through hole TSV1 and the first routing wiring RM1, the second through hole TSV2 and the second routing wiring RM2 may not be positioned to correspond to the scan line GL one-to-one. In one or more embodiments, the number of the second through holes TSV2 and the number of the second routing wiring RM2 may be less than the number of the first through holes TSV1 and the number of the first routing wiring RM1.

[0119] The third routing wiring RM3 may be connected to the second pad PD2 in the display part 200 and the first pad PD1 in the driving part 100. The third routing wiring RM3 may be located in a third through hole TSV3 formed in the second single crystal semiconductor substrate 210. The third through hole TSV3 is arranged to overlap with the second pad PD2 and the circuit board 300 in the second pad area PDA2, and a portion of the third routing wiring RM3 may be located in the connection wiring layer 500 and may overlap with the driving part 100. The third routing wiring RM3 may be a wiring that transmits a signal applied from the circuit board 300 to the driving part 100.

[0120] Routing arrangements RM1, RM2 and RM3 may include Fig.12 and Fig.13 The connection wirings RML1, RML2 and RML3 located in the connection wiring layer 500 and Fig.12 and Fig.13 The conductive vias RVA1, RVA2, and RVA3 in the through-holes TSV1, TSV2, and TSV3 in the second single crystal semiconductor substrate 210 are located. The routing wirings RM1, RM2, and RM3 are wirings that electrically connect the layer above the second single crystal semiconductor substrate 210 and the layer below the second single crystal semiconductor substrate 210. The arrangement and design of the through-holes TSV1, TSV2, and TSV3 in the second single crystal semiconductor substrate 210 may vary according to the arrangement of the layers electrically connected to the routing wirings RM1, RM2, and RM3.

[0121] The driving part 100 of the display device 10 may have a smaller area than the display part 200 and may partially overlap the display area DAA but not overlap the through holes TSV1, TSV2, and TSV3 in the non-display area NA. Fig.12 and Fig.13 The connection wirings RML1, RML2 and RML3 are partially overlapped, and the connection wirings RML1, RML2 and RML3 are connected to the conductive vias RVA1, RVA2 and RVA3 in the through holes TSV1, TSV2 and TSV3. Figure 8 As shown in FIG. 1 , the driving part 100 may partially overlap the data routing wiring GDL and the control routing wiring TCL.

[0122] The display device 10 may include a driving portion 100 and a display portion 200, the driving portion 100 and the display portion 200 including different single crystal semiconductor substrates (e.g., a first single crystal semiconductor substrate 110 and a second single crystal semiconductor substrate 210), and may further include routing wirings RM1, RM2, and RM3, the routing wirings RM1, RM2, and RM3 connecting the driving portion 100 and the display portion 200, and may define through-holes TSV1, TSV2, and TSV3 in which the routing wirings RM1, RM2, and RM3 are positioned. The through-holes TSV1, TSV2, and TSV3 are positioned to penetrate the second single crystal semiconductor substrate 210 of the display portion 200, thereby allowing corresponding diameters and spacings (e.g., predetermined diameters and spacings). The driving circuit part 400, the gate driving parts 610 and 620, and the data driving part 700 can be appropriately distributed between the driving part 100 and the display part 200, so that the number of routing wirings RM1, RM2, and RM3 connecting the driving circuit part 400, the gate driving parts 610 and 620, and the data driving part 700 can be reduced or minimized. The number of through holes TSV1, TSV2, and TSV3 can be reduced so that the through holes TSV1, TSV2, and TSV3 can all be accommodated in the non-display area NA of the display part 200, thereby reducing or minimizing the area occupied by the through holes TSV1, TSV2, and TSV3. Although the area of ​​the non-display area NA in the display device 10 is limited, the through holes TSV1, TSV2, and TSV3 can still be arranged with sufficient diameter and spacing due to their reduced number. Therefore, the potential interference between the routing wirings RM1, RM2, and RM3 in the through holes TSV1, TSV2, and TSV3 can be reduced.

[0123] The structures of the driving circuit layer 120 of the driving section 100 and the display element layer 230 of the display section 200 will be described below.

[0124] Fig. 9 is a cross-sectional view of a driving portion according to one or more embodiments of the present disclosure.

[0125] Reference Fig. 9 The driving part 100 may include a first single crystal semiconductor substrate 110 , and a driving circuit layer 120 located on the first single crystal semiconductor substrate 110 . Fig. 9 The cross-sectional structure of the data driving unit 700 located in the circuit unit of the driving unit 100 is shown.

[0126] The first single crystal semiconductor substrate 110 may be a Si, Ge or SiGe substrate. The first single crystal semiconductor substrate 110 may be a substrate doped with a first type of impurity. A plurality of well regions WA may be located on the top surface of the first single crystal semiconductor substrate 110. The well region WA may be a region doped with a second type of impurity. The second type of impurity may be different from the first type of impurity. For example, if the first type of impurity is a P-type impurity, the second type of impurity may be an N-type impurity. Alternatively, if the first type of impurity is an N-type impurity, the second type of impurity may be a P-type impurity.

[0127] Each of the well areas WA may include a source area SA corresponding to a source electrode of the first transistor PTR1 , a drain area DA corresponding to a drain electrode of the first transistor PTR1 , and a channel area CH located between the source area SA and the drain area DA.

[0128] The bottom insulating film BINS may be located between the gate electrode GE of the first transistor PTR1 and the well area WA. The side insulating film SINS may be located on the side of each of the gate electrodes GE. The side insulating film SINS may be located on the bottom insulating film BINS.

[0129] The source region SA and the drain region DA may be doped with first type impurities. The gate electrode of the first transistor PTR1 may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be located on a side of the gate electrode GE, and the drain region DA may be located on the other side of the gate electrode GE.

[0130] The well area WA may further include a first low-doped impurity area LDD1 and a second low-doped impurity area LDD2, the first low-doped impurity area LDD1 being located between the channel area CH and the source area SA, and the second low-doped impurity area LDD2 being located between the channel area CH and the drain area DA. The first low-doped impurity area LDD1 may be a region having a lower impurity concentration than the source area SA due to the bottom insulating film BINS. Similarly, the second low-doped impurity area LDD2 may be a region having a lower impurity concentration than the drain area DA also due to the bottom insulating film BINS. Due to the first low-doped impurity area LDD1 and the second low-doped impurity area LDD2, the distance between the source area SA and the drain area DA may be increased. Therefore, as the length of the channel area CH of the first transistor PTR1 increases, punch-through and hot carrier phenomena that may be caused by a short channel may be reduced or prevented.

[0131] The first single crystal semiconductor substrate 110 may include a plurality of first transistors PTR1 forming circuit elements in the driving part 100. The first transistors PTR1 formed on the first single crystal semiconductor substrate 110 may form the driving circuit part 400 or the data driving part 700.

[0132] Once the driving circuit layer 120 is formed on the Si wafer substrate, the first single crystalline semiconductor substrate 110 may be thinned and may be thinner than the Si wafer substrate on which the step of forming the driving circuit layer 120 has been performed. In some embodiments, the thickness of the first single crystalline semiconductor substrate 110 may be less than about 100 μm (e.g., in a range of about 80 μm to about 100 μm).

[0133] The driving circuit layer 120 may include a first semiconductor insulating layer SINS1, a second semiconductor insulating layer SINS2, a plurality of contact electrodes CTE, a first interlayer insulating layer INS1, a second interlayer insulating layer INS2, a plurality of conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8, and a plurality of vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8. The driving circuit layer 120 may include wiring electrically connected to the first transistor PTR1 included in the first single crystal semiconductor substrate 110.

[0134] The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be located on the first single crystal semiconductor substrate 110. The first semiconductor insulating layer SINS1 is an insulating layer located on the first single crystal semiconductor substrate 110, and the second semiconductor insulating layer SINS2 may be an insulating layer located on the gate electrode GE of the first transistor PTR1 and on the first semiconductor insulating layer SINS1. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may be formed of a silicon carbon nitride (SiCN)-based or silicon oxide (SiO x ), but the present disclosure is not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 are shown as separate layers having corresponding thicknesses, but the present disclosure is not limited thereto. The first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2 may have a structure in which one or more layers are stacked on top of each other.

[0135] The contact electrode CTE may be located on the first single crystal semiconductor substrate 110. The contact electrode CTE may be connected to the gate electrode GE, the source region SA, or the drain region DA of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact electrode CTE may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or an alloy thereof. The top surface of the contact electrode CTE may be exposed without being covered by the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2.

[0136] The first interlayer insulating layer INS1 may be located on the contact electrode CTE and the first and second semiconductor insulating layers SINS1 and SINS2. The second interlayer insulating layer INS2 may be located on the first interlayer insulating layer INS1. The first and second interlayer insulating layers INS1 and INS2 may be formed of SiCN-based or SiO-based materials. x The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 are shown as single layers having corresponding thicknesses, but the present disclosure is not limited thereto. The first interlayer insulating layer INS1 and the second interlayer insulating layer INS2 may have a structure in which one or more layers are stacked on top of each other, and may be located between conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8 to be described later.

[0137] The conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8 may be electrically connected to the contact electrode CTE and may form the driving circuit portion 400 or the data driving portion 700 of the driving portion 100. The first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be electrically connected through the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8 forming the driving circuit portion 400 and the data driving portion 700 of the driving portion 100 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7, and VA8.

[0138] The first conductive layer ML1 may be connected to the contact electrode CTE through the first via VA1. The first conductive layer ML1 is located on the contact electrode CTE, and the first via VA1 is located between the first conductive layer ML1 and the contact electrode CTE and contacts the first conductive layer ML1 and the contact electrode CTE. The second conductive layer ML2 may be connected to the first conductive layer ML1 through the second via VA2. The second conductive layer ML2 is located on the first conductive layer ML1, and the second via VA2 is located between the first conductive layer ML1 and the second conductive layer ML2 and contacts the first conductive layer ML1 and the second conductive layer ML2.

[0139] The third conductive layer ML3 may be connected to the second conductive layer ML2 through the third via VA3. The fourth conductive layer ML4 may be connected to the third conductive layer ML3 through the fourth via VA4, the fifth conductive layer ML5 may be connected to the fourth conductive layer ML4 through the fifth via VA5, and the sixth conductive layer ML6 may be connected to the fifth conductive layer ML5 through the sixth via VA6. The third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be sequentially located on the second conductive layer ML2. The third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may be located between the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6, respectively. The third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 may each contact different metal layers located above and below them. The seventh via VA7 may be located on the sixth conductive layer ML6. The seventh via VA7 may contact the sixth conductive layer ML6 and the seventh conductive layer ML7 located on the seventh via VA7.

[0140] The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, and the seventh via VA7 may be located on the first interlayer insulating layer INS1. The first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, and the seventh via VA7 may form a first driving circuit layer in the first interlayer insulating layer INS1 of the driving circuit layer 120.

[0141] The seventh conductive layer ML7 may be connected to the sixth conductive layer ML6 through the seventh via VA7. The seventh conductive layer ML7 is located on the first interlayer insulating layer INS1 and the sixth conductive layer ML6, and the seventh via VA7 is located between the sixth conductive layer ML6 and the seventh conductive layer ML7, and contacts the sixth conductive layer ML6 and the seventh conductive layer ML7. The eighth conductive layer ML8 may be connected to the seventh conductive layer ML7 through the eighth via VA8. The eighth conductive layer ML8 is located on the seventh conductive layer ML7, and the eighth via VA8 is located between the seventh conductive layer ML7 and the eighth conductive layer ML8, and contacts the seventh conductive layer ML7 and the eighth conductive layer ML8. The top surface of the eighth conductive layer ML8 may be exposed without being covered by the second interlayer insulating layer INS2, and may be electrically connected to the routing wirings RM1, RM2, and RM3 located in the display portion 200.

[0142] The seventh conductive layer ML7 , the eighth via hole VA8 , and the eighth conductive layer ML8 may be located in the second interlayer insulating layer INS2 . The seventh conductive layer ML7 , the eighth via hole VA8 , and the eighth conductive layer ML8 may form a second driving circuit layer in the second interlayer insulating layer INS2 of the driving circuit layer 120 .

[0143] The conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 are shown as being stacked alternately in sequence with each other, but the arrangement of the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 may vary depending on the design of the driving circuit unit 400 and the data driving unit 700 in the driving unit 100. Fig. 9 The connection structure shown in FIG. 1 is only an example, and the connection within the driving circuit layer 120 of the driving part 100 of the display device 10 is not specifically limited. Optionally, the driving circuit layer 120 may not include the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8. Alternatively, some of the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 may be omitted, or additional conductive layers may be further positioned.

[0144] The conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 may be formed of substantially the same material. For example, the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd or alloys thereof.

[0145] The thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6. The thickness of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately 1360Å, the thickness of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5 and the sixth conductive layer ML6 may be approximately 1440Å, and the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5 and the sixth via VA6 may be approximately 1150Å.

[0146] The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh via VA7 and the eighth via VA8. The thickness of the seventh via VA7 and the eighth via VA8 may be greater than the thickness of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may both be approximately 9000Å. The thickness of the seventh via VA7 and the eighth via VA8 may both be approximately 6000Å.

[0147] Fig.10 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display portion according to one or more embodiments of the present disclosure.

[0148] Reference Fig.10 , each of the plurality of pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. Each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include a light emitting area. For example, the first sub-pixel SP1 may include a first light emitting area EA1, the second sub-pixel SP2 may include a second light emitting area EA2, and the third sub-pixel SP3 may include a third light emitting area EA3.

[0149] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a quadrilateral shape such as a square, a rectangle, or a diamond shape in a plan view. For example, the first light emitting area EA1 may have a rectangular plane shape having a short side in the first direction DR1 and a long side in the second direction DR2. Similarly, the second light emitting area EA2 and the third light emitting area EA3 may have a rectangular plane shape having a long side in the first direction DR1 and a short side in the second direction DR2.

[0150] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be defined by the pixel defining film PDL. For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may be defined by the first pixel defining film PDL1.

[0151] The length of the third light emitting area EA3 in the first direction DR1 may be smaller than that of the first light emitting area EA1 and may also be smaller than that of the second light emitting area EA2 in the first direction DR1. The lengths of the first and second light emitting areas EA1 and EA2 in the first direction DR1 may be substantially the same.

[0152] In each pixel PX, the first light emitting area EA1 and the second light emitting area EA2 may be adjacent to each other in the second direction DR2, the first light emitting area EA1 and the third light emitting area EA3 may be adjacent to each other in the first direction DR1, and the second light emitting area EA2 and the third light emitting area EA3 may be adjacent to each other in the first direction DR1. The areas of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may all be different.

[0153] The first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 are shown to have a rectangular plane shape, but the present disclosure is not limited thereto. Optionally, the first light emitting area EA1, the second light emitting area EA2 and the third light emitting area EA3 may have various other plane shapes such as a non-rectangular polygonal shape, a circular shape or an elliptical shape.

[0154] The first light emitting area EA1 may emit light of a first color, the second light emitting area EA2 may emit light of a second color, and the third light emitting area EA3 may emit light of a third color. Here, the first color light may be red wavelength light, the second color light may be green wavelength light, and the third color light may be blue wavelength light. For example, blue wavelength light may refer to light whose main peak wavelength is in the range from about 370nm to about 460nm, green wavelength light may refer to light whose main peak wavelength is in the range from about 480nm to about 560nm, and red wavelength light may refer to light whose main peak wavelength is in the range from about 600nm to about 750nm.

[0155] The first electrode AND of each light emitting element (see Fig.12 ) may have a rectangular planar shape. The planar shape of the first electrode AND may be different between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the first electrode AND of the first sub-pixel SP1 and the second sub-pixel SP2 may have a rectangular planar shape having a long side in the first direction DR1 and a short side in the second direction DR2. The first electrode AND of the third sub-pixel SP3 may have a rectangular planar shape having a short side in the first direction DR1 and a long side in the second direction DR2. The length of the first electrode AND of the third sub-pixel SP3 in the first direction DR1 may be less than the length of the first electrode AND of the first sub-pixel SP1 and the second sub-pixel SP2 in the second direction DR2. The length of the first electrode AND of the first sub-pixel SP1 in the second direction DR2 may be greater than the length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2.

[0156] The first electrode AND of each light emitting element can be connected through the electrode via hole VAP (see Fig.12 ) connected to Fig.12 The electrode via VAP may overlap the first pixel defining film PDL1, the second pixel defining film PDL2, and / or the third pixel defining film PDL3 in the third direction DR3.

[0157] One or more grooves TRC may be a structure for interrupting at least one charge generation layer of each light emitting stack IL between adjacent light emitting areas EA1, EA2, and EA3. The groove TRC may be located between the first light emitting area EA1 and the second light emitting area EA2, between the first light emitting area EA1 and the third light emitting area EA3, and between the second light emitting area EA2 and the third light emitting area EA3. For example, the groove TRC may be located between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0158] Fig.11 is a plan view illustrating first electrodes, light emitting regions, and pixel defining films of a plurality of sub-pixels arranged in a display region of a display portion according to one or more other embodiments of the present disclosure.

[0159] In addition to the plane shapes of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, corresponding to Fig.11 One or more embodiments corresponding to Fig.10 One or more embodiments of the present invention are basically the same, so the following will mainly focus on the corresponding Fig.10 The differences of one or more embodiments are described.

[0160] The first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a hexagonal planar shape and may be arranged in a hexagonal structure. In this case, the first light emitting area EA1 and the second light emitting area EA2 may be adjacent to each other in the first direction DR1, the second light emitting area EA2 and the third light emitting area EA3 may be adjacent to each other in the first diagonal direction DD1, and the first light emitting area EA1 and the third light emitting area EA3 may be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 refers to a direction between the first direction DR1 and the second direction DR2 (for example, a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2), and the second diagonal direction DD2 may be orthogonal to the first diagonal direction DD1.

[0161] Fig.10 and Fig.11 It is shown that each pixel PX includes three emission areas (eg, a first emission area EA1, a second emission area EA2, and a third emission area EA3), but the present disclosure is not limited thereto. Alternatively, each pixel PX may include four emission areas.

[0162] In addition, the arrangement of the light emitting area of ​​each pixel PX is not particularly limited to Fig.11 Alternatively, the light emitting regions of each pixel PX may be arranged in various other structures, such as a stripe structure in which the light emitting regions are arranged along the first direction DR1, a PenTile structure in which the light emitting regions are arranged in a diamond shape, or a PenTile structure in which the light emitting regions are arranged in a diamond shape. ® structure, or a hexagonal structure (PenTile) in which a light emitting area having a hexagonal planar shape is arranged ® and PENTILE ® is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0163] Fig.12 and Fig.13 is a cross-sectional view showing a portion of a display region and a non-display region of a display portion according to one or more embodiments of the present disclosure. Fig.12 and Fig.13 Schematic cross-sectional structures of the display area DAA, the non-display area NA, and the pad area PDA are shown.

[0164] Reference Fig.12 and Fig.13 , the display unit 200 may include a semiconductor backplane SBP, an emitter backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens LNS, and a cover layer DCL. In one or more embodiments, the display unit 200 may further include a polarizing plate located on the cover layer DCL. The connection wiring layer 500 may be located between the second single crystal semiconductor substrate 210 and the first single crystal semiconductor substrate 110 of the semiconductor backplane SBP. Optionally, the connection wiring layer 500 may be located between the light emitting element layer EML and the first single crystal semiconductor substrate 110.

[0165] The semiconductor backplane SBP includes a second single crystal semiconductor substrate 210, which includes a plurality of second transistors PTR2, a plurality of semiconductor insulating films located on the second transistors PTR2, and a plurality of contact electrodes CTE electrically connected to the pixel transistors. Figure 6 The first to sixth transistors T1 , T2 , T3 , T4 , T5 , and T6 or the scanning transistors of the gate driving parts 610 and 620 correspond.

[0166] The second single crystal semiconductor substrate 210 may be a Si, Ge or SiGe substrate. The second single crystal semiconductor substrate 210 may be a substrate doped with impurities. A plurality of well regions WA may be located on the top surface of the second single crystal semiconductor substrate 210. The well regions WA may be doped with second type impurities. The second type impurities may be different from the first type impurities. For example, if the first type impurity is a P-type impurity, the second type impurity may be an N-type impurity. Alternatively, if the first type impurity is an N-type impurity, the second type impurity may be a P-type impurity.

[0167] The second single crystalline semiconductor substrate 210 may include a plurality of second transistors PTR2 similar to the first single crystalline semiconductor substrate 110. The structure of the second transistor PTR2 may be the same as that of the first transistor PTR1, and thus, a detailed description thereof will be omitted.

[0168] The first wafer substrate on which the first transistor PTR1 located on the first single crystal semiconductor substrate 110 of the driving part 100 is formed may be different from the second wafer substrate on which the second transistor PTR2 located on the second single crystal semiconductor substrate 210 of the display part 200 is formed. The size and line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be different from the size and line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210.

[0169] For example, the minimum line width of the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 may be smaller than the minimum line width of the second transistor PTR2 formed on the second single crystal semiconductor substrate 210. The semiconductor process performed on the first wafer substrate for forming the first transistor PTR1 may have a higher resolution than the semiconductor process performed on the second wafer substrate for forming the second transistor PTR2. As a result, a device (such as a transistor) that is smaller than that on the second wafer substrate may be formed on the first wafer substrate. In other words, the semiconductor process performed on the first wafer substrate may be finer than the semiconductor process performed on the second wafer substrate.

[0170] As described above, the first single crystal semiconductor substrate 110 of the driving part 100 may have a smaller plane area than the second single crystal semiconductor substrate 210 of the display part 200, and small-sized devices may be arranged on the first single crystal semiconductor substrate 110 with a high integration density, thereby reducing power consumption and improving yield. On the other hand, the second single crystal semiconductor substrate 210 of the display part 200 may have a larger plane area than the first single crystal semiconductor substrate 110, and a process with a relatively larger line width may be performed on the second single crystal semiconductor substrate 210. The second transistor PTR2 forming the pixel circuit may be formed over a larger area on the second single crystal semiconductor substrate 210 than formed on the first single crystal semiconductor substrate 110, and a high integration density may not be required. Therefore, the semiconductor process performed may be performed as a high-cost process with a relatively small line width on the first wafer substrate, and may be performed as a low-cost process with a relatively large line width on the second wafer substrate.

[0171] The length of the channel region CH of the first transistor PTR1 may be different from the length of the channel region CH of the second transistor PTR2. For example, the minimum line width of the first transistor PTR1 or the length of the channel region CH of the first transistor PTR1 may be smaller than the minimum line width of the second transistor PTR2 or the length of the channel region CH of the second transistor PTR2. The minimum line width of the first transistor PTR1 or the length of the channel region CH of the first transistor PTR1 may be 100 nm or less or in the range of about 2 nm to about 80 nm. The minimum line width of the second transistor PTR2 or the length of the channel region CH of the second transistor PTR2 may be about 100 nm or more or in the range of about 100 nm to about 5 μm.

[0172] The second single crystal semiconductor substrate 210 may include through holes TSV1, TSV2, and TSV3. The through holes TSV1, TSV2, and TSV3 penetrate from the top surface of the second single crystal semiconductor substrate 210 to the bottom surface, and may also penetrate the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4 and the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, and the fifth interlayer insulating layer INS5 located on the second single crystal semiconductor substrate 210. The conductive vias RVA1, RVA2, and RVA3 of the routing wirings RM1, RM2, and RM3 may be located in the through holes TSV1, TSV2, and TSV3. The through holes TSV1, TSV2, and TSV3 may form a connection path of the routing wirings RM1, RM2, and RM3 for electrically connecting the driving part 100 with the pixel circuit part 220 of the display part 200 and the second pad PD2. In some embodiments, the through holes TSV1, TSV2, and TSV3 in the second single crystal semiconductor substrate 210 may be formed by a through silicon via (TSV) process that penetrates a wafer substrate to form a hole. Through the through holes TSV1 , TSV2 , and TSV3 formed in the second single crystalline semiconductor substrate 210 , the display element layer 230 and the driving part 100 may be electrically connected to each other through the routing wires RM1 , RM2 , and RM3 without separate wires.

[0173] The second single crystal semiconductor substrate 210 may be thinned after bonding the driving part 100 to the Si wafer substrate, and thus may be thinner than the wafer substrate on which the process of forming the conductive layer is performed. In some embodiments, the thickness of the second single crystal semiconductor substrate 210 may be less than about 100 μm, for example, in the range of about 80 μm to about 100 μm.

[0174] The pixel circuit portion 220 may be located on the second single crystalline semiconductor substrate 210. The pixel circuit portion 220 may include a portion of a semiconductor back plate SBP and an emitter back plate EBP.

[0175] The third semiconductor insulating layer SINS3 may be located on the second single crystal semiconductor substrate 210. The third semiconductor insulating layer SINS3 may be formed based on SiCN or based on SiO x The present invention further includes an inorganic film, but the present disclosure is not limited thereto.

[0176] The fourth semiconductor insulating layer SINS4 may be located on the third semiconductor insulating layer SINS3. The fourth semiconductor insulating layer SINS4 may be formed based on SiO x The present invention further includes an inorganic film, but the present disclosure is not limited thereto.

[0177] The contact electrode CTE may be connected to the gate electrode GE, the source area SA, or the drain area DA of the second transistor PTR2 through a hole penetrating the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4. The contact electrode CTE may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or alloys thereof.

[0178] The emitter backplane EBP may include a third interlayer insulating layer INS3, a fourth interlayer insulating layer INS4, a fifth interlayer insulating layer INS5, a sixth interlayer insulating layer INS6, and a seventh interlayer insulating layer INS7 and a plurality of routing conductive layers RMT. The routing conductive layer RMT may include wiring electrically connected to the second transistor PTR2 on the second single crystal semiconductor substrate 210, and may also include a scan line GL, a data line DL, and a plurality of terminals (DTD and GDT) located in the display part 200.

[0179] The third interlayer insulating layer INS3 may be located on the contact electrode CTE and the third and fourth semiconductor insulating layers SINS3 and SINS4. The fourth interlayer insulating layer INS4 may be located on the third interlayer insulating layer INS3. The fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, and the seventh interlayer insulating layer INS7 may be sequentially located on the fourth interlayer insulating layer INS4. The routing conductive layer RMT may be located between the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, and the seventh interlayer insulating layer INS7. The third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7 may be formed as SiCN-based or SiO-based. x The third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7 are shown as a single layer, but the present disclosure is not limited thereto. The third to seventh interlayer insulating layers INS3, INS4, INS5, INS6, and INS7 may have a structure in which one or more layers are stacked on each other, and may be located between a plurality of conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7, and ML8 to be described later.

[0180] The routing conductive layer RMT may include a structure similar to the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 in the driving circuit layer 120. The routing conductive layer RMT may include one or more conductive layers and vias located between the conductive layers and connectors or terminals DTD and GTD formed in the display portion 200. For example, the routing conductive layer RMT located in the display area DAA of the pixel circuit portion 220 may be electrically connected to the second transistor PTR2. The routing conductive layer RMT may be connected to the second transistor PTR2 and may be formed as shown in FIG. Figure 6 The pixel circuit shown in . The routing conductive layer RMT can be used as a connection wiring that connects the second transistor PTR2 to the circuit component. In addition, in one or more embodiments, some of the routing conductive layer RMT located in the display area DAA of the pixel circuit portion 220 can be used as a scan line GL, a data line DL, or a connection wiring that forms the gate driving portions 610 and 620.

[0181] The pixel circuit portion 220 may include terminals DTD and GTD located in the non-display area NA. The terminals DTD and GTD may include a data terminal DTD electrically connected to the data line DL and a gate terminal GTD connected to the gate driving portions 610 and 620. The data terminal DTD may be electrically connected to the data line DL and the first routing wiring RM1, and the gate terminal GTD may be electrically connected to the gate driving portions 610 and 620 and the second routing wiring RM2.

[0182] The connection wiring layer 500 may be located on the bottom surface of the second single crystalline semiconductor substrate 210. The connection wiring layer 500 may include an interlayer insulating layer RINS and a plurality of connection wirings RML1, RML2, and RML3.

[0183] The interlayer insulating layer RINS may be located on the bottom surface of the second single crystal semiconductor substrate 210 or below the second single crystal semiconductor substrate 210. The interlayer insulating layer RINS may be formed based on SiCN or based on SiO x The interlayer insulating layer RINS is shown as a single layer, but the present disclosure is not limited thereto. Alternatively, the interlayer insulating layer RINS may have a structure in which one or more layers are stacked on each other, and may be located between the connection wirings RML1, RML2, and RML3.

[0184] The connecting wirings RML1, RML2 and RML3 may form routing wirings RM1, RM2 and RM3 together with the conductive vias RVA1, RVA2 and RVA3. The connecting wirings RML1, RML2 and RML3 may include one or more conductive layers and vias connecting the conductive layers. The connectivity and structure of the connecting wirings RML1, RML2 and RML3 may be similar to the connectivity and structure of the conductive layers ML1, ML2, ML3, ML4, ML5, ML6, ML7 and ML8 and the vias VA1, VA2, VA3, VA4, VA5, VA6, VA7 and VA8 described previously. The connection wirings RML1, RML2 and RML3 may be electrically connected to the pixel circuit portion 220 or the second pad PD2 through conductive vias RVA1, RVA2 and RVA3, the conductive vias RVA1, RVA2 and RVA3 being located in the through holes TSV1, TSV2 and TSV3 of the second single crystal semiconductor substrate 210, and the connection wirings RML1, RML2 and RML3 may be electrically connected to the driving circuit layer 120 of the driving portion 100.

[0185] The display portion 200 of the display device 10 may include a first through hole TSV1, a second through hole TSV2, and a third through hole TSV3, each of which penetrates the second single crystalline semiconductor substrate 210. The first through hole TSV1, the second through hole TSV2, and the third through hole TSV3 may all be located in the non-display area NA. As described above, the first through hole TSV1 and the third through hole TSV3 may be located in the pad area PDA of the display portion 200, and the second through hole TSV2 may be located in the non-display area NA to overlap with the gate driving portions 610 and 620.

[0186] The first routing wiring RM1 connecting the data terminal DTD and the driving circuit layer 120 of the driving unit 100 may be located in the first through hole TSV1, and the data terminal DTD is connected to the data line DL. The first through hole TSV1 may penetrate the second single crystal semiconductor substrate 210, the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4, and the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, and the fifth interlayer insulating layer INS5 from the bottom surface of the data terminal DTD to the bottom surface of the second single crystal semiconductor substrate 210. The first conductive via RVA1 may be located from the bottom surface of the data terminal DTD to the bottom surface of the second single crystal semiconductor substrate 210, and may be connected to the data terminal DTD and the first connection wiring RML1 thereby. The first connection wiring RML1 may be Figure 8 Data routing wiring GDL.

[0187] The second routing wiring RM2 connecting the gate terminal GTD and the driving circuit layer 120 of the driving part 100 may be located in the second through hole TSV2, and the gate terminal GTD is connected to the gate driving parts 610 and 620. The second through hole TSV2 may penetrate the second single crystal semiconductor substrate 210, the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4, and the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4 and the fifth interlayer insulating layer INS5 from the bottom surface of the gate terminal GTD to the bottom surface of the second single crystal semiconductor substrate 210. The second conductive via RVA2 may be positioned from the bottom surface of the gate terminal GTD to the bottom surface of the second single crystal semiconductor substrate 210, and may be connected thereby to the gate terminal GTD and the second connection wiring RML2. The second connection wiring RML2 may be Figure 8 The control routing wiring TCL.

[0188] lie in Fig.12 The through hole and the conductive via in the non-display area NA may be the first through hole TSV1 or the second through hole TSV2 and the first conductive via RVA1 or the second conductive via RVA2, respectively. Fig.12 The terminal depicted in may be a data terminal DTD or a gate terminal GTD. The first and second routing wirings RM1 and RM2 and the first and second through vias TSV1 and TSV2 may have similar cross-sectional structures and may differ only in their placement, number, and connectivity.

[0189] The third routing wiring RM3 that can connect the second pad PD2 in the pad area PDA of the display part 200 with the first pad PD1 of the driving part 100 can be located in the third through hole TSV3. The third through hole TSV3 can penetrate the second single crystal semiconductor substrate 210, the third semiconductor insulating layer SINS3 and the fourth semiconductor insulating layer SINS4, and the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, and the fifth interlayer insulating layer INS5 from the bottom surface of the second pad PD2 to the bottom surface of the second single crystal semiconductor substrate 210. The third conductive via RVA3 can be located from the bottom surface of the second pad PD2 to the bottom surface of the second single crystal semiconductor substrate 210, and can be connected to the second pad PD2 and the third connection wiring RML3 thereby.

[0190] By forming the circuit part in the driving part 100 using a high-cost, fine semiconductor process, a high integration density can be achieved on the first single crystal semiconductor substrate 110, which has a relatively small area. The manufacture of the driving part 100 can produce a high output per wafer substrate, and the circuit components (e.g., the first transistor) can have a small size, thereby reducing power consumption. In addition, by placing pixel circuits, some circuit components and wiring for emission of the light-emitting element on the display part 200, the excessive integration density on the first single crystal semiconductor substrate 110 can be alleviated. In addition, by improving or optimizing the number of through-holes TSV1, TSV2 and TSV3 where the routing wiring RM1, RM2 and RM3 are located, the space suitable for placing through-holes TSV1, TSV2 and TSV3 with corresponding diameter and spacing designs can be reduced or minimized.

[0191] The reflective electrode layer RL may be located on the seventh interlayer insulating layer INS7. The reflective electrode layer RL may include one or more reflective electrodes RL1, RL2, RL3, and RL4. Fig.12 The reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0192] The first reflective electrode RL1 may be located on the seventh interlayer insulating layer INS7 and may be connected to a via hole penetrating the seventh interlayer insulating layer INS7. The first reflective electrode RL1 may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0193] The second reflective electrode RL2 may be located on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. For example, the second reflective electrode RL2 may include Al.

[0194] The third reflective electrode RL3 may be located on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. For example, the third reflective electrode RL3 may include TiN.

[0195] The fourth reflective electrode RL4 may be located on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. For example, the fourth reflective electrode RL4 may include Ti.

[0196] The thickness of the fourth reflective electrode RL4, which is an electrode that substantially reflects light from the light emitting element, may be greater than the thickness of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3. For example, the thickness of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be approximately 100Å, and the thickness of the fourth reflective electrode RL4 may be approximately 850Å.

[0197] The eighth interlayer insulating layer INS8 may be located on the seventh interlayer insulating layer INS7. The eighth interlayer insulating layer INS8 may be located between adjacent portions of the reflective electrode layer RL. The eighth interlayer insulating layer INS8 may also be located on the reflective electrode layer RL in the first sub-pixel SP1. The eighth interlayer insulating layer INS8 may be formed based on SiO x The present invention further includes an inorganic film, but the present disclosure is not limited thereto.

[0198] The ninth interlayer insulating layer INS9 may be located on the eighth interlayer insulating layer INS8 and the reflective electrode layer RL. The ninth interlayer insulating layer INS9 may be formed based on SiO x The present invention further includes an inorganic film, but the present disclosure is not limited thereto.

[0199] In the first subpixel SP1 , the second subpixel SP2 , and / or the third subpixel SP3 , the eighth and ninth interlayer insulating layers INS8 and INS9 may not be located under the first electrode AND in consideration of a resonance distance of light emitted from the light emitting element.

[0200] For example, the first electrode AND of the third subpixel SP3 may be directly located on the fourth reflective electrode RL4 and may not overlap the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9. The first electrode AND of the second subpixel SP2 may be located on the ninth interlayer insulating layer INS9, and the ninth interlayer insulating layer INS9 may be directly located on the fourth reflective electrode RL4. Therefore, the first electrode AND of the second subpixel SP2 may not overlap the eighth interlayer insulating layer INS8. The first electrode AND of the first subpixel SP1 may be located on the ninth interlayer insulating layer INS9 and may overlap the eighth interlayer insulating layer INS8.

[0201] In one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL may be different among the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. According to the main wavelength of light emitted from each of the sub-pixels SP1, SP2, and SP3, the presence or absence of the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 in each of the sub-pixels SP1, SP2, and SP3 may be determined to adjust the distance from the reflective electrode layer RL to the second electrode CAT. For example, Fig.12As shown in , the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and greater than the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3. However, the present disclosure is not limited thereto. The distances between the first electrodes AND and the reflective electrode layer RL of the sub-pixels SP1, SP2, and SP3 may be varied and designed differently.

[0202] Fig.12 The presence of the eighth interlayer insulating layer INS8 and the ninth interlayer insulating layer INS9 is shown, and the tenth interlayer insulating layer may be further located under the first electrodes AND of the sub-pixels SP1, SP2, and SP3. In this case, the ninth interlayer insulating layer INS9 and the tenth interlayer insulating layer may both be located under the first electrode AND of the second sub-pixel SP2, and the eighth interlayer insulating layer INS8, the ninth interlayer insulating layer INS9, and the tenth interlayer insulating layer may be located under the first electrode AND of the first sub-pixel SP1.

[0203] The electrode via hole VAP may be connected to the fourth reflective electrode RL4 exposed through the eighth interlayer insulating layer INS8 and / or the ninth interlayer insulating layer INS9 in the first subpixel SP1 and the second subpixel SP2. The electrode via hole VAP may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. The thickness of the electrode via hole VAP in the second subpixel SP2 may be smaller than the thickness of the electrode via hole VAP in the first subpixel SP1.

[0204] The display element layer 230 may be located on the emitter backplane EBP. The display element layer 230 may include a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, and a cover layer DCL. The display element layer 230 may include a light emitting element electrically connected to the pixel circuit part 220 and the driving part 100 to emit light.

[0205] The light emitting element layer EML may be on the reflective electrode layer RL and the ninth interlayer insulating layer INS9. The light emitting element layer EML may include a light emitting element, a pixel defining layer PDL, and a trench TRC, and the light emitting element may include a first electrode AND, a light emitting stack IL, and a second electrode CAT.

[0206] The first electrode AND of the light emitting element may be located on the ninth interlayer insulating layer INS9 or the reflective electrode layer RL, and may be connected to the electrode via VAP. The first electrode AND of the light emitting element may be connected to the second transistor PTR2 through the electrode via VAP, the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, the fourth reflective electrode RL4, the routing conductive layer RMT, and the contact electrode CTE. The first electrode AND of the light emitting element may be formed of Cu, Al, W, Mo, Cr, Au, Ti, Ni, Nd, or an alloy thereof. For example, the first electrode AND of the light emitting element may include TiN.

[0207] The pixel defining film PDL may be located on a portion of the first electrode AND of the light emitting element. The pixel defining film PDL may cover an edge of the first electrode AND of the light emitting element. The pixel defining film PDL may define and separate the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0208] The first light emitting area EA1 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT in the first sub-pixel SP1 are sequentially stacked to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT in the second sub-pixel SP2 are sequentially stacked to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the light emitting stack IL, and the second electrode CAT in the third sub-pixel SP3 are sequentially stacked to emit light.

[0209] The pixel definition film PDL may include a first pixel definition film PDL1, a second pixel definition film PDL2, and a third pixel definition film PDL3. The first pixel definition film PDL1 may be located on the edge of the first electrode AND of the light emitting element, the second pixel definition film PDL2 may be located on the first pixel definition film PDL1, and the third pixel definition film PDL3 may be located on the second pixel definition film PDL2. The first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 may be formed based on SiO x The thickness of the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may be approximately 500Å.

[0210] If a single pixel defining film PDL is formed instead of the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3, the single pixel defining film PDL may become too high, possibly causing discontinuity in the first inorganic encapsulation layer TFE1 due to step coverage. Step coverage may refer to the ratio of the thickness of a film applied on a flat surface to the thickness of a film applied on an inclined surface, and lower step coverage may mean a higher possibility of the film being disconnected on the inclined surface.

[0211] In order to reduce or prevent the possibility of discontinuity in the first inorganic encapsulation layer TFE1 due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a step-shaped cross-sectional structure. For example, the width of the first pixel defining film PDL1 may be greater than the widths of the second pixel defining film PDL2 and the third pixel defining film PDL3, and the width of the second pixel defining film PDL2 may be greater than the width of the third pixel defining film PDL3. The width of the first pixel defining film PDL1 refers to the length of the first pixel defining film PDL1 in the horizontal direction (e.g., the first direction DR1 or the second direction DR2).

[0212] The trench TRC may penetrate the first pixel defining film PDL1 , the second pixel defining film PDL2 , and the third pixel defining film PDL3 . In the trench TRC, the eighth interlayer insulating layer INS8 may be partially recessed, and the ninth interlayer insulating layer INS9 may be completely penetrated.

[0213] One or more trenches TRC may be located between the sub-pixels SP1 , SP2 , and SP3 . Fig.12 and Fig.13 It is shown that two trenches TRC are located between the sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0214] The light emitting stack IL may include a plurality of intermediate layers. The light emitting stack IL may have a 3-series structure having a first intermediate layer IL1, a second intermediate layer IL2, and a third intermediate layer IL3, but the present disclosure is not limited thereto. Alternatively, the light emitting stack IL may have a 2-series structure having two intermediate layers.

[0215] The light emitting stack IL may have a 3-series structure having a plurality of intermediate layers for emitting light of different colors. For example, the light emitting stack IL may include a first intermediate layer IL1 emitting a first color light, a second intermediate layer IL2 emitting a third color light, and a third intermediate layer IL3 emitting a second color light. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked.

[0216] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer for emitting a first color light, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer for emitting a third color light, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer for emitting a second color light, and a third electron transport layer are sequentially stacked.

[0217] A first charge generation layer for supplying charges to the second intermediate layer IL2 and electrons to the first intermediate layer IL1 may be located between the first intermediate layer IL1 and the second intermediate layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first intermediate layer IL1, and may include a P-type charge generation layer that supplies holes to the second intermediate layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0218] The second charge generation layer for supplying charges to the third intermediate layer IL3 and for supplying electrons to the second intermediate layer IL2 may be located between the second intermediate layer IL2 and the third intermediate layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second intermediate layer IL2, and may include a P-type charge generation layer for supplying holes to the third intermediate layer IL3.

[0219] The first intermediate layer IL1 may be located on the first electrode AND and the pixel defining film PDL, and may be placed at the bottom surface of the groove TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between the sub-pixels SP1, SP2, and SP3. The second intermediate layer IL2 may be located on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between the sub-pixels SP1, SP2, and SP3. The cavity or empty space ESS may be located between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be located on the second intermediate layer IL2. The third intermediate layer IL3 may not be disconnected by the groove TRC, and may be positioned to cover the second intermediate layer IL2 in the groove TRC. That is, in the 3-series structure, the groove TRC may be used as a structure for disconnecting the first intermediate layer IL1 and the second intermediate layer IL2 of the light-emitting element layer EML between the sub-pixels SP1, SP2, and SP3, and the first charge generation layer and the second charge generation layer, and in the 2-series structure, the groove TRC may be used as a structure for disconnecting the lower intermediate layer and the charge generation layer located between the lower intermediate layer and the upper intermediate layer.

[0220] In order to reliably disconnect the first intermediate layer IL1 and the second intermediate layer IL2 of the light emitting element layer EML between the sub-pixels SP1, SP2 and SP3, the height of the groove TRC may be greater than the height of the pixel defining film PDL. The height of the groove TRC refers to the length of the groove TRC in the third direction DR3. The height of the pixel defining film PDL refers to the length of the pixel defining film PDL in the third direction DR3. In order to disconnect the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EML between the sub-pixels SP1, SP2 and SP3, another structure may be provided to replace the groove TRC. For example, an inverted tapered spacer may be located on the pixel defining film PDL.

[0221] The number of intermediate layers (IL1, IL2, and IL3) emitting light of different colors is not specifically limited. Alternatively, for example, the light emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other intermediate layer may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In addition, a charge generating layer may be located between the two intermediate layers to supply electrons to one of the two intermediate layers and to supply charges to the other intermediate layer.

[0222] Fig.12 and Fig.13 It is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are respectively located in the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3, but the present disclosure is not limited thereto. Optionally, the first intermediate layer IL1 may be located in the first light-emitting area EA1 but not in the second light-emitting area EA2 and the third light-emitting area EA3. The second intermediate layer IL2 may be located in the second light-emitting area EA2 but not in the first light-emitting area EA1 and the third light-emitting area EA3. The third intermediate layer IL3 may be located in the third light-emitting area EA3 but not in the first light-emitting area EA1 and the second light-emitting area EA2. In this case, the plurality of color filters (CF1, CF2, and CF3) of the optical layer OPL may not be provided.

[0223] The second electrode CAT may be located on the third intermediate layer IL3. For example, the second electrode CAT may also be located on the third intermediate layer IL3 within each of the grooves TRC. The second electrode CAT may be formed of a transparent conductive oxide (TCO) such as indium tin oxide (ITO) or indium zinc oxide (IZO) or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy thereof. If the second electrode CAT is formed of a semi-transmissive conductive material, the luminous efficiency of the sub-pixels SP1, SP2, and SP3 may be enhanced due to a microcavity or the like.

[0224] The encapsulation layer TFE may be located on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic encapsulation layer to reduce or prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0225] The first inorganic encapsulation layer TFE1 may be located on the second electrode CAT, the organic encapsulation layer TFE2 may be located on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be located on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed to alternately stack silicon nitride (SiN x ), silicon oxynitride (SiO x N y )、SiO x 、TiO x and / or aluminum oxide (AlO x ). The organic encapsulation layer TFE2 may be a monomer. The organic encapsulation layer TFE2 may be an organic film such as a film of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0226] The adhesive layer ADL may be located on the encapsulation layer TFE. The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to other layers. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive or a transparent adhesive resin.

[0227] The optical layer OPL may include a color filter layer CFL, a lens LNS, and a filling layer FIL. The color filter layer CFL may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be located on the adhesive layer ADL.

[0228] The first color filter CF1 may overlap the first light emitting area EA1. The first color filter CF1 may transmit the first color light (eg, light in a red wavelength range). The red wavelength range may be about 600 nm to about 750 nm. The first color filter CF1 may transmit the first color light emitted from the first light emitting area EA1 therethrough.

[0229] The second color filter CF2 may overlap the second light emitting area EA2. The second color filter CF2 may transmit the second color light (e.g., light in a green wavelength range). The green wavelength range may be about 480 nm to about 560 nm. The second color filter CF2 may transmit the second color light emitted from the second light emitting area EA2 therethrough.

[0230] The third color filter CF3 may overlap the third light emitting area EA3. The third color filter CF3 may transmit light of a third color (e.g., light in a blue wavelength range). The blue wavelength range may be about 370 nm to about 460 nm. The third color filter CF3 may transmit light of a third color emitted from the third light emitting area EA3.

[0231] Lenses LNS may be respectively positioned on the first, second, and third color filters CF1, CF2, and CF3. The lenses LNS may serve to increase the ratio of light directed toward the front of the display device 10. The lens LNS may have a convex cross-sectional shape in an upward direction.

[0232] The filling layer FIL may be located on the lens LNS. The filling layer FIL may have a refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at the interface between the lens LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film of acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0233] The covering layer DCL may be located on the filling layer FIL. The covering layer DCL may be a glass substrate or a polymer resin. If the covering layer DCL is a glass substrate, the covering layer DCL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used as an adhesive for bonding the covering layer DCL. If the covering layer DCL is a glass substrate, the covering layer DCL may also be used as a packaging substrate. If the covering layer DCL is a polymer resin, the covering layer DCL may be directly applied to the filling layer FIL.

[0234] In one or more embodiments, the display unit 200 may further include a polarizer located on the cover layer DCL. The polarizer may be located on one surface of the cover layer DCL. The polarizer may be used as a structure for reducing or preventing visibility reduction due to external light reflection. The polarizer may include a linear polarizer and a phase delay film. For example, the phase delay film may be a quarter wave plate (e.g., a λ / 4 plate), but the present disclosure is not limited thereto. However, if the visibility reduction caused by external light reflection is sufficiently improved by the color filters (CF1, CF2, and CF3), the polarizer may not be provided.

[0235] Various embodiments of the display device 10 will be described hereinafter with reference to other drawings.

[0236] Fig.14 and Fig.15 is a cross-sectional view of a display device according to other embodiments of the present disclosure.

[0237] Reference Fig.14 , the driving circuit section 400 of the driving section 100 may be located on the circuit board 300. The driving circuit section 400 may be located on the circuit board 300 as a separate chip without including the first transistor PTR1 formed on the first single crystal semiconductor substrate 110 of the driving section 100. Therefore, the gate driving sections 610 and 620 may be electrically connected to the driving circuit section 400 through the second pad PD2 in the display section 200, and the data driving section 700 may be electrically connected to the driving circuit section 400 through the second routing wiring RM2. In one or more embodiments, the second routing wiring RM2 may be electrically connected to the circuit board 300 and the driving circuit section 400 through the second pad PD2.

[0238] Reference Fig.15 , the circuit board 300 may be located on the back side of the driving part 100. The first single crystal semiconductor substrate 110 of the driving part 100 may include / define a through hole penetrating the first single crystal semiconductor substrate 110. The third routing wiring RM3 may be located in the through hole. The circuit board 300 may be attached to the back side of the driving part 100 and the protective layer 900, and may be electrically connected to the driving circuit part 400 and / or the data driving part 700 of the driving part 100 through the third routing wiring RM3 positioned in the through hole penetrating the first single crystal semiconductor substrate 110.

[0239] In one or more embodiments, the third through hole TSV3 may be omitted in the second single crystal semiconductor substrate 210 of the display part 200, and only the first through hole TSV1 and the second through hole TSV2 may be formed in the second single crystal semiconductor substrate 210. The display part 200 and the driving part 100 may be connected to each other through the first routing wiring RM1 and the second routing wiring RM2.

[0240] Fig.16 is a cross-sectional view of a display device according to one or more other embodiments of the present disclosure. Fig.17 yes Fig.16 A bottom view of a display device.

[0241] Reference Fig.16 and Fig.17 , the display device 10 may not include the connection wiring layer 500, and the plurality of through holes TSV1, TSV2, and TSV3 and the routing wirings RM1, RM2, and RM3 may overlap with the driving part 100. The driving part 100 may have a width of 100. Figure 7 and Figure 8The area of ​​its corresponding part is large, and it can overlap with the through holes TSV1, TSV2 and TSV3 formed in the display part 200. As the area of ​​the driving part 100 increases, terminals connected to the routing wirings RM1, RM2 and RM3 can be formed at positions corresponding to the through holes TSV1, TSV2 and TSV3 in the driving part 100. The routing wirings RM1, RM2 and RM3 may only include conductive vias RVA1, RVA2 and RVA3 located in the through holes TSV1, TSV2 and TSV3, and the conductive vias RVA1, RVA2 and RVA3 may directly contact the terminals formed in the driving circuit layer 120 of the driving part 100. For example, the first routing wiring RM1 may directly contact the terminal connected to the data driving part 700, the second routing wiring RM2 may directly contact the terminal connected to the driving circuit part 400, and the third routing wiring RM3 may directly contact the first pad PD1.

[0242] The driving part 100 may have a smaller area than the display part 200 but may be large enough to cover the region where the vias TSV1, TSV2 and TSV3 are located. Therefore, connection lines connecting the vias TSV1, TSV2 and TSV3 and the routing wirings RM1, RM2 and RM3 of the driving part 100 may not be provided.

[0243] Fig.18 is a perspective view of an HMD device according to one or more embodiments of the present disclosure. Fig.19 yes Fig.18 An exploded perspective view of the HMD device.

[0244] Reference Fig.18 and Fig.19 The HMD device 1000 may include a first display device 11, a second display device 12, a display device housing 1100, a housing cover 1200, a first eyepiece lens 1210, a second eyepiece lens 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600, and a connector.

[0245] The first display device 11 provides an image to the left eye of the user, and the second display device 12 provides an image to the right eye of the user. Figure 1 The display devices 10 are substantially the same, and thus a detailed description of the first display device 11 and the second display device 12 will be omitted.

[0246] The first optical member 1510 may be located between the first display device 11 and the first eyepiece lens 1210. The second optical member 1520 may be located between the second display device 12 and the second eyepiece lens 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0247] The middle frame 1400 may be located between the first display device 11 and the control circuit board 1600, and between the second display device 12 and the control circuit board 1600. The middle frame 1400 supports and fixes the first display device 11, the second display device 12, and the control circuit board 1600.

[0248] The control circuit board 1600 may be located between the middle frame 1400 and the display device housing 1100. The control circuit board 1600 may be connected to the first display device 11 and the second display device 12 through a connector. The control circuit board 1600 may convert an external video source into digital video data DATA, and may transmit the digital video data DATA to the first display device 11 and the second display device 12 through the connector.

[0249] The control circuit board 1600 may transmit digital video data DATA corresponding to an image suitable or optimized for the left eye of the user to the first display device 11, and transmit digital video data DATA corresponding to an image suitable or optimized for the right eye of the user to the second display device 12. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to both the first display device 11 and the second display device 12.

[0250] The display device housing 1100 accommodates the first display device 11, the second display device 12, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The housing cover 1200 is positioned to cover the opening side of the display device housing 1100. The housing cover 1200 may include a first eyepiece lens 1210 for the left eye of the user and a second eyepiece lens 1220 for the right eye of the user. Fig.18 The first eyepiece lens 1210 and the second eyepiece lens 1220 are shown to be separate, but the present disclosure is not limited thereto. Alternatively, the first eyepiece lens 1210 and the second eyepiece lens 1220 may be integrated into a single unit.

[0251] The first eyepiece lens 1210 is aligned with the first display device 11 and the first optical member 1510, and the second eyepiece lens 1220 is aligned with the second display device 12 and the second optical member 1520. Therefore, the user can view the image from the first display device 11 magnified as a virtual image by the first optical member 1510 through the first eyepiece lens 1210, and can also view the image from the second display device 12 magnified as a virtual image by the second optical member 1520 through the second eyepiece lens 1220.

[0252] The headband 1300 fixes the display device housing 1100 to the user's head, thereby ensuring that the first eyepiece lens 1210 and the second eyepiece lens 1220 remain correctly positioned over the user's left eye and right eye, respectively. If the display device housing 1100 is implemented to be lightweight and small, the HMD device 1000 may be equipped with a headband such as Fig. 20 , rather than the headband 1300 .

[0253] In addition, the HMD device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving a video source. The external connection port may be a universal serial bus (USB) port, a display port, or a high-definition multimedia interface (HDMI) port, and the wireless communication module may include a 5G module, a 4G module, a Wi-Fi module, or a Bluetooth module.

[0254] Fig. 20 is a perspective view of an HMD device according to one or more other embodiments of the present disclosure.

[0255] Reference Fig. 20 , the HMD device 1000_1 may be in the form of glasses having a lightweight and compact display device housing 1200_1. The HMD device 1000_1 may include a display device 13, a left eyepiece lens 1010, a right eyepiece lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path conversion member 1070, and a display device housing 1200_1.

[0256] The display device housing 1200_1 may house the display device 13, the optical member 1060, and the optical path conversion member 1070. The image displayed on the display device 13 may be magnified by the optical member 1060, and its optical path may be changed by the optical path conversion member 1070 to be transmitted to the user's right eye through the right eyepiece lens 1020. As a result, the user may view an AR image into which the virtual image displayed on the display device 13 and the real image viewed through the right eyepiece lens 1020 are combined.

[0257] The display device housing 1200_1 is shown as being located at the right end of the support frame 1030, but the present disclosure is not limited thereto. Alternatively, the display device housing 1200_1 may be located at the left end of the support frame 1030, in which case the image from the display device 13 may be provided to the left eye of the user. Alternatively, the display device housing 1200_1 may be located at both the left and right ends of the support frame 1030, in which case the user may view the image from the display device 13 through both eyes.

[0258] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the aspects of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display device, comprising: a first single crystal semiconductor substrate having a first transistor positioned thereon; as well as A second single crystal semiconductor substrate, on which a second transistor is positioned, has a planar area larger than a planar area of ​​the first single crystal semiconductor substrate, the second single crystal semiconductor substrate is located above the first single crystal semiconductor substrate, the second single crystal semiconductor substrate includes a display area on which a sub-pixel including a light-emitting element is positioned, the second single crystal semiconductor substrate defines a first through hole in which a first conductive via electrically connected to a data line is positioned, and defines a second through hole in which a second conductive via electrically connected to a gate driving unit is positioned, the data line is connected to the sub-pixel, and the gate driving unit is connected to the sub-pixel.

2. The display device according to claim 1, wherein: The number of the first through holes is greater than the number of the second through holes.

3. The display device according to claim 1, wherein: The number of the first through holes is equal to the number of columns of the sub-pixels.

4. The display device according to claim 1, further comprising: a circuit board, over a pad, the pad being located in a non-display area around the display area of ​​the second single crystal semiconductor substrate, The second single crystal semiconductor substrate defines a third through hole overlapping the pad.

5. The display device according to claim 4, wherein: The first through hole overlaps the circuit board in a thickness direction.

6. The display device according to claim 4, wherein: The third through hole overlaps the circuit board and the first single crystal semiconductor substrate.

7. The display device according to claim 4, wherein: The first through hole does not overlap the pad.

8. The display device according to claim 1, further comprising: a circuit board, on a bottom surface of the first single crystal semiconductor substrate, Wherein the first single crystal semiconductor substrate defines a third through hole in which there is a conductive via connected to the circuit board.

9. The display device according to claim 8, further comprising: The driving circuit part is on the circuit board.

10. The display device according to claim 1, wherein: The width of the first single crystal semiconductor substrate in one direction is greater than the width of the display region in the one direction.

11. The display device according to claim 1, wherein: The first through hole and the second through hole are in a non-display area located around the display area in a plan view.

12. The display device according to claim 1, wherein: The data line extends in a first direction over the second single crystal semiconductor substrate and is electrically connected to some of the first transistors, and The display device further includes: a scan line electrically connected to the gate driving unit and extending in a second direction intersecting the first direction above the second single crystal semiconductor substrate.

13. The display device according to claim 12, wherein: The first through holes are arranged along the first direction parallel to the data lines.

14. The display device according to claim 12, wherein: The number of the first through holes is equal to the number of the data lines.

15. The display device according to claim 1, further comprising: A connection wiring layer is between the first single crystal semiconductor substrate and the second single crystal semiconductor substrate and is connected to the first conductive via and the second conductive via.

16. A head-mounted display device, comprising: a frame configured to be worn on a user's body and to correspond to the user's eyes; a display device, in said frame; as well as A lens, above the display device, The display device includes: a first single crystal semiconductor substrate, on which a first transistor is positioned; and a second single crystal semiconductor substrate, which is above the first single crystal semiconductor substrate and on which a second transistor is positioned. wherein the second single crystal semiconductor substrate includes a display area where a sub-pixel including a light emitting element is located, the second single crystal semiconductor substrate defines a first through hole where a first conductive via electrically connected to a data line is located, and defines a second through hole where a second conductive via electrically connected to a gate driving unit is located, the data line is connected to the sub-pixel, the gate driving unit is electrically connected to the sub-pixel, and Wherein, a plane area of ​​the first single crystal semiconductor substrate is smaller than a plane area of ​​the second single crystal semiconductor substrate.

17. The head mounted display device according to claim 16, wherein: The number of the first through holes is equal to the number of columns of the sub-pixels.

18. The head mounted display device according to claim 16, wherein: The width of the first single crystal semiconductor substrate in one direction is greater than the width of the display region in the one direction.

19. The head mounted display device according to claim 18, wherein: The first through hole and the second through hole are in a non-display area located around the display area.

20. The head mounted display device according to claim 16, further comprising: a circuit board, over a pad, the pad being in a non-display area located around the display area of ​​the second single crystal semiconductor substrate in a plan view, wherein the second single crystal semiconductor substrate defines a third through hole overlapping the pad, and Wherein, the first through hole overlaps with the circuit board in the thickness direction.

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