A fault injection method, device, equipment and storage medium
By pruning the fault injection space in graph computation tasks, determining the target iteration round and vertices, and performing fault injection, the problems of high energy consumption and time overhead in traditional methods are solved, and the efficiency of fault tolerance strategies in graph processing systems is improved.
Patent Information
- Application Number
- CN202510182784.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-19
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2045-02-19
AI Technical Summary
In graph computing tasks, existing technologies, when affected by hardware failures, require a large number of random fault injection methods, resulting in unacceptable time and energy consumption, which affects the efficiency of graph processing systems.
By using iterative graph processing based on graph computation tasks, the target iteration round and active vertex set are determined, and the fault injection space is pruned to reduce the number of fault injections. The simulation injection results are statistically analyzed using a preset granularity to reduce energy consumption and time overhead.
While ensuring effectiveness and reliability, reduce the number of fault injections, improve the efficiency of the fault tolerance strategy of the graph processing system, and reduce energy consumption and time overhead.
Smart Images
Figure CN120045463B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data processing, and in particular to a fault injection method, apparatus, device, and storage medium. Background Technology
[0002] To improve the processing efficiency of graph computing tasks, acceleration is typically achieved on general-purpose graphics processors and customized domain-specific hardware. However, as the integration of these platforms increases, circuitry has evolved to the nanometer scale. In this context, the probability of hardware failure due to factors such as [unspecified factors] rises. Common troubleshooting measures include instruction duplication and hardware redundancy; however, indiscriminate redundancy can lead to significant energy consumption and time overhead.
[0003] Currently, in order to analyze the parts of a graph processing system that need protection under the influence of hardware failures, traditional solutions usually rely on random fault injection into the program fault space, which often requires a large number of injections. However, since the program fault space is often very large and the data scale of graph processing is increasing day by day, a large number of fault injections will consume unacceptable time and energy. Summary of the Invention
[0004] In view of this, the purpose of this invention is to provide a fault injection method, apparatus, device, and storage medium that can reduce the number of fault injections while ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and thus improving the efficiency of fault tolerance strategies for subsequent guidance graph processing. The specific solution is as follows:
[0005] Firstly, this application provides a fault injection method, including:
[0006] Iterative graph processing is performed based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results.
[0007] The target iteration round to be injected with fault is determined from each iteration round based on the task processing results and the pre-determined fault resilience exploration results. The set of active vertices corresponding to the target iteration round is analyzed to determine the target vertex to be injected with fault based on the obtained set analysis results.
[0008] Based on the fault resilience exploration results, the corresponding bits in the dynamic instructions corresponding to the graph processing program are marked with fault injection results to obtain the marked program;
[0009] Hardware faults are simulated and injected using the target iteration rounds, the target vertex, and the marked program. The injection results are statistically analyzed using each preset granularity to obtain the corresponding fault injection results.
[0010] Optionally, the iterative graph processing based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results includes:
[0011] By executing the graph processing program corresponding to the graph computation task, the corresponding iterative graph processing operation is completed, and the corresponding program output information, dynamic instructions and register information corresponding to the graph processing program, and the set of active vertices in each iteration are recorded.
[0012] Optionally, determining the target iteration round for fault injection from each iteration round based on the task processing results and pre-determined fault resilience exploration results includes:
[0013] Based on the task processing results and the pre-determined fault resilience exploration results, the degree of overlap of active vertices in each iteration round is analyzed to obtain the corresponding iteration round analysis results;
[0014] Based on the analysis results of the iteration rounds, multiple iteration groups are determined, and the target iteration rounds for fault injection are selected from each iteration group.
[0015] Optionally, the step of analyzing the set of active vertices corresponding to the target iteration round, and determining the target vertex to be injected with fault based on the obtained set analysis results, includes:
[0016] Based on the task processing results and the fault resilience exploration results, a neighbor set similarity analysis is performed on the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding first set analysis results;
[0017] Using the analysis results of the first set, target vertices to be injected with faults are selected from each set of active vertices.
[0018] Optionally, the step of analyzing the set of active vertices corresponding to the target iteration round, and determining the target vertex to be injected with fault based on the obtained set analysis results, includes:
[0019] Based on the task processing results and the fault resilience exploration results, clustering coefficients are calculated among the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding second set analysis results.
[0020] The target vertices to be injected with faults are selected from each set of active vertices using the analysis results of the second set.
[0021] Optionally, the step of marking the corresponding bit in the dynamic instruction corresponding to the graph processing program with fault injection results based on the fault resilience exploration results includes:
[0022] The dynamic instructions corresponding to the graph processing program are divided based on the instruction type to obtain the corresponding instruction division results;
[0023] Based on the fault resilience exploration results, the corresponding bit bits in the numerical calculation instructions and address calculation instructions in the instruction partitioning results are used to trigger the corresponding first fault injection result marking operation and second fault injection result marking operation to obtain the marked program.
[0024] Optionally, the step of simulating hardware fault injection using the target iteration round, the target vertex, and the marked program, and statistically analyzing the injection results using each preset granularity, includes:
[0025] After simulating hardware fault injection into the marked program, for any preset granularity, the program output is monitored, and the injection results of the marked area and the fault injection area in the marked program are analyzed and statistically analyzed using the task processing results and the preset fault injection result type, so as to obtain the fault injection result corresponding to the current preset granularity.
[0026] Secondly, this application provides a fault injection device, comprising:
[0027] The program execution module is used to perform iterative graph processing based on the graph processing program corresponding to the graph computation task, so as to determine and record the corresponding task processing results.
[0028] The injection exploration module is used to determine the target iteration round to be injected into from each iteration round through the task processing results and the pre-determined fault elasticity exploration results, and to analyze the set of active vertices corresponding to the target iteration round, so as to determine the target vertex to be injected into based on the obtained set analysis results.
[0029] The instruction marking module is used to mark the corresponding bits in the dynamic instruction corresponding to the graph processing program based on the fault resilience exploration results, so as to obtain the marked program.
[0030] The fault injection module is used to simulate and inject hardware faults using the target iteration round, the target vertex, and the marked program, and to statistically analyze the injection results using each preset granularity to obtain the corresponding fault injection results.
[0031] Thirdly, this application provides an electronic device, comprising:
[0032] Memory, used to store computer programs;
[0033] A processor is used to execute the computer program to implement the steps of the aforementioned fault injection method.
[0034] Fourthly, this application provides a computer-readable storage medium for storing a computer program, which, when executed by a processor, implements the steps of the aforementioned fault injection method.
[0035] As can be seen, in this application, iterative graph processing is performed based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results; the target iteration round to be injected with faults is determined from each iteration round through the task processing results and the pre-determined fault resilience exploration results, and the set of active vertices corresponding to the target iteration round is analyzed to determine the target vertices to be injected with faults based on the obtained set analysis results; the corresponding bits in the dynamic instructions corresponding to the graph processing program are marked with fault injection results based on the fault resilience exploration results to obtain the marked program; the target iteration round, the target vertices, and the marked program are used to simulate hardware fault injection, and the injection results are statistically analyzed using each preset granularity to obtain the corresponding fault injection results. In other words, this application first obtains the task processing results corresponding to the graph computation task, then uses the task processing results and pre-determined fault resilience exploration results to determine the target iteration round and target vertex to be injected with faults, and marks the corresponding bits in the graph processing program with fault injection results. Then, based on the marked program, target iteration round, and target vertex, fault injection is performed, and different preset granularities are used to statistically analyze the injection results to determine the fault injection outcome. This reduces the number of fault injections while ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and ultimately improving the efficiency of subsequent fault-tolerant strategies guiding graph processing. Attached Figure Description
[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0037] Figure 1 A flowchart of a fault injection method provided in this application;
[0038] Figure 2 A schematic diagram illustrating the exploration of fault resilience from an iterative perspective, as provided in this application;
[0039] Figure 3 A schematic diagram illustrating the exploration of fault resilience from a graph topology perspective, as provided in this application;
[0040] Figure 4A schematic diagram illustrating the fault injection results of different bits in an address calculation instruction provided in this application;
[0041] Figure 5 A schematic diagram of fault injection results for different bits of a numerical calculation instruction provided in this application;
[0042] Figure 6 A schematic diagram of a fault injection device provided in this application;
[0043] Figure 7 This application provides a structural diagram of an electronic device. Detailed Implementation
[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0045] To analyze the components of a graph processing system that require protection under the influence of hardware failures, traditional solutions typically rely on random fault injection into the program fault space. This often requires a large number of injection attempts, but since the program fault space is often enormous and the data scale of graph processing is increasing daily, a large number of fault injections consumes unacceptable time and energy. Therefore, this application provides a fault injection scheme that reduces the number of fault injection attempts while ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and ultimately improving the efficiency of subsequent fault-tolerance strategies guiding graph processing.
[0046] See Figure 1 As shown, an embodiment of the present invention discloses a fault injection method, including:
[0047] Step S11: Perform iterative graph processing based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results.
[0048] In this embodiment, the program is first executed and analyzed, that is, the graph processing program corresponding to the graph computation task is executed to complete the corresponding iterative graph processing operation, and the corresponding program output information is recorded (as a standard for comparing the correctness of the fault injection results later), the dynamic instructions and register information corresponding to the graph processing program, and the set of active vertices in each iteration round.
[0049] Step S12: Determine the target iteration round to be injected with fault from each iteration round based on the task processing results and the pre-determined fault resilience exploration results, and analyze the set of active vertices corresponding to the target iteration round to determine the target vertex to be injected with fault based on the obtained set analysis results.
[0050] It should be understood that this embodiment explores the fault resilience pattern through some experiments in advance. Starting from the execution mode of graph processing (i.e., the iteration perspective) and the graph topology perspective, the fault resilience characteristics are gradually identified. In this way, only representative fault points can be selected for fault injection, or the behavior of certain fault points under hardware failure can be predicted in advance, thereby reducing the number of fault injections.
[0051] An exploration of fault resilience from an iterative perspective, combined with Figure 2 As shown, it was found that the set of active vertices changes continuously in different iterations during the graph processing iterations. Experiments revealed that iterations with highly overlapping active vertex sets exhibit similar performance under fault conditions. It was observed that the number of active vertices in iterations 9-19 is essentially the same (and upon inspection, their active vertex sets are also very similar), while their SC and BC probabilities (which are respectively...)... Figure 2 The red and green broken lines in the graph also show a similar pattern. That is, it has been found that for an iterative set with highly overlapping active vertex sets, it is only necessary to select one iteration cycle for representative fault injection to represent the fault resilience of this iterative set.
[0052] The exploration of fault resilience from a graph topology perspective reveals that in graph topology (i.e., the input of graph processing), (1) if the neighbor sets of different vertices are similar, then the program output results caused by faults occurring at these vertices will also have similar distributions; (2) if different vertices are highly clustered, i.e., the edges between vertices are dense, then the program output results caused by faults occurring at these vertices will also have similar distributions. This is because the vertex execution mode and error propagation mode that satisfy these conditions are very similar. For details, please refer to [link to relevant documentation]. Figure 3 As shown, Figure 3 The image illustrates the performance of vertex sets (each black box) with high neighbor similarity and clustering under fault conditions. It shows that the error distribution of vertices within each box is similar. In other words, it was discovered that fault injection can be performed by identifying vertex sets with high neighbor similarity and those with high clustering levels, and then selecting representative vertices from each set.
[0053] Furthermore, regarding the predictability of fault results during execution, it was found that the instructions executed by the program can be broadly categorized into numerical calculation instructions and address calculation instructions. Figure 4This demonstrates the results of fault injection at different bit positions in address calculation instructions. Most detected errors in the program are caused by errors in address calculation instructions. Errors in the higher bits (bits 28-63) can cause the program to access addresses outside its allocated range, while errors in the lower two bits can cause the program to access illegal addresses; both situations can lead to program crashes. Furthermore, for numerical calculation instructions, binary data storage in computers is similar to decimal data storage, where higher bits often have greater weight. In numerical calculation instructions, if the fault occurs in a lower bit, it indicates a lower initial deviation, unlikely to significantly affect the final result of the program, just like... Figure 5 Bits 0-16 in the address space are unlikely to cause a fault injection (SC). In other words, it has been found that the fault injection results of some bits in both address and numerical calculation instructions are predictable, thus eliminating the need for fault injection into this part of the fault space.
[0054] Based on the above findings, corresponding fault resilience exploration results can be determined and applied to guide fault injection. This allows for fault space pruning from iteration rounds to vertices to instruction bits, significantly reducing the fault space compared to the original, thus improving fault injection efficiency. Specifically, firstly, based on the task processing results and pre-determined fault resilience exploration results, the overlap of active vertices in each iteration round is analyzed to obtain corresponding iteration round analysis results. Based on these iteration round analysis results, multiple iteration groups are determined, and target iteration rounds for fault injection are selected from each iteration group. Then, based on the task processing results and the fault resilience exploration results, neighbor set similarity analysis is performed between vertices in each active vertex set corresponding to the target iteration round to obtain corresponding first set analysis results. Target vertices for fault injection are selected from each active vertex set using the first set analysis results. Then, based on the task processing results and the fault resilience exploration results, clustering coefficients are calculated between vertices in each active vertex set corresponding to the target iteration round to obtain corresponding second set analysis results. Target vertices for fault injection are selected from each active vertex set using the second set analysis results. In other words, this embodiment calculates the degree of overlap of active vertices in different iterations and selects iterations with similar active vertices as a flexible similarity iteration group. An iteration is selected from each iteration group for representative fault injection. By calculating the neighbor similarity of different vertices and identifying sets of neighbor-similar vertices, where every pair of vertices in each set has similar neighbors, a vertex is selected from each set for representative fault injection. Furthermore, by calculating the clustering coefficients of different vertices and identifying highly clustered vertex sets, where each vertex set represents a subgraph with high connectivity, a vertex is selected from each set for representative fault injection.
[0055] Step S13: Based on the fault resilience exploration results, mark the corresponding bits in the dynamic instructions corresponding to the graph processing program with fault injection results to obtain the marked program.
[0056] In this embodiment, after completing fault space pruning from iteration rounds to vertices, fault space pruning of instruction bits is also required. Dynamic instructions are distinguished into numerical calculation instructions and address calculation instructions. For numerical calculation instructions, the lower-order fault results are directly marked as BC (e.g., in IEEE 754 data format, the lower 16 bits can be marked as BC). For address calculation instructions, based on the address space allocated to the program, the higher-order fault results are directly marked as Detected (no fault injection is required). That is, firstly, dynamic instructions corresponding to the graph processing program are divided based on instruction type to obtain corresponding instruction division results; then, based on the fault elastic exploration results, the corresponding first fault injection result marking operation and second fault injection result marking operation are triggered in the corresponding bits of the numerical calculation instructions and address calculation instructions in the instruction division results to obtain the marked program.
[0057] Step S14: Simulate hardware fault injection using the target iteration round, the target vertex, and the marked program, and statistically analyze the injection results using each preset granularity to obtain the corresponding fault injection results.
[0058] In this embodiment, after pruning the fault space, fault injection is only performed on the remaining fault space. Furthermore, after fault injection, results are statistically analyzed for different preset granularities of the graph processing system (which can be assembly instruction level, vertex level, subgraph level, kernel function level, or other granularities or combinations thereof can be selected or customized according to actual needs).
[0059] Furthermore, regarding result statistics, after simulating hardware fault injection into the marked program in this embodiment, for any preset granularity, the program output is monitored, and the injection results of the marked region and fault injection region in the marked program are analyzed and statistically analyzed using the task processing results and preset fault injection result types, respectively, to obtain the fault injection result corresponding to the current preset granularity. Specifically, the following calculations are performed for each preset granularity: For regions with known results of BC, the proportion of the region to the total fault region, the probability of BC, the probability of SC, and the probability of Detected are (a, 1, 0, 0); for regions with known results of Detected, the proportion of the region to the total fault region, the probability of BC, the probability of SC, and the probability of Detected are (b, 0, 0, 1); for fault injection regions, the proportion of the region to the total fault region, the probability of BC, the probability of SC, and the probability of Detected are (c, x, y, z), where... The distribution of fault injection results at this granularity can be calculated as follows:
[0060] ;
[0061] In the formula, This represents the probability of a benign error. This represents the probability of a critical error. This represents the detectable error probability. This allows us to obtain fault injection results at all preset granularities. Then, based on the determined fault injection results, we can identify hardware fault-sensitive parts of the graph processing system and selectively protect them—that is, parts that are prone to graph processing result corruption after being subjected to hardware fault interference.
[0062] In summary, this embodiment addresses the hardware failure problem in large-scale graph processing systems by designing an efficient fault injection method for graph computation tasks. Specifically, it reduces the fault injection space by considering the execution characteristics of the graph processing process. Compared to traditional random fault injection methods, this method reduces the number of fault injections and overhead while ensuring the accuracy of the system reliability assessment. Furthermore, this embodiment also supports multi-dimensional analysis of the reliability of the graph processing system, providing valuable insights for efficiently reducing the overhead of program fault tolerance strategies.
[0063] Therefore, in this embodiment, iterative graph processing is performed based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results; the target iteration round to be injected with faults is determined from each iteration round through the task processing results and the pre-determined fault resilience exploration results, and the set of active vertices corresponding to the target iteration round is analyzed to determine the target vertices to be injected with faults based on the obtained set analysis results; the corresponding bits in the dynamic instructions corresponding to the graph processing program are marked with fault injection results based on the fault resilience exploration results to obtain the marked program; the target iteration round, the target vertex, and the marked program are used to simulate hardware fault injection, and the injection results are statistically analyzed using each preset granularity to obtain the corresponding fault injection results. In other words, this application first obtains the task processing results corresponding to the graph computation task, then uses the task processing results and pre-determined fault resilience exploration results to determine the target iteration round and target vertex to be injected with faults, and marks the corresponding bits in the graph processing program with fault injection results. Then, based on the marked program, target iteration round, and target vertex, fault injection is performed, and different preset granularities are used to statistically analyze the injection results to determine the fault injection outcome. This reduces the number of fault injections while ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and ultimately improving the efficiency of subsequent fault-tolerant strategies guiding graph processing.
[0064] See Figure 6 As shown in the figure, this application also discloses a fault injection device, including:
[0065] The program execution module 11 is used to perform iterative graph processing based on the graph processing program corresponding to the graph computation task, so as to determine and record the corresponding task processing results;
[0066] The injection exploration module 12 is used to determine the target iteration round to be injected into from each iteration round through the task processing results and the pre-determined fault elasticity exploration results, and to analyze the set of active vertices corresponding to the target iteration round, so as to determine the target vertex to be injected into based on the obtained set analysis results.
[0067] The instruction marking module 13 is used to mark the corresponding bit in the dynamic instruction corresponding to the graph processing program based on the fault resilience exploration result, so as to obtain the marked program.
[0068] The fault injection module 14 is used to simulate the injection of hardware faults using the target iteration round, the target vertex, and the marked program, and to perform statistical analysis of the injection results using each preset granularity to obtain the corresponding fault injection results.
[0069] For more detailed information on the working process of each of the above modules, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.
[0070] Therefore, this application first obtains the task processing results corresponding to the graph computation task, then uses the task processing results and pre-determined fault resilience exploration results to determine the target iteration round and target vertex to be injected with faults, and marks the corresponding bits in the graph processing program with fault injection results. Then, based on the marked program, target iteration round, and target vertex, fault injection is performed, and different preset granularities are used to statistically analyze the injection results to determine the fault injection outcome. In this way, the number of fault injections can be reduced while ensuring effectiveness and reliability, thereby reducing energy consumption and time overhead, and ultimately improving the efficiency of subsequent fault-tolerant strategies guiding graph processing.
[0071] In some specific embodiments, the program execution module 11 can be used to execute a graph processing program corresponding to the graph computation task to complete the corresponding iterative graph processing operation, and record the corresponding program output information, the dynamic instructions and register information corresponding to the graph processing program, and the set of active vertices in each iteration round.
[0072] In some specific embodiments, the injection exploration module 12 can be used to analyze the degree of overlap of active vertices in each iteration round based on the task processing results and the pre-determined fault resilience exploration results, so as to obtain the corresponding iteration round analysis results; determine multiple iteration groups based on the iteration round analysis results, and select the target iteration round to be injected from each iteration group.
[0073] In some specific embodiments, the injection exploration module 12 can be used to perform neighbor set similarity analysis on the vertices in each active vertex set corresponding to the target iteration round based on the task processing result and the fault elastic exploration result, so as to obtain the corresponding first set analysis result; and use the first set analysis result to select the target vertex to be fault injected from each of the active vertex sets.
[0074] In some specific embodiments, the injection exploration module 12 can be used to calculate the clustering coefficients between vertices in each active vertex set corresponding to the target iteration round based on the task processing results and the fault elastic exploration results, so as to obtain the corresponding second set analysis results; and use the second set analysis results to select the target vertex to be injected from each active vertex set.
[0075] In some specific embodiments, the instruction marking module 13 can be used to divide the dynamic instructions corresponding to the graph processing program based on the instruction type to obtain the corresponding instruction division results; based on the fault elastic exploration results, the corresponding bit bits in the numerical calculation instructions and address calculation instructions in the instruction division results are triggered to trigger the corresponding first fault injection result marking operation and second fault injection result marking operation to obtain the marked program.
[0076] In some specific embodiments, the fault injection module 14 can be used to perform hardware fault simulation injection on the marked program, and for any preset granularity, monitor the program output and use the task processing result and preset fault injection result type to analyze and statistically analyze the injection result of the marked area and the fault injection area in the marked program, so as to obtain the fault injection result corresponding to the current preset granularity.
[0077] Furthermore, embodiments of this application also disclose an electronic device, Figure 7 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.
[0078] Figure 7This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the fault injection method disclosed in any of the foregoing embodiments. Alternatively, the electronic device 20 in this embodiment may specifically be an electronic computer.
[0079] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.
[0080] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.
[0081] The operating system 221 is used to manage and control the various hardware devices on the electronic device 20 and the computer program 222, which may be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program capable of performing the fault injection method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, the computer program 222 may further include a computer program capable of performing other specific tasks.
[0082] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned fault injection method. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.
[0083] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0084] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0085] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0086] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0087] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A fault injection method, characterized in that, include: Iterative graph processing is performed based on the graph processing program corresponding to the graph computation task to determine and record the corresponding task processing results. The target iteration round for fault injection is determined from each iteration round based on the task processing results and the pre-determined fault resilience exploration results. The active vertex set corresponding to the target iteration round is analyzed to determine the target vertex for fault injection based on the obtained set analysis results. The fault resilience exploration results include those corresponding to the iteration angle of graph processing and the graph topology angle, respectively. The fault resilience exploration results corresponding to the iteration angle indicate that during the iteration process of graph processing, for iteration sets with highly overlapping active vertex sets, an iteration round is selected from the iteration set for representative fault injection. The fault resilience exploration results corresponding to the graph topology angle indicate that in the graph topology, by identifying vertex sets with high neighbor set similarity and vertex sets with high clustering degree, representative vertices are selected from each vertex set for fault injection. Based on the fault resilience exploration results, the corresponding bits in the dynamic instructions corresponding to the graph processing program are marked with fault injection results to obtain the marked program; Hardware faults are simulated and injected using the target iteration rounds, the target vertex, and the marked program. The injection results are statistically analyzed using each preset granularity to obtain the corresponding fault injection results.
2. The fault injection method according to claim 1, characterized in that, The iterative graph processing based on the graph processing program corresponding to the graph computation task, to determine and record the corresponding task processing results, includes: By executing the graph processing program corresponding to the graph computation task, the corresponding iterative graph processing operation is completed, and the corresponding program output information, dynamic instructions and register information corresponding to the graph processing program, and the set of active vertices in each iteration are recorded.
3. The fault injection method according to claim 1, characterized in that, The step of determining the target iteration round for fault injection from each iteration round based on the task processing results and the pre-determined fault resilience exploration results includes: Based on the task processing results and the pre-determined fault resilience exploration results, the degree of overlap of active vertices in each iteration round is analyzed to obtain the corresponding iteration round analysis results; Based on the analysis results of the iteration rounds, multiple iteration groups are determined, and the target iteration rounds for fault injection are selected from each iteration group.
4. The fault injection method according to claim 1, characterized in that, The step of analyzing the set of active vertices corresponding to the target iteration round, and determining the target vertices to be injected with faults based on the obtained set analysis results, includes: Based on the task processing results and the fault resilience exploration results, a neighbor set similarity analysis is performed on the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding first set analysis results; Using the analysis results of the first set, target vertices to be injected with faults are selected from each set of active vertices.
5. The fault injection method according to claim 1, characterized in that, The step of analyzing the set of active vertices corresponding to the target iteration round, and determining the target vertices to be injected with faults based on the obtained set analysis results, includes: Based on the task processing results and the fault resilience exploration results, clustering coefficients are calculated among the vertices in each active vertex set corresponding to the target iteration round to obtain the corresponding second set analysis results. The target vertices to be injected with faults are selected from each set of active vertices using the analysis results of the second set.
6. The fault injection method according to claim 1, characterized in that, The step of marking the corresponding bits in the dynamic instructions corresponding to the graph processing program with fault injection results based on the fault resilience exploration results includes: The dynamic instructions corresponding to the graph processing program are divided based on the instruction type to obtain the corresponding instruction division results; Based on the fault resilience exploration results, the corresponding bit bits in the numerical calculation instructions and address calculation instructions in the instruction partitioning results are used to trigger the corresponding first fault injection result marking operation and second fault injection result marking operation to obtain the marked program.
7. The fault injection method according to any one of claims 1 to 6, characterized in that, The process of simulating hardware fault injection using the target iteration rounds, the target vertex, and the marked program, and statistically analyzing the injection results at each preset granularity, includes: After simulating hardware fault injection into the marked program, for any preset granularity, the program output is monitored, and the injection results of the marked area and the fault injection area in the marked program are analyzed and statistically analyzed using the task processing results and the preset fault injection result type, so as to obtain the fault injection result corresponding to the current preset granularity.
8. A fault injection device, characterized in that, include: The program execution module is used to perform iterative graph processing based on the graph processing program corresponding to the graph computation task, so as to determine and record the corresponding task processing results. An injection exploration module is used to determine the target iteration round for fault injection from each iteration round based on the task processing results and pre-determined fault resilience exploration results, and to analyze the active vertex set corresponding to the target iteration round to determine the target vertex for fault injection based on the obtained set analysis results. The fault resilience exploration results include those corresponding to the iteration angle of graph processing and the graph topology angle, respectively. The fault resilience exploration results corresponding to the iteration angle indicate that during the iteration process of graph processing, for iteration sets with highly overlapping active vertex sets, an iteration round is selected from the iteration set for representative fault injection. The fault resilience exploration results corresponding to the graph topology angle indicate that in the graph topology, by identifying vertex sets with high neighbor set similarity and vertex sets with high clustering degree, representative vertices are selected for fault injection in each vertex set. The instruction marking module is used to mark the corresponding bits in the dynamic instruction corresponding to the graph processing program based on the fault resilience exploration results, so as to obtain the marked program. The fault injection module is used to simulate and inject hardware faults using the target iteration round, the target vertex, and the marked program, and to statistically analyze the injection results using each preset granularity to obtain the corresponding fault injection results.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the fault injection method as described in any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, Used to store a computer program, which, when executed by a processor, implements the fault injection method as described in any one of claims 1 to 7.