Display panel and display device

Abstract

The invention relates to a display panel and a display device, and the display panel comprises a plurality of first wires which are arranged in a fan-out area at intervals, and each first wire comprises a first wire segment extending in the first direction and a second wire segment which is connected with the first wire segment and extends in the second direction; the first signal lines are arranged at intervals, and each first signal line comprises a first signal line segment extending in the third direction, a third signal line segment extending in the fourth direction and a second signal line segment connected between the first signal line segment and the third signal line segment; the first insulating layer is arranged between the plurality of first wires and the plurality of first signal lines; wherein the orthographic projection of at least part of the second signal line segment on the substrate is overlapped with the orthographic projection of the first wire on the substrate; the distance between every two adjacent second signal line segments is larger than the distance between every two adjacent first signal line segments and the distance between every two adjacent third signal line segments. Wiring short circuit of the display panel can be avoided.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the continuous development of display technologies, in order to improve the display effect of a display panel, a display panel with a narrow border has gradually become one of the development directions of display technologies. In the fanout area (Fanout area, or fan-shaped area) of the narrow-border display panel, the wiring is becoming more and more dense, the spacing between adjacent traces is getting smaller and smaller, and at least two or more layers of wiring that overlap at least partially in the thickness direction of the display panel need to be provided.

[0003] However, in the prior art, the dense wiring easily causes a short-circuit problem. Summary of the Invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to solve the problem that the dense wiring in the prior art easily causes a short circuit.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area surrounding the display area. The non-display area includes a fanout area. The display panel includes a substrate, and the following components provided in the fanout area:

[0006] A plurality of first traces arranged at intervals, provided on one side of the substrate. The first trace includes a first trace segment extending in a first direction and a second trace segment connecting the first trace segment and extending in a second direction. The first direction intersects with the second direction;

[0007] A plurality of first signal lines arranged at intervals, provided on one side of the substrate and located on one side of the plurality of first traces in a direction perpendicular to the plane where the substrate is located. The first signal line includes a first signal line segment extending in a third direction, a third signal line segment extending in a fourth direction, and a second signal line segment connecting between the first signal line segment and the third signal line segment. The third direction intersects with both the first direction and the second direction, and the fourth direction intersects with both the first direction and the second direction;

[0008] A first insulating layer provided between the plurality of first traces and the plurality of first signal lines;

[0009] Wherein, the positive projection of at least part of the second signal line segment on the substrate overlaps with the positive projection of the first trace on the substrate;

[0010] The spacing between two adjacent second signal line segments is greater than the spacing between two adjacent first signal line segments and the spacing between two adjacent third signal line segments.

[0011] In some embodiments, the distance between two adjacent first signal line segments is a first distance, the distance between two adjacent second signal line segments is a second distance, and the distance between two adjacent third signal line segments is a third distance. The second distance is greater than the first distance and the third distance, and the second distance is greater than or equal to 1.1 micrometers.

[0012] In some embodiments, at least part of the first signal line segments and at least part of the third signal line segments are straight; and / or,

[0013] At least part of the second signal line segments are zigzag, arc-shaped or curved.

[0014] In some embodiments, the second signal line segment includes a first sub-signal line segment extending in a fifth direction and a second sub-signal line segment connected to the first sub-signal line segment and extending in a sixth direction. The fifth direction intersects both the third direction and the fourth direction, and the sixth direction intersects both the third direction and the fourth direction.

[0015] In some embodiments, one of the fifth direction and the sixth direction is parallel to the first direction, and the other of the fifth direction and the sixth direction is parallel to the second direction.

[0016] In some embodiments, the first signal line segment, the first sub-signal line segment, the second sub-signal line segment, and the third signal line segment are connected in sequence, and the sixth direction is parallel to the first direction;

[0017] The orthographic projection of the second sub-signal line segment on the substrate overlaps with the orthographic projection of the first routing segment on the substrate.

[0018] In some embodiments, the first signal line segment and the third signal line segment connected by the second signal line segment are on the same straight line.

[0019] In some embodiments, including a plurality of thin film transistors, the display panel further includes:

[0020] A first metal layer disposed on one side of the substrate. The first metal layer includes the gate of the thin film transistor and at least part of the first signal line;

[0021] The first insulating layer is disposed on the side of the first metal layer away from the substrate, and the first insulating layer is an inorganic material;

[0022] A second metal layer is disposed on a side of the first insulating layer away from the substrate. The second metal layer includes a source electrode and a drain electrode of the thin film transistor, and at least a portion of the first trace.

[0023] In some embodiments, it further includes:

[0024] A second insulating layer is disposed between the first metal layer and the first insulating layer. The second insulating layer is an inorganic material;

[0025] A third metal layer is disposed between the second insulating layer and the first insulating layer. The third metal layer includes at least a portion of the first signal line.

[0026] In a second aspect, based on the same inventive concept, an embodiment of the present application further provides a display device. The display device includes any one of the display panels provided in the first aspect.

[0027] In an embodiment of the present application, when the first trace is located on a side of the first signal line away from the substrate, the distance between two adjacent second signal line segments is greater than the distance between two adjacent first signal line segments and the distance between two adjacent third signal line segments. Thereby, the surface roughness of the surface of the first insulating layer away from the substrate can be reduced, the depth of the depression can be reduced and / or the width of the depression can be increased. By providing that the first signal line includes a first signal line segment extending in a third direction, a third signal line segment extending in a fourth direction, and a second signal line segment connected between the first signal line segment and the third signal line segment, the distance between two adjacent second signal line segments can be further increased, thereby further reducing the surface roughness of the surface of the first insulating layer away from the substrate, further reducing the depth of the depression and / or increasing the width of the depression. Thus, during the manufacturing process of the display panel, when etching the second metal layer to form multiple first traces, the etching can be completed at the depression (the residual metal is completely etched), thereby avoiding short - circuit between adjacent first traces.

[0028] In an embodiment of the present application, when the first trace is located on a side of the first signal line close to the substrate, the distance between two adjacent second signal line segments is greater than the distance between two adjacent first signal line segments and the distance between two adjacent third signal line segments, that is, the second distance is larger. During the manufacturing process of the display panel, when etching the metal layer to form the first signal line, there is more etching solution between two adjacent second signal line segments, which is easy to be etched completely to avoid residue, or even if there is a little residual metal, it cannot connect two adjacent second signal line segments, thereby avoiding short - circuit between two adjacent first signal lines. Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0030] Figure 1 A top view schematic diagram of the wiring of the prior art provided by the embodiments of the present application.

[0031] Figure 2 A cross-sectional schematic diagram of the wiring of the prior art provided by the embodiments of the present application.

[0032] Figure 3 An overall schematic diagram of a display panel provided by the embodiments of the present application.

[0033] Figure 4 A first partial top view schematic diagram of the wiring of a display panel provided by the embodiments of the present application.

[0034] Figure 5 A first partial cross-sectional schematic diagram of the wiring of a display panel provided by the embodiments of the present application.

[0035] Figure 6 A first partial cross-sectional schematic diagram of the film layer structure of a display panel provided by the embodiments of the present application.

[0036] Figure 7 A first partial top view schematic diagram of the first signal line of a display panel provided by the embodiments of the present application.

[0037] Figure 8 A second partial top view schematic diagram of the wiring of a display panel provided by the embodiments of the present application.

[0038] Figure 9 A second partial cross-sectional schematic diagram of the wiring of a display panel provided by the embodiments of the present application.

[0039] Figure 10 A second partial cross-sectional schematic diagram of the film layer structure of a display panel provided by the embodiments of the present application.

[0040] Figure 11 A third partial top view schematic diagram of the wiring of a display panel provided by the embodiments of the present application.

[0041] Figure 12 A schematic diagram of a display device provided by some embodiments of the present application.

[0042] Reference numerals:

[0043] Display device 200; Display panel 100; Display area AA; Non-display area BB; Fan-out area BB1; Pad area 101; First trace 60; First signal line 70; First trace segment 61; Second trace segment 62; First signal line segment 71; Third signal line segment 73; Second signal line segment 72; First metal layer 31; First insulating layer 32; Second metal layer 33; Second insulating layer 35; Third metal layer 34;; First sub-signal line segment 731; Second sub-signal line segment 732; First sub-line 70a; Second sub-line 70b;

[0044] First direction Y; Second direction X; Third direction W1; Fourth direction W2; First distance d1; Second distance d2; Third distance d3; Fifth direction u; Sixth direction v; Depression 102a; Residual metal 33c; Thin film transistor T1; Gate 121; Source 181; Drain 182; Active part 141;

[0045] Substrate 11; First conductive layer 12; Gate insulating layer 13; Semiconductor layer 14; First interlayer insulating layer 15; Second conductive layer 16; Second interlayer insulating layer 17; Third conductive layer 18. Detailed implementation mode

[0046] For ease of understanding the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0048] When describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another element, it can be directly on the other element or there can also be intermediate elements. Further, when a layer is referred to as being "under" another layer, it can be directly below or there can be one or more intermediate elements. It can also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can also be one or more intermediate elements.

[0049] In the case of using "comprising", "having", and "including" described herein, unless an explicit limiting term is used, such as "only", "consisting of", etc., another component may also be added. Unless otherwise mentioned, a term in the singular form may include the plural form and should not be construed as having only one in number.

[0050] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0051] It should also be understood that when interpreting an element, although not explicitly described, the element is interpreted as including an error range, and this error range should be within the acceptable deviation range of a specific value determined by those skilled in the art. For example, "about", "approximately", or "substantially" may mean within one or more standard deviations, which is not limited herein.

[0052] In addition, in the specification, the phrase "schematic diagram of planar distribution" refers to the drawing when observing the target part from above, and the phrase "schematic cross-sectional view" refers to the drawing when observing the cross-section intercepted by vertically cutting the target part from the side.

[0053] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the various elements are only drawn by way of example in the drawings and not necessarily to the true scale.

[0054] As described in the background art section, dense wiring in the prior art easily leads to the problem of short circuits. Please refer to Figure 1 and Figure 2 , Figure 1 which is a top view schematic diagram of the wiring of the prior art provided for the embodiment of the present application, Figure 2 which is a cross-sectional schematic diagram of the wiring of the prior art provided for the embodiment of the present application. Figure 2 is Figure 1Cross-sectional schematic view at the first virtual coil 102. The display panel 100 includes a plurality of first traces 60 arranged at intervals and a plurality of first signal lines 70 arranged at intervals. The first traces 60 include a first trace segment 61 extending along the first direction Y and a second trace segment 62 connecting the first trace segment 61 and extending along the second direction X. The first direction Y intersects the second direction X. The plurality of first signal lines 70 arranged at intervals are disposed on one side of the substrate and are located on one side of the plurality of first traces 60 in the direction perpendicular to the plane of the substrate 11. The first signal lines 70 extend along the third direction W1, and at least a part of the positive projection of the first signal lines 70 on the substrate overlaps with the positive projection of the first traces 60 on the substrate 11. The first traces 60 are formed by patterning the second metal layer 33, and the first signal lines 70 are formed by patterning the first metal layer 31. A first insulating layer 32 is provided between the first metal layer 31 and the second metal layer 33. Figure 1 and Figure 2 It is shown that the first trace 60 is located on the side of the first signal line 70 away from the substrate 11. The inventor found that the reason for the above phenomenon is that in order to achieve a narrower bezel design, the distance between adjacent first signal lines 70 becomes smaller and the surface roughness of the surface of the first insulating layer 32 away from the substrate 11 is relatively large, resulting in the formation of a depression 102a. During the manufacturing process of the display panel 100, when etching the second metal layer 33 to form a plurality of first traces 60, residual metal 33c is likely to be formed at the depression 102a. The residual metal 33c is likely to connect between adjacent two first traces 60, leading to a short circuit and thus abnormal display. Especially when the first trace 60 includes a first trace segment 61 extending along the first direction Y and a second trace segment 62 connecting the first trace segment 61 and extending along the second direction X, a short circuit problem caused by the residual metal 33c is more likely to occur near the connection between the first trace segment 61 and the second trace segment 62.

[0055] Based on the above technical problems, the inventor's research found that the distance between adjacent two second signal line segments is greater than the distance between adjacent two first signal line segments and the distance between adjacent two third signal line segments. Thus, the surface roughness of the surface of the first insulating layer away from the substrate can be reduced, the depth of the depression can be reduced and / or the width of the depression can be increased. By setting the first signal line to include a first signal line segment extending along the third direction and a third signal line segment extending along the fourth direction, and a second signal line segment connecting between the first signal line segment and the third signal line segment, the distance between adjacent second signal line segments can be further increased, thereby further reducing the surface roughness of the surface of the first insulating layer away from the substrate, further reducing the depth of the depression and / or increasing the width of the depression. Thus, during the manufacturing process of the display panel, when etching the second metal layer to form a plurality of first traces, the etching can be complete at the depression (the residual metal is etched completely), thereby avoiding a short circuit between adjacent first traces.

[0056] Refer to Figures 3 to 11 . Figure 3 It is an overall schematic diagram of a display panel provided by an embodiment of the present application. Figure 4 It is a first partial top view schematic diagram of the wiring of a display panel provided by an embodiment of the present application. Figure 5 It is a first partial cross-sectional schematic diagram of the wiring of a display panel provided by an embodiment of the present application. Figure 6 It is a first partial cross-sectional schematic diagram of the film layer structure of a display panel provided by an embodiment of the present application. Figure 7 It is a first partial top view schematic diagram of the first signal line of a display panel provided by an embodiment of the present application. Figure 6 It is Figure 5 a schematic diagram of an example of the film layer structure of a more specific array substrate in Figure 7 only schematically shows Figure 5 the first signal line in Figure 5 It is Figure 4 a cross-sectional schematic diagram at the first virtual coil 102 in

[0057] Figure 8 It is a second partial top view schematic diagram of the wiring of a display panel provided by an embodiment of the present application. Figure 9 It is a second partial cross-sectional schematic diagram of the wiring of a display panel provided by an embodiment of the present application. Figure 10 It is a second partial cross-sectional schematic diagram of the film layer structure of a display panel provided by an embodiment of the present application. Figure 10 It is Figure 9 a schematic diagram of an example of the film layer structure of a more specific array substrate in Figure 9 It is Figure 8 a cross-sectional schematic diagram at the first virtual coil 102 in

[0058] Figure 11 It is a third partial top view schematic diagram of the wiring of a display panel provided by an embodiment of the present application.

[0059] The present application provides a display panel 100. The display panel 100 includes a display area AA and a non-display area BB surrounding the display area AA. The non-display area BB includes a fan-out area BB1. The display panel 100 includes a substrate 11. The display panel 100 includes a plurality of first traces 60 arranged at intervals, a plurality of first signal lines 70 arranged at intervals, and a first insulating layer 32 disposed in the fan-out area BB1. The plurality of first traces 60 arranged at intervals are disposed on one side of the substrate 11. The first trace 60 includes a first trace segment 61 extending along a first direction Y, and a second trace segment 62 connecting the first trace segment 61 and extending along a second direction X. The first direction Y intersects with the second direction X. The plurality of first signal lines 70 arranged at intervals are disposed on one side of the substrate 11 and are located on one side of the plurality of first traces 60 in a direction perpendicular to the plane where the substrate 11 is located. The first signal line 70 includes a first signal segment 71 extending along a third direction W1, a third signal segment 73 extending along a fourth direction W2, and a second signal segment 72 connected between the first signal segment 71 and the third signal segment 73. The third direction W1 intersects with both the first direction Y and the second direction X. The fourth direction W2 intersects with both the first direction Y and the second direction X. The first insulating layer 32 is disposed between the plurality of first traces 60 and the plurality of first signal lines 70. Wherein, at least a part of the positive projection of the second signal segment 72 on the substrate 11 overlaps with the positive projection of the first trace 60 on the substrate 11. The distance between two adjacent second signal segments 72 is greater than the distance between two adjacent first signal segments 71 and the distance between two adjacent third signal segments 73.

[0060] Exemplarily, as Figure 3 shown, the display panel 100 includes a display area AA and a non-display area BB surrounding the display area AA. The wiring in the display panel 100 of the present application includes a plurality of first traces 60 arranged at intervals and a plurality of first signal lines 70 arranged at intervals. The wiring is a signal line or a trace, etc.

[0061] It should be noted that, in some embodiments, the wiring of the present application can be disposed in the non-display area BB1 or in the display area AA. The wiring of the present application can be disposed in the fan-out area BB1 or in an area other than the fan-out area BB1.

[0062] Exemplarily, as Figure 3 shown, the display panel 100 further includes a pad area 101. The pad area 101 can be electrically connected to or provided with a driving chip. The wiring can be electrically connected to the pad area 101, but is not limited thereto.

[0063] Exemplarily, as Figures 4 to 6 shown, the first trace 60 is formed by patterning a second metal layer 33, and the first signal line 70 is formed by patterning a first metal layer 31. A first insulating layer 32 is disposed between the first metal layer 31 and the second metal layer 33.

[0064] Exemplarily, as Figures 4 to 10 shown, in some embodiments, the first trace 60 is located on the side of the first signal line 70 away from the substrate.

[0065] Exemplarily, as Figure 11 shown, in some other embodiments, the first trace 60 is located on the side of the first signal line 70 close to the substrate.

[0066] Exemplarily, as Figure 4 shown, the orthogonal projection of at least a part of the second signal line segment 72 on the substrate 11 overlaps with the orthogonal projection of the first trace 60 on the substrate 11, that is, at least a part of the second signal line segment 72 is at least partially overlapped with at least a part of the first trace 60 in the direction perpendicular to the substrate 11.

[0067] Exemplarily, as Figure 4 shown, the third direction W1 is parallel to the fourth direction W2. In some embodiments, the third direction W1 and the fourth direction W2 may also intersect.

[0068] Exemplarily, comparing Figure 2 and Figure 5 , or comparing Figure 2 and Figure 9 , in the embodiments of the present application, when etching the second metal layer 33 to form a plurality of first traces 60, the etching can be completed at the recess 102a (the residual metal 33c is completely etched), so as to avoid short circuit between adjacent first traces 60.

[0069] In the embodiments of the present application, the distance between two adjacent second signal line segments 72 is greater than the distance between two adjacent first signal line segments 71 and the distance between two adjacent third signal line segments 73, so that the surface roughness of the surface of the first insulating layer 32 away from the substrate 11 can be reduced, the depth of the recess 102a is reduced and / or the width of the recess 102a is increased. By setting the first signal line 70 to include a first signal line segment 71 extending along the third direction W1, a third signal line segment 73 extending along the fourth direction W2, and a second signal line segment 72 connected between the first signal line segment 71 and the third signal line segment 73, the distance between two adjacent second signal line segments 72 can be further increased, so as to further reduce the surface roughness of the surface of the first insulating layer 32 away from the substrate 11, further reduce the depth of the recess 102a and / or increase the width of the recess 102a. Thus, in the manufacturing process of the display panel, when etching the second metal layer 33 to form a plurality of first traces 60, the etching can be completed at the recess 102a (the residual metal 33c is completely etched), so as to avoid short circuit between adjacent first traces 60.

[0070] In some embodiments, as Figure 7As shown, the distance between two adjacent first signal line segments 71 is a first distance d1, the distance between two adjacent second signal line segments 72 is a second distance d2, and the distance between two adjacent third signal line segments 73 is a third distance d3. The second distance d2 is greater than the first distance d1 and the third distance d3, and the second distance d2 is greater than or equal to 1.1 micrometers.

[0071] Exemplarily, as Figure 7 shown, through verification by the inventors, it is found that in order to achieve a narrow bezel design, it is necessary to reduce the first distance d1 and the third distance d3. When the second distance d2 is set to be greater than the first distance d1 and the third distance d3, and the second distance d2 is greater than or equal to 1.1 micrometers, when etching the second metal layer 33 to form multiple first traces 60, the etching can be completed at the recess 102a (the residual metal 33c is completely etched), thereby avoiding short circuits between adjacent first traces 60.

[0072] Exemplarily, the first distance d1, the second distance d2, and the third distance d3 are all distances in a direction parallel to the plane where the substrate 11 is located.

[0073] It should be noted that, as Figures 8 to 10 shown, when multiple first signal lines 70 are formed by patterning metal layers of different layers, for example, multiple first signal lines 70 include first sub-lines 70a and second sub-lines 70b arranged alternately at intervals. The first sub-lines 70a are formed by patterning the first metal layer 31, and the second sub-lines 70b are formed by patterning the third metal layer 34. The first metal layer 31 and the third metal layer 34 are located in different film layers. At this time, the first distance d1 is the distance between the positive projections of two adjacent first signal line segments 71 on the substrate 11, the second distance d2 is the distance between the positive projections of two adjacent second signal line segments 72 on the substrate 11, and the third distance d3 is the distance between the positive projections of two adjacent third signal line segments 73 on the substrate 11.

[0074] Exemplarily, in some embodiments, the inventors have found that when the difference between the second distance d2 and the first distance d1 is greater than or equal to 0.5 micrometers, and the difference between the second distance d2 and the third distance is greater than or equal to 0.5 micrometers, when etching the second metal layer 33 to form multiple first traces 60, the etching can be completed at the recess 102a (the residual metal 33c is completely etched), thereby avoiding short circuits between adjacent first traces 60.

[0075] Exemplarily, in some embodiments, the width of the second signal line segment 72 is less than the width of the first signal line segment 71 and less than the width of the third signal line segment 73, which can help increase the second distance d2.

[0076] In some embodiments, as Figure 7As shown, at least part of the first signal line segment 71 and at least part of the third signal line segment 73 are straight; and / or, at least part of the second signal line segment 72 is zigzag, arc-shaped or curved.

[0077] Exemplarily, as Figure 4 , Figure 7 , Figure 8 and Figure 11 shown, the first signal line segment 71 and the third signal line segment 73 are straight, which can reduce the first distance d1 and the third distance d3, contributing to achieving a narrower border. The second signal line segment 72 being zigzag, arc-shaped or curved can increase the second distance d2, which can better avoid or improve short circuits caused by metal residues.

[0078] Exemplarily, Figure 7 illustrates that at least part of the second signal line segment 72 is zigzag.

[0079] In some embodiments, as Figure 7 shown, the second signal line segment 72 includes a first sub-signal line segment 731 extending along a fifth direction u, and a second sub-signal line segment 732 connected to the first sub-signal line segment 731 and extending along a sixth direction v. The fifth direction u intersects both the third direction W1 and the fourth direction W2, and the sixth direction v intersects both the third direction W1 and the fourth direction W2.

[0080] Exemplarily, the extending direction of the first sub-signal line segment 731 is different from both the extending direction of the first signal line segment 71 and the extending direction of the third signal line segment 73, and the extending direction of the second sub-signal line segment 732 is different from both the extending direction of the first signal line segment 71 and the extending direction of the third signal line segment 73, which can better increase the second distance d2.

[0081] In some embodiments, as Figures 4 to 7 shown, one of the fifth direction u and the sixth direction v is parallel to the first direction Y, and the other of the fifth direction u and the sixth direction v is parallel to the second direction X.

[0082] Exemplarily, as Figures 4 to 7As shown, due to the etching process, the width of the second signal line segment 72 is likely to become wider or narrower at the recess 102a. When the fifth direction u is parallel to the first direction Y and the sixth direction v is parallel to the second direction X, or the sixth direction v is parallel to the first direction Y and the fifth direction u is parallel to the second direction X, in the top view structure, the overlapping area where the second signal line segment 72 obliquely crosses and overlaps with the extending direction of the recess 102a can be reduced, the width uniformity of the first sub-signal line segment 731 and the width uniformity of the second sub-signal line segment 732 can be improved, thereby better avoiding the risk of short circuit. At the same time, the first sub-signal line segment 731 and the second sub-signal line segment 732 can be regularly arranged, which helps to avoid the short circuit problem with a smaller second distance d2 and is conducive to the narrow border design.

[0083] In some embodiments, as Figures 4 to 7 shown, the first signal line segment 71, the first sub-signal line segment 731, the second sub-signal line segment 732, and the third signal line segment 73 are connected in sequence, and the sixth direction v is parallel to the first direction Y; the orthographic projection of the second sub-signal line segment 732 on the substrate 11 overlaps with the orthographic projection of the first routing segment 61 on the substrate 11.

[0084] Exemplarily, as Figures 4 to 7 shown, the sixth direction v is parallel to the first direction Y, and the orthographic projection of the second sub-signal line segment 732 on the substrate 11 overlaps with the orthographic projection of the first routing segment 61 on the substrate 11, which can prevent the second sub-signal line segment 732 from being completely located in the recess 102a, thereby improving the width uniformity between different second sub-signal line segments 732.

[0085] In some embodiments, as Figure 7 shown, the first signal line segment 71 and the third signal line segment 73 connected through the second signal line segment 72 are on the same straight line.

[0086] Exemplarily, comparing Figure 1 and Figure 4 、or comparing Figure 1 and Figure 7 shown, the first signal line segment 71 and the third signal line segment 73 connected through the second signal line segment 72 are on the same straight line, without changing the overall extending direction of the first signal line 70, which helps to achieve a narrower border and enables both ends of the third signal line segment 73 to be well connected to the preset target electrodes or wiring parts.

[0087] In some embodiments, as Figure 4 and Figure 5 shown, and in combination with Figure 6As shown, the display panel 100 includes a plurality of thin film transistors T1. The display panel 100 further includes a first metal layer 31, a first insulating layer 32, and a second metal layer 33. The first metal layer 31 is disposed on one side of the substrate 11. The first metal layer 31 includes the gate 121 of the thin film transistor T1 and at least part of the first signal line 70. The first insulating layer 32 is disposed on the side of the first metal layer 31 away from the substrate 11, and the first insulating layer 32 is an inorganic material. The second metal layer 33 is disposed on the side of the first insulating layer 32 away from the substrate 11. The second metal layer 33 includes the source electrode 181 and the drain electrode 182 of the thin film transistor T1 and at least part of the first trace 60.

[0088] Exemplarily, the first insulating layer 32 is an inorganic material. The thickness of the first insulating layer 32 is generally smaller than the thickness of the first metal layer 31, such that a relatively deep recess 102a is formed on the surface plane of the first insulating layer 32 away from the substrate 11. Therefore, the solution of the embodiment of the present application needs to be adopted to solve or improve the short - circuit problem.

[0089] Exemplarily, in some embodiments, such as Figure 4 and Figure 5 shown, and in combination with Figure 6 shown, in the direction perpendicular to the plane of the substrate 11, the first metal layer 31, the first insulating layer 32, and the second metal layer 33 are stacked in sequence. The first metal layer 31 includes the gate 121 of the thin film transistor T1 and at least part of the first signal line 70, that is, the gate 121 of the thin film transistor T1 and at least part of the first signal line 70 are made of the same process and the same material, which can simplify the manufacturing process.

[0090] Exemplarily, in some embodiments, such as Figure 4 and Figure 5 shown, and in combination with Figure 6 shown, the second metal layer 33 includes the source electrode 181 and the drain electrode 182 of the thin film transistor T1 and at least part of the first trace 60, that is, the source electrode 181 and the drain electrode 182 of the thin film transistor T1 and at least part of the first trace 60 are made of the same process and the same material, which can simplify the manufacturing process.

[0091] Exemplarily, in some embodiments, such as Figure 4 and Figure 5 shown, and in combination with Figure 6 shown, Figure 6 illustrates a film layer structure of a display panel by way of example. In Figure 6Among them, the display panel includes a substrate 11, a first conductive layer 12, a gate insulating layer 13, a semiconductor layer 14, a second interlayer insulating layer 17, and a third conductive layer 18 which are stacked. The first conductive layer 12 is a first metal layer 31, and the first conductive layer 12 includes a gate 121 of a thin film transistor T1 and a first signal line 70. The semiconductor layer 14 includes an active portion 141 of the thin film transistor T1. The second interlayer insulating layer 17 is a first insulating layer 32. The third conductive layer 18 is a second metal layer 33, and the third conductive layer 18 includes a source 181 and a drain 182 of the thin film transistor T1, and a first trace 60. It should be noted that the film layer structure of the display panel is not limited to Figure 6 the example shown. For example, the film layer positions of the first conductive layer 12 and the semiconductor layer 14 are interchanged.

[0092] In some embodiments, such as Figure 8 and Figure 9 shown, and in combination with Figure 10 shown, the display panel 100 further includes a second insulating layer 35 and a third metal layer 34. The second insulating layer 35 is disposed between the first metal layer 31 and the first insulating layer 32, and the second insulating layer 35 is an inorganic material; the third metal layer 34 is disposed between the second insulating layer 35 and the first insulating layer 32, and the third metal layer 34 includes at least a part of the first signal line 70.

[0093] Exemplarily, in some embodiments, such as Figure 8 and Figure 9 shown, and in combination with Figure 10 shown, in the direction perpendicular to the plane of the substrate 11, the first metal layer 31, the second insulating layer 35, the third metal layer 34, the first insulating layer 32, and the second metal layer 33 are sequentially stacked, and the third metal layer 34 includes at least a part of the first signal line 70, that is, at least a part of the first signal line 70 is patterned by the third metal layer 34.

[0094] Exemplarily, in some embodiments, such as Figure 8 and Figure 9 shown, and in combination with Figure 10 shown, multiple first signal lines 70 include first sub-lines 70a and second sub-lines 70b which are alternately and spaced apart. The first sub-lines 70a are patterned by the first metal layer 31, the second sub-lines 70b are patterned by the third metal layer 34, and the first metal layer 31 and the third metal layer 34 are located in different film layers.

[0095] Exemplarily, in some embodiments, such as Figure 8 and Figure 9 shown, and in combination with Figure 10 shown, Figure 10 illustrates another film layer structure of the display panel by way of example. In Figure 10Among them, the display panel includes a substrate 11, a first conductive layer 12, a gate insulating layer 13, a semiconductor layer 14, a first interlayer insulating layer 15, a second conductive layer 16, a second interlayer insulating layer 17, and a third conductive layer 18 which are stacked. The first conductive layer 12 is a first metal layer 31, and the first conductive layer 12 includes a gate 121 of the thin film transistor T1 and at least part of the first signal line 70 (first sub-line 70a). The semiconductor layer 14 includes an active portion 141 of the thin film transistor T1. The first interlayer insulating layer 15 is a second insulating layer 35. The second conductive layer 16 is a third metal layer 34, and the second conductive layer 16 includes at least part of the first signal line 70 (second sub-line 70b). The second interlayer insulating layer 17 is a first insulating layer 32. The third conductive layer 18 is a second metal layer 33, and the third conductive layer 18 includes a source 181 and a drain 182 of the thin film transistor T1, and at least part of the first trace 60. It should be noted that the film layer structure of the display panel is not limited to Figure 10 the example shown. For example, the first conductive layer 12 is a light-shielding metal layer, the first conductive layer 12 includes a plurality of light-shielding electrodes and at least part of the first signal line 70, the second conductive layer 16 is a gate metal layer, and the second conductive layer 16 includes a gate of the thin film transistor and at least part of the first signal line 70.

[0096] It should be noted that, in some embodiments, in Figure 10 the example, the first signal line 70 may also be entirely formed by patterning the first conductive layer 12. In some embodiments, in Figure 10 the example, the first signal line 70 may also be entirely formed by patterning the second conductive layer 16.

[0097] It should be noted that the thin film transistor T1 may be located in the display area AA. For example, the thin film transistor T1 constitutes a pixel driving circuit. The thin film transistor T1 may be located in the non-display area BB. For example, the thin film transistor T1 constitutes a gate driving circuit.

[0098] It should be noted that, as Figures 4 to 6 shown, or as Figures 8 to 10 shown, in some embodiments, it is schematically shown that the first trace 60 is located on the side of the first signal line 70 away from the substrate 11.

[0099] It should be noted that, as Figure 11 shown, in some other embodiments, the first trace 60 is located on the side of the first signal line 70 close to the substrate 11. In Figure 11In the example, the first signal line 70 may also be configured with any of the above structures. At this time, the second distance d2 is relatively large. During the manufacturing process of the display panel, when etching the metal layer, there is more etching solution between two adjacent second signal segments 72, making it easy to completely avoid residue during etching, or even if there is a small amount of residual metal, it cannot connect two adjacent second signal segments 72, thus preventing a short circuit between two adjacent first signal lines 70.

[0100] Please refer to Figure 12 , Figure 12 which is a schematic diagram of a display device provided by some embodiments of the present application.

[0101] In a second aspect, based on the same inventive concept, the present application also provides a display device 200. The display device 200 includes the display panel 100 of any one of the above, or the display device 200 includes the display panel 100 combined with several of the above features.

[0102] Exemplarily, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. The same parts can be understood by referring to the explanation of the display panel 100 above, and will not be elaborated below.

[0103] Exemplarily, the display device 200 provided by the embodiments of the present application can be Figure 12 the mobile phone shown in the figure, or any electronic product with a display function, including but not limited to the following categories: televisions, laptop computers, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, industrial control devices, medical display screens, touch interaction terminals, etc. The embodiments of the present application do not make special limitations on this.

[0104] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as these combinations of technical features do not conflict, they should be considered as within the scope described in this specification.

[0105] The above embodiments only represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the inventive concept of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A display panel, characterized in that, it includes a display area and a non-display area surrounding the display area, the non-display area includes a fan-out area, the display panel includes a substrate, and disposed in the fan-out area are: Multiple first traces arranged at intervals, disposed on one side of the substrate, the first traces include first trace segments extending in a first direction, and second trace segments connecting the first trace segments and extending in a second direction, the first direction intersects with the second direction; Multiple first signal lines arranged at intervals, disposed on one side of the substrate, and located on one side of the multiple first traces in a direction perpendicular to the plane where the substrate is located, the first signal lines include first signal line segments extending in a third direction and third signal line segments extending in a fourth direction, and second signal line segments connecting between the first signal line segments and the third signal line segments, the third direction intersects with both the first direction and the second direction, the fourth direction intersects with both the first direction and the second direction; A first insulating layer, disposed between the multiple first traces and the multiple first signal lines; wherein, at least a part of the positive projection of the second signal line segments on the substrate overlaps with the positive projection of the first traces on the substrate; The distance between two adjacent second signal line segments is greater than the distance between two adjacent first signal line segments and the distance between two adjacent third signal line segments.

2. The display panel according to claim 1, characterized in that, The distance between two adjacent first signal line segments is a first distance, the distance between two adjacent second signal line segments is a second distance, the distance between two adjacent third signal line segments is a third distance, the second distance is greater than the first distance and the third distance, and the second distance is greater than or equal to 1.1 micrometers.

3. The display panel according to claim 1, characterized in that, At least a part of the first signal line segments and at least a part of the third signal line segments are linear; and / or, At least a part of the second signal line segments are zigzag, arc-shaped or curved.

4. The display panel according to claim 1, characterized in that, The second signal line segments include first sub-signal line segments extending in a fifth direction, and second sub-signal line segments connected to the first sub-signal line segments and extending in a sixth direction, the fifth direction intersects with both the third direction and the fourth direction, the sixth direction intersects with both the third direction and the fourth direction.

5. The display panel according to claim 4, characterized in that, One of the fifth direction and the sixth direction is parallel to the first direction, and the other of the fifth direction and the sixth direction is parallel to the second direction.

6. The display panel according to claim 5, characterized in that, The first signal line segments, the first sub-signal line segments, the second sub-signal line segments and the third signal line segments are connected in sequence, and the sixth direction is parallel to the first direction; The positive projection of the second sub-signal line segments on the substrate overlaps with the positive projection of the first trace segments on the substrate.

7. The display panel according to claim 1, wherein, the first signal line segment and the third signal line segment connected through the second signal line segment are located on the same straight line.

8. The display panel according to claim 1, wherein, it includes a plurality of thin film transistors, and the display panel further includes: a first metal layer disposed on one side of the substrate, the first metal layer including the gate of the thin film transistor and at least part of the first signal line; the first insulating layer disposed on the side of the first metal layer away from the substrate, the first insulating layer being an inorganic material; a second metal layer disposed on the side of the first insulating layer away from the substrate, the second metal layer including the source and drain of the thin film transistor and at least part of the first trace.

9. The display panel according to claim 8, wherein, it further includes: a second insulating layer disposed between the first metal layer and the first insulating layer, the second insulating layer being an inorganic material; a third metal layer disposed between the second insulating layer and the first insulating layer, the third metal layer including at least part of the first signal line.

10. A display device, wherein, it includes the display panel according to any one of claims 1 to 9.

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