Display device

Abstract

A display device includes: a light emitting element including an anode and a cathode; a first transistor connected to an anode and a power supply line, and a voltage through a first node being switchable; a second transistor connected to a data line and a second node and switchable by a write scan signal; a capacitor connected to the first node and the second node; and an initialization transistor connected to an anode and an initialization line configured to receive an initialization voltage, and switchable by biasing a scan signal to which a write scan signal is applied at a first frequency or a second frequency lower than the first frequency. When converting from the first frequency to the second frequency, the level of the initialization voltage may be gradually reduced in the k-th frame of the second frequency.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2023-0165633, filed on November 24, 2023, and all benefits derived therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure herein relates to a display device. Background Art

[0003] Generally, electronic devices that provide images to users, such as smart phones, digital cameras, laptop computers, navigation systems, and smart TVs, include a display device for displaying images. The display device generates images and provides the generated images to users through a display screen.

[0004] The display device includes a plurality of pixels for generating an image and a driver for driving the pixels. Each of the pixels includes a light emitting element, a plurality of transistors connected to the light emitting element, and at least one capacitor connected to the transistor. The pixels are capable of generating various images and are driven by various frequencies to generate various images.

[0005] When the driving frequency of the pixel is converted from high frequency to low frequency, the hysteresis characteristics of the pixel change. For example, each of the pixels includes a driving transistor for driving a light emitting element, and when the driving frequency is converted from high frequency to low frequency, the hysteresis characteristics of the driving transistor change.

[0006] The above-mentioned change of hysteresis characteristic may affect brightness. In the initial frame of low frequency, the change of hysteresis characteristic is large, and in the subsequent frames, the change of hysteresis characteristic may gradually decrease. In the initial frame with large change of hysteresis characteristic, the brightness of the pixel driven by low frequency may be higher than the brightness of the pixel driven by high frequency.

[0007] Such a brightness difference may be visually recognized by a user, and a phenomenon in which the brightness difference is visually recognized by the user may be defined as a flicker phenomenon. Development of technology for reducing the flicker phenomenon is desirable. Summary of the invention

[0008] The present disclosure provides a display device that can reduce a flicker phenomenon when a driving frequency of a pixel is converted from a high frequency to a low frequency.

[0009] An embodiment of the present invention provides a display device, comprising: a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line, and switchable by a voltage of a first node; a second transistor connected to a data line and a second node, and switchable by a write scan signal; a capacitor connected to the first node and the second node; an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage, and switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency or a second frequency lower than the first frequency. When converting from the first frequency to the second frequency, in the kth frame of the second frequency, the level of the initialization voltage can be gradually reduced.

[0010] In an embodiment of the present invention, a display device includes: a light emitting element including an anode and a cathode; a first transistor connected to the anode and a power line and switchable by a voltage of a first node; a second transistor connected to a data line and a second node and switchable by a write scan signal; a capacitor connected to the first node and the second node; an initialization transistor connected to the anode and an initialization line configured to receive an initialization voltage and switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency or a second frequency lower than the first frequency. When converting from the first frequency to the second frequency, in each of the kth frame of the second frequency and the k+1th frame of the second frequency, the level of the initialization voltage gradually changes, and the amount of change in the initialization voltage of the kth frame is greater than the amount of change in the initialization voltage of the k+1th frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the present invention and together with the description serve to explain the principles of the present invention. In the drawings:

[0012] Figure 1 is a perspective view of a display device according to an embodiment of the present invention;

[0013] Figure 2 It is shown as an example Figure 1 A view of a cross section of the display device shown in ;

[0014] Figure 3 It is shown as an example Figure 2 A view of a cross section of a display panel shown in ;

[0015] Figure 4 yes Figure 1 A block diagram of a display device shown in ;

[0016] Figure 5 It is shown Figure 4A view of an equivalent circuit of one pixel shown in ;

[0017] Figure 6 Is used to drive Figure 5 A timing diagram of a signal of a pixel shown in ;

[0018] Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A and Fig. 10B It is a timing diagram of scanning signals and transmitting signals according to various frequencies;

[0019] Fig.11 is a view showing a graph of changes in brightness of a pixel when a driving frequency of the pixel is switched from a first frequency to a second frequency;

[0020] Fig.12 yes Fig.11 An enlarged view of the area AA shown in;

[0021] Fig.13 is a view showing a level change of a second initialization voltage according to an embodiment of the present invention;

[0022] FIG. 14A to FIG. 14C is a view showing various lowering modes of a second initialization voltage according to an embodiment of the present invention;

[0023] Fig.15A and Fig. 15B is a view showing the timing of a bias scan signal according to another embodiment of the present invention; and

[0024] Fig.16A and Fig. 16B is a view showing the timing of a bias scan signal according to still another embodiment of the present invention. DETAILED DESCRIPTION

[0025] In the present disclosure, when an element (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another element, this means that the element may be directly on, directly connected to or coupled to the other element, or a third element may be disposed between the element and the other element.

[0026] The same reference numerals refer to the same elements. In addition, in the drawings, for the effective description of the technical contents, the thickness, ratio and size of the elements are exaggerated.

[0027] The term "and / or" includes any and all combinations of one or more of the associated elements that may be defined.

[0028] It will be understood that although the terms "first", "second", etc. may be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and a second element may also be referred to as a first element in a similar manner without departing from the scope of the rights of the present invention. Terms in the singular may include plural forms unless the context clearly indicates otherwise.

[0029] In addition, terms such as "below", "lower", "above", and "upper" are used to describe the relationship of components shown in the drawings. These terms are used as relative concepts and are described with reference to directions indicated in the drawings.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present invention belongs. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the prior art, and unless explicitly defined in this article, these terms are not interpreted in an overly idealized or overly formal sense.

[0031] It should be understood that the terms “including” or “having” are intended to specify the presence of the features, integers, steps, operations, elements, parts, or combinations thereof stated in the present disclosure, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, or combinations thereof.

[0032] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the present invention.

[0034] refer to Figure 1 The display device DD according to the embodiment of the present invention may have long sides extending in the first direction DR1, and may have short sides extending in the second direction DR2 crossing the first direction DR1. The corners of the display device DD may have an arc shape. Figure 1 The shape of the display device DD shown in FIG. 1 is exemplarily shown, and the shape of the display device DD is not limited to Figure 1 The shapes shown in .

[0035] Hereinafter, a direction substantially perpendicularly intersecting a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3.

[0036] The image IM generated in the display device DD may be provided to the user through the upper surface of the display device DD viewed in the third direction DR3. The upper surface of the display device DD may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and may define an edge of the display device DD to be printed in a predetermined color.

[0037] Illustratively, the display device DD is shown as a mobile phone, but is not limited thereto, and the display device DD can be used for various electronic devices. For example, the display device DD can be used for large electronic devices such as televisions, monitors, or external billboards. In addition, the display device DD can be used for small and medium-sized electronic devices such as personal computers (e.g., laptop computers or tablet computers), car navigation systems, game consoles, or cameras.

[0038] Figure 2 It is shown as an example Figure 1 A view of a cross section of a display device is shown in FIG.

[0039] Illustratively, Figure 2 A cross section of the display device DD viewed in a first direction DR1 is shown.

[0040] refer to Figure 2 , the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0041] The display panel DP according to an embodiment of the present invention may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots and / or quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0042] The input sensing unit ISP may be provided on the display panel DP. The input sensing unit ISP may include a plurality of sensors (not shown) for sensing external input in a capacitive manner. When manufacturing the display device DD, the input sensing unit ISP may be directly manufactured on the display panel DP. However, embodiments of the present invention are not limited thereto, and the input sensing unit ISP may be manufactured as a panel separated from the display panel DP and may be attached to the display panel DP by an adhesive layer.

[0043] The anti-reflection layer RPL may be disposed on the input sensing unit ISP. When manufacturing the display device DD, the anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP. However, the embodiments of the present invention are not limited thereto, and the anti-reflection layer RPL may be manufactured as a separate panel and may be attached to the input sensing unit ISP through an adhesive layer.

[0044] The anti-reflection layer RPL may be defined as an anti-external light reflection film. The anti-reflection layer RPL may reduce the reflectivity of external light incident from above the display device DD toward the display panel DP. Due to the anti-reflection layer RPL, the external light may not be visible to the user.

[0045] When external light traveling toward the display panel DP is reflected from the display panel DP and returned to an external user like a mirror, the user may visually recognize the external light. To prevent the above phenomenon, illustratively, the anti-reflection layer RPL may include a plurality of color filters for displaying the same color as the color of the pixels of the display panel DP.

[0046] The color filter may filter the external light into the same color as the color of the pixel. In this case, the external light may not be visually recognized by the user. However, the embodiments of the present invention are not limited thereto, and the anti-reflection layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of the external light.

[0047] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0048] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect a lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate ("PET").

[0049] The first adhesive layer AL1 is disposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF can be combined with each other through the first adhesive layer AL1. The second adhesive layer AL2 is disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL can be combined with each other through the second adhesive layer AL2.

[0050] Figure 3 It is shown as an example Figure 2 A view of a cross section of a display panel is shown in FIG.

[0051] Illustratively, Figure 3 A cross section of the display panel DP viewed in the first direction DR1 is shown.

[0052] refer to Figure 3 The display panel DP includes a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0053] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide ("PI"). The display element layer DP-OLED may be disposed on the display area DA.

[0054] A plurality of pixels may be provided in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the pixels may include a transistor provided in the circuit element layer DP-CL and a light emitting element provided in the display element layer DP-OLED and connected to the transistor.

[0055] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and foreign matter.

[0056] Figure 4 yes Figure 1 Block diagram of the display device shown in .

[0057] refer to Figure 4 , the display device DD may include a display panel DP, a driving controller 100, a data driving circuit 200, a scan driving circuit SDC, a light emitting driving circuit EDC, and a voltage generator 300. The driving controller 100 may be defined as a timing controller.

[0058] The display panel DP may include a plurality of scan lines GIL1, GIL2, ... GILn, GCL1, GCL2, ... GCLn, GWL1, GWL2, ... GWLn and EBL1, EBL2, ... EBLn, a plurality of emission lines EML1, EML2, ... EMLn, a plurality of data lines DL1, DL2, ... DLm, and a plurality of pixels PX. n and m may be natural numbers greater than zero.

[0059] A plane area of ​​the display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The pixels PX may be disposed in the display area DA.

[0060] The pixels PX may be electrically connected to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn and EBL1 to EBLn, the emission lines EML1 to EMLn and the data lines DL1 to DLm, respectively. Each of the pixels PX may be electrically connected to four corresponding scan lines, one corresponding data line and one corresponding emission line.

[0061] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn may include a plurality of initialization scan lines GIL1 to GILn, a plurality of compensation scan lines GCL1 to GCLn, a plurality of write scan lines GWL1 to GWLn, and a plurality of bias scan lines EBL1 to EBLn.

[0062] Each of the pixels PX may be connected to a corresponding one of the initialization scan lines GIL1 to GILn, a corresponding one of the compensation scan lines GCL1 to GCLn, a corresponding one of the write scan lines GWL1 to GWLn, and a corresponding one of the bias scan lines EBL1 to EBLn.

[0063] The scan driving circuit SDC may be disposed at a first side of the display panel DP. The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn may extend from the scan driving circuit SDC in the second direction DR2.

[0064] The light emitting driving circuit EDC may be disposed at a second side of the display panel DP opposite to the first side of the display panel DP. The light emitting lines EML1 to EMLn may extend from the light emitting driving circuit EDC in a direction opposite to the second direction DR2.

[0065] exist Figure 4 In the example shown in , the scanning driving circuit SDC and the light emitting driving circuit EDC are arranged facing each other, wherein the pixel PX is interposed between the scanning driving circuit SDC and the light emitting driving circuit EDC, but the embodiments of the present invention are not limited thereto. For example, the scanning driving circuit SDC and the light emitting driving circuit EDC may be arranged adjacent to the first side or the second side of the display panel DP. In another embodiment, the scanning driving circuit SDC and the light emitting driving circuit EDC may be formed as one circuit.

[0066] The scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn and the emission lines EML1 to EMLn may be arranged to be spaced apart from each other in the first direction DR1. The data lines DL1 to DLm may extend from the data driving circuit 200 in a direction opposite to the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2.

[0067] The driving controller 100 may receive the image signal RGB and the control signal CTRL. The driving controller 100 may generate the image data signal DS obtained by converting the data format of the image signal RGB to meet the interface specification with the data driving circuit 200. The driving controller 100 may output the scanning control signal SCS, the data control signal DCS, and the emission control signal ECS in response to the control signal CTRL.

[0068] The data driving circuit 200 may receive a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 may convert the image data signal DS into a data signal and may output the data signal. The data signal may be defined as an analog data voltage corresponding to the grayscale of the image data signal DS. The data signal may be applied to the pixel PX through the data lines DL1 to DLm.

[0069] The voltage generator 300 may generate voltages for operation of the display panel DP. The voltage generator 300 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, a second initialization voltage AINT, and a reference voltage VR. The first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT, the second initialization voltage AINT, and the reference voltage VR may be applied to the pixel PX.

[0070] In an embodiment of the present invention, the level of the second initialization voltage AINT may be changed depending on the driving frequency of the pixel PX. Hereinafter, the above operation will be described in detail. Although not shown, the level of the second initialization voltage AINT may be changed by various control circuits. For example, depending on the control of a system board (e.g., a graphics processor or an application processor) or a drive controller 100, the level of the second initialization voltage AINT may be changed.

[0071] The scan driving circuit SDC may receive a scan control signal SCS from the driving controller 100. The scan driving circuit SDC may output a scan signal to the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn in response to the scan control signal SCS. The scan signal may be applied to the pixels PX through the scan lines GIL1 to GILn, GCL1 to GCLn, GWL1 to GWLn, and EBL1 to EBLn.

[0072] The light emitting driving circuit EDC may receive a light emitting control signal ECS from the driving controller 100. In response to the light emitting control signal ECS, the light emitting driving circuit EDC may output a light emitting signal to the light emitting lines EML1 to EMLn. The light emitting signal may be applied to the pixel PX through the light emitting lines EML1 to EMLn.

[0073] The pixel PX may be supplied with a data voltage in response to the scan signal, and the pixel PX may display an image by emitting light having a brightness corresponding to the data voltage in response to the light emission signal.

[0074] Figure 5 It is shown Figure 4 A view of the equivalent circuit of one pixel is shown in FIG. Figure 6 Is used to drive Figure 5 0 is a timing diagram of the signals of the pixel shown in .

[0075] refer to Figure 5 , the pixel PXij may include a pixel circuit PC and a light emitting element ED connected to the pixel circuit PC. i and j are natural numbers greater than zero. The pixel circuit PC may drive the light emitting element ED. The light emitting element ED may be defined as an organic light emitting element. The light emitting element ED may include an anode AE ​​and a cathode CE.

[0076] The pixel circuit PC may include a plurality of transistors T1 to T10 and a plurality of capacitors C1 and C2. The transistors T1 to T10 and the capacitors C1 and C2 may control the amount of current flowing in the light emitting element ED. The light emitting element ED may generate light with a predetermined brightness according to the amount of current provided.

[0077] Pixel PXij can be connected to the i-th data line DLi, the j-th write scan line GWLj, the j-th compensation scan line GCLj, the j-th initialization scan line GILj, the j-th bias scan line EBLj, the j-th emission line EMLj, the first initialization line VIL1, the second initialization line VIL2, the reference line VL, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0078] The jth write scan line GWLj may receive the jth write scan signal GWj, and the jth compensation scan line GCLj may receive the jth compensation scan signal GCj. The jth initialization scan line GILj may receive the jth initialization scan signal GIj, and the jth bias scan line EBLj may receive the jth bias scan signal EBj. The jth emission line EMLj may receive the jth emission signal EMj.

[0079] The first initialization line VIL1 may receive a first initialization voltage VINT, and the second initialization line VIL2 may receive a second initialization voltage AINT. The bias line VBL may receive a bias voltage VBIAS, and the reference line VL may receive a reference voltage VR. The first power line PL1 may receive a first driving voltage ELVDD, and the second power line PL2 may receive a second driving voltage ELVSS.

[0080] The transistors T1 to T10 may each include a source electrode, a drain electrode, and a gate electrode. Figure 5 In the embodiment, any one of the source electrode and the drain electrode is defined as a first electrode, and the other of the source electrode and the drain electrode is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0081] The transistors T1 to T10 may include first to tenth transistors T10. The first to tenth transistors T10 may be PMOS transistors, but are not limited thereto, and the first to tenth transistors T10 may be NMOS transistors. The capacitors C1 and C2 may include a first capacitor C1 and a second capacitor C2.

[0082] The first transistor T1 may be connected to the anode AE ​​and the first power line PL1, and may be switchable by the voltage of the first node N1. In other words, the gate electrode of the first transistor T1 may receive the voltage of the first node N1. The first transistor T1 may be connected to the anode AE ​​through the sixth transistor T6, and may be connected to the first power line PL1 through the eighth transistor T8. The first transistor T1 may be disposed between the sixth transistor T6 and the eighth transistor T8, and may be connected to the sixth transistor T6 and the eighth transistor T8.

[0083] The first transistor T1 may include a first electrode connected to the eighth transistor T8, a second electrode connected to the sixth transistor T6, and a control electrode connected to the first node N1. The first transistor T1 may control the amount of current flowing in the light emitting element ED according to the voltage of the first node N1 applied to the control electrode of the first transistor T1. The first transistor T1 may be defined as a driving transistor.

[0084] The second transistor T2 may be disposed between the i-th data line DLi and the second node N2, and may be connected to the i-th data line DLi and the second node N2. The second transistor T2 may be switchable by the j-th write scan signal GWj. The second transistor T2 may include a first electrode connected to the i-th data line DLi, a second electrode connected to the second node N2, and a control electrode connected to the j-th write scan line GWLj.

[0085] The first capacitor C1 may be connected to the first node N1 and the second node N2. The first capacitor C1 may be connected to the control electrode of the first transistor T1 through the first node N1, and may be connected to the second electrode of the second transistor T2 through the second node N2. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0086] The second transistor T2 may be turned on by the jth write scan signal GWj applied through the jth write scan line GWLj. The turned-on second transistor T2 may receive the data voltage VD through the i-th data line DLi. The data voltage VD may be provided to the first capacitor C1 through the turned-on second transistor T2. The second transistor T2 may be defined as a switching transistor.

[0087] The third transistor T3 may be connected to the first node N1 and the second electrode of the first transistor T1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the jth compensation scan line GCLj.

[0088] The third transistor T3 may be turned on by the jth compensation scan signal GCj applied through the jth compensation scan line GCLj to electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 may be connected in a diode form. The third transistor T3 may be defined as a compensation transistor.

[0089] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the j-th initialization scan line GILj.

[0090] The fourth transistor T4 may be turned on by the jth initialization scan signal GIj applied through the jth initialization scan line GILj. The turned-on fourth transistor T4 may provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1. The fourth transistor T4 may be defined as a first initialization transistor.

[0091] The fifth transistor T5 may include a first electrode connected to the second node N2, a second electrode connected to the reference line VL, and a control electrode connected to the j-th compensation scan line GCLj. The fifth transistor T5 may be turned on by the j-th compensation scan signal GCj applied through the j-th compensation scan line GCLj. The turned-on fifth transistor T5 may provide a reference voltage VR applied through the reference line VL to the second node N2.

[0092] The sixth transistor T6 may be connected to the first transistor T1 and the anode AE, and may be switchable by the j-th light emitting signal EMj. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the j-th light emitting line EMLj. The sixth transistor T6 may be turned on by the j-th light emitting signal EMj applied through the j-th light emitting line EMLj. The sixth transistor T6 may be defined as a first light emitting control transistor.

[0093] The seventh transistor T7 may be connected to the anode AE ​​and the second initialization line VIL2 and may be switchable by the jth bias scan signal EBj. The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the jth bias scan line EBLj.

[0094] The seventh transistor T7 may be turned on by the jth bias scan signal EBj applied through the jth bias scan line EBLj. The turned-on seventh transistor T7 may provide the second initialization voltage AINT received through the second initialization line VIL2 to the anode AE ​​of the light emitting element ED. The seventh transistor T7 may be defined as a second initialization transistor.

[0095] The eighth transistor T8 may include a first electrode connected to the first power line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a control electrode connected to the j-th emission line EMLj.

[0096] The eighth transistor T8 may be turned on by the jth light emitting signal EMj applied through the jth light emitting line EMLj. The eighth transistor T8 may be defined as a second light emitting control transistor. When the sixth transistor T6 and the eighth transistor T8 are turned on, the first driving voltage ELVDD may be provided to the light emitting element ED to allow the driving current to flow in the light emitting element ED. As a result, the light emitting element ED may emit light.

[0097] The ninth transistor T9 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the j-th bias scan line EBLj.

[0098] The ninth transistor T9 may be turned on by the jth bias scan signal EBj applied through the jth bias scan line EBLj. The turned-on ninth transistor T9 may provide the bias voltage VBIAS received through the bias line VBL to the first electrode of the first transistor T1.

[0099] The tenth transistor T10 may include a first electrode connected to the first power line PL1 , a second electrode connected to the first electrode of the first transistor T1 , and a control electrode connected to the j-th compensation scan line GCLj.

[0100] The tenth transistor T10 may be turned on by the jth compensation scan signal GCj applied through the jth compensation scan line GCLj. The turned-on tenth transistor T10 may supply the first driving voltage ELVDD applied through the first power line PL1 to the first electrode of the first transistor T1.

[0101] The second capacitor C2 may include a first electrode connected to the second electrode of the second transistor T2 and a second electrode connected to the first power line PL1 .

[0102] The anode AE ​​may be connected to the first power line PL1 through the sixth transistor T6, the first transistor T1, and the eighth transistor T8. The anode AE ​​may receive the first driving voltage ELVDD through the sixth transistor T6, the first transistor T1, and the eighth transistor T8.

[0103] The cathode CE may be connected to the second power line PL2. The cathode CE may receive the second driving voltage ELVSS having a level lower than that of the first driving voltage ELVDD through the second power line PL2.

[0104] Figure 6 Is used to describe Figure 5 0 is a timing diagram of scanning signals and light emitting signals for the operation of a pixel shown in FIG.

[0105] In the following, Figure 6 In the timing diagram, the activation period of each signal indicates a low level, and Figure 6 In the timing diagram of , the deactivation period of each signal indicates a high level.

[0106] refer to Figure 5 and Figure 6 , the jth light emitting signal EMj may include a non-light emitting period NLP and a light emitting period LP. The non-light emitting period NLP may be defined as a deactivation period (e.g., a high level period) of the jth light emitting signal EMj, and the light emitting period LP may be defined as an activation period (e.g., a low level period) of the jth light emitting signal EMj.

[0107] The jth initialization scan signal GIj and the jth compensation scan signal GCj may be repeatedly activated in the non-light emitting period NLP. The jth initialization scan signal GIj may be activated first, and then the jth compensation scan signal GCj may be activated. The activation period of the jth initialization scan signal GIj may not overlap with the activation period of the jth compensation scan signal GCj.

[0108] Illustratively, each of the jth initialization scan signal GIj and the jth compensation scan signal GCj may be activated twice in the non-light emitting period NLP. In the light emitting period LP, the jth initialization scan signal GIj and the jth compensation scan signal GCj may be deactivated.

[0109] In the non-light emitting period NLP, after the jth initialization scan signal GIj and the jth compensation scan signal GCj are deactivated, the jth write scan signal GWj may be activated, and then the jth bias scan signal EBj may be activated. In the light emitting period LP, the jth write scan signal GWj and the jth bias scan signal EBj may be deactivated.

[0110] In the non-light emitting period NLP, the fourth transistor T4 may be turned on by the activated jth initialization scan signal GIj. The first initialization voltage VINT may be provided to the first node N1 through the turned-on fourth transistor T4, and the first transistor T1 may be initialized. The above operation may be defined as an initialization operation.

[0111] Thereafter, in the non-light emission period NLP, the activated j-th compensation scan signal GCj may be applied to the third transistor T3 and the tenth transistor T10 to turn on the third transistor T3 and the tenth transistor T10 .

[0112] The second electrode of the first transistor T1 and the control electrode of the first transistor T1 may be connected through the turned-on third transistor T3. As a result, the first transistor T1 may be connected in a diode form. The first driving voltage ELVDD may be applied to the first electrode of the first transistor T1 through the turned-on tenth transistor T10.

[0113] In this case, a compensation voltage (ELVDD-Vth) that reduces the threshold voltage (Vth) of the first transistor T1 from the first driving voltage ELVDD may be applied to the control electrode of the first transistor T1. The above operation may be defined as a threshold voltage compensation operation.

[0114] In the non-light emitting period NLP, the activated j-th compensation scan signal GCj may be applied to the fifth transistor T5 to turn on the fifth transistor T5. The reference voltage VR may be applied to the second node N2 through the turned-on fifth transistor T5.

[0115] As the jth initialization scan signal GIj and the jth compensation scan signal GCj are repeatedly activated, the above initialization operation and threshold voltage compensation operation can be repeatedly performed. As the initialization operation is repeatedly performed, the data written in the first node N1 in the previous frame is completely removed, so that the first transistor T1 can be completely initialized.

[0116] A parasitic capacitor may exist in the third transistor T3 and the fourth transistor T4. The level of the gate-source voltage of the third transistor T3 and the fourth transistor T4 may fluctuate due to the above-mentioned parasitic capacitor. The second capacitor C2 may have a capacitance greater than the capacitance of the parasitic capacitor. The second capacitor C2 having a larger capacitance may be connected to the third transistor T3 and the fourth transistor T4 through the first node N1. The second capacitor C2 having a larger capacitance may suppress the fluctuation of the level of the gate-source voltage of the third transistor T3 and the fourth transistor T4.

[0117] Thereafter, in the non-light emitting period NLP, the activated j-th write scan signal GWj may be applied to the second transistor T2 to turn on the second transistor T2. The data voltage VD may be provided to the first capacitor C1 through the turned-on second transistor T2. In this case, the data voltage VD may be applied to the second node N2, and the voltage of the first node N1 may be ELVDD-Vth+VD-VR.

[0118] Thereafter, the seventh transistor T7 and the ninth transistor T9 may be turned on by the activated j-th bias scan signal EBj. The second initialization voltage AINT may be provided to the anode AE ​​through the turned-on seventh transistor T7 to initialize the voltage of the anode AE ​​to the second initialization voltage AINT. The bias voltage VBIAS may be applied to the first electrode of the first transistor T1 through the turned-on ninth transistor T9.

[0119] Thereafter, during the emission period LP, the activated jth emission signal EMj may be applied to the sixth and eighth transistors T6 and T8 to turn on the sixth and eighth transistors T6 and T8. A driving current may be provided to the light emitting element ED through the turned-on sixth transistor T6 to allow the light emitting element ED to emit light.

[0120] The source-gate voltage (Vsg) of the first transistor T1 may be defined as a voltage difference between the first driving voltage ELVDD and the voltage of the first node N1 (ELVDD-Vth+VD-VR). When the source-gate voltage (Vsg) of the first transistor T1 is substituted into the following equation 1, the threshold voltage (Vth) may be removed, and the driving current (Id) in equation 1 may be the square value of a value obtained by subtracting the data voltage VD from the reference voltage VR (VR-VD). 2 Therefore, the driving current (Id) can be determined regardless of the threshold voltage (Vth) of the first transistor T1.

[0121] [Equation 1]

[0122] Id=(1 / 2)μCox(W / L)(Vsg-Vth)2

[0123] Equation 1 is a typical transistor current and voltage relationship equation.

[0124] The bias voltage VBIAS may be applied to the first electrode of the first transistor T1 through the ninth transistor T9 after the threshold voltage (Vth) of the first transistor T1 is compensated and before the light emitting element ED emits light. The offset of the hysteresis curve of the first transistor T1 may be suppressed by the bias voltage VBIAS. The above operation may be defined as a bias operation.

[0125] The pixel PXij can be driven at various frequencies. The timing of the scanning signals GIj, GCj, GWj and EBj and the luminous signal EMj according to the frequency will be Figures 7 to 10B Shown in.

[0126] Figure 7 , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A and Fig. 10B It is a timing diagram of scanning signals and transmitting signals according to various frequencies.

[0127] refer to Figure 5 and Figure 7 , the driving frequency DF1 of the pixel PXij may be about 360 Hz. Therefore, the driving frequency DF1 may include 360 ​​frames 1F, 2F, 3F, ... 359F and 360F. The driving frequency DF1 may be defined as the highest driving frequency among the driving frequencies of the pixel PXij.

[0128] Each of the frames 1F to 360F may include a plurality of cycle periods CYC1 and CYC2. Each of the cycle periods CYC1 and CYC2 may be defined as one cycle of the j-th light emitting signal EMj having a deactivation period and an activation period.

[0129] Each of the cycle periods CYC1 and CYC2 of each of the frames 1F to 360F may include a first cycle period CYC1 and a second cycle period CYC2. The first cycle period CYC1 may be defined as a write cycle period WR, and the second cycle period CYC2 may be defined as a hold cycle period HD. The write cycle period WR may be one, the hold cycle period HD may be one, and the total number of cycle periods CYC1 and CYC2 may be two.

[0130] During the first cycle period CYC1, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be activated and applied to the pixel PXij. In each of the first cycle period CYC1 and the second cycle period CYC2, the jth bias scan signal EBj may be activated and applied to the pixel PXij.

[0131] refer to Fig. 8A and Figure 8B , the driving frequency DF2 of the pixel PXij may be about 180 Hz. Therefore, the driving frequency DF2 may include 180 frames 1F to 180F. Illustratively, Fig. 8A A first frame 1F and a second frame 2F are shown, and Figure 8B The 179th frame 179F and the 180th frame 180F are shown.

[0132] Each of the frames 1F to 180F may include a plurality of cycle periods CYC1, CYC2, CYC3, and CYC4. Each of the cycle periods CYC1, CYC2, CYC3, and CYC4 may be defined as one cycle of the j-th light emitting signal EMj.

[0133] The cycle periods CYC1, CYC2, CYC3, and CYC4 of each of the frames 1F to 180F may include a first cycle period CYC1, a second cycle period CYC2, a third cycle period CYC3, and a fourth cycle period CYC4. The first cycle period CYC1 may be defined as a write cycle period WR, and the second cycle period CYC2, the third cycle period CYC3, and the fourth cycle period CYC4 may be defined as a hold cycle period HD. The write cycle period WR may be one, the hold cycle period HD may be three, and the total number of the cycle periods CYC1, CYC2, CYC3, and CYC4 may be four.

[0134] During the first cycle period CYC1, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be activated and applied to the pixel PXij. In each of the first cycle period CYC1, the second cycle period CYC2, the third cycle period CYC3, and the fourth cycle period CYC4, the jth bias scan signal EBj may be activated and applied to the pixel PXij.

[0135] refer to Fig. 9A and Fig. 9B , the driving frequency DF3 of the pixel PXij may be about 90 Hz. Therefore, the driving frequency DF3 may include 90 frames 1F to 90F. Illustratively, Fig. 9A A first frame 1F and a second frame 2F are shown, and Fig. 9BThe 89th frame 89F and the 90th frame 90F are shown.

[0136] Each of the frames 1F to 90F may include a plurality of cycle periods CYC1, CYC2, CYC3, ..., and CYC8. Each of the cycle periods CYC1, CYC2, CYC3, ..., and CYC8 may be defined as one cycle of the j-th light emitting signal EMj.

[0137] The cycle periods CYC1, CYC2, CYC3, ..., and CYC8 of each of the frames 1F to 90F may include a first cycle period CYC1 to an eighth cycle period CYC8. The first cycle period CYC1 may be defined as a write cycle period WR, and the second cycle period CYC2 to the eighth cycle period CYC8 may be defined as a hold cycle period HD. The write cycle period WR may be one, the hold cycle period HD may be seven, and the total number of cycle periods CYC1 to CYC8 may be eight.

[0138] During the first cycle period CYC1, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be activated and applied to the pixel PXij. In each of the first to eighth cycle periods CYC1 to CYC8, the jth bias scan signal EBj may be activated and applied to the pixel PXij.

[0139] refer to Fig. 10A and Fig. 10B , the driving frequency DF4 of the pixel PXij may be about 30 Hz. Therefore, the driving frequency DF4 may include 30 frames 1F to 30F. Illustratively, Fig. 10A A first frame 1F and a second frame 2F are shown, and Fig. 10B The 29th frame 29F and the 30th frame 30F are shown. The driving frequency DF4 may be defined as the lowest driving frequency among the driving frequencies of the pixels PXij.

[0140] Each of the frames 1F to 30F may include a plurality of cycle periods CYC1, CYC2, CYC3, ..., and CYC24. Each of the cycle periods CYC1, CYC2, CYC3, ..., and CYC24 may be defined as one cycle of the j-th light emitting signal EMj.

[0141] The cycle periods CYC1, CYC2, CYC3, ..., and CYC24 of each of the frames 1F to 30F may include a first cycle period CYC1 to a twenty-fourth cycle period CYC24. The first cycle period CYC1 may be defined as a write cycle period WR, and the second cycle period CYC2 to the twenty-fourth cycle period CYC24 may be defined as a hold cycle period HD. The write cycle period WR may be one, the hold cycle period HD may be twenty-three, and the total number of cycle periods CYC1 to CYC24 may be twenty-four.

[0142] During the first cycle period CYC1, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be activated and applied to the pixel PXij. In each of the first to twenty-fourth cycle periods CYC1 to CYC24, the jth bias scan signal EBj may be activated and applied to the pixel PXij.

[0143] Hereinafter, a description in which a signal is applied to a pixel PXij may mean an operation in which an activated signal is applied to the pixel PXij. A description in which a signal is not applied to a pixel PXij may mean an operation in which a deactivated signal is applied to the pixel PXij.

[0144] Illustratively, driving frequencies DF1, DF2, DF3, and DF4 of 360 Hz, 180 Hz, 90 Hz, and 30 Hz are described, but embodiments of the present invention are not limited thereto, and the pixel PXij may be driven at various driving frequencies within a range of about 360 Hz to about 30 Hz.

[0145] According to the foregoing description, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be applied to the pixel PXij according to the driving frequencies DF1, DF2, DF3, and DF4. That is, the number of times the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj are applied to the pixel PXij may be determined according to the driving frequencies DF1, DF2, DF3, and DF4.

[0146] The number of times the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj are applied to the pixel PXij may decrease as the driving frequencies DF1 , DF2 , DF3 , and DF4 decrease.

[0147] The write cycle period WR may be defined as a time period during which the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj are applied to the pixel PXij. Each of the hold cycle periods HD may be defined as a time period during which the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj are not applied to the pixel PXij. In each of the write cycle period WR and the hold cycle period HD, the jth bias scan signal EBj may be applied to the pixel PXij.

[0148] Table 1 below shows the number of write cycle periods WR, hold cycle periods HD, and total cycle periods constituting one frame according to various driving frequencies.

[0149] [Table 1]

[0150]

[0151] As the driving frequency decreases, the number of sustain cycle periods HD and total cycle periods in one frame may increase. A driving frequency of 360 Hz includes one sustain cycle period HD, but a driving frequency below 180 Hz may include a plurality of sustain cycle periods HD.

[0152] Fig.11 is a view showing a graph of changes in luminance of a pixel when a driving frequency of the pixel is switched from a first frequency to a second frequency. Fig.12 yes Fig.11 Magnified view of area AA shown in FIG.

[0153] Fig.11 and Fig.12 The graph shown in FIG. 1 basically shows the brightness change of the pixel PXij when the aforementioned second initialization voltage AINT has a constant level. For ease of description, Fig.11 and Fig.12 Only some of the symbols of frames HF and LF are shown.

[0154] refer to Fig.11 and Fig.12 , the pixel PXij may be driven at the first frequency FQ1, and then may be driven at the second frequency FQ2. That is, the driving frequency of the pixel PXij may be converted from the first frequency FQ1 to the second frequency FQ2.

[0155] The first frequency FQ1 may be defined as a high frequency, and the second frequency FQ2 may be defined as a low frequency. Specifically, the first frequency FQ1 may be defined as a driving frequency having a higher frequency than the second frequency FQ2. The second frequency FQ2 may be defined as a driving frequency having a lower frequency than the first frequency FQ1.

[0156] Illustratively, the first frequency FQ1 may be a driving frequency DF1 of 360 Hz, and the second frequency FQ2 may be a driving frequency DF4 of 30 Hz, but in the case where the first frequency FQ1 is higher than the second frequency FQ2 , the values ​​of the first frequency FQ1 and the second frequency FQ2 are not limited thereto.

[0157] As described above, the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj may be applied to the pixel PXij at the first frequency FQ1 or the second frequency FQ2. According to the jth initialization scan signal GIj, the jth compensation scan signal GCj, and the jth write scan signal GWj applied to the pixel PXij at the first frequency FQ1 or the second frequency FQ2, the transistor of the pixel PXij may be switched.

[0158] The first frequency FQ1 may include a plurality of frames HF, and the second frequency FQ2 may include a plurality of frames LF. Fig.11 Any number of frames HF and any number of frames LF are shown in . The period of each of the frames HF of the first frequency FQ1 being a high frequency may be smaller than the period of each of the frames LF of the second frequency FQ2 being a low frequency.

[0159] The brightness of the light emitting element ED of the pixel PXij may have a first brightness BR1 at the first frequency FQ1, and may have a second brightness BR2 at the second frequency FQ2. That is, in the frame HF of the first frequency FQ1, the light emitting element ED may emit light to have the first brightness BR1, and in the frame LF of the second frequency FQ2, the light emitting element ED may emit light to have the second brightness BR2.

[0160] The average brightness of the light of the light emitting element ED generated at the first frequency FQ1 may be defined as an average level AL of the first brightness BR1. The average level AL of the first brightness BR1 is Fig.11 According to the above pixel PXij initialization operation, at the boundary between frames HF shown as a vertical dotted line, the first brightness BR1 may temporarily decrease to a first low brightness level LBR1 lower than the average level AL, and then may gradually rise to a level higher than the average level AL.

[0161] According to the initialization operation of the pixel PXij, at the boundary between the frames LF shown as a vertical dotted line, the second brightness BR2 can be temporarily reduced to a second low brightness level LBR2, and then can gradually rise to a level higher than the average level AL. Even at the boundary between two frames HF and LF adjacent to each other, according to the initialization operation of the pixel PXij, the brightness of the light emitting element ED can be temporarily reduced to a lower brightness level LBR lower than the average level AL.

[0162] Fig.12 The bar graph shown in FIG. 1 exemplarily shows the number of times the light emitting element ED emits light in the frames HF and LF, and the number of times the light emitting element ED emits light should not be interpreted as Fig.12 The number of bars shown in the .

[0163] When the driving frequency of the pixel PXij is converted from the first frequency FQ1 to the second frequency FQ2, the hysteresis characteristic of the first transistor T1 of the pixel PXij may change. The change in the hysteresis characteristic is the largest in the first frame 1F which is the initial frame among the frames LF of the second frequency FQ2, and then the change in the hysteresis characteristic may be gradually reduced in the subsequent frames LF.

[0164] If the change in the second brightness BR2 of the light of the light emitting element ED generated at the second frequency FQ2 relative to the average brightness (ie, average level AL) of the light of the light emitting element ED generated at the first frequency FQ1 exceeds a predetermined range, the brightness change can be visually recognized.

[0165] For example, if the second brightness BR2 of the light of the light emitting element ED generated at the second frequency FQ2 changes by more than 4% relative to the average level AL of the first brightness BR1, the brightness change can be visually recognized. If the second brightness BR2 changes by less than 4% relative to the average level AL of the first brightness BR1, the brightness change may not be visually recognized. The point where the second brightness BR2 changes by about 4% relative to the average level AL of the first brightness BR1 is Fig.11 It is shown as a dot-dash line and can be defined as the flicker reference point FRP.

[0166] Illustratively, in the first frame 1F and the second frame 2F among the frames LF, the variation of the second brightness BR2 relative to the average level AL of the first brightness BR1 may exceed 4%. As a result, a flicker phenomenon in which brightness variation is visually recognized may occur in the first frame 1F and the second frame 2F.

[0167] However, this is described only illustratively, and the amount of change in brightness may exceed 4% and the brightness change may be visually recognized not only in the second frame 2F but also in a predetermined frame LF (e.g., the third frame 3F) after the second frame 2F. In addition, the amount of change in brightness may exceed 4% only in the first frame 1F.

[0168] In addition, although the flicker reference point FRP causing the flicker phenomenon to occur is set based on 4%, this is only described illustratively, and the flicker reference point FRP may be set based on various standards such as 3% or 5%.

[0169] Fig.13is a view showing a level change of a second initialization voltage according to an embodiment of the present invention.

[0170] Fig.13 Shows Fig.11 , and a brightness curve diagram of some frames HF of the first frequency FQ1 and some frames LF of the second frequency FQ2 and the second initialization voltage AINT. For convenience of description, only some of the symbols of the frames HF and LF are shown.

[0171] refer to Figure 5 and Fig.13 , the level of the second initialization voltage AINT can be adjusted differently in the frame LF of the second frequency FQ2. In the kth frame and the k+1th frame of the second frequency FQ2, the level of the second initialization voltage AINT can be gradually changed. For example, in each of the kth frame and the k+1th frame of the second frequency FQ2, the level of the second initialization voltage AINT can be gradually reduced. k is a natural number greater than zero, and hereinafter, it will be assumed that k is 1 to describe an embodiment of the present invention.

[0172] The first frame 1F and the second frame 2F may be defined as frames adjacent to a time point when the first frequency FQ1 is converted to the second frequency FQ2. That is, the kth frame and the k+1th frame may be adjacent to a time point when the first frequency FQ1 is converted to the second frequency FQ2.

[0173] In each of the first frame 1F and the second frame 2F, the level of the second initialization voltage AINT may gradually change, and specifically, the level of the second initialization voltage AINT may gradually decrease. The amount of change of the second initialization voltage AINT of the first frame 1F may be greater than the amount of change of the second initialization voltage AINT of the second frame 2F. Therefore, the amount of decrease of the second initialization voltage AINT of the first frame 1F may be greater than the amount of decrease of the second initialization voltage AINT of the second frame 2F.

[0174] That is, the change in the second initialization voltage AINT of the kth frame can be greater than the change in the second initialization voltage AINT of the k+1th frame, and specifically, the total decrease in the second initialization voltage AINT during the kth frame can be greater than the total decrease in the second initialization voltage AINT during the k+1th frame.

[0175] Since the change amount of the second brightness BR2' is the largest in the first frame 1F, the total reduction amount of the second initialization voltage AINT during the first frame 1F can be set to the maximum. Since the change amount of the second brightness BR2' of the second frame 2F is smaller than the change amount of the second brightness BR2' of the first frame 1F, the total reduction amount of the second initialization voltage AINT during the second frame 2F can be smaller than the total reduction amount of the second initialization voltage AINT during the first frame 1F.

[0176] In an embodiment, a first voltage difference △V1 between a maximum value and a minimum value of a level of the second initialization voltage AINT of the first frame 1F may be greater than a second voltage difference △V2 between a maximum value and a minimum value of a level of the second initialization voltage AINT of the second frame 2F. That is, a first voltage difference △V1 between a maximum value and a minimum value of a level of the second initialization voltage AINT of the kth frame may be greater than a second voltage difference △V2 between a maximum value and a minimum value of a level of the second initialization voltage AINT of the k+1th frame.

[0177] When the level of the second initialization voltage AINT for initializing the anode AE ​​decreases, the brightness of the light emitting element ED may decrease. Since the level of the second initialization voltage AINT of the first frame 1F gradually decreases, the second brightness BR2' in the first frame 1F may be increased from Fig.11 The level of the second brightness BR2 shown in Fig.13 The dashed line in the figure further decreases.

[0178] Since the level of the second initialization voltage AINT of the second frame 2F is gradually reduced, the second brightness BR2′ in the second frame 2F can be increased from Fig.11 The level of the second brightness BR2 shown in Fig.13 The dashed line in the figure further decreases.

[0179] As the reduction amount of the second initialization voltage AINT increases, the second brightness BR2' may be further reduced. Therefore, the second brightness BR2' may be further reduced in the first frame 1F than in the second frame 2F. Fig.11 Compared with the second brightness BR2 shown in , the reduction amount of the second brightness BR2 ′ of the first frame 1F may be greater than the reduction amount of the second brightness BR2 ′ of the second frame 2F.

[0180] The second brightness BR2' of each of the first frame 1F and the second frame 2F may be lower than the brightness corresponding to the flicker reference point FRP. As a result, the flicker phenomenon may not occur in the first frame 1F and the second frame 2F.

[0181] Illustratively, the level of the second initialization voltage AINT is adjusted to Fig.13 In each of the first frame 1F and the second frame 2F, the level of the second initialization voltage AINT is gradually reduced, but the embodiments of the present invention may not be limited thereto. Since the second brightness BR2 may be higher than the brightness corresponding to the flicker reference point FRP in the predetermined frame LF after the second frame 2F, in another embodiment, the level of the second initialization voltage AINT may also be adjusted to gradually decrease in the predetermined frame LF after the second frame 2F.

[0182] FIG. 14A to FIG. 14C2 is a view showing various lowering modes of a second initialization voltage according to an embodiment of the present invention.

[0183] Illustratively, FIG. 14A to FIG. 14C The frames shown in FIG. 1 can be defined as the kth frame Fk and the k+1th frame Fk+1, and can be basically respectively Fig.13 The first frame 1F and the second frame 2F shown in FIG. 2 correspond to each other.

[0184] refer to FIG. 14A to FIG. 14C Each of the k-th frame Fk and the k+1-th frame Fk+1 may include a plurality of cycle periods CYC1, CYC2, CYC3, ... and CYCg. g is a natural number greater than 3. The cycle periods CYC1 to CYCg may be the same as those in the above reference. Fig. 10A and Fig. 10B The described cycle periods CYC1 to CYC24 correspond.

[0185] The cycle periods CYC1 to CYCg may include a write cycle period WR and a plurality of hold cycle periods HD. The first cycle period CYC1 may be defined as a write cycle period WR, and subsequent cycle periods CYC2 to CYCg may be defined as hold cycle periods HD.

[0186] The level of the second initialization voltage AINT of the write cycle period WR of the k+1 frame Fk+1 may be the same as the level of the second initialization voltage AINT of the write cycle period WR of the k frame Fk. That is, the level of the second initialization voltage AINT of the first cycle period CYC1 of the k+1 frame Fk+1 may be the same as the level of the second initialization voltage AINT of the first cycle period CYC1 of the k frame.

[0187] like FIG. 14A to FIG. 14C As shown in , the decreasing mode of the second initialization voltage AINT may be variously set.

[0188] refer to Fig.14A In each of the kth frame Fk and the k+1th frame Fk+1, the level of the second initialization voltage AINT may be gradually reduced as the cycle periods CYC1 to CYCg increase. For example, in each of the kth frame Fk and the k+1th frame Fk+1, the level of the second initialization voltage AINT of the h+1th cycle period may be lower than the level of the second initialization voltage AINT of the hth cycle period. h is a natural number greater than zero.

[0189] Specifically, in each of the kth frame Fk and the k+1th frame Fk+1, the level of the second initialization voltage AINT of the second cycle period CYC2 may be lower than the level of the second initialization voltage AINT of the first cycle period CYC1. In addition, the level of the second initialization voltage AINT of the third cycle period CYC3 may be lower than the level of the second initialization voltage AINT of the second cycle period CYC2. In each of the kth frame Fk and the k+1th frame Fk+1, the above-mentioned reduction mode may be repeated until the gth cycle period CYCg.

[0190] According to the above description, in the same frame, the level of the second initialization voltage AINT may gradually decrease as the cycle periods CYC1 to CYCg increase.

[0191] In the same holding period HD of the kth frame Fk and the k+1th frame Fk+1, the level of the second initialization voltage AINT of the holding period HD of the k+1th frame Fk+1 may be higher than the level of the second initialization voltage AINT of the holding period HD of the kth frame Fk. For example, the level of the second initialization voltage AINT of the pth holding period of the k+1th frame Fk+1 may be higher than the level of the second initialization voltage AINT of the pth holding period of the kth frame Fk. p is a natural number greater than zero.

[0192] Specifically, the level of the second initialization voltage AINT of the first hold period HD (e.g., second period CYC2) of the k+1th frame Fk+1 may be higher than that of the first hold period HD (e.g., second period CYC2) of the kth frame Fk.

[0193] In addition, the level of the second initialization voltage AINT of the second holding cycle period HD (e.g., the third cycle period CYC3) of the k+1th frame Fk+1 may be higher than the level of the second initialization voltage AINT of the second holding cycle period HD (e.g., the third cycle period CYC3) of the kth frame Fk. The above-mentioned reduction mode may be repeated until the g-th cycle period CYCg of the k-th frame Fk and the k+1-th frame Fk+1.

[0194] refer to Fig. 14B and Fig. 14C , in each of the kth frame Fk and the k+1th frame Fk+1, a level of the second initialization voltage AINT of the h+1th cycle period may be lower than or equal to a level of the second initialization voltage AINT of the hth cycle period.

[0195] refer to Fig. 14BIn the kth frame Fk, the level of the second initialization voltage AINT of the second cycle period CYC2 may be the same as that of the first cycle period CYC1. In the kth frame Fk, the level of the second initialization voltage AINT of the third cycle period CYC3 may be lower than that of the second cycle period CYC2.

[0196] In the k+1th frame Fk+1, the level of the second initialization voltage AINT of the second cycle period CYC2 may be the same as the level of the second initialization voltage AINT of the first cycle period CYC1. In the k+1th frame Fk+1, the level of the second initialization voltage AINT of the third cycle period CYC3 may be lower than the level of the second initialization voltage AINT of the second cycle period CYC2.

[0197] refer to Fig. 14C , in the kth frame Fk, the level of the second initialization voltage AINT of the second cycle period CYC2 may be lower than the level of the second initialization voltage AINT of the first cycle period CYC1. In the kth frame Fk, the level of the second initialization voltage AINT of the third cycle period CYC3 may be lower than the level of the second initialization voltage AINT of the second cycle period CYC2. In the kth frame Fk, the levels of the second initialization voltage AINT of some consecutive cycle periods in the subsequent cycle periods may be the same.

[0198] In the k+1th frame Fk+1, the level of the second initialization voltage AINT of the second cycle period CYC2 may be the same as the level of the second initialization voltage AINT of the first cycle period CYC1. In the k+1th frame Fk+1, the level of the second initialization voltage AINT of the third cycle period CYC3 may be lower than the level of the second initialization voltage AINT of the second cycle period CYC2. In the k+1th frame Fk+1, the levels of the second initialization voltage AINT of some consecutive cycle periods in the subsequent cycle periods may be the same.

[0199] In each of the k-th frame Fk and the k+1-th frame Fk+1, the above-described decreasing mode may be repeated until the g-th cycle period CYCg.

[0200] According to the above description, period periods adjacent to each other in the same frame may have the same level of the second initialization voltage AINT, or may have different levels of the second initialization voltage AINT, wherein the level of the second initialization voltage AINT may gradually decrease.

[0201] refer to Fig. 14B and Fig. 14C, a level of the second initialization voltage AINT of the p-th sustain period HD of the k+1-th frame may be higher than or equal to a level of the second initialization voltage AINT of the p-th sustain period HD of the k-th frame.

[0202] refer to Fig. 14B , the level of the second initialization voltage AINT of the first hold cycle period HD (e.g., the second cycle period CYC2) of the k+1th frame Fk+1 can be the same as the level of the second initialization voltage AINT of the first hold cycle period HD (e.g., the second cycle period CYC2) of the kth frame Fk.

[0203] The level of the second initialization voltage AINT of the second sustaining period HD (eg, the third period CYC3 ) of the k+1th frame Fk+1 may be higher than that of the second sustaining period HD (eg, the third period CYC3 ) of the kth frame Fk.

[0204] refer to Fig. 14C , a level of the second initialization voltage AINT of the first hold period HD (e.g., the second period CYC2) of the k+1th frame Fk+1 may be higher than a level of the second initialization voltage AINT of the first hold period HD (e.g., the second period CYC2) of the kth frame Fk.

[0205] The level of the second initialization voltage AINT of the second sustaining period HD (eg, the third period CYC3 ) of the k+1th frame Fk+1 may be higher than that of the second sustaining period HD (eg, the third period CYC3 ) of the kth frame Fk.

[0206] The above-described decreasing mode may be repeated until the g-th cycle period CYCg of the k-th frame Fk and the k+1-th frame Fk+1.

[0207] Fig.14A , Fig. 14B and Fig. 14C The decreasing mode of the second initialization voltage AINT in FIG. 1 is exemplarily shown, but is not limited thereto, and the decreasing mode of the second initialization voltage AINT may be variously set.

[0208] According to the decreasing pattern of the second initialization voltage AINT, the brightness can be reduced in the initial frame of the second frequency FQ2. As a result, the flicker phenomenon can be reduced.

[0209] Table 2 below illustratively shows the level of the second initialization voltage AINT of the cycle periods CYC1 to CYC24 of each of the first frame 1F, the second frame 2F, and the third frame 3F at the driving frequency DF4 of 30 Hz.

[0210] [Table 2]

[0211]

[0212]

[0213] Referring to Table 2, the levels of the second initialization voltages AINT of the first frame 1F and the second frame 2F may vary, and the level of the second initialization voltage AINT of the third frame 3F may not vary.

[0214] Similar to the above description, in each of the first frame 1F and the second frame 2F, the level of the second initialization voltage AINT of the h+1th cycle period may be lower than or equal to the level of the second initialization voltage AINT of the hth cycle period.

[0215] For example, the level of the second initialization voltage AINT of the second cycle period CYC2 of the first frame 1F may be the same as the level of the second initialization voltage AINT of the first cycle period CYC1 of the first frame 1F. The level of the second initialization voltage AINT of the third cycle period CYC3 of the first frame 1F may be lower than the level of the second initialization voltage AINT of the second cycle period CYC2 of the first frame 1F.

[0216] Similar to the above description, the level of the second initialization voltage AINT of the pth cycle period of the second frame 2F may be higher than or equal to that of the pth sustain cycle period of the first frame 1F. In Table 2, the sustain cycle period may be started from the second cycle period CYC2.

[0217] For example, the level of the second initialization voltage AINT of the second cycle period CYC2 of the second frame 2F may be the same as the level of the second initialization voltage AINT of the second cycle period CYC2 of the first frame 1F. The level of the second initialization voltage AINT of the fourth cycle period CYC4 of the second frame 2F may be higher than the level of the second initialization voltage AINT of the fourth cycle period CYC4 of the first frame 1F.

[0218] Table 3 below is a test result showing the amount of change in brightness of the first frame 1F and the second frame 2F according to the level change of the second initialization voltage AINT. The amount of change in brightness of the third frame 3F is also described for reference.

[0219] The numerical values ​​described in the items of the first frame 1F, the second frame 2F, and the third frame 3F represent the amount of change in the brightness of the low frequency relative to the brightness of the high frequency, and the unit is %. Before conversion, it represents the high frequency, and after conversion, it represents the low frequency. The test was performed at a low brightness of 11 grayscales.

[0220] [Table 3]

[0221]

[0222]

[0223] Refer to Table 3, when Fig.13 When the level of the second initialization voltage AINT is adjusted as shown in , as shown in Table 3, the variation of the low-frequency second brightness BR2 relative to the high-frequency first brightness BR1 may be 4% or less.

[0224] Fig.15A and Fig. 15B is a view showing the timing of a bias scan signal according to another embodiment of the present invention.

[0225] Illustratively, Fig.15A and Fig. 15B The timing of the signals of the first frame 1F and the second frame 2F of the low frequency when performing the conversion from the high frequency to the low frequency is shown, and Fig.15A and Fig. 15B In Fig. 9A and Fig. 9B As shown in , the driving frequency DF3 may be 90 Hz.

[0226] In addition, Fig.13 Similarly, as an operation for reducing the brightness of the first frame 1F and the second frame 2F, timings of the scanning signals GIj, GCj, GWj, and EBj and the light emitting signal EMj of the first frame 1F and the second frame 2F are shown.

[0227] In the following, we will focus on Fig. 9A and Fig. 9B The different timings shown in Fig.15A and Fig. 15B The timing of the signals shown in .

[0228] refer to Fig.15A and Fig. 15B The timing of the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj and the jth light emitting signal EMj can be Fig. 9A and Fig. 9B The timing shown in is essentially the same.

[0229] In each of the holding cycle periods HD of the kth frame and the k+1th frame, the number of times the jth bias scanning signal EBj is applied per holding cycle period can be changed. For example, in the first frame 1F, as the order of the cycle periods CYC1 to CYC8 increases (for example, from the first cycle period CYC1 toward the eighth cycle period CYC8), the number of times the jth bias scanning signal EBj is applied per cycle period can be gradually increased. In addition, as the order of the holding cycle period HD among the holding cycle periods HD of each of the first frame 1F and the second frame 2F is later, the number of times the jth bias scanning signal EBj is applied per holding cycle period can be gradually increased.

[0230] When the seventh transistor T7 for initializing the anode AE ​​is turned on more frequently, the second initialization voltage AINT can be provided to the anode AE ​​more frequently. In this case, the anode AE ​​can be further initialized to reduce the brightness of the light emitting element ED. Therefore, the brightness of the first frame 1F and the second frame 2F is reduced to reduce the aforementioned flicker phenomenon.

[0231] The operation of changing the number of times the j-th bias scan signal EBj is applied may be performed together with the above-mentioned operation of changing the level of the second initialization voltage AINT. However, the embodiments of the present invention are not limited thereto, and in another embodiment, the operation of changing the number of times the j-th bias scan signal EBj is applied may be performed and the operation of changing the level of the second initialization voltage AINT may not be performed.

[0232] Fig.16A and Fig. 16B is a view showing the timing of a bias scan signal according to still another embodiment of the present invention.

[0233] Illustratively, like Fig.15A and Fig. 15B Same, Fig.16A and Fig. 16B 1F and 2F of the low-frequency signal are shown when the conversion from high frequency to low frequency is performed, and the driving frequency DF3 may be 90 Hz. Fig.16A and Fig. 16B Can be used with Fig.15A and Fig. 15B The timing diagram shown in .

[0234] In the following, we will focus on Fig.15A and Fig. 15B The different timings shown in Fig.16A and Fig. 16B The timing of the signals shown in .

[0235] refer to Fig.16A and Fig. 16BThe timing of the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj and the jth light emitting signal EMj can be Fig.15A and Fig. 15B The timing shown in is essentially the same.

[0236] In each of the holding cycle period HD of the kth frame and the k+1th frame, the width of the jth bias scanning signal EBj (e.g., the duration of maintaining the activation level) may change. For example, in the first frame 1F, as the cycle periods CYC1 to CYC8 increase in sequence (e.g., from the first cycle period CYC1 toward the eighth cycle period CYC8), the width of the jth bias scanning signal EBj may gradually increase. In addition, as the holding cycle period HD of each of the first frame 1F and the second frame 2F increases in sequence, the width of the jth bias scanning signal EBj may gradually increase.

[0237] When the seventh transistor T7 for initializing the anode AE ​​is turned on for a long time, the second initialization voltage AINT can be provided to the anode AE ​​for a long time. In this case, the anode AE ​​can be further initialized to reduce the brightness of the light emitting element ED. Therefore, the brightness of the first frame 1F and the second frame 2F is reduced to reduce the aforementioned flicker phenomenon.

[0238] The operation of changing the width of the j-th bias scan signal EBj (e.g., the duration of maintaining the activation level) may be performed together with the above-mentioned operation of changing the level of the second initialization voltage AINT. However, the embodiments of the present invention are not limited thereto, and the operation of changing the width of the j-th bias scan signal EBj may be performed and the operation of changing the level of the second initialization voltage AINT may not be performed.

[0239] According to an embodiment of the present invention, when the driving frequency of a pixel is converted from a high frequency to a low frequency, in an initial frame of a low frequency, the second initialization voltage is gradually reduced, so that the increase in the brightness of the pixel can be suppressed. As a result, the brightness difference of the pixel between the initial frame of the low frequency and the frame of the high frequency is reduced, which can reduce the flicker phenomenon.

[0240] Although the present invention has been described with reference to the embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made to it in form and detail without departing from the spirit and scope of the present invention as set forth in the claims. In addition, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, and all technical concepts falling within the scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention.

Claims

1. A display device, comprising: A light emitting element, comprising an anode and a cathode; a first transistor connected to the anode and a power supply line and switchable by a voltage at a first node; a second transistor connected to the data line and the second node and switchable by writing a scan signal; a capacitor connected to the first node and the second node; as well as an initialization transistor connected to the anode and configured to receive an initialization voltage and is switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency or a second frequency lower than the first frequency, and When converting from the first frequency to the second frequency, in a kth frame of the second frequency, the level of the initialization voltage gradually decreases, wherein k is a natural number greater than zero.

2. The display device according to claim 1, wherein: In a (k+1)th frame of the second frequency, the level of the initialization voltage gradually decreases.

3. The display device according to claim 2, wherein: The reduction amount of the initialization voltage of the k-th frame is greater than the reduction amount of the initialization voltage of the k+1-th frame.

4. The display device according to claim 3, wherein: A first voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k-th frame is greater than a second voltage difference between a maximum value and a minimum value of the level of the initialization voltage in the k+1-th frame.

5. The display device according to claim 3, wherein: The kth frame and the k+1th frame are adjacent to a time point when the first frequency is converted into the second frequency.

6. The display device according to claim 5, wherein: The k is 1.

7. The display device according to claim 2, wherein: Each of the k-th frame and the k+1-th frame includes a plurality of cycle periods, The multiple periodic time periods include: a write cycle period during which the write scan signal and the bias scan signal are applied; and A plurality of holding cycle periods during which the write scan signal is not applied and the bias scan signal is applied.

8. The display device according to claim 7, wherein: The level of the initialization voltage during the write cycle period of the k+1th frame is the same as the level of the initialization voltage during the write cycle period of the kth frame.

9. The display device according to claim 7, wherein: In each of the kth frame and the k+1th frame, the level of the initialization voltage during an h+1th cycle period is lower than the level of the initialization voltage during an hth cycle period, wherein h is a natural number greater than zero.

10. The display device according to claim 7, wherein: The level of the initialization voltage during the p-th sustain period of the k+1-th frame is higher than the level of the initialization voltage during the p-th sustain period of the k-th frame, wherein p is a natural number greater than zero.

11. The display device according to claim 7, wherein: In each of the kth frame and the k+1th frame, the level of the initialization voltage during an h+1th cycle period is lower than or equal to the level of the initialization voltage during an hth cycle period, wherein h is a natural number greater than zero.

12. The display device according to claim 7, wherein: The level of the initialization voltage during the p-th sustain period of the k+1-th frame is higher than or equal to the level of the initialization voltage during the p-th sustain period of the k-th frame, wherein p is a natural number greater than zero.

13. The display device according to claim 7, further comprising: A light emission control transistor is connected to the first transistor and the anode and is switchable by a light emission signal, wherein each of the plurality of cycle periods is defined as one cycle of the light emission signal.

14. The display device according to any one of claims 7 to 13, wherein: In the plurality of holding period periods of each of the k-th frame and the k+1-th frame, the number of times the bias scanning signal is applied per holding period period is changed.

15. The display device according to claim 14, wherein: The number of times the bias scanning signal is applied per sustaining period increases gradually as the sustaining period among the plurality of sustaining period of each of the k-th frame and the k+1-th frame is later in order.

16. The display device according to any one of claims 7 to 13, wherein: In the plurality of sustain period periods of each of the k-th frame and the k+1-th frame, a duration of an activation level of the bias scan signal is changed.

17. The display device according to claim 16, wherein: The duration of the activation level of the bias scanning signal in the sustain period period gradually increases as the sustain period period among the plurality of sustain period periods of each of the kth frame and the k+1th frame is later in order.

18. A display device comprising: A light emitting element, comprising an anode and a cathode; a first transistor connected to the anode and a power supply line and switchable by a voltage at a first node; a second transistor connected to the data line and the second node and switchable by writing a scan signal; a capacitor connected to the first node and the second node; as well as an initialization transistor connected to the anode and configured to receive an initialization voltage and is switchable by a bias scan signal, wherein the write scan signal is applied to the second transistor at a first frequency or a second frequency lower than the first frequency, and Wherein, when converting from the first frequency to the second frequency, in each of the kth frame of the second frequency and the k+1th frame of the second frequency, the level of the initialization voltage gradually changes, and the change in the initialization voltage of the kth frame is greater than the change in the initialization voltage of the k+1th frame, wherein k is a natural number greater than zero.

19. The display device according to claim 18, wherein: In each of the k-th frame and the k+1-th frame, the level of the initialization voltage gradually decreases.

20. The display device according to claim 19, wherein: A total decrease amount of the initialization voltage during the k-th frame is greater than a total decrease amount of the initialization voltage during the k+1-th frame.

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