Display device

Abstract

According to an aspect of the present disclosure, a display device includes a display panel in which a plurality of pixel groups are defined, in each of the plurality of pixel groups, one PAM circuit, a plurality of PWM circuits connected to the one PAM circuit, and a plurality of light emitting diodes connected to the plurality of PWM circuits are provided. In each of the plurality of pixel groups, the plurality of PWM circuits are connected in parallel to an output terminal of one PAM circuit. Accordingly, a plurality of PWM circuits share one PAM circuit to reduce the number of total transistors and simplify the structure of the display device.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0166454, filed with the Korean Intellectual Property Office on November 27, 2023, the disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display device, and more particularly, to a display device that simplifies the structure of a pixel circuit. Background art

[0004] As display devices for monitors for computers, televisions, cellular phones, etc., there are organic light - emitting display (OLED) devices as self - emitting devices, liquid crystal display (LCD) devices that require a separate light source, etc.

[0005] The application scope of display devices has been diversified to personal mobile devices as well as monitors for computers and televisions, and display devices with a large display area and reduced volume and weight are being studied.

[0006] Among them, various types of display elements can be used for display devices, and in recent years, light - emitting diodes (LEDs) or micro - LEDs (micro light - emitting diodes) formed of inorganic materials with high reliability and excellent luminous efficiency have been used. In addition, pixel circuits for driving LEDs are configured by a pulse - amplitude modulation (PAM) method representing gray levels by the amplitude of a driving current and / or a pulse - width modulation (PWM) method representing gray levels by the pulse width of a driving current. Summary of the invention

[0007] An object to be achieved by the present disclosure is to provide a display device in which a plurality of sub - pixels share one PAM circuit to reduce the number of transistors.

[0008] Another object to be achieved by the present disclosure is to provide a display device in which the number of transistors provided in each of a plurality of sub - pixels is reduced to reduce the design area of each sub - pixel.

[0009] Yet another object to be achieved by the present disclosure is to provide a display device in which the design area of each of a plurality of sub - pixels is reduced to achieve high resolution.

[0010] Yet another object to be achieved by the present disclosure is to provide a display device in which color coordinate distortion of light - emitting diodes in a low - current band is minimized.

[0011] Yet another object to be achieved by the present disclosure is to provide a display device in which the emission timing of each of a plurality of sub - pixels sharing a PAM circuit can be independently controlled.

[0012] Another object to be achieved by the present disclosure is to provide a display device that compensates for the threshold voltage of a driving transistor in each of a PAM circuit and a PWM circuit using an external compensation method.

[0013] Another object to be achieved by the present disclosure is to provide a display device that compensates for the threshold voltage of a driving transistor in each of a PAM circuit and a PWM circuit using an internal compensation method.

[0014] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0015] To achieve the above object, according to one aspect of the present disclosure, a display device includes: a display panel including a plurality of pixel groups, each pixel group of the plurality of pixel groups including a plurality of light-emitting diodes; a plurality of pulse amplitude modulation (PAM) circuits, each PAM circuit being connected to one pixel group of the plurality of pixel groups; a set of pulse width modulation (PWM) circuits, wherein a corresponding plurality of PWM circuits in the set of PWM circuits are included in each pixel group of the plurality of pixel groups, and are connected to the PAM circuit connected to the pixel group and connected to the plurality of light-emitting diodes included in the pixel group, wherein, in each pixel group of the plurality of pixel groups, the corresponding plurality of PWM circuits are connected in parallel to an output terminal of the PAM circuit connected to the pixel group. Accordingly, a plurality of PWM circuits share one PAM circuit to reduce the total number of transistors and simplify the structure of the display device.

[0016] Other detailed matters of the exemplary embodiment are included in the detailed description and the drawings.

[0017] According to the present disclosure, a plurality of sub-pixels share one PAM circuit to reduce the number of transistors.

[0018] According to the present disclosure, the number of transistors provided in each of the plurality of sub-pixels is reduced to reduce the design area of the sub-pixel.

[0019] According to the present disclosure, the design area of each of the plurality of sub-pixels is reduced to implement a display device with high resolution.

[0020] According to the present disclosure, a driving current not including a low current band is supplied to a light-emitting diode that has color coordinate distortion to minimize the color coordinate distortion.

[0021] According to the present disclosure, the emission timing and gray level of each of the plurality of sub-pixels sharing one PAM circuit can be independently controlled.

[0022] According to the present disclosure, an external compensation method for directly sensing and compensating the threshold voltage of driving transistors in each of a PAM circuit and a PWM circuit is used to reduce the luminance difference between a plurality of sub-pixels.

[0023] According to the present disclosure, an internal compensation method for internally sampling and compensating the threshold voltage of driving transistors in each of a PAM circuit and a PWM circuit is used to reduce the luminance difference between a plurality of sub-pixels.

[0024] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects, features, and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0026] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 2 is a schematic diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 3 is a circuit diagram of a first pixel group of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figures 4A to 4C is a driving timing diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0030] Figure 5A is a circuit diagram of a first pixel group of a display device during an initialization period according to an exemplary embodiment of the present disclosure;

[0031] Figure 5B is a circuit diagram of a first pixel group of a display device during a data writing period according to an exemplary embodiment of the present disclosure;

[0032] Figure 5C is a circuit diagram of a first pixel group of a display device during an emission period according to an exemplary embodiment of the present disclosure;

[0033] Figure 6 is a timing diagram of external compensation of a PAM circuit of a display device according to an exemplary embodiment of the present disclosure;

[0034] Figure 7 is a circuit diagram of a first pixel group of a display device during an external compensation period of a PAM circuit according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 is a timing diagram of external compensation of a PWM circuit of a display device according to an exemplary embodiment of the present disclosure;

[0036] Figure 9 is a circuit diagram of a first pixel group of a display device according to an exemplary embodiment of the present disclosure during an external compensation period of a PWM circuit;

[0037] Figure 10 is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure;

[0038] Figure 11 is a driving timing diagram of sub-pixels of a display device according to another exemplary embodiment of the present disclosure;

[0039] Figure 12A is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a first initialization period;

[0040] Figure 12B is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a second initialization period;

[0041] Figure 12C is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a sampling and data writing period of a first PWM circuit;

[0042] Figure 12D is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a first PWM circuit and a sampling and data writing period of a second PWM circuit;

[0043] Figure 12E is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a second PWM circuit and a sampling and data writing period of a third PWM circuit; and

[0044] Figure 12F is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a third PWM circuit. Detailed Embodiments

[0045] Advantages and features of the present disclosure, and methods for achieving these advantages and features, will become apparent by referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various forms. The exemplary embodiments are provided only as examples, so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0046] The shapes, sizes, ratios, angles, numbers, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, like reference numerals generally denote like elements. Further, in the following description of the present disclosure, detailed descriptions of known related arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising," "having," and "consisting of" used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only." Any reference to the singular may include the plural, unless otherwise expressly stated.

[0047] Components are interpreted to include a normal error range, even if not explicitly stated.

[0048] When terms such as "on," "above," "below," and "next to" are used to describe the positional relationship between two parts, unless these terms are used together with the term "immediately" or "directly," one or more parts may be located between these two parts.

[0049] When an element or layer is disposed "on" another element or layer, the element or layer may be directly disposed on the other element or layer, or other layers or other elements may be interposed therebetween.

[0050] Although terms such as "first," "second," etc. are used to describe each component, these components are not limited by these terms. These terms are merely used to distinguish one component from other components. Therefore, in the technical concept of the present disclosure, the first component mentioned below may be the second component.

[0051] Throughout the specification, like reference numerals generally denote like elements.

[0052] For convenience of description, the dimensions and thicknesses of each component shown in the drawings are shown, but the present disclosure is not limited to the dimensions and thicknesses of the components shown.

[0053] The features of the various embodiments of the present disclosure may be partially or wholly attached to or combined with each other, and may be interrelated and operated in various ways technically, and the embodiments may be executed independently of each other or in relation to each other.

[0054] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0055] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. In Figure 1 , for ease of description, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC among various components of the display device 100 are shown.

[0056] Referring to Figure 1 , the display device 100 includes: a display panel PN including a plurality of sub-pixels SP; a gate driver GD and a data driver DD that supply various signals to the display panel PN; and a timing controller TC that controls the gate driver GD and the data driver DD.

[0057] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Although in Figure 1 one gate driver GD is shown as being disposed at a distance from one side of the display panel PN, the number and arrangement of the gate drivers GD are not limited thereto.

[0058] The data driver DD supplies data voltages to a plurality of data lines DL according to a plurality of data control signals and image data supplied from the timing controller TC. The data driver DD can convert the image data into data voltages using a reference gamma voltage and supply the converted data voltages to the plurality of data lines DL.

[0059] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals input from the outside such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. The timing controller TC supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0060] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP can be formed at the intersections of the scan lines SL and the data lines DL.

[0061] In the display panel PN, an active area AA and a non-active area NA can be defined.

[0062] The active region AA is the region where an image is displayed in the display device 100. In the active region AA, a plurality of sub-pixels SP that constitute a plurality of pixels and a pixel circuit for driving the plurality of sub-pixels SP can be provided. The sub-pixel SP is the smallest unit that constitutes the active region AA, and m sub-pixels SP can form one pixel, where m is an integer greater than 1. In each of the plurality of sub-pixels SP, a thin-film transistor for driving a plurality of light-emitting diodes EL can be provided. The plurality of light-emitting diodes EL can be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel PN, the light-emitting diode EL can be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0063] In the active region AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines can include a plurality of data lines DL for supplying data voltages to each of the plurality of sub-pixels SP and a plurality of scan lines SL for supplying scan signals to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active region AA to connect to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active region AA to connect to the plurality of sub-pixels SP. In addition, in the active region AA, a low-potential power line, a high-potential power line, etc. can also be provided, but are not limited thereto.

[0064] The non-active region NA is a region where no image is displayed, so that the non-active region NA can be defined as a region extending from the active region AA. In the non-active region NA, link lines, pad electrodes, or driving ICs such as a gate driver IC or a data driver IC for transmitting signals to the sub-pixels SP of the active region AA can be provided.

[0065] Among them, the non-active region NA can be located on the rear surface of the display panel PN, that is, the surface on which no sub-pixels SP are provided, or can be omitted, and is not limited to as shown in the drawings.

[0066] Among them, drivers such as a gate driver GD, a data driver DD, and a timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-active region NA in a gate-in-panel (GIP) manner or between a plurality of sub-pixels SP in the active region AA in a gate-in-active (GIA) manner.

[0067] For example, the data driver DD and the timing controller TC are formed in a separate flexible film and printed circuit board. The display panel PN can be electrically connected to the data driver DD and the timing controller TC by bonding the flexible film and the printed circuit board to the pad electrodes formed in the non-active region NA of the display panel PN.

[0068] As another example, when the gate driver GD is mounted in the active area AA in the GIA manner and side lines are formed to connect signal lines on the front surface of the display panel PN to pad electrodes on the rear surface of the display panel PN to bond a flexible film and a printed circuit board to the rear surface of the display panel PN, the non-active area NA on the front surface of the display panel PN can be minimized. Therefore, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel with substantially no bezel can be achieved.

[0069] Hereinafter, reference will be made to Figure 2 describe the plurality of sub-pixels SP in more detail.

[0070] Figure 2 is a schematic diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0071] Referring to Figure 2 , the plurality of sub-pixels SP include a plurality of first sub-pixels SP1, a plurality of second sub-pixels SP2, and a plurality of third sub-pixels SP3. Each of the plurality of sub-pixels SP includes a light-emitting diode EL and a pixel circuit to emit light independently. The plurality of sub-pixels SP may include first sub-pixels SP1, second sub-pixels SP2, and third sub-pixels SP3 that emit different color lights. For example, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but is not limited thereto.

[0072] The plurality of first sub-pixels SP1 may be arranged to form a plurality of columns, and the plurality of second sub-pixels SP2 may be arranged in columns adjacent to the columns in which the plurality of first sub-pixels SP1 are arranged. The plurality of third sub-pixels SP3 may be arranged in columns adjacent to the columns in which the plurality of first sub-pixels SP1 and the plurality of second sub-pixels SP2 are arranged. That is, the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, and the plurality of third sub-pixels SP3 may be arranged in different columns. Therefore, the plurality of sub-pixels SP may be arranged such that the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 are repeatedly arranged in this order in the row direction.

[0073] Among them, the plurality of first sub-pixels SP1, the plurality of second sub-pixels SP2, and the plurality of third sub-pixels SP3 may respectively form a plurality of first pixel groups GSP1, a plurality of second pixel groups GSP2, and a plurality of third pixel groups GSP3. Each of the plurality of pixel groups may be formed by k sub-pixels SP, where k is an integer greater than 1. Each of the plurality of pixel groups may include k pulse width modulation (PWM) circuits and one pulse amplitude modulation (PAM) circuit.

[0074] In this case, each of the plurality of sub-pixels SP includes a PWM circuit PWM, a PAM circuit PAM, and a light-emitting diode EL, and the PAM circuits PAM of the plurality of sub-pixels SP are integrated into one, such that the plurality of sub-pixels SP can be defined as sharing one PAM circuit PAM. One pixel group composed of k sub-pixels SP can be defined as including k PWM circuits PWM and one PAM circuit PAM (for example, a single PAM circuit PAM). Therefore, the display device includes a set of PWM circuits, and corresponding ones of the plurality of PWM circuits in the set of PWM circuits are included in each pixel group.

[0075] The PWM circuit PWM is a circuit that represents a gray level by the pulse width of a driving current. When the PWM circuit PWM is used, the time for the light-emitting diode EL to emit light is adjusted by configuring the pulse width of the driving current differently to display an image with various gray levels. At this time, the pulse width can be represented by the duty ratio of the driving current or the duration of the driving current. For example, when displaying an image with a low gray level, the PWM circuit PWM shortens the pulse width of the driving current, for example, reduces the duty ratio of the driving current or the output duration of the driving current, to reduce the emission period of the light-emitting diode EL and display an image with a low gray level. Conversely, when displaying an image with a high gray level, the PWM circuit PWM increases the pulse width of the driving current, for example, increases the duty ratio of the driving current or the output duration of the driving current, to increase the emission period of the light-emitting diode EL and display an image with a high gray level.

[0076] The PAM circuit PAM is a circuit that represents a gray level by the amplitude of a driving current. When the PAM circuit PAM is used, the time for the light-emitting diode EL to emit light is adjusted by configuring the amplitude of the driving current, that is, the intensity of the driving current, differently to display an image with various gray levels. For example, when displaying an image with a low gray level, the PAM circuit PAM reduces the intensity of the driving current to reduce the brightness of the light emitted from the light-emitting diode EL and display an image with a low gray level. Conversely, when displaying an image with a high gray level, the PAM circuit PAM increases the intensity of the driving current to increase the brightness of the light emitted from the light-emitting diode EL and display an image with a high gray level.

[0077] Refer again to Figure 2, each of the plurality of first pixel groups GSP1 may include k first sub-pixels SP1 arranged in the same column. Each of the plurality of first pixel groups GSP1 may include k first sub-pixels SP1 continuously arranged in the same column, and each of the k first sub-pixels SP1 may include a PAM circuit PAM and a PWM circuit PWM. At this time, the k first sub-pixels SP1 may share one PAM circuit PAM. Specifically, each of the k first sub-pixels SP1 forming one first pixel group GSP1 may include a corresponding PWM circuit PWM that operates independently of other PWM circuits PWM. At this time, the k first sub-pixels SP1 may share one PAM circuit PAM. Therefore, one first pixel group GSP1 includes one PAM circuit PAM, and the k PWM circuits PWM of the k first sub-pixels SP1 in one first pixel group GSP1 may be connected in parallel to one PAM circuit PAM.

[0078] That is to say, in the first pixel group GSP1, k PWM circuits PWM and one PAM circuit PAM may be provided to drive k first sub-pixels SP1. For example, the first pixel group GSP1 may include one PAM circuit PAM and a plurality of PWM circuits PWM, and the plurality of PWM circuits PWM may include a first PWM circuit PWM1, a second PWM circuit PWM2, and a third PWM circuit PWM3.

[0079] At this time, an emission control transistor ET may be connected between each of the plurality of PWM circuits PWM and the PAM circuit PAM. For example, a first emission control transistor ET turned on or off by a first emission control signal EM1 may be connected between the first PWM circuit PWM1 and the PAM circuit PAM. A second emission control transistor ET turned on or off by a second emission control signal EM2 may be connected between the second PWM circuit PWM2 and the PAM circuit PAM. A third emission control transistor ET turned on or off by a third emission control signal EM3 may be connected between the third PWM circuit PWM3 and the PAM circuit PAM. The plurality of emission control transistors ET may control the driving timings of each PWM circuit PWM in the plurality of PWM circuits PWM, which will be described in more detail with reference to Figure 3 More detailed description.

[0080] The plurality of second pixel groups GSP2 and the plurality of third pixel groups GSP3 may be formed in substantially the same configuration as the plurality of first pixel groups GSP1.

[0081] Specifically, each of the multiple second pixel groups GSP2 may include k second sub-pixels SP2 arranged in the same column. Each of the multiple second pixel groups GSP2 may include k second sub-pixels SP2 continuously arranged in the same column, and each of the k second sub-pixels SP2 may include a PAM circuit PAM and a PWM circuit PWM. At this time, the PAM circuits PAM of the k second sub-pixels SP2 are integrated such that the k second sub-pixels SP2 can share one PAM circuit PAM. Specifically, each of the k second sub-pixels SP2 forming one second pixel group GSP2 may include a PWM circuit PWM that operates independently. The k second sub-pixels SP2 can share one PAM circuit PAM. Therefore, in one second pixel group GSP2, k PWM circuits PWM and one PAM circuit PAM can be provided to drive the k second sub-pixels SP2.

[0082] Each of the multiple third pixel groups GSP3 may include k third sub-pixels SP3 arranged in the same column. Each of the multiple third pixel groups GSP3 may include k third sub-pixels SP3 continuously arranged in the same column, and each of the k third sub-pixels SP3 may include a PAM circuit PAM and a PWM circuit PWM. At this time, the PAM circuits PAM of the k third sub-pixels SP3 are integrated such that the k third sub-pixels SP3 can share one PAM circuit PAM. Specifically, each of the k third sub-pixels SP3 forming one third pixel group GSP3 may include a PWM circuit PWM that operates independently. The k third sub-pixels SP3 can share one PAM circuit PAM. Therefore, in one third pixel group GSP3, k PWM circuits PWM and one PAM circuit PAM can be provided to drive the k third sub-pixels SP3.

[0083] Although three sub-pixels SP are shown as being included in one pixel group in Figure 2 , this is illustrative, and the number of sub-pixels SP included in one pixel group is not limited thereto.

[0084] Hereinafter, the PAM circuit PAM and the PWM circuit PWM forming one pixel group will be described in detail with reference to Figure 3 .

[0085] Figure 3 is a circuit diagram of a first pixel group of a display device according to an exemplary embodiment of the present disclosure. Although only the circuit diagram of the first pixel group GSP1 among the multiple pixel groups is shown in Figure 3 , the circuit diagrams of the second pixel group GSP2 and the third pixel group GSP3 are substantially the same as the circuit diagram of the first pixel group GSP1.

[0086] Refer toFigure 3 , a plurality of transistors are provided in a first pixel group GSP1. The plurality of transistors can be N-type transistors or P-type transistors. In an N-type transistor, the carriers are electrons, such that electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a P-type transistor, the carriers are holes, such that holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one of the plurality of transistors can be an N-type transistor, and the other transistors of the plurality of transistors can be P-type transistors.

[0087] Hereinafter, it is assumed that the plurality of transistors are N-type transistors, but it is not limited thereto.

[0088] First, a plurality of first sub-pixels SP1 forming a first pixel group GSP1 share a PAM circuit PAM. The PAM circuit PAM includes a first switching transistor ST1, a first driving transistor DT1, a first sensing transistor SST1, and a first capacitor C1. The PAM circuit PAM can be connected to a first data line, a first scan line, a sensing line, a reference line, and a high potential power line VDD.

[0089] The first switching transistor ST1 is a transistor that is turned on by a first scan signal SCAN1 to transmit a first data voltage Data_PAM to the first driving transistor DT1. The gate electrode of the first switching transistor ST1 is connected to the first scan line, the drain electrode is connected to the first data line, and the source electrode is connected to the gate electrode of the first driving transistor DT1 that serves as a first node N1. The first switching transistor ST1 is turned on by the first scan signal SCAN1 from the first scan line to transmit the first data voltage Data_PAM of the first data line to the gate electrode of the first driving transistor DT1.

[0090] The first driving transistor DT1 is a transistor that controls the intensity of a driving current based on the first data voltage Data_PAM transmitted from the first switching transistor ST1. The gate electrode of the first driving transistor DT1 is connected to the first node N1, the drain electrode is connected to the high potential power line VDD, and the source electrode is connected to a second node N2. The driving current of the PAM circuit PAM can be output from the first driving transistor DT1 to each of the plurality of PWM circuits PWM.

[0091] The first sensing transistor SST1 is a transistor that senses the threshold voltage of the first driving transistor DT1 to compensate for the threshold voltage difference of the first driving transistor DT1. The gate electrode of the first sensing transistor SST1 is connected to the sensing line, the drain electrode is connected to the reference line, and the source electrode is connected to the second node N2. The first sensing transistor SST1 is turned on by a sensing signal Sense from the sensing line to connect the second node N2, which is the source electrode of the first driving transistor DT1, to the reference line.

[0092] Next, when the light-emitting diode EL emits light, the first capacitor C1 maintains the potential difference between the gate electrode and the source electrode of the first driving transistor DT1 to supply a constant driving current. The first capacitor C1 includes a plurality of capacitor electrodes, and some of the capacitor electrodes are connected to the first node N1, and the remaining capacitor electrodes are connected to the second node N2.

[0093] Next, each of the plurality of PWM circuits includes a second switching transistor ST2, a second driving transistor DT2, an emission control transistor ET, a second sensing transistor SST2, a third sensing transistor SST3, a second capacitor C2, and a third capacitor C3. The PWM circuit PWM can be connected to a second data line, a second scan line, a third scan line, a sensing line, a reference line, and a low-potential power line VSS. Each of the plurality of PWM circuits PWM can be electrically connected to the second node N2 which is the output terminal of the PAM circuit PAM, and a driving current is output from the output terminal. That is, the plurality of PWM circuits PWM can be connected in parallel to one PAM circuit PAM.

[0094] First, the second switching transistor ST2 is a transistor that is turned on by the second scan signal SCAN2 to transmit the second data voltage Data_PWM to the second driving transistor DT2. The gate electrode of the second switching transistor ST2 is connected to the second scan line, the drain electrode is connected to the second data line, and the source electrode is connected to the gate electrode of the second driving transistor DT2 which is the third node N3. The second switching transistor ST2 is turned on by the second scan signal SCAN2 from the second scan line to transmit the second data voltage Data_PWM of the second data line to the gate electrode of the second driving transistor DT2.

[0095] The second driving transistor DT2 is a transistor that controls the driving current based on the second data voltage Data_PWM transmitted from the second switching transistor ST2. The gate electrode of the second driving transistor DT2 is connected to the third node N3, the drain electrode is connected to the fourth node N4, and the source electrode is connected to the fifth node N5. The second driving transistor DT2 is turned on to supply a driving current to the light-emitting diode EL.

[0096] The second sensing transistor SST2 is a transistor that senses the threshold voltage of the second driving transistor DT2 to compensate for the threshold voltage difference of the second driving transistor DT2. The gate electrode of the second sensing transistor SST2 is connected to the sensing line, the drain electrode is connected to the reference line, and the source electrode is connected to the fifth node N5. The second sensing transistor SST2 is turned on by the sensing signal Sense from the sensing line to connect the fifth node N5 which is the source electrode of the second driving transistor DT2 to the reference line.

[0097] The emission control transistor ET is a transistor that blocks or connects the path through which the drive current flows between the PAM circuit PAM and the PWM circuit PWM. The gate electrode of the emission control transistor ET is connected to the emission control line, the drain electrode is connected to the second node N2 that is the output terminal of the PAM circuit PAM, and the source electrode is connected to the fourth node N4 that is the drain electrode of the second drive transistor DT2. The emission control transistor ET is turned on by the emission control signal EM from the emission control line to transmit the drive current from the PAM circuit PAM to the second drive transistor DT2.

[0098] At this time, the emission control transistors ET of each of the plurality of PWM circuits PWM can be connected to different emission control lines. Each of the plurality of PWM circuits PWM is connected to a different emission control line to independently control the emission period of the light-emitting diode EL connected to each of the plurality of PWM circuits PWM. That is to say, the emission period of each of the plurality of PWM circuits PWM can be controlled individually. For example, one of the emission control transistors ET of the three PWM circuits PWM is connected to the first emission control line to be applied with the first emission control signal EM1. Another emission control transistor ET is connected to the second emission control line to be applied with the second emission control signal EM2. Another emission control transistor ET is connected to the third emission control line to be applied with the third emission control signal EM3. Therefore, the first emission control signal EM1, the second emission control signal EM2, and the third emission control signal EM3 are respectively applied to the first emission control line, the second emission control line, and the third emission control line. Therefore, the on and off operations of the emission control transistors ET of the plurality of PWM circuits PWM can be independently controlled.

[0099] Among them, in the present disclosure, the PWM circuit PWM is only referred to as the plurality of PWM circuits PWM without distinction. However, the plurality of PWM circuits PWM can be respectively defined as the first PWM circuit connected to the first emission control line, the second PWM circuit connected to the second emission control line, and the third PWM circuit connected to the third emission control line, but not limited thereto.

[0100] Next, the third sensing transistor SST3 is a transistor that supplies a voltage to the drain electrode of the second driving transistor DT2 when sensing the threshold voltage of the second driving transistor DT2. The gate electrode of the third sensing transistor SST3 is connected to the third scan line, the drain electrode is connected to the sensing voltage line, and the source electrode is connected to the drain electrode of the second driving transistor DT2, which is the fourth node N4. The third sensing transistor SST3 is turned on by the third scan signal SCAN3 of the third scan line and transmits the sensing voltage V_sense to the drain electrode of the second driving transistor DT2. The sensing current can flow from the drain electrode to the source electrode of the second driving transistor DT2 through the sensing voltage V_sense. The second sensing transistor SST2 transmits the sensing current to the reference line to sense the threshold voltage of the second driving transistor DT2. Specifically, the drain electrode of the first driving transistor DT1 is connected to the high-potential power line VDD, such that the sensing current can flow even if the third sensing transistor SST3 is not connected. However, the drain electrode of the second driving transistor DT2 is not connected to a separate power line, such that the sensing current may not flow in the second driving transistor as in the first driving transistor DT1. Therefore, only when the third sensing transistor SST3 is connected to the drain electrode of the second driving transistor DT2 to sense the threshold voltage, the sensing voltage V_sense is supplied to the drain electrode of the second driving transistor DT2 to make the sensing current flow.

[0101] Wherein, one third sensing transistor SST3 can be connected to the fourth node N4 of each PWM circuit PWM among a plurality of PWM circuits PWM. That is, a plurality of PWM circuits PWM can share one third sensing transistor SST3. Therefore, a plurality of PWM circuits PWM include one third sensing transistor SST3 to reduce the total number of transistors and simplify the design.

[0102] The second capacitor C2 is a capacitor connected between the sweep line and the third node N3 to transmit the sweep signal Sweep of the sweep line to the third node N3. The second capacitor C2 includes a plurality of capacitor electrodes, and some capacitor electrodes are connected to the sweep line, and the remaining capacitor electrodes are connected to the third node N3, which is the gate electrode of the second driving transistor DT2. The sweep signal Sweep applied to the sweep line linearly changes. During the emission period, when the sweep signal Sweep is applied to one end of the second capacitor C2, a coupling voltage can be generated in the floating gate electrode of the second driving transistor DT2. Therefore, the voltage of the gate electrode of the second driving transistor DT2 is coupled to the sweep signal Sweep to be decreased or increased, and the second driving transistor DT2 can be turned off or on.

[0103] When the light-emitting diode EL emits light, the third capacitor C3 maintains the potential difference between the gate electrode and the source electrode of the second driving transistor DT2 to supply a constant driving current. The third capacitor C3 includes a plurality of capacitor electrodes, some of the capacitor electrodes are connected to the third node N3, and the remaining capacitor electrodes are connected to the fifth node N5.

[0104] Next, the light-emitting diode EL is connected to the fifth node N5 of each PWM circuit PWM among the plurality of PWM circuits PWM. The light-emitting diode EL includes an anode and a cathode. The anode of the light-emitting diode EL is connected to the fifth node N5, and the cathode is connected to the low-potential power line VSS supplied with the low-potential power voltage. Therefore, the light-emitting diode EL can emit light based on the driving current transmitted from the second driving transistor DT2 to the anode.

[0105] Among them, a micro LED having excellent luminous efficiency can be mainly used as the light-emitting diode EL. In the micro LED, the color coordinates are distorted in the low-current band. When a driving current in the low-current band is supplied to the light-emitting diode EL according to the characteristics of the image to be displayed, the color coordinates of the light-emitting diode EL are distorted, thereby reducing the image display quality.

[0106] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the first data voltage Data_PAM having a constant value is applied to the PAM circuit PAM. Therefore, the color coordinate distortion of the light-emitting diode EL generated in the low-current band can be suppressed, and the light-emitting diode EL can be stably driven. The PAM circuit is a circuit configured to adjust the amplitude of the driving current, that is, the intensity of the driving current. If only the first data voltage Data_PAM having a specific value is applied to the PAM circuit PAM, the PAM circuit PAM can generate a driving current having a constant intensity at all times and output the driving current to the PWM circuit PWM. That is, the PAM circuit PAM can generate and output a driving current that is always constant regardless of the gray level of the image to be displayed. At this time, the first data voltage Data_PAM can be set so that the driving current primarily generated in the PAM circuit PAM is fixed to a current that does not include the low-current band. Therefore, the first data voltage Data_PAM is fixed to a specific value to supply a driving current having a constant intensity to the light-emitting diode EL at all times, so that color coordinate distortion can be prevented from occurring.

[0107] At this time, the first data voltage Data_PAM applied to the PAM circuit can be determined according to the efficiency of the light-emitting diodes EL of the pixel group in which the PAM circuit PAM is provided. That is to say, the first data voltage Data_PAM has a constant value depending on the color of the light-emitting diodes EL of the pixel group. Different types of light-emitting diodes EL can be provided in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in the first sub-pixel SP1 as the red sub-pixel SP, a red light-emitting diode that emits red light can be provided. In the second sub-pixel SP2 as the green sub-pixel SP, a green light-emitting diode that emits green light can be provided. In the third sub-pixel SP3 as the blue sub-pixel SP, a blue light-emitting diode that emits blue light can be provided. The red light-emitting diode, the green light-emitting diode, and the blue light-emitting diode that emit different colors of light have different efficiencies, so that even if a driving current of the same intensity is supplied, the brightness of the light emitted from the red light-emitting diode, the green light-emitting diode, and the blue light-emitting diode may be different. Therefore, the first data voltage Data_PAM of the PAM circuit PAM supplied to each of the first pixel group GSP1, the second pixel group GSP2, and the third pixel group GSP3 can be determined in consideration of the characteristics of the light-emitting diodes EL of each pixel group.

[0108] Among them, when using the PAM circuit PAM that generates a driving current with a constant intensity all the time, it may be difficult to represent various gray levels. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the PWM circuit PWM that controls the pulse width of the driving current is used together to display an image with various gray levels. The PWM circuit PWM is connected between the PAM circuit PAM and the light-emitting diode EL to adjust the duty cycle or duration during which the driving current generated in the PAM circuit PAM is supplied to the light-emitting diode EL. The PWM circuit PWM adjusts the duty cycle or duration during which the driving current is supplied to the light-emitting diode EL to display an image with various gray levels. At this time, different from the first data voltage Data_PAM, the second data voltage Data_PWM applied to the PWM circuit PWM may vary according to the gray level. For example, the value of the second data voltage Data_PWM output for a low gray level image and the value of the second data voltage Data_PWM output for a high gray level image may be different. The PWM circuit PWM can differently adjust the emission time of the light-emitting diode EL based on the second data voltage Data_PWM. Therefore, the amplitude of the second data voltage Data_PWM depends on the image. For example, the second data voltage Data_PWM may have a first amplitude corresponding to the first image at the first time, such that the driving current is supplied to the second driving transistor DT2 for the first duration, and the second data voltage Data_PWM has a second amplitude corresponding to the second image at the second time, such that the driving current is supplied to the second driving transistor DT2 for a second duration different from the first duration. Therefore, the display device 100 according to an exemplary embodiment of the present disclosure uses the PAM circuit PAM and the PWM circuit PWM together to stably drive the light-emitting diode EL and improve the display quality of the image while suppressing color coordinate distortion in the low current band. The PAM circuit PAM generates a driving current with a constant intensity in a band other than the low current band, and the PWM circuit PWM adjusts the pulse width of the driving current generated in the PAM circuit to supply the driving current to the light-emitting diode EL to represent the gray level.

[0109] Hereinafter, reference will be made to Figures 4A to 5C describe in more detail the driving process of the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure.

[0110] Figures 4A to 4C is a driving timing diagram of the sub-pixel of the display device according to an exemplary embodiment of the present disclosure. Figure 5A is a circuit diagram of the first pixel group of the display device according to an exemplary embodiment of the present disclosure during the initialization period. Figure 5BIt is a circuit diagram of a first pixel group of a display device according to an exemplary embodiment of the present disclosure during a data writing period. Figure 5C It is a circuit diagram of a first pixel group of a display device according to an exemplary embodiment of the present disclosure during a light emission period. Figure 3 , Figures 5A to 5C , Figure 7 , Figure 9 In, add "(n)" after the reference signs "EM1", "EM2", "EM3", "Sweep" to indicate that the corresponding signal is a signal applied to the corresponding component in the pixel group located in the n-th row, where n is a positive integer.

[0111] Referring to Figure 4A , the plurality of sub-pixels SP of the display device 100 according to an exemplary embodiment of the present disclosure can be driven in the order of an initialization period, a data writing period, and a light emission period. The period between time A and time B is the initialization period, the period between time B and time D is the data writing period, and the light emission period is after time D.

[0112] Among them, each of the plurality of PWM circuits is connected to a different sweep line, a second scan line, and a sense line, so that the driving timings of the initialization period and the data writing period can be independently controlled. For example, the first PWM circuit is connected to the n-th line to which the n-th sweep signal Sweep(n), the n-th second scan signal SCAN2(n), and the n-th sense signal Sense(n) are applied among the plurality of lines. The second PWM circuit is connected to the (n + 1)-th line to which the (n + 1)-th sweep signal sweep(n + 1), the (n + 1)-th second scan signal SCAN2(n + 1), and the (n + 1)-th sense signal Sense(n + 1) are applied among the plurality of lines. The third PWM circuit is connected to the (n + 2)-th line to which the (n + 2)-th sweep signal Sweep(n + 2), the (n + 2)-th second scan signal SCAN2(n + 2), and the (n + 2)-th sense signal Sense(n + 2) are applied among the plurality of lines. At this time, the driving timings of the initialization period and the data writing period of each of the first PWM circuit, the second PWM circuit, and the third PWM circuit can be determined according to the timings when signals are output to each of the n-th line, the (n + 1)-th line, and the (n + 2)-th line.

[0113] In Figure 4AFor ease of description, the following will be described: The n-th sweep signal Sweep(n), the (n + 1)-th sweep signal Sweep(n + 1), and the (n + 2)-th sweep signal Sweep(n + 2) are shown as being unified into one sweep signal Sweep. The n-th second scan signal SCAN2(n), the (n + 1)-th second scan signal SCAN2(n + 1), and the (n + 2)-th second scan signal SCAN2(n + 2) are shown as being unified into one second scan signal SCAN2. The n-th sense signal Sense(n), the (n + 1)-th sense signal Sense(n + 1), and the (n + 2)-th sense signal Sense(n + 2) are shown as being unified into one sense signal Sense. In addition, all of the plurality of PWM circuits PWM are applied with the second data voltage Data_PWM at the same timing. However, each of the plurality of PWM circuits PWM may be applied with the second data voltage Data_PWM at different timings, but is not limited thereto.

[0114] Refer together to Figure 4A and Figure 5A During the initialization period between time A and time B, a high-level sense signal Sense is output to the sense line. Accordingly, the first sense transistor SST1 and the second sense transistor SST2 whose gate electrodes are connected to the sense line are turned on to apply the reference voltage Vref to the second node N2 and the fifth node N5. Accordingly, the source electrodes of the first driving transistor DT1 of the PAM circuit PAM and the second driving transistor DT2 of the PWM circuit PWM can be initialized to the reference voltage Vref.

[0115] Refer together to Figure 4A and Figure 5B During the data writing period between time B and time D, a high-level first scan signal SCAN1 is output to the first scan line, and a high-level second scan signal SCAN2 is output to the second scan line. The first switching transistor ST1 of the PAM circuit PAM is turned on by the first scan signal SCAN1 to transmit the first data voltage Data_PAM to the first node N1. The second switching transistor ST2 of the PWM circuit PWM is turned on by the second scan signal SCAN2 to transmit the second data voltage Data_PWM to the third node N3.

[0116] Among them, in the present disclosure, it is described that the first scan signal SCAN1 and the second scan signal SCAN2 are output in different periods so that the periods for writing the data voltage into the PAM circuit PAM and the PWM circuit PWM are configured differently. However, the data voltage may be written into the PAM circuit PAM and the PWM circuit PWM simultaneously, but is not limited thereto.

[0117] Next, refer to Figure 4Aand Figure 5C During the emission period after time D, a high-level emission control signal EM is output to the emission control line. Therefore, the drive current from the PAM circuit PAM can flow through the turned-on emission control transistor ET to the second drive transistor DT2 of the PWM circuit PWM. The second drive transistor DT2 can transmit the drive current to the light-emitting diode EL according to the sweep signal Sweep applied to the gate electrode. Finally, the light-emitting diode EL can be supplied with drive currents from the first drive transistor DT1 and the second drive transistor DT2 to emit light.

[0118] The second drive transistor DT2 can determine the length of the period during which the light-emitting diode EL actually emits light within the period when the emission control transistor ET is turned on. The actual emission period of the light-emitting diode EL can correspond to the period during which the second drive transistor DT2 is turned on within the period when the emission control transistor ET is turned on. For example, even if the emission control transistor ET is turned on, the second drive transistor DT2 can be turned off to control the light-emitting diode EL not to emit light. As another example, only during a partial period of the period when the emission control transistor ET is turned on, the second drive transistor DT2 is turned on to control the light-emitting diode EL to emit light only during the partial period.

[0119] Among them, the emission signals can be output to the emission control line in various orders. For example, referring to Figure 4B , a plurality of pixel groups are arranged to form a plurality of rows, and include a first emission control signal EM1 (shown as EM1(1), EM1(2)…EM1(n) in Figure 4B ), a second emission control signal EM2 ( Figure 4B shown as EM2(1), EM2(2)…EM2(n)) and a third emission control signal EM3 (in Figure 4BThe emission control signal EM, shown as EM3(1), EM3(2)…EM3(n)) in the figure, can be sequentially applied to pixel groups starting from the pixel group in the uppermost row. The first emission control signal EM1(1), the second emission control signal EM2(1), and the third emission control signal EM3(1) can be sequentially applied to the first emission control line, the second emission control line, and the third emission control line connected to the pixel group in the first row. The first emission control signal EM1(2), the second emission control signal EM2(2), and the third emission control signal EM3(2) can be sequentially applied to the first emission control line, the second emission control line, and the third emission control line connected to the pixel group in the second row. Finally, the first emission control signal EM1(n), the second emission control signal EM2(n), and the third emission control signal EM3(n) can be applied to the first emission control line, the second emission control line, and the third emission control line connected to the pixel group in the lowermost row. Thus, the multiple sub-pixels SP arranged to form multiple rows can emit light sequentially in the order from the sub-pixels SP in the uppermost row to the sub-pixels SP in the lowermost row.

[0120] As another example, referring to Figure 4C , the first emission control signal EM1 (shown as EM1(1), EM1(2)…EM1(n)) in Figure 4C can be first applied to the first emission control line of each pixel group among the multiple pixel groups. In this case, among the three sub-pixels SP included in each pixel group among the multiple pixel groups, only the sub-pixel SP connected to the first emission control line can emit light first. Next, the second emission control signal EM2 (shown as EM2(1), EM2(2)…EM2(n)) in Figure 4C can be applied to the second emission control line of each pixel group among the multiple pixel groups. Thus, the sub-pixel SP connected to the second emission control line can emit light. Finally, the third emission control signal EM3 (shown as EM3(1), EM3(2)…EM3(n)) in Figure 4C can be connected to the third emission control line of each pixel group among the multiple pixel groups. Thus, among the three sub-pixels SP included in each pixel group among the multiple pixel groups, the sub-pixel SP connected to the third emission control line can emit light last.

[0121] Thus, in the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of sub-pixels SP share one PAM circuit PAM to reduce the number of transistors. That is, only the PWM circuit PWM is provided in each of the plurality of sub-pixels SP, and the plurality of PWM circuits PWM are connected in parallel to the output terminal of one PAM circuit PAM to drive the light-emitting diode EL. Therefore, the PAM circuit PAM separately provided in each of the plurality of sub-pixels SP is deleted to reduce the total number of transistors. Accordingly, the design area occupied by one sub-pixel SP can be reduced, and a larger number of sub-pixels SP can be formed in the same area. Thus, the design area of each of the plurality of sub-pixels SP is reduced to implement a display device 100 with high resolution.

[0122] Hereinafter, with reference to Figures 6 to 9 the external compensation process of the PAM circuit PAM and the PWM circuit PWM will be described.

[0123] Figure 6 is a timing diagram of the external compensation of the PAM circuit of the display device according to an exemplary embodiment of the present disclosure. Figure 7 is a circuit diagram of a first pixel group of the display device according to an exemplary embodiment of the present disclosure during the external compensation period of the PAM circuit. Figure 8 is a timing diagram of the external compensation of the PWM circuit of the display device according to an exemplary embodiment of the present disclosure. Figure 9 is a circuit diagram of a first pixel group of the display device according to an exemplary embodiment of the present disclosure during the external compensation period of the PWM circuit.

[0124] In the display device 100 according to an exemplary embodiment of the present disclosure, the threshold voltages of the first driving transistor DT1 of the PAM circuit PAM and the second driving transistor DT2 of the PWM circuit PWM can be sensed and compensated by an external compensation method using a source follower. The threshold voltages can be sensed and compensated only in the state where the display device 100 is turned off, and the threshold voltages of the first driving transistor DT1 of the PAM circuit PAM and the second driving transistor DT2 of the PWM circuit PWM can be sensed in different time periods.

[0125] First, with reference to Figure 6 and Figure 7 , the threshold voltage of the first driving transistor DT1 of the PAM circuit PAM can be sensed in the order of an initialization period, a source follower period, and a sampling period. The period between time A and time B is the initialization period, the period between time B and time C is the source follower period, and the sampling period is after time C.

[0126] During an initialization period between time A and time B, the voltage of the source electrode of the first driving transistor DT1 of the PAM circuit PAM can be initialized. At time A, a high-level sense signal Sense is applied to the sense line to turn on the first sense transistor SST1 and connect the reference line and the second node N2 that serves as the source electrode of the first driving transistor DT1. Accordingly, at time A, the voltage of the source electrode of the first driving transistor DT1 can be initialized.

[0127] Next, during a source-following period between time B and time C, a sense current can flow while maintaining the voltage of the gate electrode of the first driving transistor DT1 of the PAM circuit PAM. At time B, a high-level first scan signal SCAN1 is output to the first scan line to apply a sense data voltage to the gate electrode of the first driving transistor DT1. The sense current can flow from the drain electrode to the source electrode of the first driving transistor DT1, and the voltage of the source electrode of the first driving transistor DT1 can gradually increase. The sense current flowing through the first driving transistor DT1 can flow until the potential difference between the source electrode and the gate electrode of the first driving transistor DT1 is equal to the threshold voltage.

[0128] Finally, during a sampling period after time C, a high-level sense signal Sense is output to the sense line to turn on the first sense transistor SST1. When the sense current does not flow, the analog-to-digital converter can detect the voltage of the source electrode of the first driving transistor DT1 through the turned-on first sense transistor SST1 and the reference line. Accordingly, the threshold voltage of the first driving transistor DT1 can be detected based on the sense data voltage applied to the gate electrode of the first driving transistor DT1 and the voltage of the source electrode of the first driving transistor DT1. Therefore, the data driver DD compensates the first data voltage Data_PAM based on the threshold voltage of the first driving transistor DT1 and outputs the compensated voltage to the sub-pixel SP.

[0129] Next, referring to Figure 8 and Figure 9 , the threshold voltage of the second driving transistor DT2 of the PWM circuit PWM can be sensed in the order of the initialization period, the source-following period, and the sampling period. The period between time A and time B is the initialization period, the period between time B and time C is the source-following period, and the sampling period is after time C.

[0130] During an initialization period between time A and time B, the voltage of the source electrode of the second driving transistor DT2 of the PWM circuit PWM can be initialized. At time A, a high-level sensing signal Sense is applied to the sensing line to turn on the second sensing transistor SST2 and connect the reference line and the fifth node N5 that serves as the source electrode of the second driving transistor DT2. Therefore, at time A, the voltage of the source electrode of the second driving transistor DT2 can be initialized.

[0131] Next, during a source-following period between time B and time C, the voltage of the gate electrode of the second driving transistor DT2 of the PWM circuit PWM is held for sensing the data voltage, and a sensing voltage V_sense is applied to the drain electrode to cause a sensing current to flow in the second driving transistor DT2. At time B, a high-level second scan signal SCAN2 is output to the second scan line to apply the sensing data voltage to the gate electrode of the second driving transistor DT2. A high-level third scan signal SCAN3 is output to the third scan line to turn on the third sensing transistor SST3. During the entire period of the sensing threshold voltage, the third scan line can continuously output the high-level third scan signal SCAN3, and the sensing voltage V_sense can be applied to the fourth node N4 that serves as the drain electrode of the second driving transistor DT2. Therefore, the sensing current can flow from the drain electrode to the source electrode of the second driving transistor DT2, and the voltage of the source electrode of the second driving transistor DT2 can gradually increase. The sensing current flowing through the second driving transistor DT2 can flow until the potential difference between the source electrode and the gate electrode of the second driving transistor DT2 is equal to the threshold voltage.

[0132] Finally, during a sampling period after time C, a high-level sensing signal Sense is output to the sensing line to turn on the second sensing transistor SST2. The analog-to-digital converter can detect the voltage of the source electrode of the second driving transistor DT2 through the turned-on second sensing transistor SST2 and the reference line. Therefore, the threshold voltage of the second driving transistor DT2 can be detected based on the sensing data voltage applied to the gate electrode of the second driving transistor DT2 and the voltage of the source electrode of the second driving transistor DT2. Therefore, the data driver DD compensates the second data voltage Data_PWM based on the threshold voltage of the second driving transistor DT2 and outputs the compensated voltage to the sub-pixel SP.

[0133] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the first sensing transistor SST1 can be used to sense the threshold voltage of the first driving transistor DT1 of the PAM circuit PAM. In addition, the second sensing transistor SST2 and the third sensing transistor SST3 can be used to sense the threshold voltage of the second driving transistor DT2 of the PWM circuit PWM. Therefore, the threshold voltage difference between multiple sub-pixels SP is compensated to apply the first data voltage Data_PAM and the second data voltage Data_PWM, so as to improve the brightness uniformity and the display quality of the image.

[0134] Figure 10 is a circuit diagram of the first pixel group of a display device according to another exemplary embodiment of the present disclosure. In Figures 10 to 12F add “(n)” after the reference numerals “ISCAN”, “SCAN1”, “SCAN2”, “SCAN3”, “SCAN4”, “SCAN5”, “EM1”, “EM2”, “EM3”, “EM4”, “Sweep1”, “Sweep2” and “Sweep3” to illustrate that the corresponding signal is a signal applied to the corresponding component in the pixel group located in the nth row, where n is a positive integer. Figure 10 The display device 1000 includes a circuit that senses and compensates for the threshold voltages of the first driving transistor DT1 of the PAM circuit PAM and the second driving transistor DT2 of the PWM circuit PWM through an internal compensation method. This is different from Figures 1 to 9 the circuit configuration of the sub-pixel SP of the display device 100. However, other configurations are basically the same, so redundant descriptions will be omitted. Although Figure 10 only shows the circuit diagram of the first pixel group GSP1 among multiple pixel groups, the circuits of the second pixel group GSP2 and the third pixel group GSP3 are basically the same as the circuit of the first pixel group GSP1.

[0135] Referring to Figure 10 , a plurality of transistors are provided in one first pixel group GSP1. The plurality of transistors can be N-type transistors in which current flows from the drain electrode to the source electrode or P-type transistors in which current flows from the source electrode to the drain electrode. Hereinafter, it is assumed that the plurality of transistors are P-type transistors, but it is not limited thereto.

[0136] A plurality of first sub-pixels SP1 forming a first pixel group GSP1 share a PAM circuit PAM. The PAM circuit PAM includes a first switching transistor ST1, a second switching transistor ST2, a third switching transistor ST3, a fourth switching transistor ST4, a first driving transistor DT1, a first emission control transistor ET1, and a first capacitor C1. The PAM circuit PAM is connected to a first data line, a first scan line, a second scan line, a first emission control line, a reference line, and a high potential power line VDD.

[0137] The first switching transistor ST1 is a transistor configured to be turned on by a first scan signal SCAN1 to transmit a first data voltage Data_PAM to the inside of the PAM circuit PAM. The gate electrode of the first switching transistor ST1 is connected to the first scan line, the source electrode is connected to the first data line, and the drain electrode is connected to one end of the first capacitor C1 serving as a first node N1. The first switching transistor ST1 is turned on by the first scan signal SCAN1 from the first scan line to transmit the first data voltage Data_PAM of the first data line to the first capacitor C1.

[0138] The second switching transistor ST2 is a transistor that samples the threshold voltage of the first driving transistor DT1 to compensate for the threshold voltage difference between the first driving transistors DT1 of the plurality of sub-pixels SP. The gate electrode of the second switching transistor ST2 is connected to the second scan line, and the source electrode and the drain electrode are connected to a second node N2 and a third node N3. The second switching transistor ST2 shorts the gate electrode and the drain electrode of the first driving transistor DT1, and can form a diode connection of the first driving transistor DT1. In the diode connection, the gate electrode and the drain electrode are shorted so that the transistor operates as a diode.

[0139] The third switching transistor ST3 is a transistor for transmitting a reference voltage Vref to the first node N1. The gate electrode of the third switching transistor ST3 is connected to the first emission control line, the source electrode is connected to the reference line, and the drain electrode is connected to the first node N1. The third switching transistor ST3 can transmit the reference voltage Vref to the first node N1 when a low-level first emission control signal EM1 is applied from the first emission control line, and the first node N1 can be initialized to the reference voltage Vref.

[0140] The fourth switching transistor ST4 is a transistor for transmitting a reference voltage Vref to the fourth node N4. The gate electrode of the fourth switching transistor ST4 is connected to the second scan line, the source electrode is connected to the reference line, and the drain electrode is connected to the fourth node N4. The fourth switching transistor ST4 is turned on by the second scan signal SCAN2 to transmit the reference voltage Vref to the fourth node N4. The reference voltage Vref of the fourth node N4 can be transmitted to the third node N3, which is the drain electrode of the first driving transistor DT1, through the first emission control transistor ET1 turned on together with the fourth switching transistor ST4. The voltages of the gate electrode and the drain electrode of the first driving transistor DT1 can be initialized using the third switching transistor ST3 and the fourth switching transistor ST4, which will be described in more detail with reference to Figures 12A to 12F be described in more detail.

[0141] The first driving transistor DT1 is a transistor that controls the intensity of the driving current based on the first data voltage Data_PAM. The gate electrode of the first driving transistor DT1 is connected to the second node N2, the source electrode is connected to the high-potential power line VDD, and the drain electrode is connected to the third node N3. The driving current of the PAM circuit PAM can be output from the first driving transistor DT1 to each of the plurality of PWM circuits PWM.

[0142] The first emission control transistor ET1 is a transistor for transmitting the driving current from the first driving transistor DT1 to each PWM circuit of the plurality of PWM circuits PWM. The gate electrode of the first emission control transistor ET1 is connected to the first emission control line, the source electrode is connected to the third node N3, and the drain electrode is connected to the fourth node N4. The first emission control transistor is turned on to transmit the reference voltage Vref from the fourth switching transistor ST4 to the drain electrode of the first driving transistor DT1, or to transmit the driving current from the first driving transistor DT1 to each of the plurality of PWM circuits PWM.

[0143] When the light-emitting diode EL emits light, the first capacitor C1 maintains the potential difference between the gate electrode and the drain electrode of the first driving transistor DT1 to supply a constant driving current. The first capacitor C1 includes a plurality of capacitor electrodes, and some of the capacitor electrodes are connected to the first node N1, and the remaining capacitor electrodes are connected to the second node N2.

[0144] Next, a plurality of first sub-pixels SP1 include a plurality of PWM circuits PWM. Each of the plurality of PWM circuits PWM includes a fifth switching transistor ST5, a sixth switching transistor ST6, a second driving transistor DT2, a second emission control transistor ET2, and a second capacitor C2. The plurality of PWM circuits PWM can share and include one initialization transistor IT. The PWM circuit PWM is connected to a second data line, a third scan line, a second emission control line, a sweep frequency line, an initialization line, and a low potential power line VSS. Each of the plurality of PWM circuits PWM can be electrically connected to a fourth node N4, which is an output terminal of a PAM circuit PAM from which a driving current is output. That is, the plurality of PWM circuits PWM can be connected in parallel to one PAM circuit PAM.

[0145] The fifth switching transistor ST5 is a transistor that is turned on by a third scan signal SCAN3 to transfer a second data voltage Data_PWM to the second driving transistor DT2. The gate electrode of the fifth switching transistor ST5 is connected to the third scan line, the source electrode is connected to the second data line, and the drain electrode is connected to the fifth node N5. The fifth switching transistor ST5 is turned on by the third scan signal SCAN3 from the third scan line to transfer the second data voltage Data_PWM of the second data line to the fifth node N5, which is the source electrode of the second driving transistor DT2.

[0146] The sixth switching transistor ST6 is a transistor that samples the threshold voltage of the second driving transistor DT2 to compensate for the threshold voltage difference of the second driving transistor DT2 of the plurality of sub-pixels SP. The gate electrode of the sixth switching transistor ST6 is connected to the third scan line, and the source electrode and the drain electrode are connected to the sixth node N6 and the seventh node N7. The sixth switching transistor ST6 shorts the gate electrode and the drain electrode of the second driving transistor DT2 and forms a diode connection of the second driving transistor DT2.

[0147] The second driving transistor DT2 is a transistor that controls a driving current based on the second data voltage Data_PWM. The gate electrode of the second driving transistor DT2 is connected to the sixth node N6, the source electrode is connected to the fifth node N5, and the drain electrode is connected to the seventh node N7. The second driving transistor DT2 is turned on to supply a driving current to the light emitting diode EL.

[0148] The second emission control transistor ET2 is a transistor that blocks or connects the path through which the drive current flows between the PAM circuit PAM and the PWM circuit PWM. The gate electrode of the second emission control transistor ET2 is connected to any one of the second emission control line, the third emission control line, and the fourth emission control line, and the source electrode is connected to the fourth node N4 that serves as the output terminal of the PAM circuit PAM. In addition, the drain electrode is connected to the fifth node N5 that serves as the source electrode of the second drive transistor DT2. The second emission control transistor ET2 is turned on by the second emission control signal EM2 from the second emission control line to transmit the drive current from the PAM circuit PAM to the second drive transistor DT2.

[0149] The second emission control transistor ET2 of each PWM circuit PWM among the plurality of PWM circuits PWM can be connected to a different emission control line. Each of the plurality of PWM circuits PWM is connected to a different emission control line to independently control the emission period of the light-emitting diode EL connected to each PWM circuit PWM among the plurality of PWM circuits PWM. That is, the emission period of each PWM circuit PWM among the plurality of PWM circuits PWM can be controlled individually. For example, the second emission control transistor ET2 of the first PWM circuit PWM1 among the three PWM circuits PWM is connected to the second emission control line to which the second emission control signal EM2 is applied. The second emission control transistor ET2 of the second PWM circuit PWM2 among the three PWM circuits PWM is connected to the third emission control line to which the third emission control signal EM3 is applied. The second emission control transistor ET2 of the third PWM circuit PWM3 among the three PWM circuits PWM is connected to the fourth emission control line to which the fourth emission control signal EM4 is applied. Therefore, the second emission control signal EM2, the third emission control signal EM3, and the fourth emission control signal EM4 are respectively applied to the second emission control line, the third emission control line, and the fourth emission control line. Therefore, the on and off operations of the second emission control transistor ET2 of the plurality of PWM circuits PWM can be independently controlled.

[0150] The second capacitor C2 is a capacitor that transmits the sweep signal of the sweep line to the sixth node N6 that serves as the gate electrode of the second drive transistor DT2. The second capacitor C2 includes a plurality of second capacitor electrodes, and some of the second capacitor electrodes are connected to the sweep line, and the remaining second capacitor electrodes are connected to the sixth node N6 that serves as the gate electrode of the second drive transistor DT2. When the sweep signal is applied to one end of the second capacitor C2, a coupled voltage can be generated in the gate electrode of the second drive transistor DT2. Therefore, the voltage of the gate electrode of the second drive transistor DT2 is coupled to the sweep signal to decrease or increase, and the second drive transistor DT2 can be turned off or on.

[0151] Each of the second capacitors C2 of the plurality of PWM circuits PWM can also be connected to different sweep lines. Each of the plurality of PWM circuits PWM is connected to a different sweep line to independently control the emission period of the light-emitting diode EL connected to each PWM circuit PWM of the plurality of PWM circuits PWM. For example, the second capacitor C2 of the first PWM circuit PWM1 among the three PWM circuits PWM is connected to the first sweep line to which the first sweep signal Sweep1 is applied. The second capacitor C2 of the second PWM circuit PWM2 among the three PWM circuits PWM is connected to the second sweep line to which the second sweep signal Sweep2 is applied. The second capacitor C2 of the third PWM circuit PWM3 among the three PWM circuits PWM is connected to the third sweep line to which the third sweep signal Sweep3 is applied. Therefore, the first sweep signal Sweep1, the second sweep signal Sweep2, and the third sweep signal Sweep3 are applied to the first sweep line, the second sweep line, and the third sweep line to independently control the on and off operations of the second drive transistor DT2 coupled to the second capacitor C2 in each of the plurality of PWM circuits PWM.

[0152] An initialization transistor IT is connected to the sixth node of each PWM circuit PWM of the plurality of PWM circuits PWM. That is, the plurality of PWM circuits PWM can share one initialization transistor IT. Therefore, the plurality of PWM circuits PWM includes one initialization transistor IT to reduce the total number of transistors and simplify the design.

[0153] The initialization transistor IT is a transistor that is connected to the sixth node N6 of each PWM circuit PWM of the plurality of PWM circuits PWM and initializes the voltage of the gate electrode of the second drive transistor DT2. The gate electrode of the initialization transistor IT is connected to the initialization scan line, the source electrode is connected to the initialization line, and the drain electrode is connected to the sixth node N6 that is the gate electrode of the second drive transistor DT2. The initialization transistor IT is turned on by the initialization scan signal ISCAN of the initialization scan line to transfer the initialization voltage Vini from the initialization line to the gate electrode of the second drive transistor DT2.

[0154] Next, the light-emitting diode EL is connected to the seventh node N7 of each PWM circuit PWM of the plurality of PWM circuits PWM. The light-emitting diode EL includes an anode and a cathode. The anode of the light-emitting diode EL is connected to the seventh node N7, and the cathode is connected to the low-potential power line VSS supplied with the low-potential power voltage. Therefore, the light-emitting diode EL can emit light based on the drive current transferred from the second drive transistor DT2 to the anode.

[0155] Among them, in the display device 1000 according to another exemplary embodiment of the present disclosure, each of the PAM circuit PAM and the plurality of PWM circuits PWM can compensate for the threshold voltage difference between the first driving transistor DT1 and the second driving transistor DT2 by an internal compensation method when the display device 1000 is driven.

[0156] Hereinafter, reference will be made to Figures 11 to 12F The driving process of the sub-pixel SP of the display device 1000 according to another exemplary embodiment of the present disclosure will be described in more detail.

[0157] Figure 11 It is a driving timing diagram of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure. Figure 12A It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a first initialization period. Figure 12B It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a second initialization period. Figure 12C It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a sampling and data writing period of a first PWM circuit. Figure 12D It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a first PWM circuit and a sampling and data writing period of a second PWM circuit. Figure 12E It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a second PWM circuit and a sampling and data writing period of a third PWM circuit. Figure 12F It is a circuit diagram of a first pixel group of a display device according to another exemplary embodiment of the present disclosure during a transmission period of a third PWM circuit.

[0158] Refer to Figure 11, the plurality of sub-pixels SP of the display device 1000 according to another exemplary embodiment of the present disclosure may be driven in the order of a first initialization period, a second initialization period, a sampling and data writing period, and an emission period. The period between time A and time B is the first initialization period, and the period between time B and time C is the second initialization period. The period from time C when the first scan signal SCAN1 and the third scan signal SCAN3 are at a low level is the sampling and data writing period of the PAM circuit PAM and the first PWM circuit PWM1. The period between time D and time F is the emission period of the light-emitting diode EL connected to the first PWM circuit PWM1. The period from time E when the fourth scan signal SCAN4 is at a low level is the sampling and data writing period of the second PWM circuit PWM2, and the period between time F and time H is the emission period of the light-emitting diode EL connected to the second PWM circuit PWM2. The period from time G when the fifth scan signal SCAN5 is at a low level is the sampling and data writing period of the third PWM circuit PWM3, and the period between time H and time I is the emission period of the light-emitting diode EL connected to the third PWM circuit PWM3.

[0159] Among them, different from the display device 100 according to the exemplary embodiment of the present disclosure that directly senses the threshold voltage of the driving transistor through an external compensation method, the display device 1000 according to another exemplary embodiment of the present disclosure uses an internal compensation method. According to the internal compensation method, when the data voltage is written, the threshold voltage of the driving transistor is sampled together for compensation.

[0160] First, referring to Figure 11 and Figure 12A , during the first initialization period between time A and time B, a low-level initialization scan signal ISCAN is output to the initialization scan line. Accordingly, the initialization transistor IT whose gate electrode is connected to the initialization scan line is turned on to apply the initialization voltage Vini to the sixth node N6 which is the gate electrode of the second driving transistor DT2 of the plurality of PWM circuits PWM. Accordingly, during the first initialization period, the voltage of the sixth node N6 which is the voltage of the gate electrode of the second driving transistor DT2 of the plurality of PWM circuits PWM can be initialized to the initialization voltage Vini.

[0161] In addition, although Figure 12AAlthough not shown in the figure, during a first initialization period between time A and time B, some nodes of the PAM circuit PAM can be initialized to the reference voltage Vref. For example, during the period between time A and time B, the first emission control signal EM1 with a low output level turns on the third switching transistor ST3 and the first emission control transistor ET1, thereby transmitting the reference voltage Vref to the first node N1 and the third node N3.

[0162] Next, referring to Figure 11 and Figure 12B , during a second initialization period between time B and time C, the second scan signal SCAN2 with a low level is output to the second scan line. At this time, the first emission control signal EM1 with a low level can be output to the first emission control line simultaneously with the second scan signal SCAN2 with a low level. Therefore, the second switching transistor ST2 and the fourth switching transistor ST4 of the PAM circuit PAM can be turned on by the second scan signal SCAN2, and the third switching transistor ST3 and the first emission control transistor ET1 can be turned on by the first emission control signal EM1. The reference voltage Vref can be transmitted to the fourth node N4, the third node N3, and the second node N2 through the turned-on fourth switching transistor ST4, the first emission control transistor ET1, and the second switching transistor ST2. The voltage of the gate electrode and the drain electrode of the first driving transistor DT1 and the voltage of the fourth node N4 can be initialized to the reference voltage Vref. The reference voltage Vref can be applied to the first node N1 through the turned-on third switching transistor ST3. Therefore, during the second initialization period between time B and time C, the voltage across the first capacitor C1 of the PAM circuit is initialized to the reference voltage Vref, and the voltages of the gate electrode and the drain electrode of the first driving transistor DT1 can also be initialized to the reference voltage Vref.

[0163] Referring to Figure 11 and Figure 12C , during the period when the third scan signal SCAN3 is output at a low level starting from time C, that is, during the sampling and data writing period of the PAM circuit PAM and the first PWM circuit PWM1, the first scan signal SCAN1 with a low level is output to the first scan line, and the third scan signal SCAN3 with a low level is output to the third scan line. The second scan signal SCAN2 that starts to be output at a low level at time B is also continuously output at a low level at time C.

[0164] First, the first switching transistor ST1 of the PAM circuit PAM is turned on by the first scan signal SCAN1 with a low level output at time C, and the first data voltage Data_PAM can be applied to the first node N1 through the turned-on first switching transistor ST1. At this time, the fourth switching transistor ST4 is turned on by the second scan signal SCAN2 continuously output at a low level, and the reference voltage Vref can be applied to the fourth node N4. When the second switching transistor ST2 is turned on by the second scan signal SCAN2, the first driving transistor DT1 can be in a diode-connected state where the gate electrode and the drain electrode of the first driving transistor DT1 are connected. In this case, the first driving transistor DT1 operates as a diode, allowing current to flow from the source electrode to the drain electrode of the first driving transistor DT1. The voltages of the second node N2 and the third node N3 can have a value VDD+Vth obtained by adding the high-potential power supply voltage and the threshold voltage of the first driving transistor DT1. Therefore, during the period when the first scan signal SCAN1 and the second scan signal SCAN2 with low levels are simultaneously output starting from time C, the voltage of the first node N1 of the PAM circuit PAM is the first data voltage DATA_PAM. In addition, the voltage of the second node N2 can be the voltage VDD+Vth obtained by adding the high-potential power supply voltage and the threshold voltage of the first driving transistor DT1.

[0165] Next, the fifth switching transistor ST5 and the sixth switching transistor ST6 of the first PWM circuit PWM1 can be turned on by the third scan signal SCAN3 with a low level output at time C. The second data voltage Data_PWM is applied to the fifth node N5 through the turned-on fifth switching transistor ST5, and the second driving transistor DT2 can be in a diode-connected state through the turned-on sixth transistor. Current flows through the second data voltage Data_PWM transmitted to the fifth node N5, which is the source electrode of the second driving transistor DT2, in the second driving transistor DT2 in the diode-connected state. The voltage of the sixth node N6, which is the gate electrode of the second driving transistor DT2, can be a value Data_PWM+Vth obtained by adding the threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM. Therefore, during the period when the third scan signal SCAN3 with a low level is simultaneously output starting from time C, the voltage Data_PWM+Vth reflected by the threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM can be charged into the sixth node N6 and the second capacitor C2 connected to the sixth node N6.

[0166] Next, referring to Figure 11 and Figure 12D, the period between time D and time F is the emission period of the light-emitting diode EL connected to the first PWM circuit PWM1. The first emission control signal EM1 at a low level is output to the first emission control line, and the second emission control signal EM2 at a low level is output to the second emission control line. Therefore, the first emission control transistor ET1 and the third switch transistor ST3 of the PAM circuit PAM are turned on, and the second emission control transistor ET2 of the first PWM circuit PWM1 can be turned on.

[0167] First, in the PAM circuit PAM, the reference voltage Vref can be supplied to the first node N1 through the turned-on third switch transistor ST3. In this case, the voltage of the first node N1 drops from the first data voltage Data_PAM to the reference voltage Vref, and the voltage change amount of the first node N1 can be a value Data_PAM - Vref obtained by subtracting the reference voltage Vref from the first data voltage Data_PAM. In addition, the second switch transistor ST2 is turned off, and the floating second node N2 is coupled to the first node N1, so that the voltage can change according to the voltage change of the first node N1. For example, the voltage change amount of the first node N1 is reflected in the second node N2, so that the voltage of the second node N2 can be reduced by the voltage change amount of the first node N1 from the voltage VDD + Vth set in the previous period. Therefore, the voltage of the second node N2 can be a voltage VDD + Vth - (Vdata - Vref) obtained by subtracting the value obtained by subtracting the reference voltage Vref from the first data voltage Data_PAM from the value obtained by adding the high-potential power supply voltage and the threshold voltage of the first driving transistor DT1. Vdata represents the first data voltage Data_PAM. That is, the voltage of the second node N2, which is the voltage of the gate electrode of the first driving transistor DT1, can be VDD + Vth - Vdata + Vref.

[0168] The gate-source voltage of the first driving transistor DT1 can be determined according to the voltage of the second node N2, and the driving current flowing through the first driving transistor DT1 can be determined by the gate-source voltage of the first driving transistor DT1. For example, the gate-source voltage is a value obtained by subtracting the voltage of the source electrode from the voltage of the gate electrode. The driving current can be determined based on the value obtained by subtracting the threshold voltage of the first driving transistor DT1 from the gate-source voltage Vgs of the first driving transistor DT1, as shown in Equation 1 below.

[0169] [Equation 1]

[0170] I = K(Vgs - Vth) 2

[0171] = K((VDD + Vth - Vdata + Vref) - VDD) - Vth 2

[0172] = K(Vdata - Vref) 2

[0173] Therefore, the drive current supplied to each PWM circuit PWM of the plurality of PWM circuits PWM from the PAM circuit PAM is not affected by the threshold voltage of the first drive transistor DT1, but can be determined only by the first data voltage Data_PAM and the reference voltage Vref. Therefore, the threshold voltage of the first drive transistor DT1 of the PAM circuit PAM can be compensated through the second initialization period, the sampling and data writing period, and the emission period. In each of the plurality of sub-pixels SP, the luminance difference according to the threshold voltage difference of the first drive transistor DT1 can be compensated.

[0174] Next, during the period between time D and time F, a low-level second emission control signal EM2 is output to the second emission control line to turn on the second emission control transistor ET2 of the first PWM circuit PWM1. The drive current from the PAM circuit PAM can flow through the turned-on second emission control transistor ET2 to the second drive transistor DT2 of the first PWM circuit PWM1. The drive current from the first drive transistor DT1 can flow from the third node N3 to the fourth node N4 through the turned-on first emission control transistor ET1, and flow to the second emission control transistor ET2 of each PWM circuit PWM of the plurality of PWM circuits PWM. At this time, during the period between time D and time F, only the second emission control transistor ET2 of the first PWM circuit PWM1 is turned on to supply the drive current only to the fifth node N5 of the first PWM circuit PWM1. Therefore, the drive current from the PAM circuit PAM can flow through the turned-on second emission control transistor ET2 to the second drive transistor DT2 of the first PWM circuit PWM1. That is, a predetermined voltage can be applied to the source electrode of the second drive transistor DT2 through the turned-on first drive transistor DT1 of the PAM circuit PAM, the turned-on first emission control transistor ET1, and the turned-on second emission control transistor ET2 of the first PWM circuit PWM1.

[0175] At this time, the drive current flowing in the second drive transistor DT2 can also be determined by the above formula 1. In this case, the drive current flowing in the second drive transistor DT2 can be proportional to the value obtained by subtracting the threshold voltage Vth of the second drive transistor DT2 from the gate-source voltage, and the gate-source voltage is the value obtained by subtracting the voltage of the fifth node N5 from the voltage of the gate electrode of the second drive transistor DT2, which is Data_PWM + Vth. During the process of calculating the value obtained by subtracting the threshold voltage Vth of the second drive transistor DT2 from the gate-source voltage of the second drive transistor DT2, the threshold voltage of the second drive transistor DT2 can be canceled out. The threshold voltage of the second drive transistor DT2 of the PWM circuit PWM can be compensated by the first initialization period, the sampling and data writing period, and the emission period. In each of the plurality of sub-pixels SP, the luminance difference according to the threshold voltage difference of the second drive transistor DT2 can be compensated. Therefore, the first PWM circuit PWM1 can also internally compensate the threshold voltage of the second drive transistor DT2 by the same method as the PAM circuit PAM, and can determine the drive current flowing in the second drive transistor DT2 independently of the threshold voltage of the second drive transistor DT2.

[0176] Among them, the voltage of the gate electrode of the second drive transistor DT2 of the first PWM circuit PWM1 can be coupled to the first sweep signal Sweep1 through the second capacitor C2 connected to the gate electrode. In this case, the voltage change amount of the first sweep signal Sweep1 is reflected in the voltage of the gate electrode of the second drive transistor DT2, so that the voltage of the gate electrode can be changed, and the second drive transistor DT2 can be turned on or off. For example, the first sweep signal Sweep1 gradually increases to increase the voltage of the gate electrode of the second drive transistor DT2, and when the voltage of the gate electrode is higher than the threshold voltage, the second drive transistor DT2 can be turned off. Therefore, the first sweep signal Sweep1 can be used to control the time for supplying the drive current to the light-emitting diode EL in the first PWM circuit PWM1 and the actual emission period of the light-emitting diode EL. Therefore, as long as the second drive transistor DT2 is turned on by the first sweep signal Sweep1 during the period between time D and time E, the drive current is supplied to the light-emitting diode EL connected to the first PWM circuit PWM1 to allow the light-emitting diode EL to emit light.

[0177] Next, at time E, a low-level fourth scan signal SCAN4 is output to the fourth scan line to turn on a fifth switching transistor ST5 and a sixth switching transistor ST6 of a second PWM circuit PWM2. A period during which a light-emitting diode EL connected to a first PWM circuit PWM1 emits light may overlap with a sampling and data writing period of the second PWM circuit PWM2. In the second PWM circuit PWM2, a second data voltage Data_PWM is applied to a fifth node N5 through the turned-on fifth switching transistor ST5, and a second driving transistor DT2 may be in a diode-connected state through the turned-on sixth switching transistor ST6. Accordingly, current may flow in the second driving transistor DT2 in the diode-connected state, and a voltage of a sixth node N6 serving as a gate electrode of the second driving transistor DT2 may be a value Data_PWM+Vth obtained by adding a threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM. Accordingly, the second data voltage Data_PWM may be charged while sampling a threshold voltage of the second driving transistor DT2 of the second PWM circuit PWM2 at time E. For example, a voltage Data_PWM+Vth reflected by the threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM may be charged into a sixth node N6 of the second PWM circuit PWM2 and a second capacitor C2 connected to the sixth node N6.

[0178] Next, referring to Figure 11 and Figure 12E , during a period between time F and time H, a low-level third emission control signal EM3 is output to a third emission control line to turn on a second emission control transistor ET2 of the second PWM circuit PWM2. Accordingly, a driving current from a PAM circuit PAM may flow to the second driving transistor DT2 of the second PWM circuit PWM2 through the turned-on second emission control transistor ET2. The second driving transistor DT2 of the second PWM circuit PWM2 may supply a driving current to the light-emitting diode EL based on the second data voltage Data_PWM written at a previous time E and a second sweep signal Sweep2. At this time, similar to the first PWM circuit PWM1, a driving current flowing in the second driving transistor DT2 is not affected by a threshold voltage of the second driving transistor DT2 and may be determined by the second data voltage Data_PWM. Accordingly, an actual on period of the second driving transistor DT2 of the second PWM circuit PWM2 may be determined according to a voltage change of the second sweep signal Sweep2 during the period between time F and time H. During the period between time F and time H, a driving current is supplied to the light-emitting diode EL connected to the second PWM circuit PWM2, such that the light-emitting diode EL may emit light.

[0179] At time G in the period between time F and time H, a low-level fifth scan signal SCAN5 is output to the fifth scan line to turn on the fifth switching transistor ST5 and the sixth switching transistor ST6 of the third PWM circuit PWM3. The period during which the light-emitting diode EL connected to the second PWM circuit PWM2 emits light may overlap with the sampling and data writing periods of the third PWM circuit PWM3. In the third PWM circuit PWM3, the second data voltage Data_PWM is applied to the fifth node N5 through the turned-on fifth switching transistor ST5, and the second driving transistor DT2 may be in a diode-connected state through the turned-on sixth switching transistor ST6. Therefore, current flows in the second driving transistor DT2 in the diode-connected state, and the voltage of the sixth node N6, which is the gate electrode of the second driving transistor DT2, may be a value Data_PWM + Vth obtained by adding the threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM. Therefore, the second data voltage Data_PWM can be charged while sampling the threshold voltage of the second driving transistor DT2 of the third PWM circuit PWM3 at time G. For example, the voltage Data_PWM + Vth reflected by the threshold voltage of the second driving transistor DT2 and the second data voltage Data_PWM may be charged into the sixth node N6 of the third PWM circuit PWM3 and the second capacitor C2 connected to the sixth node N6.

[0180] Finally, refer to Figure 11 and Figure 12F, during the period between time H and time I, a fourth emission control signal EM4 at a low level is output to a fourth emission control line to turn on a second emission control transistor ET2 of a third PWM circuit PWM3. Accordingly, a drive current from a PAM circuit PAM can flow through the turned-on second emission control transistor ET2 to a second drive transistor DT2 of the third PWM circuit PWM3. The second drive transistor DT2 of the third PWM circuit PWM3 can supply a drive current to a light-emitting diode EL based on a second data voltage Data_PWM written at a previous time G and a third sweep signal Sweep3. At this time, similar to the first PWM circuit PWM1 and the second PWM circuit PWM2, the drive current flowing through the second drive transistor DT2 is not affected by the threshold voltage of the second drive transistor DT2 and can be determined by the second data voltage Data_PWM. Accordingly, an actual turn-on period of the second drive transistor DT2 of the third PWM circuit PWM3 can be determined according to a voltage change of the third sweep signal Sweep3 during the period between time H and time I. During the period between time H and time I, a drive current is supplied to the light-emitting diode EL connected to the third PWM circuit PWM3, such that the light-emitting diode EL emits light.

[0181] Accordingly, in a display device 1000 according to another exemplary embodiment of the present disclosure, a threshold voltage difference between a first drive transistor DT1 of a PAM circuit PAM and second drive transistors DT2 of a plurality of PWM circuits PWM is internally compensated. Accordingly, a luminance difference between a plurality of sub-pixels SP can be minimized. Specifically, in the PAM circuit, a second switching transistor ST2 formed as a diode connection for forming the first drive transistor DT1 is formed to sample the threshold voltage of the first drive transistor DT1. A drive current generated in the PAM circuit is generated based on a value obtained by subtracting the threshold voltage from a gate-source voltage of the first drive transistor DT1, such that the finally generated drive current can be not affected by the threshold voltage of the first drive transistor DT1. In addition, also in the PWM circuit PWM, a sixth switching transistor ST6 formed as a diode connection for forming the second drive transistor DT2 is formed to sample the threshold voltage of the second drive transistor DT2. During a process of writing a data voltage and generating a drive current, the threshold voltage is canceled, such that the drive current can be compensated to not change according to the threshold voltage difference. Accordingly, in a display device 1000 according to another exemplary embodiment of the present disclosure, a threshold voltage difference between a first drive transistor DT1 of a PAM circuit PAM and second drive transistors DT2 of a plurality of PWM circuits PWM is internally compensated to improve luminance uniformity of the display device 1000 and improve display quality.

[0182] Exemplary embodiments of the present disclosure may also be described as follows:

[0183] According to one aspect of the present disclosure, a display device includes: a display panel including a plurality of pixel groups, each of the plurality of pixel groups including a plurality of light-emitting diodes; a plurality of pulse amplitude modulation (PAM) circuits, each PAM circuit being connected to one of the plurality of pixel groups; and a set of pulse width modulation (PWM) circuits, wherein corresponding ones of the set of PWM circuits are included in each of the plurality of pixel groups and are connected to the PAM circuit connected to the pixel group and to the plurality of light-emitting diodes included in the pixel group, and wherein, in each of the plurality of pixel groups, the corresponding plurality of PWM circuits are connected in parallel to an output terminal of the PAM circuit connected to the pixel group.

[0184] The PAM circuit among the plurality of PAM circuits may be configured to adjust the intensity of a driving current based on a first data voltage, the driving current driving the plurality of light-emitting diodes included in the pixel group connected to the PAM circuit.

[0185] The first data voltage may be applied to the plurality of pixel groups.

[0186] The PAM circuit may be configured to supply driving currents having the same intensity to the plurality of PWM circuits connected to the PAM circuit.

[0187] Each of the plurality of PWM circuits connected to the PAM circuit may be configured to adjust the pulse width of the driving current output from the PAM circuit based on a second data voltage.

[0188] The second data voltage applied to each of the plurality of PWM circuits may vary based on the gray level of an image.

[0189] The display device may further include: a plurality of emission control transistors, each emission control transistor being connected to the PAM circuit and to the PWM circuit among the corresponding plurality of PWM circuits connected to the PAM circuit, and each emission control transistor may be configured to connect or disconnect a driving current path between the PAM circuit and the plurality of PWM circuits.

[0190] The display device may further include: a plurality of emission control lines connected to gate electrodes of the plurality of emission control transistors, and each of the plurality of emission control transistors may be connected to a different one of the plurality of emission control lines.

[0191] The above-mentioned one PAM circuit may include a first driving transistor that controls the intensity of a driving current based on a first data voltage, and each of the plurality of PWM circuits may include a second driving transistor that controls a period during which a driving current is supplied to the plurality of light-emitting diodes based on a second data voltage.

[0192] The emission period of each of the plurality of light-emitting diodes in the pixel group may be the same as the period during which the second driving transistor of the corresponding plurality of PWM circuits and the plurality of emission control transistors are turned on.

[0193] The PAM circuit may further include a first sensing transistor connected to the first driving transistor of the PAM circuit, and each of the corresponding plurality of PWM circuits may further include a second sensing transistor connected to the second driving transistor.

[0194] The display device may further include: a plurality of third sensing transistors, each third sensing transistor is connected to the corresponding second driving transistor forming the corresponding plurality of PWM circuits and supplies a sensing voltage to the corresponding second driving transistor, and either the source electrode and the drain electrode of each first driving transistor may be connected to a high-potential power line and the other of the source electrode and the drain electrode of the first driving transistor may be connected to the first sensing transistor, and either the source electrode and the drain electrode of the second driving transistor may be connected to the third sensing transistor and the other of the source electrode and the drain electrode of the second driving transistor may be connected to the second sensing transistor.

[0195] The PAM circuit may further include: a first capacitor having a first end connected to the gate electrode of the first driving transistor and a second end; a first switching transistor connected to the second end of the first capacitor, the first switching transistor transmits the first data voltage to the first capacitor; and a second switching transistor connected to either the source electrode and the drain electrode of the first driving transistor and the gate electrode of the first driving transistor, and the second switching transistor may be configured to be turned on and diode-connect the first driving transistor.

[0196] Each of the corresponding plurality of PWM circuits may further include: a second capacitor having a first end connected to the gate electrode of the second driving transistor; a fifth switching transistor connected to the second driving transistor, the fifth switching transistor transmits the second data voltage to the second driving transistor; and a sixth switching transistor connected to either the source electrode and the drain electrode of the second driving transistor and the gate electrode of the second driving transistor, and the sixth switching transistor may be configured to be turned on and diode-connect the second driving transistor.

[0197] According to another aspect of the present disclosure, a display device includes: a plurality of light-emitting elements that emit light of the same color; a pulse amplitude modulation (PAM) circuit including a first driving transistor that controls the intensity of a driving current generated by the PAM circuit based on a first data voltage; and a plurality of pulse width modulation (PWM) circuits electrically connected to the PAM circuit and receiving the driving current generated by the PAM circuit, each of the PWM circuits including a second driving transistor connected to a corresponding one of the plurality of light-emitting elements and controlling a duration during which the driving current from the PAM circuit is supplied to the corresponding light-emitting element based on a second data voltage having an amplitude related to an image.

[0198] The first data voltage may have a constant value.

[0199] The second data voltage may have a first amplitude corresponding to a first image at a first time such that the driving current is supplied to the second driving transistor for a first duration, and the second data voltage may have a second amplitude corresponding to a second image at a second time such that the driving current is supplied to the second driving transistor for a second duration different from the first duration.

[0200] The display device may further include a plurality of emission control transistors, each emission control transistor being connected to the PAM circuit and a corresponding one of the plurality of PWM circuits, and each emission control transistor may be configured to connect or disconnect the PAM circuit from the corresponding PWM circuit.

[0201] The display device may further include a plurality of emission control lines connected to gate electrodes of the plurality of emission control transistors, and each of the plurality of emission control transistors may be connected to a different one of the plurality of emission control lines.

[0202] The first driving transistor may include a gate electrode, a first electrode, and a second electrode connected to each of the plurality of emission control transistors, and the PAM circuit may further include: a first switching transistor including a gate electrode receiving a first scan signal, a first electrode receiving a first driving voltage, and a second electrode connected to the gate electrode of the first driving transistor, the first switching transistor being configured to supply the first driving voltage to the gate electrode of the first driving transistor in response to the first scan signal; a first sensing transistor including a gate electrode receiving a sensing signal, a second electrode connected to the second electrode of the first driving transistor and a first electrode of each of the plurality of emission control transistors, and a second electrode connected to a reference line; and a first capacitor connected to the gate electrode and the second electrode of the first driving transistor.

[0203] Each second driving transistor may include a gate electrode, a first electrode, and a second electrode of the second driving transistor, and each PWM circuit among the plurality of PWM circuits may further include: a second switching transistor including a gate electrode receiving a second scan signal, a first electrode receiving a second data voltage, and a second electrode connected to the gate electrode of the second driving transistor, the second switching transistor being configured to supply the second data voltage to the gate electrode of the second driving transistor in response to the second scan signal; a second sensing transistor including a gate electrode receiving a sensing signal, a first electrode connected to the second electrode of the second driving transistor and a first electrode of a light-emitting element, and a second electrode connected to a reference line; a second capacitor connected to the gate electrode of the second driving transistor; and a third capacitor connected to the gate electrode of the second driving transistor, the second electrode of the second driving transistor, and the first electrode of the second sensing transistor.

[0204] The plurality of PWM circuits may further include a third sensing transistor including a gate electrode receiving a third scan signal, a first electrode connected to the first electrode of each second driving transistor among the second driving transistors included in the plurality of PWM circuits, and a second electrode connected to a sensing line.

[0205] The first driving transistor may include a gate electrode, a first electrode, and a second electrode connected to the second electrode of each emission control transistor among the plurality of emission control transistors, and the PAM circuit may further include: a first capacitor having a first end connected to the gate electrode of the first driving transistor and a second end; a first switching transistor including a gate electrode receiving a scan signal, a first electrode receiving a first data voltage, and a second electrode connected to the second end of the first capacitor, the first switching transistor transmitting the first data voltage to the first capacitor in response to the first scan signal; a second switching transistor including a gate electrode receiving a second scan signal, a first electrode connected to the gate electrode of the first driving transistor, and a second electrode connected to the second electrode of the first driving transistor, the second switching transistor being configured to be turned on in response to the second scan signal and diode-connect the first driving transistor; a third switching transistor including a gate electrode receiving an emission signal, a first electrode connected to the second electrode of the first switching transistor and the second end of the first capacitor, and a second electrode connected to a reference line; and a fourth switching transistor including a gate electrode connected to the gate electrode of the second switching transistor and receiving the second scan signal, a first electrode connected to the reference line and the second electrode of the third switching transistor, and a second electrode connected to the second electrode of the plurality of emission control transistors.

[0206] Each second driving transistor may include a gate electrode, a first electrode, and a second electrode of the second driving transistor, and each of the plurality of PWM circuits may further include: a second capacitor having a first end connected to the gate electrode of the second driving transistor; a fifth switching transistor including a gate electrode receiving a third scan signal, a first electrode receiving a second data voltage, and a second electrode connected to the first electrode of the second driving transistor, the fifth switching transistor transmitting the second data voltage to the second driving transistor in response to the third scan signal; and a sixth switching transistor including a gate electrode connected to the gate electrode of the fifth switching transistor and the gate electrode of the second driving transistor and receiving the third scan signal, a first electrode connected to the first end of the second capacitor and the second electrode of the second driving transistor, and a second electrode connected to the second electrode of the second driving transistor and the second electrode of the light-emitting element.

[0207] The plurality of PWM circuits may further include an initialization transistor including a gate electrode receiving an initialization scan signal, a first electrode receiving an initialization voltage, and a second electrode connected to the gate electrode of each of the second driving transistors and the first electrode of each of the sixth switching transistors.

[0208] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in various different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of pixel groups, each of the plurality of pixel groups comprising a plurality of light emitting diodes; a plurality of pulse amplitude modulation (PAM) circuits, each PAM circuit being connected to one pixel group among the plurality of pixel groups; a set of pulse width modulation (PWM) circuits, wherein corresponding ones of the set of PWM circuits are included in each of the plurality of pixel groups and are connected to the PAM circuit connected to the pixel group and to the plurality of light emitting diodes included in the pixel group, Wherein, in each of the plurality of pixel groups, the corresponding plurality of PWM circuits are connected in parallel to an output terminal of a PAM circuit connected to the pixel group.

2. The display device according to claim 1, wherein: A PAM circuit among the plurality of PAM circuits is configured to adjust the intensity of a driving current, which drives the plurality of light emitting diodes included in a pixel group connected to the PAM circuit, based on a first data voltage.

3. The display device according to claim 2, wherein: The first data voltage is applied to the plurality of pixel groups.

4. The display device according to claim 3, wherein: The PAM circuit is configured to supply driving currents having the same strength to the plurality of PWM circuits connected to the PAM circuit.

5. The display device according to claim 2, wherein: Each of a plurality of PWM circuits connected to the PAM circuit is configured to adjust a pulse width of a driving current output from the PAM circuit based on a second data voltage.

6. The display device according to claim 5, wherein: The second data voltage applied to each of the plurality of PWM circuits varies based on a grayscale of an image.

7. The display device according to claim 5, further comprising: a plurality of emission control transistors, each emission control transistor being connected to the PAM circuit and to a PWM circuit of the corresponding plurality of PWM circuits connected to the PAM circuit, Each emission control transistor is configured to connect or disconnect a driving current path between the PAM circuit and the plurality of PWM circuits.

8. The display device according to claim 7, further comprising: a plurality of emission control lines connected to gate electrodes of the plurality of emission control transistors, Wherein, each of the plurality of emission control transistors is connected to a different emission control line among the plurality of emission control lines.

9. The display device according to claim 7, wherein: The PAM circuit includes a first driving transistor that controls the intensity of the driving current based on the first data voltage, and each of the plurality of PWM circuits includes a second driving transistor that controls a period of supplying the driving current to a light emitting diode among the plurality of light emitting diodes connected to the PWM circuit based on the second data voltage.

10. The display device according to claim 9, wherein: An emission period of each of the plurality of light emitting diodes in the pixel group is the same as a period during which the second driving transistors of the corresponding plurality of PWM circuits and the plurality of emission control transistors are turned on.

11. The display device according to claim 9, wherein: The PAM circuit further includes a first sense transistor connected to the first drive transistor of the PAM circuit, and each of the corresponding plurality of PWM circuits further includes a second sense transistor connected to the second drive transistor.

12. The display device according to claim 11, further comprising: a plurality of third sensing transistors, each of which is connected to a corresponding second driving transistor in the corresponding plurality of PWM circuits and supplies a sensing voltage to the corresponding second driving transistor, wherein any one of the source electrode and the drain electrode of each first driving transistor is connected to a high potential power line and the other of the source electrode and the drain electrode of the first driving transistor is connected to the first sensing transistor, and any one of the source electrode and the drain electrode of the second driving transistor is connected to the third sensing transistor and the other of the source electrode and the drain electrode of the second driving transistor is connected to the second sensing transistor.

13. The display device according to claim 9, wherein: The PAM circuit further comprises: a first capacitor having a first terminal connected to the gate electrode of the first drive transistor and a second terminal; a first switch transistor connected to the second end of the first capacitor, the first switch transistor transmitting the first data voltage to the first capacitor; and A second switching transistor connected to any one of a source electrode and a drain electrode of the first driving transistor and a gate electrode of the first driving transistor, the second switching transistor being configured to be turned on and diode-connect the first driving transistor.

14. The display device according to claim 13, wherein: Each of the corresponding plurality of PWM circuits further comprises: a second capacitor having a first terminal connected to the gate electrode of the second drive transistor; a fifth switching transistor, the fifth switching transistor being connected to the second driving transistor, the fifth switching transistor transmitting the second data voltage to the second driving transistor; and A sixth switch transistor is connected to any one of the source electrode and the drain electrode of the second drive transistor and the gate electrode of the second drive transistor, and is configured to be turned on and diode-connect the second drive transistor.

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