Display device, data processor and data processing method

Abstract

Embodiments of the present disclosure relate to a display device, a data processor, and a data processing method, and in particular, may provide a display device including: a display panel including a plurality of sub-pixels; a memory system configured to process input data in units of sectors; a timing controller configured to control a data read operation and a data write operation to the memory system; and a data processor configured to hold sector data stored in a first region within a sector and store the input data in a second region within the sector based on an address of the input data.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10 - 2023 - 0166446, filed on November 27, 2023, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical field

[0003] Embodiments of the present disclosure relate to a display device, a data processor, and a data processing method, and more particularly, to a display device, a data processor, and a data processing method capable of processing data in sectors or less than a sector. Background art

[0004] In response to the development of the information society, various demands for image display devices are increasing. In this regard, a series of display devices such as liquid crystal display (LCD) devices and organic light - emitting display devices have recently been widely used.

[0005] Among these display devices, organic light - emitting display devices are advantageous in terms of fast response rate, high contrast ratio, high emission efficiency, high brightness, wide viewing angle, etc., because organic light - emitting diodes that emit light by themselves are used therein.

[0006] Such an organic light - emitting display device may include organic light - emitting diodes (OLEDs) provided in a plurality of sub - pixels arranged in a display panel, and may control the light emission of the OLEDs by controlling the current flowing through the OLEDs, thereby displaying an image while controlling the brightness of the sub - pixels.

[0007] These display devices may use flash memory, which has sectors of a fixed size as basic units.

[0008] Therefore, in order to use flash memory in a display device, there is a problem that the flash memory must be divided by sectors, and the address must be modified in units of sectors to process data. Summary of the invention

[0009] Therefore, the inventors of the present disclosure have invented a display device, a data processor, and a data processing method capable of processing data in sectors or less than a sector.

[0010] Embodiments of the present disclosure may provide a display device, a data processor, and a data processing method that can process data in sectors or less than a sector by dividing a start address and an end address in units of sectors and processing the data in units of sectors or less than a sector according to the positions of the start address and the end address.

[0011] Embodiments of the present disclosure may provide a display device, including: a display panel including a plurality of sub-pixels; a memory system configured to process input data in units of sectors; a timing controller configured to control a data read operation and a data write operation of the memory system; and a data processor configured to hold sector data stored in a first region within a sector based on an address of the input data and store the input data in a second region within the sector.

[0012] Embodiments of the present disclosure provide a data processor incorporated into a memory system that processes data in units of sectors, including: a data input unit configured to receive input data; an address input unit configured to receive an address of the input data; an address counter configured to use the address of the input data to determine a first region for holding sector data stored in the memory system and a second region for writing the input data into a sector; a read buffer configured to transfer the sector data provided from the memory system; a switch circuit configured to transfer the input data or the sector data under the control of the address counter; and a write buffer configured to write the data transferred from the switch circuit into the memory system.

[0013] Embodiments of the present disclosure provide a data processing method for a display device, including steps of receiving input data and an address, using sector information of a memory system to determine a position digit and a size digit of the address, extracting count information corresponding to the input data for processing data in units of sectors, and processing data in units of sectors using the count information.

[0014] According to embodiments of the present disclosure, data can be processed in units of sectors or less than a sector.

[0015] According to embodiments of the present disclosure, data can be processed in units of sectors or less than a sector by dividing a start address and an end address in units of sectors and processing data in units of sectors or less than a sector according to positions of the start address and the end address.

[0016] According to embodiments of the present disclosure, power consumption can be reduced and low-power operation can be achieved by using a non-volatile memory such as a flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a view schematically showing a display device according to an embodiment;

[0019] Figure 2 is an example diagram showing a system of a display device according to an embodiment;

[0020] Figure 3 is a view showing a structure of a memory system in a display device according to an embodiment;

[0021] Figure 4 is a block diagram showing a configuration of a data processor in a display device according to an embodiment;

[0022] Figure 5 is a view showing an example in which a start address and an end address for writing data are located in the middle of sectors in a display device according to an embodiment;

[0023] Figures 6 to 9 is a view showing count information generated by an address counter of a data processor for processing input data in a display device according to an embodiment;

[0024] Figures 10 to 12 is a view showing a state of written data in each sector in a display device according to an embodiment;

[0025] Figure 13 is a flowchart of a data processing method according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In the following description of examples or embodiments of the present disclosure, reference will be made to the drawings, in which specific examples or embodiments that can be implemented are shown by way of illustration, and in which the same or similar components may be denoted by the same reference numerals and symbols even when shown in different drawings. Further, in the following description of examples or embodiments of the present disclosure, when it is determined that the description may obscure the subject matter in some embodiments of the present disclosure, detailed descriptions of well-known functions and components incorporated herein will be omitted. Terms such as "comprising", "having", "containing", "constituting", "consisting of", and "formed of" as used herein are generally intended to allow the addition of other components, unless these terms are used together with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0027] This disclosure may use terms such as "first", "second", "A", "B", "(A)", or "(B)" to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence, quantity, etc. of the element, but is only used to distinguish the corresponding element from other elements.

[0028] When referring to a first element being "connected or coupled to", "in contact with or overlapping", etc. a second element, it should be interpreted that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlapping" the second element, but also a third element can be "inserted" between the first element and the second element, or the first element and the second element can be "connected or coupled", "in contact with or overlapping", etc. with each other via a fourth element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled", "in contact with or overlapping", etc. with each other.

[0029] When using time - relative terms such as "after", "subsequently", "next", "before" to describe a process or operation of an element or configuration, or a flow or step in an operation, process, manufacturing method, these terms can be used to describe a non - continuous or non - sequential process or operation, unless the terms "directly" or "immediately" are used together.

[0030] In addition, when referring to any size, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of an element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.) even when the relevant description is not specified. Furthermore, the term "may" fully encompasses all meanings of the term "can".

[0031] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a view schematically showing a display device according to an embodiment.

[0033] Referring to Figure 1 , a display device 100 according to an embodiment may include a display panel 110 and a driving circuit for driving the display panel 110.

[0034] The display panel 110 may include a display area DA on which an image is displayed and a non - display area NDA on which no image is displayed. The non - display area NDA may also be referred to as a border area.

[0035] The display panel 110 may include a plurality of sub-pixels SP to display an image. For example, the plurality of sub-pixels SP may be disposed in the display area DA. In some cases, at least one sub-pixel SP may be disposed in the non-display area NDA. The at least one sub-pixel SP disposed in the non-display area NDA is referred to as a dummy sub-pixel.

[0036] The display panel 110 may include a plurality of signal lines to drive the plurality of sub-pixels SP. For example, the plurality of signal lines may include a plurality of data lines DL and a plurality of gate lines GL. Depending on the structure of the sub-pixel SP, the signal lines may further include other signal lines in addition to the plurality of data lines DL and the plurality of gate lines GL. For example, the other signal lines may include a driving voltage line, a reference voltage line, and the like.

[0037] The plurality of data lines DL may intersect the plurality of gate lines GL. Each of the plurality of data lines DL may be set to extend in a first direction. Each of the plurality of gate lines GL may be set to extend in a second direction. Here, the first direction may be the column direction, and the second direction may be the row direction. In this specification, the column direction and the row direction are relative terms. In an example, the column direction may be the vertical direction, and the row direction may be the horizontal direction. In another example, the column direction may be the horizontal direction, and the row direction may be the vertical direction.

[0038] The driving circuit may include a data driving circuit 130 for driving the plurality of data lines DL and a gate driving circuit 120 for driving the plurality of gate lines GL. The driving circuit may further include a timing controller 140 to control the data driving circuit 130 and the gate driving circuit 120.

[0039] The data driving circuit 130 is a circuit for driving the plurality of data lines DL, and may output a data signal (also referred to as a data voltage) corresponding to an image signal to the plurality of data lines DL. The gate driving circuit 120 is a circuit for driving the plurality of gate lines GL, and may generate a gate signal and output the gate signal to the plurality of gate lines GL. The gate signal may include one or more scan signals and emission signals.

[0040] The timing controller 140 may start scanning at a timing set for each frame, and control data driving at an appropriate time point in response to the scanning. The timing controller 140 may convert the image data input from an external source into image data Data having a data signal format readable by the data driving circuit 130, and output the image data Data to the data driving circuit 130.

[0041] The timing controller 140 may receive a display driving control signal and input image data from the host system 300. For example, the display driving control signal may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a clock signal, etc.

[0042] The timing controller 140 may generate a data driving control signal DCS and a gate driving control signal GCS based on the display driving control signal input from the host system 300. The timing controller 140 may control the driving operation and driving timing of the data driving circuit 130 by providing the data driving control signal DCS to the data driving circuit 130. The timing controller 140 may control the driving operation and driving timing of the gate driving circuit 120 by providing the gate driving control signal GCS to the gate driving circuit 120.

[0043] The data driving circuit 130 may include one or more source driver integrated circuits SDICs (see Figure 2 ). Each of the source driver integrated circuits SDICs may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. Each source driver integrated circuit SDIC may further include an analog-to-digital converter (ADC).

[0044] For example, each source driver integrated circuit SDIC may be connected to the display panel 110 using a tape automated bonding (TAB) structure, may be connected to the bonding pads of the display panel 110 using a chip-on-glass (COG) structure or a chip-on-panel (COP) structure, or may be implemented using a chip-on-film (COF) structure connected to the display panel 110.

[0045] The gate driving circuit 120 may output a gate signal having a conductive level voltage or a gate signal having a non-conductive level voltage under the control of the timing controller 140. The gate driving circuit 120 may sequentially drive a plurality of gate lines GL by sequentially providing a gate signal having a conductive level voltage to the plurality of gate lines GL.

[0046] For example, the display device 100 with a resolution of 2160×3840 may include four sub-pixels SP composed of a white sub-pixel W, a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. In this case, a total of 3840×4 = 15360 data lines DL may be arranged through 3840 data lines DL and 2160 gate lines GL respectively connected to the 4 sub-pixels WRGB. In addition, the sub-pixels SP may be respectively formed in the regions where the gate lines GL and the data lines DL intersect.

[0047] The gate driving circuit 120 is controlled by the timing controller 140, and controls the driving timing of the plurality of sub-pixels SP by sequentially providing gate signals to a plurality of gate lines GL disposed on the display panel 110.

[0048] In the display device 100 with a resolution of 2160×3840, for 2160 gate lines GL, the operation of sequentially providing gate signals from the first gate line to the 2160th gate line can be referred to as a 2160-phase driving operation. Alternatively, as an operation of sequentially providing gate signals from the first gate line to the fourth gate line, and then sequentially providing gate signals from the fifth gate line to the eighth gate line, the operation of sequentially providing gate signals in units of four gate lines GL can be referred to as a 4-phase driving operation. In other words, the operation of sequentially providing gate signals in units of N gate lines GL can be referred to as an N-phase driving operation.

[0049] The gate driving circuit 120 may include one or more gate driving integrated circuits GDICs (see Figure 2 ).

[0050] The gate driving circuit 120 may be connected to the display panel 110 using a TAB structure, connected to the bonding pads of the display panel 110 using a COG structure or a COP structure, or connected to the display panel 110 using a COF structure. Alternatively, the gate driving circuit 120 may be implemented using a gate-in-panel (GIP) structure provided in the non-display area NDA of the display panel 110. The gate driving circuit 120 may be provided on a circuit board or connected to a circuit board. That is, when the gate driving circuit 120 has a GIP structure, the gate driving circuit 120 may be provided in the non-display area NDA. When the gate driving circuit 120 has a COG structure, a COF structure, etc., the gate driving circuit 120 may be connected to a circuit board.

[0051] In addition, at least one of the data driving circuit 130 and the gate driving circuit 120 may be provided in the display area DA. For example, at least one of the data driving circuit 130 and the gate driving circuit 120 may be arranged not to overlap with the sub-pixels SP, or arranged such that a part or all of it overlaps with the sub-pixels SP.

[0052] The data driving circuit 130 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Depending on the driving method, the design of the display panel, etc., the data driving circuit 130 may be connected to two sides (e.g., the upper side and the lower side) of the display panel 110 or two or more sides of the four sides of the display panel 110.

[0053] The gate driving circuit 120 may be connected to one side surface (e.g., the left side surface or the right side surface) of the display panel 110. Depending on the driving method, the design of the display panel, etc., the gate driving circuit 120 may be connected to two side surfaces (e.g., the left side surface and the right side surface) of the display panel 110 or two or more of the four side surfaces of the display panel 110.

[0054] The timing controller 140 may be provided as a component separate from the data driving circuit 130, or may be combined with the data driving circuit 130 to form an integrated circuit (IC). The timing controller 140 may be a timing controller used in typical display technologies, may be a control device including a timing controller and performing other control functions, or may be a circuit in the control device. The timing controller 140 may be implemented as any one of various circuits or electronic components, such as an IC, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0055] The timing controller 140 may be mounted on a printed circuit board (PCB), a flexible printed circuit (FPC), etc., and may be electrically connected to the data driving circuit 130 and the gate driving circuit 120 through the PCB, the FPC, etc. The timing controller 140 may transmit signals to the data driving circuit 130 and receive signals from the data driving circuit 130 according to one or more predetermined interfaces. Here, for example, the interface may include a low voltage differential signaling (LVDS) interface, an embedded panel interface (EPI), a serial peripheral (SP) interface, etc.

[0056] The display device 100 according to an embodiment may be a self-emitting display device in which the display panel 110 emits light by itself. When the display device 100 according to an embodiment is a self-emitting display device, each of the plurality of sub-pixels SP may include a light-emitting element. In an example, the display device 100 according to an embodiment may be an organic light-emitting display device, in which the light-emitting element is an organic light-emitting diode (OLED). In another example, the display device 100 according to an embodiment may be an inorganic light-emitting display device, in which the light-emitting element is a light-emitting diode (LED) based on an inorganic material. In another example, the display device 100 according to an embodiment may be a quantum dot display device, in which the light-emitting element is a quantum dot serving as a self-emitting semiconductor crystal.

[0057] Figure 2 is an exemplary diagram of a system of a display device according to an embodiment.

[0058] Reference Figure 2, the display device 100 according to an embodiment is the following example: Among them, the COF structure in various structures such as TAB, COG, and COF structures is used to implement the data driving circuit 130, and the GIP structure in various structures such as TAB, COG, COF, and GIP structures is used to implement the gate driving circuit 120.

[0059] When the gate driving circuit 120 has a GIP structure, a plurality of gate driving integrated circuits GDICs of the gate driving circuit 120 can be directly formed in the non-display area of the display panel 110. Here, the gate driving integrated circuit GDIC can provide various signals (for example, a clock, a gate high signal, and a gate low signal) required for generating a scan signal through gate driving related signal lines provided in the non-display area.

[0060] In the same manner, the source driving integrated circuits SDICs of the data driving circuit 130 can be respectively mounted on the source films SF. One side of each of the source films SF can be electrically connected to the display panel 110. In addition, conductive lines for electrically connecting the source driving integrated circuit SDIC to the display panel 110 can be provided on the top portion of the source film SF.

[0061] The display device 100 may include at least one source printed circuit board SPCB and a control printed circuit board CPCB for connecting a plurality of source driving integrated circuit SDIC circuits to other devices. Here, a control component and various electrical devices can be mounted on the control printed circuit board CPCB.

[0062] Here, the other side of the source film SF on which the source driving integrated circuit SDIC is mounted can be connected to the source printed circuit board SPCB. That is, each of the source films SF on which the source driving integrated circuit SDIC is mounted can be configured such that one side thereof is electrically connected to the display panel 110 and the other side thereof is electrically connected to the source printed circuit board SPCB.

[0063] The timing controller 140 and the power management circuit 180 can be mounted on the control printed circuit board CPCB. The timing controller 140 can control the operations of the data driving circuit 130 and the gate driving circuit 120. The power management circuit 180 can supply a driving voltage or current to the display panel 110, the data driving circuit 130, the gate driving circuit 120, etc., and can control the supplied voltage or current.

[0064] The source printed circuit board SPCB and the control printed circuit board CPCB can be circuit-connected to each other through at least one connection member. The connection member can be, for example, a flexible flat cable FFC, a flexible printed circuit (FPC), etc. Additionally, the source printed circuit board SPCB and the control printed circuit board CPCB can be integrated into a single printed circuit board (PCB).

[0065] The display device 100 may further include a setting board 170 electrically connected to the control printed circuit board CPCB. Here, the setting board 170 may also be referred to as a power supply board. The setting board 170 may be provided with a main power management circuit 160 to manage the total power supply of the display device 100. The main power management circuit 160 may work in cooperation with the power management circuit 180.

[0066] In the display device 100 having the above configuration, the driving voltage is generated by the setting board 170 and transmitted to the power management circuit 180 in the control printed circuit board CPCB. The power management circuit 180 transmits the driving voltage required for display driving or eigenvalue sensing to the source printed circuit board SPCB through a flexible printed circuit or a flexible flat cable FFC. The driving voltage transmitted to the source printed circuit board SPCB is provided through a driving integrated circuit SDIC to light up or sense specific sub-pixels SP in the display panel 110.

[0067] Here, each sub-pixel SP arranged in the display panel 110 of the display device 100 may include a light-emitting element and circuit elements such as driving transistors for driving the light-emitting element.

[0068] The type and number of circuit elements provided in each sub-pixel SP can be determined diversely according to the provided functions, designs, etc.

[0069] Additionally, the display device 100 of the present disclosure may include a memory system 150 for storing image data transmitted from the host system 300 or data calculated by the timing controller 140.

[0070] The memory system 150 may include non-volatile memories such as flash memory, resistive random access memory (RRAM), etc.

[0071] When the memory system 150 is a non-volatile memory such as flash memory, the basic unit for accessing data stored in the memory system 150 can be defined as a sector, which can be determined according to the structure of the memory system 150.

[0072] At this time, the sector corresponding to the basic unit of the flash memory may have a size of 1KB, 2KB, or 4KB, and two or more consecutive sectors may form a block.

[0073] Figure 3 It is a view showing the structure of a memory system in a display device according to an embodiment.

[0074] Reference Figure 3 , the memory device 110 of the display device 100 according to an embodiment may have a core region in which memory cells are arranged, and an auxiliary region (the auxiliary region is the remaining region other than the core region) to support the operation of the memory cell array.

[0075] The core region may include pages PG and strings STR. In this core region, a plurality of word lines WL1 - WL9 and a plurality of bit lines BL are arranged to intersect.

[0076] The plurality of word lines WL1 - WL9 may be connected to the row decoder 151, and the plurality of bit lines BL may be connected to the column decoder 152. A data register 153 corresponding to the read / write circuit may exist between the plurality of bit lines BL and the column decoder 152.

[0077] The plurality of word lines WL1 - WL9 may correspond to a plurality of pages PG. For example, each of the plurality of word lines WL1 - WL9 may correspond to one page PG. On the other hand, when each of the plurality of word lines WL1 - WL9 has a large size, each of the plurality of word lines WL1 - WL9 may correspond to at least two (e.g., two or four) pages PG. Each page PG may be the minimum unit in a write operation and a read operation, and all memory cells in the same page PG may perform simultaneous operations when performing write operations and read operations.

[0078] The plurality of bit lines BL may be connected to the column decoder 152. The plurality of bit lines BL may be divided into odd bit lines and even bit lines.

[0079] When accessing the memory cell MC, the row decoder 151 and the column decoder 152 are used to specify the target memory cell based on the address. Specifying the target memory cell means accessing to write data into the memory cell at the intersection of the word lines WL1 - WL9 connected to the row decoder 151 and the bit lines BL connected to the column decoder 152, or reading the stored data.

[0080] The data register 153 plays an important role because all data processing operations (including write and read operations) of the memory system 150 occur via the data register 153. If the data processing operation by the data register 153 is delayed, all other regions need to wait until the data register 153 completes the data processing operation. In addition, the degradation of the performance of the data register 153 may lead to the degradation of the overall performance of the memory system 150.

[0081] In a memory cell string STR, a plurality of transistors TR1-TR9 may be respectively connected to a plurality of word lines WL1-WL9. The regions of the plurality of transistors TR1-TR9 correspond to memory cells.

[0082] The plurality of word lines WL1-WL9 may include two outermost word lines WL1, WL9. A first select line DSL may be additionally disposed outside the first outermost word line WL1 closer to the data register 153 among the two outermost word lines WL1, WL9. A second select line SSL may be additionally disposed outside the other second outermost word line WL9 among the two outermost word lines WL1, WL9.

[0083] A first select transistor D-TR controlled to be turned on / off by the first select line DSL has a gate electrode connected to the first select line DSL but does not include a floating gate. A second select transistor S-TR controlled to be turned on / off by the second select line SSL has a gate electrode connected to the second select line SSL but does not include a floating gate.

[0084] The first select transistor D-TR serves as a switching circuit for connecting the corresponding string STR to the data register 153. The second select transistor S-TR serves as a switching circuit for connecting the corresponding string STR to the source line SL. That is, the first select transistor D-TR and the second select transistor S-TR can be used to enable or disable the corresponding string STR at both ends of the string STR.

[0085] During a data write operation, the memory system 150 must fill the target memory cell of the bit line BL to be written with electrons. Therefore, the memory system 150 applies a predetermined conduction voltage Vcc to the gate electrode of the first select transistor D-TR to turn on the first select transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second select transistor S-TR to turn off the second select transistor S-TR.

[0086] The memory system 150 turns on both the first select transistor D-TR and the second select transistor S-TR during a read operation or a verify operation. Therefore, current can flow through the corresponding string STR and the drain to the source line SL corresponding to the ground, so that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the turn-on / turn-off timing between the first select transistor D-TR and the second select transistor S-TR.

[0087] Memory system 150 may apply a predetermined voltage (e.g., +20V) to the substrate through the source line SL during an erase operation. Memory system 150 may allow both the first select transistor D-TR and the second select transistor S-TR to float with infinite resistance during the erase operation. As a result, the functions of the first select transistor D-TR and the second select transistor S-TR are eliminated, and only electrons generated due to the potential difference between the floating gate and the substrate can operate.

[0088] Meanwhile, an EEPROM (electrically erasable PROM) may read or write data in units of bytes when mounted on a printed circuit board. However, when writing data in the EEPROM, each byte requires a time delay of several ms or more, so it is not suitable for storing a large amount of data at high speed.

[0089] In particular, as the resolution of the display device 100 increases, in cases where a large amount of data must be processed at high speed, the need to use flash memory in the storage system 150 increases.

[0090] Flash memory can read data in units of bytes. However, it is difficult to write data in real time because flash memory can only be executed in sectors while writing data.

[0091] In this way, since flash memory uses sectors as basic units, there are the following problems: when using flash memory in the display device 100, image data must be written in sectors, and the address must be corrected according to the sectors to process the data.

[0092] The display device 100 of the present disclosure uses flash memory, but allows data to be written in sectors or less than sectors, thereby improving the efficiency of using flash memory and reducing costs.

[0093] Figure 4 It is a block diagram showing the configuration of a data processor in a display device according to an embodiment.

[0094] Reference Figure 4 , the display device 100 according to an embodiment may include a data processor 200 capable of writing data in sectors or less than sectors.

[0095] The data processor 200 of the present disclosure may be implemented in the form of an integrated circuit within the timing controller 140, or may be implemented as a separate circuit controlling the printed circuit board.

[0096] The data processor 200 may include an address input unit 210, a data input unit 220, an address counter 230, a read buffer 240, a switch circuit 250, a write buffer 260, and a concatenator 270.

[0097] The data input unit 220 is a part that provides data to be written into the storage system 150.

[0098] The address input unit 210 is a part that provides an address of data to be written into the storage system 150. The address of the written data may include a start address and an end address of the input data Data_In.

[0099] When a flash memory is used in the memory system 150, there is a problem that data must be written into a sector (e.g., 4KB). Even when the start address and the end address for writing data are located in the middle of a sector, the display device 100 of the present disclosure allows data to be written into the area between the start address and the end address.

[0100] Figure 5 is a view showing an example in which the start address and the end address for writing data are located in the middle of a sector in the display device according to an embodiment.

[0101] Reference Figure 5 , the memory system 150 in the display device 100 according to an embodiment may be a flash memory divided into a plurality of sectors.

[0102] For example, the memory system 150 may be composed of a plurality of sectors having 4KB as a basic unit. In this case, the memory system 150 can store data in the sectors. Here, the first sector Sector1 to the fourth sector Sector4 are shown as examples.

[0103] If each sector of the memory system 150 has a size of 4KB, then each sector may have an address interval of 2^12. When the address is represented in hexadecimal, the size of 4KB corresponds to the lower 3 digits. Therefore, in the case of a hexadecimal address, the lower 3 digits correspond to the sector size of 4KB and may be referred to as size digits.

[0104] For example, the address from 00000000h to 00000FFFh may be assigned to the first sector Sector1, and the address from 00001000h to 00001FFFh may be assigned to the second sector Sector2. Additionally, the address from 00002000h to 00002FFFh may be assigned to the third sector Sector3, and the address from 00003000h to 00003FFFh may be assigned to the fourth sector Sector4. Here, the 'h' at the end of the 8-bit address indicates hexadecimal.

[0105] When a sector has a size of 4KB, the lower 3 digits indicate the size of the sector. Thus, if the upper 5 digits of an 8-digit address are the same, they indicate the same sector. Therefore, whether addresses belong to the same sector can be determined by whether the upper 5 digits are the same. Thus, in the case of a hexadecimal address, the upper 5 digits indicate the position of the address and can be called position digits.

[0106] On the other hand, if the size of the sector changes, the upper digits in the 8-digit address used to determine the same sector will change.

[0107] In addition, if the address is represented in hexadecimal, it may be difficult to determine a sector size of 2KB or 1KB as digits of the address. Therefore, the hexadecimal-represented address can be converted to binary, and the lower digits corresponding to the sector size and the position digits corresponding to the address position can be extracted and compared.

[0108] In this state, data can be written from the rear of the first sector Sector1 to the front of the fourth sector Sector4. For example, the starting address of the input data Data_In can be 00000FF0h located within the first sector Sector1, and the ending address can be 00003A66h located within the fourth sector Sector4.

[0109] In this way, when the starting address of the input data Data_In is located inside the first sector Sector1 and the ending address of the input data Data_In is located inside the fourth sector Sector4, the input data Data_In can be written into the entire areas of the second sector Sector2 and the third sector Sector3.

[0110] For the first sector Sector1, while maintaining the stored sector data Data_Sector from the starting point 00000000h of the first sector Sector1 to just before the starting address 00000FF0h of the input data Data_In, i.e., 00000FEFh, the input data Data_In can be written from the starting address 00000FF0h of the first sector Sector1 to the ending point 00000FFFh.

[0111] In addition, for the fourth sector Sector4, the input data Data_In can be written from the starting point 00003000h of the fourth sector Sector4 to the end address 00003A66h of the input data Data_In, while the sector data Data_Sector in the fourth sector Sector4 is maintained from the just next point 00003A67h of the end address 00003A66h of the input data Data_In to the end point 00003FFFh of the fourth sector Sector4.

[0112] For this purpose, the address counter 230 can use the starting address and the end address of the input data Data_In to determine the operation of maintaining the sector data Data_Sector or writing the input data Data_In into each sector of the memory system 150.

[0113] Figures 6 to 9 It is a view showing the count information generated by the address counter of the data processor for processing input data in a display device according to an embodiment.

[0114] In the display device 100 according to an embodiment, the address counter 230 of the data processor 200 can generate count information for processing data by using the address (starting address and end address) of the input data Data_In and the sector address.

[0115] First, referring to Figure 6 , the address counter 230 of the data processor 200 in the display device 100 according to an embodiment can determine the number of sectors for processing data by comparing the position numbers of the starting address and the end address of the input data Data_In. Here, this is called "global counting".

[0116] The global count can be determined by the difference between the position number of the end address and the position number of the starting address. For example, in the case of a flash memory with a sector size of 4KB, the positions of the starting address and the end address can be determined by the high 5 - bit numbers respectively.

[0117] If the starting address is 00000FF0h and the end address is 00003A66h, the starting address is located in the first sector Sector1 corresponding to the high 5 - bit number 00000, and the end address is located in the fourth sector Sector4 corresponding to the high 5 - bit number 00003. Therefore, by adding 1 to the difference between the high 5 - bit number 00003 of the end address and the high 5 - bit number 00000 of the starting address, the number of sectors Sector1 to Sector4 for processing data becomes 4.

[0118] Next, referring to Figure 7, the address counter 230 of the data processor 200 in the display device 100 according to an embodiment can determine the range between the start point of the sector and the start address by comparing the magnitude digit of the start address of the input data Data_In with the start point of the sector. Here, this is referred to as "front counting".

[0119] The front counting can be determined using the magnitude digit of the start address and the start point of the sector in which the start address is located. For example, in the case of a flash memory with a sector size of 4KB, the sector size can correspond to the lower 3 digits of the start address and the end address. In other words, each of the lower 3 digits of the start address and the end address has a value between the start point and the end point in one sector.

[0120] Therefore, the distance from the magnitude digit of the start address (e.g., FFFh) to the start point 000h of the sector (e.g., the first sector) in which the start address is located represents the range 000h to FEFh between the start point in the first sector Sector1 and the start address.

[0121] Since the range indicated by the front counting corresponds to the area where the input data Data_In is not written, the sector data Data_Sector stored in the memory system 150 can remain unchanged during the data processing.

[0122] Next, referring to Figure 8 , the address counter 230 of the data processor 200 in the display device 100 according to an embodiment can determine the range between the end address and the end point of the sector by comparing the magnitude digit of the end address of the input data Data_In with the end point of the sector. Here, this is referred to as "rear counting".

[0123] The rear counting can be determined by the difference between the magnitude digit of the end address and the end point of the sector in which the end address is located. For example, in the case of a flash memory with a sector size of 4KB, the sector size can correspond to the lower 3 digits of the start address and the end address. In other words, each of the lower 3 digits of the start address and the end address has a value between the start point and the end point in one sector.

[0124] Therefore, the distance from the magnitude digit of the end address (e.g., A66h) to the end point FFFh of the sector (e.g., the fourth sector) in which the end address is located represents the range A67h to FFFh between the end point of the fourth sector Sector4 and the end address.

[0125] Since the range indicated by the rear count corresponds to the area where the input data Data_In is not written, the sector data Data_Sector stored in the memory system 150 can remain as it is during the data processing.

[0126] Next, referring to Figure 9 , the address counter 230 of the data processor 200 in the display device 100 according to the embodiment can determine the range for writing the input data Data_In by using the magnitude digits of the start address or the end address of the input data Data_In. Here, this is referred to as "write count".

[0127] Figures 10 to 12 is a view showing the state of the written data in each sector in the display device according to the embodiment.

[0128] The write count can vary according to the positions of the start address or the end address. For example, if the input data Data_In has a start address located in the first sector Sector1 and an end address located in the fourth sector Sector4, the write count can be determined in different ways in the first sector Sector1, the second sector Sector2, the third sector Sector3, and the fourth sector Sector4.

[0129] In the case of a flash memory with a sector size of 4KB, the sector size can correspond to the lower 3 magnitude digits of the start address and the end address. In other words, each of the lower 3 magnitude digits of the start address and the end address has a value between the start point and the end point in one sector.

[0130] For the first sector Sector1, the distance 000h to FEFh between the magnitude digit FEFh of the start address and the start point 000h of the first sector corresponds to the front count, and the other area FF0h to FFFh except the front count corresponds to the write count in the first sector Sector1. Therefore, as Figure 10 shown, the sector data Data_Sector stored in the memory system 150 can be kept in the front count 000h to FEFh, and the input data Data_In can be written into the write count FF0h to FFFh except the front count.

[0131] In the second sector Sector2 and the third sector Sector3, the entire area 000h to FFFh corresponds to the range of the write count. Therefore, as Figure 11 shown, the input data Data_In can be written into the entire area 000h to FFFh of the second sector Sector2 and the third sector Sector3.

[0132] In the fourth sector Sector4, the distance A67h to FFFh between the size number of the end address A66h and the end point FFFh of the fourth sector Sector4 corresponds to the rear count, and the other area 000h to A66h except the rear count corresponds to the write count. Therefore, as Figure 12 shown, the sector data Data_Sector stored in the memory system 150 can be held in the rear count A67h to FFFh, and the input data Data_In can be written into the write count 000h to A66h except the rear count.

[0133] In this way, the range indicated by the write count corresponds to the area where the input data Data_In is written. Therefore, during the data processing process, the sector data Data_sector stored in the memory system 150 can be deleted, and the input data Data_In provided by the data input unit 220 can be written into the write count.

[0134] The address counter 230 can generate a switching control signal SCS for controlling the switching circuit 250 using the global count, the front count, the rear count, and the write count.

[0135] The switching circuit 250 can select the input data Data_In provided by the data input unit 220 or the sector data Data_Sector provided by the read buffer 240, and generate the output data Data_Out. The switching circuit 250 can be a multiplexer.

[0136] Meanwhile, the sector data Data_sector can be extracted from the memory system 150 in units of sectors, combined through the connector 270, and transmitted to the read buffer 240.

[0137] The output data Data_Out can be written into the memory system 150 in units of sectors through the write buffer 260.

[0138] Figure 13 is a flowchart of the data processing method according to the embodiment.

[0139] Refer to Figure 13 According to the embodiment, the data processing method may include steps S100 of receiving input data and an address, S200 of determining the position number and size number of the address using the sector information of the memory system, S300 of extracting count information for processing data in units of sectors corresponding to the input data, and S400 of processing data in units of sectors using the count information.

[0140] Step S100 of receiving input data and an address is a process of receiving information about data to be written into a memory system and an address where the data is to be written.

[0141] The address may include a start address and an end address, and the address may be represented in hexadecimal.

[0142] Step S200 of using sector information of the memory system to determine the position number and size number of an address is a process of dividing the numbers of the address into a position number and a size number based on the sector information, where the sector information is a basic unit for storing data in the memory system.

[0143] For example, if the address is represented by 8 - bit hexadecimal numbers and the sector, which is a basic unit of the memory system, is 4KB, the lower 3 - bit numbers of the address may correspond to the size number indicating the sector size, and the higher 5 - bit numbers may correspond to the position number indicating the address position.

[0144] At this time, depending on the expression of the address and the size of the sector, the position number and the size number can be changed in various ways. To distinguish the numbers corresponding to the sector size, the address can also be changed to a binary number.

[0145] Step S300 of extracting count information corresponding to the input data for processing data in units of sectors is a process of using the address and the sector information to calculate the count information for writing the input data in each sector. At this time, the count information may include a global count indicating the number of sectors for processing data, a front count indicating the range between the start point of the sector and the start address, a back count indicating the range between the end address and the end point of the sector, and a write count indicating the range for writing the input data Data_In.

[0146] Step S400 of processing data in units of sectors using the count information is a process of using the global count, the front count, the back count, and the write count to hold sector data in some areas or write the input data in at least some areas of each sector related to the input data.

[0147] In this way, according to the data processing method of the present disclosure, even when using a flash memory in which data is written in fixed units of sectors, data can be written in units of sectors or less than a sector. Therefore, data processing performance can be improved and memory cost can be reduced.

[0148] The foregoing embodiments are briefly described below.

[0149] Embodiments of the present disclosure may provide a display device, including: a display panel including a plurality of sub-pixels; a memory system configured to process input data in units of sectors; a timing controller configured to control a data read operation and a data write operation of the memory system; and a data processor configured to hold sector data stored in a first area within a sector based on an address of the input data and store the input data in a second area within the sector.

[0150] The memory system includes a flash memory.

[0151] The sector has a size of 4KB.

[0152] The address of the input data includes a position number corresponding to a position of the sector and a size number corresponding to a size of the sector.

[0153] When the address of the input data is composed of 8-bit hexadecimal digits, the position number is the upper 5 bits, and the size number is the lower 3 bits.

[0154] The data processor includes: a data input unit configured to receive input data; an address input unit configured to receive the address of the input data; an address counter configured to determine a first area and a second area using the address of the input data; a read buffer configured to transfer the sector data provided from the memory system; a switch circuit configured to transfer the input data or the sector data under the control of the address counter; and a write buffer configured to write the data transferred from the switch circuit into the memory system.

[0155] The data processor further includes a connector configured to combine the sector data in units of sectors extracted from the memory system and transfer the sector data to the read buffer.

[0156] The address counter generates a global count indicating the number of sectors for processing data by comparing a start address and an end address of the input data, a front count indicating a range between a start point of the sector and the start address, a rear count indicating a range between the end address and an end point of the sector, and a write count indicating the second area.

[0157] The front count and the rear count indicate the first area.

[0158] The data processor is provided in the timing controller.

[0159] Embodiments of the present disclosure may provide a data processor incorporated into a memory system that processes data in units of sectors, including: a data input unit configured to receive input data; an address input unit configured to receive an address of the input data; an address counter configured to use the address of the input data to determine a first area for holding sector data stored in the memory system and a second area for writing the input data into a sector; a read buffer configured to transfer the sector data provided from the memory system; a switch circuit configured to transfer the input data or the sector data under the control of the address counter; and a write buffer configured to write the data transferred from the switch circuit into the memory system.

[0160] Embodiments of the present disclosure may provide a data processing method for a display device, including steps of receiving input data and an address, using sector information of a memory system to determine a position number and a size number of the address, extracting count information for processing data in units of sectors corresponding to the input data, and processing the data in units of sectors using the count information.

[0161] The count information includes: a global count indicating the number of sectors for processing data by comparing a start address and an end address of the input data; a front count indicating a range between a start point of a sector and the start address; a rear count indicating a range between the end address and an end point of the sector; and a write count indicating an area for writing the input data.

[0162] The front count and the rear count indicate areas for holding data in a sector.

[0163] The data processing method further includes a step of converting the address into a binary number.

[0164] The above description has been presented to enable any person skilled in the art to make and use the technical conceptions of the present disclosure, and the above description has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. The above description and the drawings have provided examples of the technical conceptions of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical conceptions of the present disclosure.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; A memory system configured to process input data in units of sectors or smaller than sectors; a timing controller configured to control a data read operation and a data write operation on the memory system; as well as A data processor is configured to maintain sector data stored in a first area within a sector and store the input data in a second area within the sector based on an address of the input data.

2. The display device according to claim 1, wherein: The memory system includes flash memory.

3. The display device according to claim 1, wherein: The sector has a size of 4 KB.

4. The display device according to claim 1, wherein: The address of the input data includes: a position number corresponding to the position of the sector; and A size number corresponding to the size of the sector.

5. The display device according to claim 4, wherein: When the address of the input data consists of 8 hexadecimal digits, the position digit is the upper 5 digits, and the size digit is the lower 3 digits.

6. The display device according to claim 1, wherein: The data processor comprises: a data input unit, the data input unit being configured to receive the input data; An address input unit, the address input unit being configured to receive an address of the input data; an address counter configured to determine the first region and the second region using an address of the input data; a read buffer configured to transfer the sector data provided from the memory system; a switch circuit configured to transfer the input data or the sector data according to control of the address counter; and A write buffer is configured to write data transferred from the switch circuit to the memory system.

7. The display device according to claim 6, wherein: The data processor further includes a connector configured to combine the sector data in units of sectors extracted from the memory system and transfer the sector data to the read buffer.

8. The display device according to claim 6, wherein: The address counter generates: a global count indicating the number of sectors used to process data by comparing a starting address of the input data to an ending address; indicating a front count of a range between a start point of the sector and a start address of the input data; a back count indicating a range between an end address of the input data and an end point of the sector; as well as Indicates a write count of the second region.

9. The display device according to claim 8, wherein: The front count and the rear count indicate the first region.

10. The display device according to claim 1, wherein: The data processor is disposed in the timing controller.

11. A data processor incorporated into a memory system for processing data in units of sectors or smaller than sectors, comprising: a data input unit configured to receive input data; An address input unit, the address input unit being configured to receive an address of the input data; an address counter configured to determine a first area for holding sector data stored in the memory system and a second area for writing the input data into a sector using an address of the input data; a read buffer configured to transfer the sector data provided from the memory system; a switch circuit configured to transfer the input data or the sector data according to control of the address counter; and A write buffer is configured to write data transferred from the switch circuit to the memory system. 12 . The data processor according to claim 11 , further comprising a connector configured to combine the sector data in units of sectors extracted from the memory system and transfer the sector data to the read buffer.

13. The data processor according to claim 11, wherein: The address counter generates: a global count indicating the number of sectors used to process data by comparing a starting address of the input data to an ending address; indicating a front count of a range between a start point of the sector and a start address of the input data; a back count indicating a range between an end address of the input data and an end point of the sector; as well as Indicates a write count of the second region.

14. The data processor according to claim 13, wherein: The front count and the rear count indicate the first region.

15. A data processing method for a display device, comprising: receiving input data and an address of the input data; Using sector information of the memory system to determine the location number and the size number of the address; extracting counting information corresponding to the input data for processing data in units of sectors or less than sectors; as well as Data is processed in units of sectors or smaller than sectors using the count information.

16. The data processing method according to claim 15, wherein: When the address of the input data consists of 8 hexadecimal digits, the position digit is the upper 5 digits, and the size digit is the lower 3 digits.

17. The data processing method according to claim 15, wherein: The counting information includes: a global count indicating the number of sectors used to process data by comparing a starting address of the input data to an ending address; A front count indicating a range between a start point of a sector and a start address of the input data; a back count indicating a range between an end address of the input data and an end point of the sector; and A write count indicating a region for writing the input data.

18. The data processing method according to claim 17, wherein: The front count and the rear count indicate an area for holding data in the sector.

19. The data processing method according to claim 15, further comprising: Convert the address to a binary number.

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