Display device

Abstract

A display device is provided that includes a substrate including a display area and a peripheral area outside the display area. The first active pattern is arranged in the display area. The first gate electrode is disposed on the first active pattern. The second active pattern is disposed on the first gate electrode. A second gate electrode is disposed on the second active pattern. The dummy pattern is arranged in the peripheral area. The dummy pattern extends in a first direction. The dummy pattern and the second gate electrode are provided in the same layer.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0163697 filed in the Korean Intellectual Property Office on November 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments relate to a display device. Background Art

[0003] A display device generates an image as a view of segments containing various electrical signal information. As the display industry has developed, thinner, lighter weight, and lower power consumption display devices are being developed. Among display devices, organic light emitting display devices have advantages such as wide viewing angle, excellent contrast, and fast response speed, thereby gaining attention as the next generation display device.

[0004] The organic light-emitting display device includes a thin film transistor (TFT) and a capacitor as a driving circuit. The TFT may include an active layer and a gate electrode, the active layer including a channel region, a source region and a drain region, and the gate electrode is electrically insulated from the active layer by a gate insulating layer. Generally, the active layer of the TFT may be formed of a silicon semiconductor material such as amorphous silicon or polycrystalline silicon. Alternatively, the active layer of the TFT may be formed of an oxide semiconductor material. Summary of the invention

[0005] One or more embodiments include a display device having improved device characteristics and reduced occurrence of defects of a thin film transistor. However, the scope of the embodiments of the present disclosure is not limited in these respects.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the described non-limiting embodiments disclosed.

[0007] According to an embodiment of the present disclosure, a display device includes a substrate including a display area and a peripheral area outside the display area. A first active pattern is arranged in the display area. A first gate electrode is arranged on the first active pattern. A second active pattern is arranged on the first gate electrode. The second gate electrode is arranged on the second active pattern. A dummy pattern is arranged in the peripheral area. The dummy pattern extends in a first direction. The dummy pattern and the second gate electrode are arranged on the same layer.

[0008] In an embodiment, the second gate electrode may extend in a first direction; the second active pattern may extend in a second direction crossing the first direction; and the second active pattern may at least partially overlap the second gate electrode in a plan view.

[0009] In an embodiment, the display device may further include a first gate line extending in the first direction. The second gate electrode is electrically connected to the first gate line through a contact hole penetrating the insulating layer between the second gate electrode and the first gate line.

[0010] In an embodiment, the first gate line may be disposed between the first gate electrode and the second active pattern.

[0011] In an embodiment, the display device may further include a first sub-pixel and a second sub-pixel, the first sub-pixel including a first sub-pixel circuit, the second sub-pixel including a second sub-pixel circuit, the first sub-pixel and the second sub-pixel being arranged in a display area to be adjacent to each other. The first sub-pixel circuit may include a first active pattern, a first gate electrode, a second active pattern, and a second gate electrode, and the first sub-pixel circuit and the second sub-pixel circuit may have shapes that are symmetrical to each other based on a virtual line between the first sub-pixel circuit and the second sub-pixel circuit.

[0012] In an embodiment, the second sub-pixel circuit may include: a third active pattern on the substrate; a third gate electrode disposed on the third active pattern; a fourth active pattern disposed on the third gate electrode; and a fourth gate electrode disposed on the fourth active pattern. The second gate electrode and the fourth gate electrode are integrated with each other and include one gate pattern.

[0013] In an embodiment, the gate pattern may have a shape separated from all other patterns disposed at the same layer as the gate pattern in a plan view.

[0014] In an embodiment, each of the first active pattern and the third active pattern may include a silicon semiconductor material; and each of the second active pattern and the fourth active pattern may include an oxide semiconductor material.

[0015] In an embodiment, the display device may further include: a first power line arranged in the peripheral area and extending in the first direction; and a second power line arranged outside the first power line and extending in the first direction.

[0016] In an embodiment, the dummy pattern may be electrically connected to the first power line.

[0017] In an embodiment, the display device may further include an extending portion extending from the second power line in a second direction perpendicular to the first direction.

[0018] In an embodiment, the dummy pattern may be electrically insulated from the second power line and the extension portion.

[0019] In an embodiment, in a plan view, the dummy pattern may overlap the extension portion in a plan view.

[0020] In an embodiment, the dummy pattern may include: a first dummy pattern extending in a first direction; a second dummy pattern spaced apart from the first dummy pattern and extending in the first direction; and a connecting portion connecting the first dummy pattern to the second dummy pattern. The first dummy pattern, the second dummy pattern, and the connecting portion are integral with each other.

[0021] In an embodiment, the first dummy pattern may be arranged between the display area and the first power line in a plan view.

[0022] In an embodiment, the second dummy pattern may overlap the first power line in a plan view.

[0023] In an embodiment, the second dummy pattern may overlap at least some of the extending portions in a plan view.

[0024] In an embodiment, the dummy pattern may be spaced apart from and not overlap the extending portion in a plan view.

[0025] In an embodiment, the dummy pattern may include: a first dummy pattern extending in a first direction; a second dummy pattern spaced apart from each other in the first direction; and a connecting portion connecting the second dummy pattern to the first dummy pattern, respectively. The first dummy pattern, the second dummy pattern and the connecting portion may be integral with each other.

[0026] In an embodiment, each of the second dummy patterns may be disposed between two adjacent extending portions in a plan view. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other aspects, features and advantages of certain non-limiting embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which: Figure 1 is a schematic plan view showing a portion of a display device according to an embodiment of the present disclosure; Figure 2 The present invention is a diagram showing an embodiment of the present invention. Figure 1 A schematic side view of a display device; Figure 3 is a schematic plan view showing a display panel according to an embodiment of the present disclosure; Figure 4 and Figure 5 According to the embodiment of the present disclosure Figure 3 A schematic enlarged plan view of a portion A of FIG. Figure 6 is an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment of the present disclosure; Figure 7 is a schematic plan view showing the structure of a sub-pixel circuit according to an embodiment of the present disclosure; FIG. 8A to FIG. 8H The structure of the embodiment according to the present disclosure is shown in FIG. Figure 7 A plan view of various layers of components of a sub-pixel circuit; Fig. 9 is a schematic cross-sectional view showing a portion of a sub-pixel circuit according to an embodiment of the present disclosure; Fig.10 is a schematic plan view showing a portion of a sub-pixel circuit according to an embodiment of the present disclosure; Fig.11 is taken along line BB' according to an embodiment of the present disclosure Fig.10 A schematic cross-sectional view of a sub-pixel circuit; Fig.12 The present invention is a diagram showing an embodiment of the present invention. Fig.11 A sectional view of a modified example of ; Fig.13 According to the embodiment of the present disclosure Figure 3 A schematic enlarged plan view of a portion D of FIG. FIG. 14A to FIG. 14E The present invention is a diagram showing an embodiment of the present invention. Fig.13 Floor plans of each level of the structure; Fig.15 is taken along line II' according to an embodiment of the present disclosure Fig.13 A schematic cross-sectional view of a display panel; Fig.16 The present invention is a diagram showing an embodiment of the present invention. Fig.13 A plan view of a modified example of ; Fig.17 The present invention is a diagram showing an embodiment of the present invention. Fig.16 floor plans of some of the floors; and Fig.18 is taken along line II-II' according to an embodiment of the present disclosure Fig.16 Schematic cross-sectional view of a display panel. DETAILED DESCRIPTION

[0028] Now will refer to the embodiment in detail, examples of the embodiment are shown in the accompanying drawings, wherein the same reference numerals always represent the same elements. In this regard, the present embodiment can have different forms and should not be construed as being limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain the various aspects of this description. As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. Throughout the specification, the expression "at least one (kind / person) of ... a, b and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c or variations thereof.

[0029] Since the present disclosure allows various changes and many embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. By referring to the drawings and embodiments described in detail below, the effects and features of the present disclosure and the methods for realizing them will become apparent. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0030] The present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments are shown. Like reference numerals in the drawings represent like elements, and thus their description will not be repeated.

[0031] In the following embodiments, terms such as “first”, “second”, etc. may be used simultaneously to describe various elements, and thus these elements must not be limited to the above terms.

[0032] In the following embodiments, expressions used in the singular include expressions in the plural unless they have obviously different meanings in the context.

[0033] In the following embodiments, it will be understood that terms such as “including,” “having,” and “comprising” are intended to indicate the presence of features or elements disclosed in the specification, and are not intended to exclude the possibility that one or more other features or elements may exist or may be added.

[0034] It will be understood that when a layer, region or element is referred to as being formed on another layer, region or element, it can be directly or indirectly formed on the other layer, region or element. That is, for example, intervening layers, regions or elements may be present.

[0035] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings may be arbitrarily shown for the convenience of explanation, the embodiments of the present disclosure are not necessarily limited thereto.

[0036] When a certain embodiment can be implemented differently, a specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0037] In the present specification, "A and / or B" may include "A", "B" or "A and B". In addition, "at least one of A and B" may include "A", "B" or "A and B".

[0038] It will be understood that when a layer, region, or component is referred to as being connected to another layer, region, or component, it may be directly or indirectly connected to the other layer, region, or component. For example, there may be intervening layers, regions, or components. For example, it will be understood that when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, it may be directly or indirectly electrically connected to the other layer, region, or component. That is, for example, there may be intervening layers, regions, or components. When a layer, region, or component is referred to as being directly connected to another layer, region, or component physically or electrically, there may be no intervening elements.

[0039] The x-direction, y-direction, and z-direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, but can be interpreted in a broader sense. For example, in an embodiment, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that intersect each other but are not perpendicular to each other.

[0040] Figure 1 is a schematic plan view showing a part of a display device according to an embodiment, and Figure 2 It is shown Figure 1 A schematic side view of a display device according to an embodiment of the present invention. Figure 2 The curve is shown in the figure, but for convenience, Figure 1 The display device in is shown as not bent.

[0041] Reference Figure 1 and Figure 2 , the display device includes a display panel 10. The display device may be any type of electronic device including the display panel 10. For example, in an embodiment, the display device may be various products such as a smart phone, a tablet computer, a laptop computer, a television, a billboard, and the like.

[0042] The display panel 10 includes a display area DA and a peripheral area PA outside the display area DA (e.g., in the x and y directions). The display area DA is a portion of the display panel 10 that displays an image. A plurality of sub-pixels may be arranged in the display area DA. The display area DA may have various shapes, such as a circular shape, an elliptical shape, a polygonal shape, other specific graphic shapes, etc. Figure 1 , the display area DA is shown to have a substantially rectangular shape having rounded corners (rounded corners). However, embodiments of the present disclosure are not necessarily limited thereto.

[0043] The peripheral area PA may be arranged outside the display area DA. In an embodiment, the peripheral area PA may include a first peripheral area PA1 arranged to surround at least a portion of the display area DA and a second peripheral area PA2 extending to one side of the display area DA (e.g., -y direction). In an embodiment, the width of the second peripheral area PA2 in one direction (e.g., x direction) may be smaller than the width of the display area DA. With this structure, at least a portion of the second peripheral area PA2 may be easily bent.

[0044] In the embodiment, since the display panel 10 includes a substrate 100 (refer to Figure 3 ), so the substrate 100 may have a display area DA and a peripheral area PA as described above. Hereinafter, for convenience, the substrate 100 is described as having a display area DA and a peripheral area PA.

[0045] The display panel 10 may also be regarded as having a main region MR, a curved region BR outside the main region MR (eg, in the −y direction), and a sub-region SR positioned on opposite sides of the main region MR around the curved region BR. Figure 2 As shown in , in the curved region BR, the display panel 10 may be curved, and when viewed from the z direction, at least a portion of the sub-region SR may overlap with the main region MR. However, the embodiments of the present disclosure are not necessarily limited to curved display devices, and may also be applied to non-curved display devices. The sub-region SR may be a non-display region, as will be described below. The display panel 10 is curved at the curved region BR, so that when the display device is viewed from the front surface (in the -z direction), the non-display region may not be seen or its visible area may be reduced.

[0046] The data pad (or "pad") unit 20 may be arranged in the sub-region SR of the display panel 10. In an embodiment, the data pad unit 20 may include an integrated circuit (eg, a driving chip) driving the display panel 10. The integrated circuit may be a data driving integrated circuit that generates a data signal. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0047] The data pad unit 20 may be mounted in the sub-region SR of the display panel 10. Although the data pad unit 20 is mounted on the same surface as the display surface of the display area DA as described above, in an embodiment, when the display panel 10 is bent at the bending region BR, the data pad unit 20 may be located on the rear surface of the main region MR. In an embodiment, the data pad unit 20 may include a plurality of pads.

[0048] The printed circuit board 30 and the like may be attached to the end of the sub-region SR of the display panel 10. The printed circuit board 30 may be electrically connected to the data pad unit 20 and the like through a plurality of pads.

[0049] In the following, according to an embodiment, an organic light-emitting display device is described as an example of a display device. However, the embodiments of the present disclosure are not necessarily limited thereto, and the display device may be of various different types. For example, in an embodiment, the display device may be an inorganic light-emitting display device, an inorganic electroluminescent display device, or a quantum dot light-emitting display device. For example, an emission layer of a display element included in a display device may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

[0050] Figure 3 is a schematic plan view of a display panel according to an embodiment.

[0051] Reference Figure 3 , the display panel 10 includes a substrate 100. Various components forming the display panel 10 are arranged on the substrate 100. In an embodiment, the substrate 100 may include glass, metal, or a polymer resin. As described above, when the display panel 10 is bent at the bending region BR, the substrate 100 should be flexible or bendable. For example, in an embodiment, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In an embodiment, the substrate 100 may have a multilayer structure, and various modifications may be made, the multilayer structure including two layers and a barrier layer arranged between the two layers, both layers including a polymer, and the barrier layer including an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.).

[0052] A plurality of sub-pixels P are arranged in the display area DA. Each of the plurality of sub-pixels P may be implemented by a display element such as an organic light emitting diode (OLED). In an embodiment, the sub-pixel P may emit, for example, red, green, blue, or white light. However, the embodiments of the present disclosure are not necessarily limited thereto, and the plurality of sub-pixels P may emit a variety of different colors.

[0053] The sub-pixel P may be electrically connected to an external circuit arranged in the peripheral area PA. Figure 3 In the embodiment shown in , the first scan driving circuit 11, the second scan driving circuit 12, the emission control driving circuit 13, the terminal 14, the first power line 15 and the second power line 16 may be arranged in the peripheral area PA.

[0054] The first scan drive circuit 11 may provide a scan signal to the sub-pixel P through the scan line SL. In an embodiment, the second scan drive circuit 12 may be arranged in parallel with the first scan drive circuit 11, with the display area DA (e.g., in the x direction) between them. Some of the sub-pixels P arranged in the display area DA may be electrically connected to the first scan drive circuit 11, and the remaining sub-pixels P may be connected to the second scan drive circuit 12. However, the embodiments of the present disclosure are not necessarily limited thereto, and the number of scan drive circuits may vary. For example, in an embodiment, the second scan drive circuit 12 may be omitted.

[0055] In an embodiment, the emission control driving circuit 13 may be disposed on one side of the first scanning driving circuit 11 and provide an emission control signal to the sub-pixel P through the emission control line EL. Figure 3 In the embodiment, the emission control driving circuit 13 is arranged only on one side of the display area DA, but similar to the first scan driving circuit 11 and the second scan driving circuit 12, the emission control driving circuit 13 can also be arranged on both sides of the display area DA.

[0056] In an embodiment, the terminal 14 may be disposed in the second peripheral area PA2 of the substrate 100. In an embodiment, the terminal 14 may be exposed by not being covered by the insulating layer and may be electrically connected to the printed circuit board 30. The terminal 34 of the printed circuit board 30 may be electrically connected to the terminal 14 of the display panel 10.

[0057] The printed circuit board 30 transmits a signal or power of the controller to the display panel 10. In an embodiment, the control signal generated by the controller may be transmitted to each of the first scan driving circuit 11, the second scan driving circuit 12, and the emission control driving circuit 13 through the printed circuit board 30. In addition, the controller may provide a first power voltage ELVDD (refer to FIG. 1 ) to the first power line 15 and the second power line 16, respectively. Figure 6 ) and the second power voltage ELVSS (reference Figure 6 ). A first power voltage (e.g., a driving voltage) ELVDD may be supplied to each sub-pixel P through a driving voltage line PL connected to the first power line 15, and a second power voltage (e.g., a common voltage) ELVSS may be supplied to a counter electrode of the sub-pixel P connected to the second power line 16. In addition, the controller may generate a data signal, and the generated data signal may be transmitted to the input line IL through the data pad unit 20, and transmitted to the sub-pixel P through the data line DL connected to the input line IL.

[0058] In an embodiment, the first power line 15 may include a first-1 power line 15-1, a first-2 power line 15-2, and a first-3 power line 15-3. In an embodiment, the first-1 power line 15-1 may extend in the second direction (e.g., the y direction), and the first-2 power line 15-2 and the first-3 power line 15-3 may extend in the first direction (e.g., the x direction). For example, the first-3 power line 15-3 may extend along the second edge E2 at the upper side (e.g., in the y direction) of the display area DA. In an embodiment, the first-1 power line 15-1, the first-2 power line 15-2, and the first-3 power line 15-3 may be integrally provided (e.g., may be integral with each other). For example, in an embodiment, the first-1 power line 15-1 and the first-2 power line 15-2 of the first power line 15 may have a "Π" shape as a whole. However, embodiments of the present disclosure are not necessarily limited thereto.

[0059] In an embodiment, the second power line 16 may have a loop shape with one side open in a plan view to partially surround the display area DA. For example, the second power line 16 may extend along the second edge E2, the third edge E3, and the fourth edge E4 of the display area DA. In an embodiment, the second power line 16 may be arranged outside the first power line 15.

[0060] Figure 4 and Figure 5 yes Figure 3 Schematic enlarged plan view of portion A of FIG.

[0061] Reference Figure 4 , various signals may be applied to the display area DA. For example, a data signal for adjusting the brightness of each of the sub-pixels, etc. may be applied to the display area DA, and for this purpose, as shown in FIG. Figure 4 As shown in FIG. 1 , first to sixth data lines DL1 to DL6 substantially parallel to each other may be disposed on an upper portion of the substrate 100 within the display area DA. In an embodiment, in addition to the first to sixth data lines DL1 to DL6, various lines such as power lines, scan lines, etc. may also be positioned inside and outside the display area DA.

[0062] In an embodiment, input lines IL, such as first to sixth input lines IL1 to IL6, each connected to (e.g., directly connected to) the data pad unit 20 and receiving a data signal, may be arranged in a peripheral area PA, such as the second peripheral area PA2. In an embodiment, first to sixth data lines DL1 to DL6 may be connected to (e.g., directly connected to) the first to sixth input lines IL1 to IL6, respectively, to transmit a data signal to each sub-pixel.

[0063] For ease of explanation, Figure 4 and Figure 5 Six input lines and six data lines are shown. However, embodiments of the present disclosure are not necessarily limited thereto, and the number of input lines IL and data lines DL may vary.

[0064] The first to sixth input lines IL1 to IL6 may be sequentially arranged in a direction from the edge of the second peripheral area PA2 to the center of the second peripheral area PA2 (e.g., in the x direction). In an embodiment, the first input line IL1, the third input line IL3, and the fifth input line IL5 at odd positions may be respectively connected to the first data line DL1, the third data line DL3, and the fifth data line DL5 that are adjacent to each other and arranged continuously. In some embodiments, the first input line IL1, the third input line IL3, and the fifth input line IL5 may be formed integrally with the first data line DL1, the third data line DL3, and the fifth data line DL5, respectively, or the first input line IL1, the third input line IL3, and the fifth input line IL5 may be respectively connected to (e.g., directly connected to) the first data line DL1, the third data line DL3, and the fifth data line DL5 through the first contact hole CNT1. The first input line IL1, the third input line IL3, and the fifth input line IL5 may receive data signals from the first data line DL1, the third data line DL3, and the fifth data line DL5, respectively.

[0065] The second input line IL2, the fourth input line IL4, and the sixth input line IL6 at the even-numbered positions may be connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6, respectively, which are adjacent to each other and arranged continuously (e.g., in the -x direction). For example, the second data line DL2, the fourth data line DL4, and the sixth data line DL6 may receive data signals from the second input line IL2, the fourth input line IL4, and the sixth input line IL6, respectively, through the first to third data transmission lines DTL1 to DTL3.

[0066] The first to third data transmission lines DTL1 to DTL3 may be arranged to pass through the display area DA by bypassing a portion of the display area DA adjacent to the peripheral area PA. The second input line IL2 is electrically connected to the second data line DL2 through the first data transmission line DTL1, the fourth input line IL4 is electrically connected to the fourth data line DL4 through the second data transmission line DTL2, and the sixth input line IL6 is electrically connected to the sixth data line DL6 through the third data transmission line DTL3.

[0067] In an embodiment, one end of each of the first to third data transmission lines DTL1 to DTL3 may be respectively connected to each of the second input line IL2, the fourth input line IL4, and the sixth input line IL6 through the second contact hole CNT2, and the other end of each of the first to third data transmission lines DTL1 to DTL3 may be respectively connected to each of the second data line DL2, the fourth data line DL4, and the sixth data line DL6 through the third contact hole CNT3. Figure 4 and Figure 5 It is shown that the second contact hole CNT2 and the third contact hole CNT3 are positioned in the peripheral area PA. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the second contact hole CNT2 and / or the third contact hole CNT3 may also be positioned in the display area DA. Therefore, the second input line IL2 may transmit a data signal to the second data line DL2, the fourth input line IL4 may transmit a data signal to the fourth data line DL4, and the sixth input line IL6 may transmit a data signal to the sixth data line DL6.

[0068] Reference Figure 5 , shows the connection relationship between the first to third data transmission lines DTL1 to DTL3 and the second input line IL2, the fourth input line IL4, the sixth input line IL6, the second data line DL2, the fourth data line DL4 and the sixth data line DL6 outside the display area DA where the first to third data transmission lines DTL1 to DTL3 are arranged. Figure 5 can be understood as the above Figure 4 Schematic diagram of .

[0069] Reference Figure 5 In an embodiment, the second input line IL2 , the fourth input line IL4 , and the sixth input line IL6 may be electrically connected to the second data line DL2 , the fourth data line DL4 , and the sixth data line DL6 through the first to third data transmission lines DTL1 to DTL3 , respectively.

[0070] In an embodiment, the first to third data transmission lines DTL1 to DTL3 are shown to include first connection lines DH1 to DH3, second connection lines DV1 to DV3, and third connection lines DV1' to DV3', respectively. In an embodiment, the first connection lines DH1 to DH3 may extend in a first direction (e.g., x direction) crossing the second direction (e.g., y direction), and the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may extend in a second direction (e.g., y direction) substantially parallel to the data lines.

[0071] In an embodiment, the second input line IL2, the fourth input line IL4, and the sixth input line IL6 may be connected to the second connection lines DV1 to DV3 through the second contact holes CNT2, respectively, and the third connection lines DV1' to DV3' may be connected to the second data lines DL2, the fourth data lines DL4, and the sixth data lines DL6 through the third contact holes CNT3, respectively. The first connection lines DH1 to DH3 may be connected to the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3', respectively, through the first connection contact holes DH-CNT1 and the second connection contact holes DH-CNT2, respectively positioned at one end and the other end of each of the first connection lines DH1 to DH3.

[0072] In an embodiment, the first connection lines DH1 to DH3, the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may be arranged on the same layer with each other, or at least some of them may also be arranged on different layers. For example, in an embodiment, the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may be arranged on the same layer, and the first connection lines DH1 to DH3 may be arranged on different layers from the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3'. The lines being arranged on the same layer may mean that the lines are formed simultaneously by the same mask process and include the same materials as each other. As described above, when the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' are arranged on the same layer, the second connection lines DV1 to DV3 and the third connection lines DV1' to DV3' may be arranged on the same layer with the data lines DL.

[0073] In an embodiment, the first connection lines DH1 to DH3 may overlap some of the first to sixth data lines DL1 to DL6 (eg, in the z direction). The first connection lines DH1 to DH3 may be arranged to pass under the first to sixth data lines DL1 to DL6 (eg, in the z direction). Figure 5 As shown in the figure, the first connection line DH1 can partially overlap with the first data line DL1, the first connection line DH2 can partially overlap with the first data line DL1, the second data line DL2 and the third data line DL3, and the first connection line DH3 can partially overlap with the first data line DL1, the second data line DL2, the third data line DL3, the fourth data line DL4 and the fifth data line DL5.

[0074] In an embodiment, the dummy line may also be provided in the same layer as each of the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3'. In an embodiment, the dummy line may be formed continuously with each of the first connection lines DH1 to DH3, the second connection lines DV1 to DV3, and the third connection lines DV1' to DV3', and may be provided to be electrically disconnected in some areas to construct the first data transmission line DTL1 to the third data transmission line DTL3. The disconnected portion of the dummy line may be positioned around the above-mentioned first connection contact hole DH-CNT1 and the second connection contact hole DH-CNT2. In an embodiment, the dummy line may exist in the form of a floating electrode insulated from other electrodes and / or lines, and a signal or electrostatic voltage may also be applied to the dummy line to prevent static electricity, etc.

[0075] Figure 6 is an equivalent circuit diagram of a sub-pixel included in a display device according to an embodiment.

[0076] Reference Figure 6 , a sub-pixel P may include a sub-pixel circuit PC and an organic light emitting diode OLED.

[0077] For example, Figure 6 As shown in , the sub-pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The plurality of thin film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines SL1, SL2, SLp, SLn, EL, DL, a first initialization voltage line VL1, a second initialization voltage line VL2, and a drive voltage line PL. In an embodiment, at least one of the above lines (e.g., the drive voltage line PL) may be shared by adjacent sub-pixels P.

[0078] In an embodiment, the plurality of thin film transistors T1 to T7 may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6 and a second initialization thin film transistor T7.

[0079] In an embodiment, the organic light emitting diode OLED may include a sub-pixel electrode (e.g., an anode) and a counter electrode (e.g., a cathode), and the sub-pixel electrode of the organic light emitting diode OLED may be connected to the driving thin film transistor T1 via the emission control thin film transistor T6 to receive the driving current, and its counter electrode may be provided with a common voltage ELVSS. The organic light emitting diode OLED may emit light having a brightness corresponding to the driving current.

[0080] Some of the plurality of thin film transistors T1 to T7 may be set as n-channel metal oxide semiconductor field effect transistors (MOSFET) (NMOS), and the remaining transistors may be set as p-channel MOSFET (PMOS). For example, in an embodiment, among the plurality of thin film transistors T1 to T7, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may be set as NMOS, and the remaining transistors (e.g., T1, T2, and T5 to T7) may be set as PMOS. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0081] For example, in an embodiment, among the plurality of thin film transistors T1 to T7, the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 may be set to NMOS, and the remaining transistors (e.g., T1, T2, T5, T6) may be set to PMOS. Alternatively, only one of the plurality of thin film transistors T1 to T7 may be set to NMOS, and the remaining transistors may be set to PMOS. Alternatively, all of the plurality of thin film transistors T1 to T7 may be set to NMOS.

[0082] In an embodiment, the signal line may include a first scan line SL1 configured to transmit a first scan signal Sn, a second scan line SL2 configured to transmit a second scan signal Sn', a previous scan line SLp configured to transmit a previous scan signal Sn-1 to the first initialization thin film transistor T4, an emission control line EL configured to transmit an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, a next scan line SLn configured to transmit a next scan signal Sn+1 to the second initialization thin film transistor T7, and a data line DL crossing the scan line SL and configured to transmit a data signal Dm.

[0083] In an embodiment, the driving voltage line PL can be constructed to transmit the driving voltage ELVDD to the driving thin film transistor T1, the first initialization voltage line VL1 can be constructed to transmit the first initialization voltage Vint to initialize the driving thin film transistor T1, and the second initialization voltage line VL2 can be constructed to transmit the second initialization voltage Aint to initialize the sub-pixel electrode of the organic light emitting diode OLED.

[0084] The driving gate electrode of the driving thin film transistor T1 may be connected to the storage capacitor Cst, the driving source region of the driving thin film transistor T1 may be connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving drain region of the driving thin film transistor T1 may be electrically connected to the sub-pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 may receive the data signal Dm in response to the switching operation of the switching thin film transistor T2, and supply a driving current to the organic light emitting diode OLED.

[0085] The switching gate electrode of the switching thin film transistor T2 may be connected to the first scan line SL1 configured to transmit the first scan signal Sn, the switching source region of the switching thin film transistor T2 may be connected to the data line DL, the switching drain region of the switching thin film transistor T2 may be connected to the driving source region of the driving thin film transistor T1 and connected to the driving voltage line PL via the operation control thin film transistor T5. In an embodiment, the switching thin film transistor T2 may be turned on in response to the first scan signal Sn received through the first scan line SL1, and may perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source region of the driving thin film transistor T1.

[0086] In an embodiment, the compensation gate electrode of the compensation thin film transistor T3 is connected to the second scan line SL2. The compensation drain region of the compensation thin film transistor T3 can be connected to the sub-pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6, and is simultaneously connected to the driving drain region of the driving thin film transistor T1. The compensation source region of the compensation thin film transistor T3 can be connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin film transistor T1. In addition, the compensation source region can be connected to the first initialization drain region of the first initialization thin film transistor T4.

[0087] In an embodiment, the compensation thin film transistor T3 may be turned on in response to the second scan signal Sn′ received through the second scan line SL2 and electrically connected to the driving gate electrode and the driving drain region of the driving thin film transistor T1 to diode-connect the driving thin film transistor T1 .

[0088] In an embodiment, a first initialization gate electrode of the first initialization thin film transistor T4 may be connected to a previous scan line SLp. A first initialization source region of the first initialization thin film transistor T4 may be connected to a first initialization voltage line VL1. A first initialization drain region of the first initialization thin film transistor T4 may be connected to a first electrode CE1 of a storage capacitor Cst, a compensation source region of the compensation thin film transistor T3, and a driving gate electrode of the driving thin film transistor T1. In an embodiment, the first initialization thin film transistor T4 may be turned on in response to a previous scan signal Sn-1 received through a previous scan line SLp, and is configured to transmit a first initialization voltage Vint to a driving gate electrode of the driving thin film transistor T1 to perform an initialization operation of initializing a voltage of the driving gate electrode of the driving thin film transistor T1.

[0089] In an embodiment, the operation control gate electrode of the operation control thin film transistor T5 can be connected to the emission control line EL, the operation control source region of the operation control thin film transistor T5 can be connected to the driving voltage line PL, and the operation control drain region of the operation control thin film transistor T5 can be connected to the driving source region of the driving thin film transistor T1 and the switching drain region of the switching thin film transistor T2.

[0090] In an embodiment, the emission control gate electrode of the emission control thin film transistor T6 can be connected to the emission control line EL, the emission control source region of the emission control thin film transistor T6 can be connected to the driving drain region of the driving thin film transistor T1 and the compensation drain region of the compensation thin film transistor T3, and the emission control drain region of the emission control thin film transistor T6 can be electrically connected to the second initialization drain region of the second initialization thin film transistor T7 and the sub-pixel electrode of the organic light emitting diode OLED.

[0091] In an embodiment, the operation control thin film transistor T5 and the emission control thin film transistor T6 may be turned on in response to the emission control signal En received through the emission control line EL, and the driving voltage ELVDD may be transmitted to the organic light emitting diode OLED to allow a driving current to flow through the organic light emitting diode OLED.

[0092] In an embodiment, the second initialization gate electrode of the second initialization thin film transistor T7 may be connected to the next scan line SLn, the second initialization drain region of the second initialization thin film transistor T7 may be connected to the emission control drain region of the emission control thin film transistor T6 and the sub-pixel electrode of the organic light emitting diode OLED, and the second initialization source region of the second initialization thin film transistor T7 may be connected to the second initialization voltage line VL2 to receive the second initialization voltage Aint. In an embodiment, the second initialization thin film transistor T7 may be turned on in response to the next scan signal Sn+1 received through the next scan line SLn, and initialize the sub-pixel electrode of the organic light emitting diode OLED.

[0093] like Figure 6 As shown in , the second initialization thin film transistor T7 can be connected to the next scan line SLn. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the second initialization thin film transistor T7 can be connected to the emission control line EL to be driven in response to the emission control signal En. The positions of the source and drain regions of the plurality of thin film transistors T1 to T7 can be changed according to the type of the transistor (e.g., p-type or n-type).

[0094] In an embodiment, the storage capacitor Cst may include a first electrode CE1 and a second electrode CE2. The first electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving thin film transistor T1, and the second electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store charges corresponding to the difference between the voltage of the driving gate electrode of the driving thin film transistor T1 and the driving voltage ELVDD.

[0095] In an embodiment, the boosting capacitor Cbs may include a first electrode CE1' and a second electrode CE2'. The first electrode CE1' of the boosting capacitor Cbs may be connected to the first electrode CE1 of the storage capacitor Cst, and the second electrode CE2' of the boosting capacitor Cbs may receive the first scan signal Sn. The boosting capacitor Cbs may compensate for a voltage drop at the driving gate electrode of the driving thin film transistor T1 by increasing a voltage of the driving gate electrode of the driving thin film transistor T1 at a time point when the supply of the first scan signal Sn is stopped.

[0096] A detailed operation of each sub-pixel P according to an embodiment is as follows.

[0097] In an embodiment, during the initialization period, when a previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1, and the driving thin film transistor T1 is initialized by the first initialization voltage Vint supplied from the first initialization voltage line VL1.

[0098] In an embodiment, during a data programming period, when a first scan signal Sn and a second scan signal Sn' are provided through a first scan line SL1 and a second scan line SL2, respectively, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn'. At this time, the driving thin film transistor T1 is diode-connected through the turned-on compensation thin film transistor T3 and is biased in the forward direction.

[0099] In an embodiment, a compensation voltage Dm+Vth (where Vth is a (-) value) obtained by reducing the data signal Dm supplied from the data line DL by the threshold voltage Vth of the driving thin film transistor T1 is applied to the driving gate electrode of the driving thin film transistor T1.

[0100] In an embodiment, the driving voltage ELVDD and the compensation voltage Dm+Vth are applied to both ends of the storage capacitor Cst, and charges corresponding to a voltage difference between both ends of the storage capacitor Cst are stored in the storage capacitor Cst.

[0101] In an embodiment, during the emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on by the emission control signal En supplied from the emission control line EL. A driving current is generated according to a voltage difference between a voltage of a driving gate electrode of the driving thin film transistor T1 and the driving voltage ELVDD, and the driving current is supplied to the organic light emitting diode OLED through the emission control thin film transistor T6.

[0102] In an embodiment, at least one thin film transistor among the plurality of thin film transistors T1 to T7 includes a semiconductor layer including oxide, and the other thin film transistors include a semiconductor layer including silicon.

[0103] For example, in an embodiment, the driving thin film transistor T1 directly affecting the brightness of the display device may be configured to include a semiconductor layer including polysilicon having high reliability, thereby realizing a display device having high resolution.

[0104] Since oxide semiconductors have high carrier mobility and low leakage current, voltage drop is relatively small even if the driving time is relatively long. For example, low-frequency driving is enabled because color change of an image according to voltage drop is relatively small even during low-frequency driving.

[0105] In an embodiment, since an oxide semiconductor has a low leakage current, at least one of the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 connected to the driving gate electrode of the driving thin film transistor T1 may include an oxide semiconductor, thereby preventing leakage current that may flow to the driving gate electrode of the driving thin film transistor T1 and reducing power consumption.

[0106] although Figure 6 It is shown that the sub-pixel circuit PC includes seven transistors and two capacitors, but the embodiments of the present disclosure are not necessarily limited to this. For example, in an embodiment, the sub-pixel circuit PC may include less than seven or eight or more transistors. For example, in an embodiment, the sub-pixel circuit PC may include eight transistors. However, the number of transistors and capacitors included in the sub-pixel circuit PC can vary as needed.

[0107] Figure 7 is a schematic plan view showing the structure of a sub-pixel circuit according to an embodiment, FIG. 8A to FIG. 8H It shows the structure Figure 7 A plan view of the various layers of components of a sub-pixel circuit, Fig. 9 is a schematic cross-sectional view showing a part of a sub-pixel circuit according to an embodiment.

[0108] Reference Figure 7 , Fig. 8A and Fig. 9 , the display device may include a first sub-pixel P1 and a second sub-pixel P2 adjacent to each other (eg, in the x direction). Figure 7 As shown in , the first sub-pixel P1 and the second sub-pixel P2 may have structures that are symmetrical to each other with respect to a virtual line. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the first sub-pixel P1 and the second sub-pixel P2 may also have a structure in which the same sub-pixel structure is continuously repeated, rather than a symmetrical structure. The first sub-pixel P1 may include a first sub-pixel circuit PC1, and the second sub-pixel P2 may include a second sub-pixel circuit PC2.

[0109] Hereinafter, for the convenience of description, some conductive patterns will be described based on the first sub-pixel circuit PC1. However, these conductive patterns may also be symmetrically arranged in the second sub-pixel circuit PC2.

[0110] In an embodiment, the substrate 100 may include glass, quartz, plastic, etc. In an embodiment, the substrate 100 may include plastic, and thus, the display device may be flexible. In this embodiment, the substrate 100 may have a structure in which at least one organic film layer and at least one barrier layer (e.g., in the z direction) are alternately stacked. For example, in an embodiment, the organic film layer may be formed by using an organic material such as polyimide, and the barrier layer may be formed by using an inorganic material.

[0111] The first conductive pattern 1000 may be disposed on the substrate 100 (e.g., directly thereon in the z direction). In an embodiment, a main portion 1010 as a portion of the first conductive pattern 1000 may be disposed in each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 adjacent to each other. The main portion 1010 may be connected (e.g., directly connected) to another portion (hereinafter referred to as a branch portion 1020) of the first conductive pattern 1000 extending in a first direction (e.g., x direction) or a second direction (e.g., y direction). In an embodiment, the main portion 1010 of the first sub-pixel circuit PC1 may be directly connected to the main portion 1010 of the second sub-pixel circuit PC2. The main portion 1010 of the first conductive pattern 1000 may overlap with the first active pattern 1100 and the first gate electrode 1220 (e.g., in the z direction) of the driving thin film transistor T1.

[0112] In an embodiment, the first conductive pattern 1000 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. For example, the first conductive pattern 1000 may include silver (Ag), an alloy containing Ag, molybdenum (Mo), an alloy containing Mo, aluminum (Al), an alloy containing Al, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0113] In the embodiment, the buffer layer 111 (see Fig. 9 ) may be disposed on (e.g., directly on) the first conductive pattern 1000. The buffer layer 111 may prevent a phenomenon in which metal atoms or impurities diffuse from the substrate 100 into the first active pattern 1100. In addition, the buffer layer 111 may adjust a heat supply rate during a crystallization process for forming the first active pattern 1100, so that the first active pattern 1100 may be uniformly formed.

[0114] Reference Figure 7 , Figure 8B and Fig. 9 , the first active pattern 1100 may be disposed on the buffer layer 111 (eg, directly thereon). In an embodiment, the first active pattern 1100 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the first active pattern 1100 may include low temperature polycrystalline silicon (LTPS).

[0115] In an embodiment, ions may be implanted into the first active pattern 1100. For example, in an embodiment where the driving thin film transistor T1, the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 are PMOS, ions such as boron may be implanted into the first active pattern 1100.

[0116] In an embodiment, a portion of the first active pattern 1100 corresponding to the second sub-pixel circuit PC2 may be referred to as a third active pattern 1100'. Figure 8C As shown in FIG. 1 , the third gate electrode 1220 ′ may be disposed on the third active pattern 1100 ′.

[0117] The first gate insulating layer 113 (see Fig. 9 ) may cover the first active pattern 1100 and may be disposed throughout the substrate 100. The first gate insulating layer 113 may include an insulating material. For example, in an embodiment, the first gate insulating layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like.

[0118] Reference Figure 7 , Figure 8C and Fig. 9 The second conductive pattern 1200 may be disposed on (eg, directly on) the first gate insulating layer 113 . In an embodiment, the second conductive pattern 1200 may include a first gate line 1210 , a first gate electrode 1220 , and a second gate line 1230 .

[0119] In an embodiment, the first gate line 1210 may extend in a first direction (eg, an x ​​direction). The first gate line 1210 may extend in a first direction (eg, an x ​​direction). Figure 6 The first gate line 1210 may correspond to the first scan line SL1 of FIG. 1100. The first gate line 1210 may constitute a switching thin film transistor T2 together with the first active pattern 1100. For example, in an embodiment, a first scan signal Sn may be provided through the first gate line 1210. In addition, the first gate line 1210 may constitute a second initialization thin film transistor T7 together with the first active pattern 1100. For example, in an embodiment, a next scan signal Sn+1 may be provided through the first gate line 1210. In an embodiment, the first scan signal Sn and the next scan signal Sn+1 may have substantially the same waveform but with a time difference.

[0120] In an embodiment, the first gate electrode 1220 may be arranged in an island shape. In an embodiment, the first gate electrode 1220 may configure the driving thin film transistor T1 together with the first active pattern 1100 .

[0121] In an embodiment, the second gate line 1230 may extend in a first direction (eg, an x ​​direction). The second gate line 1230 may extend in a first direction (eg, an x ​​direction). Figure 6 In an embodiment, the second gate line 1230 may construct an operation control thin film transistor T5 and an emission control thin film transistor T6 together with the first active pattern 1100. For example, in an embodiment, an emission control signal En may be provided through the second gate line 1230.

[0122] In an embodiment, the second conductive pattern 1200 may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0123] The second gate insulating layer 115 (eg, Fig. 9 The second gate insulating layer 115 may cover the second conductive pattern 1200 and may be disposed on (eg, directly on) the first gate insulating layer 113. Like the first gate insulating layer 113, the second gate insulating layer 115 may include an insulating material.

[0124] Reference Figure 7 , Fig.8D and Fig. 9 , the third conductive pattern 1300 may be disposed on the second gate insulating layer 115. In an embodiment, the third conductive pattern 1300 may include a third gate line 1310, a fourth gate line 1320, a storage capacitor electrode 1330 (eg, Figure 6 The second electrode CE2 of FIG. 130 ) and the first initialization voltage line 1340 (eg, Figure 6 The first initialization voltage line VL1).

[0125] In an embodiment, the third gate line 1310 may extend in a first direction (eg, an x ​​direction). The third gate line 1310 may extend in a first direction (eg, an x ​​direction). Figure 6 In an embodiment, the third gate line 1310 may be spaced apart from the first gate line 1210 in a plan view. The previous scan signal Sn-1 may be provided through the third gate line 1310.

[0126] In an embodiment, the fourth gate line 1320 may extend in the first direction (eg, the x direction). The fourth gate line 1320 may extend in the first direction (eg, the x direction). Figure 6 The fourth gate line 1320 may be spaced apart from the first gate line 1210 and the third gate line 1310 in a plan view (eg, in the y direction). The second scan signal Sn′ may be provided through the fourth gate line 1320 .

[0127] The storage capacitor electrode 1330 may overlap with the first gate electrode 1220 (e.g., in the z direction) and extend in a first direction (e.g., in the x direction). For example, the storage capacitor electrode 1330 may construct a storage capacitor Cst together with the first gate electrode 1220. The driving voltage ELVDD may be provided to the storage capacitor electrode 1330. In addition, in an embodiment, an opening 1330-OP that may penetrate the storage capacitor electrode 1330 is formed in the storage capacitor electrode 1330, and the first gate electrode 1220 may be exposed through the opening 1330-OP.

[0128] The first initialization voltage line 1340 may extend in a first direction (e.g., an x ​​direction). The first initialization voltage line 1340 may be spaced apart from the third gate line 1310 in a plan view (e.g., in a y direction). A first initialization voltage Vint may be provided through the first initialization voltage line 1340. The first initialization voltage line 1340 may at least partially overlap with a second active pattern 1400 to be described below, and may transmit the first initialization voltage Vint to the second active pattern 1400. In an embodiment, the first initialization voltage line 1340 may be provided through the second active pattern 1400 to be described below. Figure 8G The described contact holes 1680CNT1, 1680CNT2, and 1680CNT3 are electrically connected to the second active pattern 1400. The first initialization voltage line 1340 may be Figure 6 The first initialization voltage line VL1 is provided.

[0129] In an embodiment, the third conductive pattern 1300 may include, for example, a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0130] In the embodiment, the first interlayer insulating layer 117 (see Fig. 9 ) may cover the third conductive pattern 1300 and may be disposed on the second gate insulating layer 115. The first interlayer insulating layer 117 may include an insulating material. For example, in an embodiment, the first interlayer insulating layer 117 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0131] Reference Figure 7 , Fig. 8E and Fig. 9 , the second active pattern 1400 may be disposed on the first interlayer insulating layer 117. In an embodiment, the second active pattern 1400 may include an oxide semiconductor. The second active pattern 1400 may be disposed at a different layer from the first active pattern 1100 and may not overlap the first active pattern 1100 (eg, in the z direction).

[0132] The third gate insulating layer 118 may cover the second active pattern 1400, and may be disposed on the first interlayer insulating layer 117. The third gate insulating layer 118 may include an insulating material.

[0133] In an embodiment, Fig. 9 As shown in FIG. 1 , the third gate insulating layer 118 may be patterned to cover a portion of the second active pattern 1400 and expose the remaining portion of the second active pattern 1400. In an embodiment, the third gate insulating layer 118 may be formed to be similar to the second active pattern 1400 described below. Figure 8F The second active pattern 1400 may be formed in the same manner as the pattern of the second gate electrode 1520 described above. Therefore, the source region and the drain region of the second active pattern 1400 may be exposed except for the channel region overlapping the second gate electrode 1520. Fig. 9 As shown in , the source region and the drain region may be in direct contact with the second interlayer insulating layer 119 .

[0134] In an embodiment, Fig. 8E , a portion corresponding to the second sub-pixel circuit PC2 may be referred to as a fourth active pattern 1400'. In this embodiment, when a portion corresponding to the first sub-pixel circuit PC1 is referred to as the second active pattern 1400 and a portion corresponding to the second sub-pixel circuit PC2 is referred to as the fourth active pattern 1400', the second active pattern 1400 and the fourth active pattern 1400' may be regarded as provided as one body (integral body).

[0135] Reference Figure 7 , Figure 8F and Fig. 9 The fourth conductive pattern 1500 may be disposed on (eg, directly on) the third gate insulating layer 118 . In an embodiment, the fourth conductive pattern 1500 may include a second gate electrode 1520 , a fifth gate line 1530 , and a first transfer pattern 1540 .

[0136] In an embodiment, the second gate electrode 1520 (e.g., gate pattern) may overlap the third gate line 1310 and the second active pattern 1400 (e.g., in the z direction). For example, the second active pattern 1400 may at least partially overlap the second gate electrode 1520 in a plan view. In an embodiment, the second gate electrode 1520 may be electrically connected to the third gate line 1310. For example, in an embodiment, the second gate electrode 1520 may directly contact the third gate line 1310 through the contact hole 1520CNT. The contact hole 1520CNT may be formed to penetrate the insulating layer (e.g., the first interlayer insulating layer 117 and the third gate insulating layer 118) between the third gate line 1310 and the second gate electrode 1520.

[0137] In an embodiment, the previous scan signal Sn-1 may be provided through the second gate electrode 1520. The third gate line 1310, the second active pattern 1400, and the second gate electrode 1520 may configure the first initialization thin film transistor T4. For example, the third gate line 1310 may correspond to the back gate electrode of the first initialization thin film transistor T4, and the second gate electrode 1520 may correspond to the top gate electrode of the first initialization thin film transistor T4.

[0138] A portion of the fourth conductive pattern 1500 corresponding to the second sub-pixel circuit PC2 may be referred to as a fourth gate electrode 1520 ′. The fourth gate electrode 1520 ′ may overlap the fourth active pattern 1400 ′ (eg, in the z direction) to configure the first initialization thin film transistor T4 in the second sub-pixel circuit PC2 .

[0139] In an embodiment, the fifth gate line 1530 may extend in a first direction (e.g., an x ​​direction). The fifth gate line 1530 may overlap with the fourth gate line 1320 and the second active pattern 1400 (e.g., in a z direction). In some embodiments, the fifth gate line 1530 may be electrically connected to the fourth gate line 1320. For example, in an embodiment, the fifth gate line 1530 may directly contact the fourth gate line 1320 through a contact hole.

[0140] The second scan signal Sn' may be provided through the fifth gate line 1530. In an embodiment, the fourth gate line 1320, the second active pattern 1400, and the fifth gate line 1530 may construct the compensation thin film transistor T3. For example, the fourth gate line 1320 may correspond to the back gate electrode of the compensation thin film transistor T3, and the fifth gate line 1530 may correspond to the top gate electrode of the compensation thin film transistor T3.

[0141] In an embodiment, the first transmission pattern 1540 may directly contact the first gate electrode 1220 exposed through the opening 1330-OP of the storage capacitor electrode 1330. The first transmission pattern 1540 may transmit the first initialization voltage Vint to the first gate electrode 1220.

[0142] The second interlayer insulating layer 119 may be arranged to cover Figure 8F The second interlayer insulating layer 119 may include an insulating material. For example, in an embodiment, the second interlayer insulating layer 119 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc.

[0143] Reference Figure 7 , Figure 8G and Fig. 9, the fifth conductive pattern 1600 may be disposed on (eg, directly on) the second interlayer insulating layer 119. In an embodiment, the fifth conductive pattern 1600 may include a first connection line 1610, a second transmission pattern 1620, a second initialization voltage line 1630, a third transmission pattern 1640, a fourth transmission pattern 1650, a fifth transmission pattern 1660, a sixth transmission pattern 1670, and a seventh transmission pattern 1680.

[0144] In an embodiment, the first connection line 1610 may extend in a first direction (eg, an x ​​direction). A data signal Dm may be provided through the first connection line 1610 .

[0145] In an embodiment, the second transmission pattern 1620 may directly contact the first active pattern 1100 through the contact hole 1620CNT. The data signal Dm may be transmitted to the first active pattern 1100 through the second transmission pattern 1620.

[0146] In an embodiment, the second initialization voltage line 1630 (eg, Figure 6 The second initialization voltage line VL2 may extend in the first direction (eg, the x direction). The second initialization voltage Aint may be provided through the second initialization voltage line 1630. In an embodiment, the second initialization voltage line 1630 may directly contact the first active pattern 1100 through the contact hole 1630CNT and may transmit the second initialization voltage Aint to the first active pattern 1100.

[0147] In an embodiment, the third transmission pattern 1640 may directly contact the second active pattern 1400 and the first transmission pattern 1540 through contact holes 1640CNT1 and 1640CNT2 respectively disposed at one side and the other side of the third transmission pattern 1640 (e.g., in the y direction). In an embodiment, the first initialization voltage Vint may be transmitted to the first gate electrode 1220 through the second active pattern 1400, the third transmission pattern 1640, and the first transmission pattern 1540.

[0148] In an embodiment, the fourth transfer pattern 1650 may directly contact the second active pattern 1400 and the first active pattern 1100 through contact holes 1650CNT1 and 1650CNT2 disposed at one side and the other side of the fourth transfer pattern 1650 (eg, in the y direction), respectively. The fourth transfer pattern 1650 may electrically connect the second active pattern 1400 to the first active pattern 1100.

[0149] In an embodiment, the fifth transmission pattern 1660 may extend in the first direction (eg, x direction). The driving voltage ELVDD may be provided through the fifth transmission pattern 1660. In an embodiment, the fifth transmission pattern 1660 may directly contact the first active pattern 1100 through the contact hole 1660CNT and may transmit the driving voltage ELVDD to the first active pattern 1100.

[0150] In an embodiment, the sixth transmission pattern 1670 may directly contact the first active pattern 1100 through the contact hole 1670CNT. The sixth transmission pattern 1670 may transmit the driving current from the first active pattern 1100 or the second initialization voltage Aint to the organic light emitting diode OLED.

[0151] In an embodiment, the seventh transfer pattern 1680 may directly contact the second active pattern 1400 through the contact holes 1680CNT1, 1680CNT2, and 1680CNT3. Fig.8D The first initialization voltage line 1340 is directly in contact with the first initialization voltage line 1340 and is connected to the first initialization voltage line 1340 through the contact holes 1680CNT2 and 1680CNT3. Fig. 8E The second active pattern 1400 is in direct contact with the first initialization thin film transistor T4 to transmit the first initialization voltage Vint to the first initialization thin film transistor T4.

[0152] In an embodiment, the first planarization insulating layer 121 may cover the fifth conductive pattern 1600 and may be disposed on (e.g., directly on) the second interlayer insulating layer 119. In an embodiment, the first planarization insulating layer 121 may include an organic insulating material. For example, in an embodiment, the first planarization insulating layer 121 may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, etc.

[0153] Reference Figure 7 , Figure 8H and Fig. 9 , the sixth conductive pattern 1700 may be disposed on (eg, directly on) the first planarization insulating layer 121 . In an embodiment, the sixth conductive pattern 1700 may include a data line 1710 , a second connection line 1720 , a voltage line 1730 , and an eighth transmission pattern 1740 .

[0154] In an embodiment, the data line 1710 may extend in the second direction (eg, the y direction). In an embodiment, the data line 1710 may extend in the second direction (eg, the y direction). Figure 6 The data line 1710 may be connected to the second transfer pattern 1620 through the contact hole 1710CNT. The data signal Dm may be transferred to the first active pattern 1100 through the data line 1710 and the second transfer pattern 1620.

[0155] In an embodiment, the second connection line 1720 may extend in the second direction (eg, the y direction). In an embodiment, the second connection line 1720 may directly contact the first connection line 1610 .

[0156] The first sub-pixel P1 and the second sub-pixel P2 are arranged Figure 3 In an embodiment of the lower side (eg, adjacent to the first edge E1) of the display panel 10 (eg, in the -y direction), the first connection line 1610 may be connected to the lower side (eg, adjacent to the first edge E1) of the display panel 10 (eg, in the -y direction). Figure 5 The data line 1710 may correspond to the first connection lines DH1 to DH3 described above. Figure 5 The second connection line 1720 may correspond to the first data line DL1 to the sixth data line DL6 described above. Figure 5 The second connection lines DV1 to DV3 or the third connection lines DV1' to DV3' described above correspond to each other. For example, different data voltages may be provided to the data lines 1710 and the second connection lines 1720. For example, a first data voltage may be transmitted to the first active pattern 1100 through the data lines 1710, and a second data voltage different from the first data voltage may be transmitted to the first connection lines 1610 through the second connection lines 1720.

[0157] The first sub-pixel P1 and the second sub-pixel P2 are arranged Figure 3 In an embodiment of an upper side (eg, adjacent to the second edge E2) of the display panel 10 (eg, in the y direction), the first connection line 1610 and the second connection line 1720 may be electrically connected to Figure 3 In an embodiment, the common voltage line may be electrically connected to the counter electrode 230 (refer to Fig. 9 ), to transmit the common voltage ELVSS to the organic light emitting diode OLED. For example, the first connection line 1610 may be a horizontal common voltage line, and the second connection line 1720 may be a vertical common voltage line.

[0158] In an embodiment, the voltage line 1730 may extend in the second direction (eg, the y direction). The voltage line 1730 may be connected to Figure 6 The driving voltage line PL corresponds to the driving voltage line PL. The voltage line 1730 can provide the driving voltage ELVDD. In an embodiment, the voltage line 1730 can be connected to (eg, directly connected to) the fifth transmission pattern 1660 through the contact hole 1730CNT, and can provide the driving voltage ELVDD to the storage capacitor electrode 1330 and the operation control thin film transistor T5.

[0159] In an embodiment, the voltage line 1730 may be shared by the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2 adjacent to each other. However, the embodiments of the present disclosure are not necessarily limited thereto. For example, in an embodiment, the voltage line 1730 may be separately provided in each of the first sub-pixel circuit PC1 and the second sub-pixel circuit PC2.

[0160] In an embodiment, the eighth transfer pattern 1740 may directly contact the sixth transfer pattern 1670 through the contact hole 1740CNT1. The eighth transfer pattern 1740 may transfer the driving current or the second initialization voltage Aint from the sixth transfer pattern 1670 to the organic light emitting diode OLED.

[0161] In the embodiment, the eighth transmission pattern 1740 can also be connected to the sub-pixel electrode 210 (see Fig. 9 The emission control thin film transistor T6 may be electrically connected to the sub-pixel electrode 210 through the eighth transfer pattern 1740 .

[0162] In an embodiment, the second planarization insulating layer 123 may cover the sixth conductive pattern 1700 and may be disposed on (e.g., directly on) the first planarization insulating layer 121. The second planarization insulating layer 123 may include an organic insulating material. For example, in an embodiment, each of the first planarization insulating layer 121 and the second planarization insulating layer 123 may include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), a general commercial polymer (such as polymethyl methacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a p-xylene polymer, a vinyl alcohol polymer, a mixture thereof, and the like.

[0163] Reference Fig. 9 The organic light emitting diode OLED is disposed on (eg, directly on) the second planarization insulating layer 123. The organic light emitting diode OLED may include a sub-pixel electrode 210, an opposing electrode 230, and an intermediate layer 220 including an organic emission layer.

[0164] In an embodiment, the sub-pixel electrode 210 may include a (semi) transparent electrode or a reflective electrode. For example, in an embodiment, the sub-pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer formed on the reflective layer, and the reflective layer includes Ag, magnesium (Mg), Al, Pt, gold (Au), Ni, neodymium (Nd), iridium (Ir), Cr, compounds thereof, etc. The transparent or semi-transparent electrode layer may include an indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O3 ), indium gallium oxide (IGO), and aluminum oxide (AZO). For example, the sub-pixel electrode 210 may include ITO / Ag / ITO.

[0165] In an embodiment, the bank layer 125 may be disposed on (eg, directly on) the second planarization insulating layer 123. The bank layer 125 may prevent arcing, etc., at the edge of the sub-pixel electrode 210 by increasing the distance between the edge of the sub-pixel electrode 210 and the counter electrode 230 above the sub-pixel electrode 210.

[0166] In an embodiment, the bank layer 125 may be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin by a spin coating method or the like.

[0167] In an embodiment, the bank layer 125 may expose a portion of the upper surface of the sub-pixel electrode 210 to form an opening OP. For example, in an embodiment, the bank layer 125 may directly contact the lateral edge of the sub-pixel electrode 210 and may expose the central portion of the sub-pixel electrode 210 to form the opening OP. The intermediate layer 220 of the organic light emitting diode OLED may be arranged in the opening OP formed by the bank layer 125. The emission region of the organic light emitting diode OLED may be defined by the opening OP.

[0168] In an embodiment, the intermediate layer 220 may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue, or white light. The organic emission layer may include a low molecular weight organic material or a polymer organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), an electron injection layer (EIL), etc. may be further selectively disposed above or below the organic emission layer.

[0169] The organic emission layer may be arranged to correspond to each of the sub-pixel electrodes 210 provided for each sub-pixel P. In addition to the organic emission layer, the intermediate layer 220 may be variously modified such as including a single layer throughout the plurality of sub-pixel electrodes 210 .

[0170] The counter electrode 230 may be a transparent electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may include a metal thin film having a low work function and including lithium (Li), calcium (Ca), Al, Ag, Mg and compounds thereof (e.g., lithium fluoride (LiF)) and a material having a multilayer structure such as lithium calcium fluoride LiF / Ca or lithium aluminum fluoride LiF / Al. In addition, a material such as ITO, IZO, ZnO or In 2 O 3A transparent conductive oxide (TCO) film may be further disposed on the metal thin film. In an embodiment, the counter electrode 230 may be integrally formed over the entire surface of the display area DA and may be disposed on the intermediate layer 220 and the bank layer 125. However, embodiments of the present disclosure are not necessarily limited thereto.

[0171] Fig.10 is a schematic plan view showing a part of a sub-pixel circuit according to the embodiment. Fig.11 It is taken along the line B-B' Fig.10 Schematic cross-sectional view of a sub-pixel circuit. Fig.12 It is used to show Fig.11 A sectional view of a modified example of .

[0172] exist Fig.10 and Fig.11 , the second active pattern 1400 and the fourth active pattern 1400' formed in one piece are referred to as the second active pattern 1400. In addition, the second gate electrode 1520 and the fourth gate electrode 1520' formed in one piece are referred to as the second gate electrode 1520. The conductive pattern forming the second gate electrode 1520 and the fourth gate electrode 1520' may be referred to as a "gate pattern". In an embodiment, the gate pattern may be arranged in an island shape. For example, the gate pattern may have a shape separated from all other patterns provided in the same layer. In an embodiment, the gate pattern may have a shape extending in a first direction (e.g., an x ​​direction).

[0173] In an embodiment, the second gate electrode 1520 and the third gate line 1310 may be disposed above and below the second active pattern 1400, respectively (e.g., in the z direction). A portion of the second gate electrode 1520 and the third gate line 1310 may overlap the second active pattern 1400 (e.g., in the z direction) to form a first initialization thin film transistor T4. In an embodiment, the second gate electrode 1520 and the third gate line 1310 may be electrically connected to each other through a contact hole 1520CNT for gate-synchronization. In an embodiment, the contact hole 1520CNT may be positioned at a central portion of the second gate electrode 1520 (e.g., gate pattern).

[0174] However, the embodiments of the present disclosure are not necessarily limited thereto. Fig.12In the embodiment shown in , the second gate electrode 1520 and the third gate line 1310" may be respectively disposed above and below the second active pattern 1400 (e.g., in the z direction) configuring the first initialization thin film transistor T4. In an embodiment, the third gate line 1310" may be included in the second conductive pattern 1200 and may be disposed on the first gate insulating layer 113 (e.g., directly thereon). The third gate line 1310" may be disposed at the same layer as the first gate line 1210, the first gate electrode 1220, and the second gate line 1230 included in the second conductive pattern 1200, and may be arranged to be spaced apart from the first gate line 1210, the first gate electrode 1220, and the second gate line 1230. The third gate line 1310" may be electrically connected to the second gate electrode 1520 through the contact hole 1520CNT. The contact hole 1520CNT may be formed to penetrate the insulating layer (eg, the second gate insulating layer 115 , the first interlayer insulating layer 117 , and the third gate insulating layer 118 ) between the third gate line 1310 ″ and the second gate electrode 1520 .

[0175] Hereinafter, an embodiment is described in which the third gate line 1310 is included in the third conductive pattern 1300 disposed between the first gate electrode 1220 and the second active pattern 1400. However, a dummy pattern of the peripheral area PA to be described below may be applied to an embodiment in which the third gate line 1310" is included in the second conductive pattern 1200 (the second conductive pattern 1200 and the first gate electrode 1220 are the same layer).

[0176] In an embodiment, the second active pattern 1400 configuring the first initialization thin film transistor T4 may include an oxide semiconductor. When hydrogen or the like generated during a process of manufacturing a display device or introduced from the outside is absorbed into the oxide semiconductor, the hydrogen or the like may be used as a carrier. A portion of the second active pattern 1400 absorbed with hydrogen or the like may be converted into a conductor.

[0177] Reference Fig.10 and Fig.11 In the second active pattern 1400, a portion overlapping the second gate electrode 1520 (e.g., in the z direction) may correspond to the channel region CH of the first initialization thin film transistor T4, and other portions exposed by not overlapping the second gate electrode 1520 (e.g., in the z direction) may correspond to the source region and the drain region of the first initialization thin film transistor T4.

[0178] Since the second gate electrode 1520 (e.g., gate pattern) has an island shape, the edge EG of the second gate electrode 1520 is relatively close to the channel region CH of the first initialization thin film transistor T4. As the distance D (e.g., the distance in the x direction) between the edge EG of the second gate electrode 1520 and the channel region CH of the first initialization thin film transistor T4 decreases, the hydrogen diffusion from the edge EG of the second gate electrode 1520 to the channel region CH of the first initialization thin film transistor T4 is relatively easy to perform. For example, when hydrogen introduced from the outside reaches the second gate electrode 1520, the region EA adjacent to the edge EG of the second gate electrode 1520 from a portion of the second active pattern 1400 overlapping the second gate electrode 1520 is easily exposed to hydrogen. When the adjacent region EA is converted into a conductor, the channel region CH of the first initialization thin film transistor T4 is reduced. Therefore, the characteristics of the first initialization thin film transistor T4 are changed.

[0179] In particular, hydrogen introduced from the outside through the peripheral area PA adjacent thereto may easily reach the edge of the display area DA (eg, the second edge E2 of the display area DA (refer to Figure 3 Therefore, it may be necessary to further pay attention to the change in the characteristics of the first initialization thin film transistor T4 having the second gate electrode 1520 in an island shape.

[0180] However, in the display device according to the embodiment, such a change in the characteristics of the first initialization thin film transistor T4 can be prevented by arranging a dummy pattern in the peripheral area PA. Figures 13 to 18 The dummy pattern is described in more detail.

[0181] Fig.13 is a schematic enlarged plan view of a portion D of a display device according to an embodiment of the present disclosure, and FIG. 14A to FIG. 14E It is shown Fig.13 Floor plans of the various levels of the structure. Fig.15 It is taken along the line I-I' Fig.13 Schematic cross-sectional view of a display device.

[0182] Fig.13 A portion of a sub-pixel circuit included in a sub-pixel arranged at an outer portion of the display area DA and a first power line 15 , a second power line 16 , and a dummy pattern 2500 arranged in the peripheral area PA are shown.

[0183] In an embodiment, the display device may include a second edge E2 (refer to Figure 3) adjacent first subpixel P1, second subpixel P2, third subpixel P3 and fourth subpixel P4. In an embodiment, the third subpixel P3 and the fourth subpixel P4 may have a structure that repeats the same subpixel structure as the first subpixel P1 and the second subpixel P2. In an embodiment, the first subpixel P1 may include a first subpixel circuit PC1, and the second subpixel P2 may include a second subpixel circuit PC2. The third subpixel P3 may include a third subpixel circuit PC3, and the fourth subpixel P4 may include a fourth subpixel circuit PC4. The first subpixel circuit PC1 may be the same as that of the first subpixel P1 and the second subpixel P2. Figures 7 to 9 The first sub-pixel circuit PC1 described corresponds to .

[0184] Reference Fig.13 , Fig.14A and Fig.15 In the peripheral area PA, the first peripheral conductive pattern 2000 may be disposed on (eg, directly on) the substrate 100 . In an embodiment, the first peripheral conductive pattern 2000 may include a first peripheral line 2010 and a first peripheral voltage line 2020 .

[0185] The first peripheral line 2010 may extend in a first direction (eg, x direction). The first peripheral line 2010 may be connected to (eg, directly connected to) a portion extending from the first conductive pattern 1000 in the display area DA.

[0186] In an embodiment, the first peripheral voltage line 2020 may extend in a first direction (eg, an x-direction).The first peripheral voltage line 2020 may be spaced apart from the first peripheral line 2010 (eg, in a y-direction) in a plan view.

[0187] The first peripheral conductive pattern 2000 may be similar to the Fig. 8A The first conductive pattern 1000 is described as being disposed at the same layer. In an embodiment, the first peripheral conductive pattern 2000 may include the same material as the first conductive pattern 1000 and may be formed in the same process as the first conductive pattern 1000.

[0188] The buffer layer 111 may be disposed on (eg, directly thereon) the first peripheral line 2010 and the first peripheral voltage line 2020 of the first peripheral conductive pattern 2000 .

[0189] Reference Fig.13 , Fig. 14B and Fig.15 , the peripheral active pattern 2100 may be disposed on (eg, directly on) the buffer layer 111 in the peripheral area PA. In an embodiment, the peripheral active pattern 2100 may include a first sub-active pattern 2110 and a second sub-active pattern 2120 .

[0190] A plurality of first sub-active patterns 2110 may be provided. The first sub-active patterns 2110 may be spaced apart from the second sub-active patterns 2120 (eg, in the y direction) in a plan view. In an embodiment, the first sub-active patterns 2110 may each be arranged in an island shape. The first sub-active patterns 2110 may be spaced apart from each other in a plan view. The first sub-active patterns 2110 may be spaced apart from each other in a plan view. Fig.14D The first sub-active pattern 2110 may prevent moisture or foreign matter from entering from the substrate 100 through the dummy hole DH (eg, in the z direction).

[0191] In an embodiment, the second sub-active pattern 2120 may extend in a first direction (eg, x direction). The second sub-active pattern 2120 may overlap with the first peripheral voltage line 2020 (eg, in z direction) in a plan view. In an embodiment, the second sub-active pattern 2120 may include an opening 2120-OP exposing the first peripheral voltage line 2020.

[0192] The peripheral active pattern 2100 can be the same as that mentioned above. Figure 8B The first active pattern 1100 is described as being disposed at the same layer. In an embodiment, the peripheral active pattern 2100 may include the same material as the first active pattern 1100 and may be formed in the same process as the first active pattern 1100.

[0193] A first gate insulating layer 113 , a second gate insulating layer 115 , a first interlayer insulating layer 117 , and a third gate insulating layer 118 may be sequentially arranged (eg, in the z-direction) on the peripheral active pattern 2100 .

[0194] Reference Fig.13 , Fig. 14C and Fig.15 The dummy pattern 2500 may be disposed on (eg, directly on) the third gate insulating layer 118 in the peripheral area PA. In an embodiment, the dummy pattern 2500 may include a first dummy pattern 2510 , a second dummy pattern 2520 , and a connecting portion 2530 .

[0195] In an embodiment, the first dummy pattern 2510 may extend in a first direction (eg, x direction). The first dummy pattern 2510 may surround at least a portion of the display area DA in a plan view. For example, in an embodiment, the first dummy pattern 2510 may extend along a second edge E2 (refer to FIG. 1 ) of the display area DA. Figure 3). The first dummy pattern 2510 may be arranged between the first peripheral voltage line 2020 and the display area DA in a plan view (e.g., in the y direction), and between the third peripheral voltage line 2710 and the display area DA in a plan view (e.g., in the y direction). That is, the first dummy pattern 2510 may be arranged between the first power line 15 and the display area DA in a plan view (e.g., in the y direction). The first dummy pattern 2510 may also be arranged between the second peripheral voltage line 2620 and the display area DA in a plan view.

[0196] In an embodiment, the second dummy pattern 2520 may extend in a first direction (eg, an x ​​direction). The second dummy pattern 2520 may be spaced apart from the first dummy pattern 2510 in a plan view (eg, in a y direction). The second dummy pattern 2520 may be spaced apart from the first peripheral voltage line 2020, Fig.14D The peripheral transmission pattern 2610 and Fig.14E The third peripheral voltage line 2710 (e.g., in the z direction) of the second dummy pattern 2520 may be overlapped. That is, the second dummy pattern 2520 may overlap the first power line 15. In an embodiment, the second dummy pattern 2520 may receive the driving voltage ELVDD through the peripheral transmission pattern 2610. The second dummy pattern 2520 may include an opening 2520-OP. The opening 2520-OP of the second dummy pattern 2520 may overlap the opening 2120-OP of the second sub-active pattern 2120 (e.g., in the z direction). The opening 2520-OP of the second dummy pattern 2520 may expose the first peripheral voltage line 2020 overlapping the opening 2120-OP of the second sub-active pattern 2120.

[0197] In an embodiment, the connection portion 2530 may extend in the second direction (eg, y direction). The connection portion 2530 may connect the first dummy pattern 2510 and the second dummy pattern 2520 to each other. In an embodiment, the first dummy pattern 2510, the second dummy pattern 2520, and the connection portion 2530 may be integrally provided.

[0198] The virtual pattern 2500 can be compared with the above reference Figure 8F The fourth conductive pattern 1500 is described as being disposed on the same layer. In an embodiment, the dummy pattern 2500 may include the same material as the fourth conductive pattern 1500 and may be formed in the same process as the fourth conductive pattern 1500. For example, the dummy pattern 2500 may be disposed on the same layer as the second gate electrode 1520 configuring the first initialization thin film transistor T4.

[0199] The display device according to the embodiment may include a dummy pattern 2500 disposed at the same layer as the second gate electrode 1520. The dummy pattern 2500 may be arranged in the peripheral area PA, and may reduce the diffusion of hydrogen from the outside into the second gate electrode 1520 of the display area DA. Therefore, the characteristic change of the first initialization thin film transistor T4 may be prevented. In addition, the process distribution of the display device may be improved, and a display device with improved reliability may be provided.

[0200] The second interlayer insulating layer 119 may be disposed on (eg, directly on) the dummy pattern 2500 .

[0201] Reference Fig.13 , Fig.14D and Fig.15 , the second peripheral conductive pattern 2600 may be disposed on the second interlayer insulating layer 119 in the peripheral area PA. In an embodiment, the second peripheral conductive pattern 2600 may include a peripheral transmission pattern 2610 , a second peripheral voltage line 2620 , and a first extension portion 2630 .

[0202] The peripheral transmission pattern 2610 may be arranged in an island shape. In an embodiment, the peripheral transmission pattern 2610 may be spaced apart from the second peripheral voltage line 2620 and the first extension portion 2630 in a plan view. The peripheral transmission pattern 2610 may be arranged between two adjacent first extension portions 2630 among the first extension portions 2630 (e.g., in the x-direction). The peripheral transmission pattern 2610 may overlap the second sub-active pattern 2120 (e.g., in the z-direction). The peripheral transmission pattern 2610 may overlap the second dummy pattern 2520 (e.g., in the z-direction). In an embodiment, the peripheral transmission pattern 2610 may directly contact the first peripheral voltage line 2020 through a contact hole 2610CNT1 overlapping the opening 2520-OP of the second dummy pattern 2520 and the opening 2120-OP of the second sub-active pattern 2120. The contact hole 2610CNT1 may penetrate the insulating layer (e.g., Fig.15 The peripheral transmission pattern 2610 may transmit the driving voltage ELVDD to the first peripheral voltage line 2020. In an embodiment, the peripheral transmission pattern 2610 may directly contact the second dummy pattern 2520 through the contact holes 2610CNT2 and 2610CNT3. The peripheral transmission pattern 2610 may transmit the driving voltage ELVDD to the second dummy pattern 2520.

[0203] In an embodiment, the second peripheral voltage line 2620 may extend in a first direction (eg, an x ​​direction). The second peripheral voltage line 2620 may extend in a first direction (eg, an x ​​direction). Figure 3 The common voltage ELVSS may be provided through the second peripheral voltage line 2620.

[0204] The first extension portion 2630 may extend from the second peripheral voltage line 2620 toward the display area DA in a second direction (eg, y direction). The first extension portion 2630 may be integrally disposed with the second peripheral voltage line 2620. The first extension portion 2630 may provide a common voltage ELVSS from the second peripheral voltage line 2620.

[0205] In an embodiment, the dummy holes DH may be formed in the same process as the contact holes 2610CNT1, 2610CNT2, and 2610CNT3 of the second peripheral conductive pattern 2600. The dummy holes DH may be respectively Fig. 14B The dummy hole DH is overlapped with the first sub-active pattern 2110 (e.g., in the z direction). The dummy hole DH may be formed by penetrating the insulating layers (e.g., the first gate insulating layer 113, the second gate insulating layer 115, the first interlayer insulating layer 117, and the third gate insulating layer 118) on the first sub-active pattern 2110. In an embodiment, the dummy hole DH may discharge hydrogen that may affect the characteristics of the oxide semiconductor to the outside (e.g., the external environment).

[0206] The second peripheral conductive pattern 2600 may be similar to the above-mentioned Figure 8G The fifth conductive pattern 1600 is described as being disposed on the same layer. In an embodiment, the second peripheral conductive pattern 2600 may include the same material as the fifth conductive pattern 1600 and may be formed in the same process as the fifth conductive pattern 1600.

[0207] The first planarization insulating layer 121 may be disposed on (eg, directly on) the second peripheral conductive pattern 2600 .

[0208] Reference Fig.13 , Fig.14E and Fig.15 , the third peripheral conductive pattern 2700 may be disposed on (eg, directly on) the first planarization insulating layer 121 in the peripheral area PA. In an embodiment, the third peripheral conductive pattern 2700 may include a third peripheral voltage line 2710, a second extension portion 2720, a fourth peripheral voltage line 2730, and a third extension portion 2740.

[0209] In an embodiment, the third peripheral voltage line 2710 may extend in a first direction (eg, an x ​​direction). The third peripheral voltage line 2710 may extend in a first direction (eg, an x ​​direction). Figure 3The third peripheral voltage line 2710 may be provided with a driving voltage ELVDD through the third peripheral voltage line 2710. The third peripheral voltage line 2710 may overlap the first peripheral voltage line 2020 and the peripheral transmission pattern 2610 (e.g., in the z direction). In an embodiment, the third peripheral voltage line 2710 may be in direct contact with the peripheral transmission pattern 2610 through the contact hole 2710CNT. The third peripheral voltage line 2710 may transmit the driving voltage ELVDD to the second dummy pattern 2520 through the peripheral transmission pattern 2610. In addition, the third peripheral voltage line 2710 may transmit the driving voltage ELVDD to the first peripheral voltage line 2020 through the peripheral transmission pattern 2610. The third peripheral voltage line 2710 may overlap the second dummy pattern 2520 (e.g., in the z direction).

[0210] The second extension portion 2720 may extend from the third peripheral voltage line 2710 in a second direction (e.g., y direction) toward the display area DA. In an embodiment, the second extension portion 2720 may be integrally provided with the third peripheral voltage line 2710. The second extension portion 2720 may be connected to (e.g., directly connected to) the voltage line 1730 of the sixth conductive pattern 1700 in the display area DA. In an embodiment, the second extension portion 2720 may be integrally provided with the voltage line 1730. The second extension portion 2720 may transmit the driving voltage ELVDD received from the third peripheral voltage line 2710 to the voltage line 1730 in the display area DA.

[0211] In an embodiment, the fourth peripheral voltage line 2730 may extend in a first direction (e.g., an x ​​direction). The fourth peripheral voltage line 2730 may be spaced apart from the third peripheral voltage line 2710 and the second extension portion 2720 in a plan view (e.g., in the y direction). The fourth peripheral voltage line 2730 may overlap with the second peripheral voltage line 2620 (e.g., in the z direction). In an embodiment, the fourth peripheral voltage line 2730 may directly contact the second peripheral voltage line 2620 through the contact hole 2730CNT. The common voltage ELVSS may be provided to the fourth peripheral voltage line 2730.

[0212] The third extension portion 2740 may extend from the second connection line 1720 of the sixth conductive pattern 1700 in the display area DA. The third extension portion 2740 may be integrally provided with the second connection line 1720. The third extension portion 2740 may be connected to the second conductive pattern 1700 through the contact holes 2740CNT, respectively. Fig.14D The third extension portion 2740 may transmit the common voltage ELVSS received from the first extension portion 2630 to the second connection line 1720.

[0213] Reference Fig.15 , the second dummy pattern 2520 may overlap at least some of the first extension portions 2630 (eg, in the z direction). For example, in an embodiment, an insulating layer (eg, Fig.15 The second interlayer insulating layer 119 of FIG. 1 may be between the second dummy pattern 2520 and the first extension portion 2630 (eg, in the z direction). As described above, the driving voltage ELVDD may be provided to the second dummy pattern 2520 and the common voltage ELVSS may be provided to the first extension portion 2630 .

[0214] Fig.16 The present invention is a diagram showing an embodiment of the present invention. Fig.13 A plan view of a modified example of . Fig.17 It is shown Fig.16 , and illustrates a plan view of some layers of the dummy pattern that is extracted and a pattern that is set on the same layer as the dummy pattern. Fig.18 It is taken along the line II-II' Fig.16 Schematic cross-sectional view of a display device. Figures 16 to 18 yes Figures 13 to 15 A modified example having a structure different in that a dummy pattern is provided. Hereinafter, the difference is mainly described, and for the sake of brevity of description, redundant description may be omitted.

[0215] Reference Fig.16 , Fig.17 and Fig.18 , the dummy pattern 2500 may be arranged in the peripheral area PA. In an embodiment, the dummy pattern 2500 may include a first dummy pattern 2510 , a second dummy pattern 2520 , and a connecting portion 2530 .

[0216] The first dummy pattern 2510 may extend in a first direction (e.g., x direction). In an embodiment, the second dummy patterns 2520 may each have an island shape. The second dummy patterns 2520 may be arranged to be spaced apart from each other in the first direction (e.g., x direction). The second dummy pattern 2520 may be spaced apart from the first dummy pattern 2510 in a plan view. The connecting portion 2530 may extend in a second direction (e.g., y direction). The connecting portion 2530 may connect the second dummy pattern 2520 to the first dummy pattern 2510, respectively.

[0217] The second dummy pattern 2520 may be spaced apart from the first extension portion 2630 in a plan view (eg, in the x-direction). The second dummy pattern 2520 may not overlap with the first extension portion 2630 (eg, in the z-direction) and may be electrically insulated therefrom. Fig.15As shown in , in the embodiment where the second dummy pattern 2520 and the first extension portion 2630 overlap each other, a short circuit and / or a burning phenomenon may occur between the second dummy pattern 2520 and the first extension portion 2630 due to external impact or impurities introduced during the manufacturing process. Fig.18 In the embodiment shown in , the second dummy pattern 2520 is spaced apart from the first extension portion 2630 and does not overlap with the first extension portion 2630 (e.g., in the z direction), and thus the probability of such short circuit and / or burning phenomenon occurring can be reduced. In addition, the characteristics of the first initialization thin film transistor T4 can be prevented from changing by including the dummy pattern 2500 disposed at the same layer as the second gate electrode 1520.

[0218] Since the display device according to the embodiment includes the dummy pattern arranged in the peripheral area, a display device having improved device characteristics and reduced occurrence of defects of a thin film transistor can be provided. However, the scope of the embodiments of the present disclosure is not limited by these effects.

[0219] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A display device, comprising: a substrate including a display area and a peripheral area outside the display area; A first active pattern, arranged in the display area; a first gate electrode, disposed on the first active pattern; a second active pattern, disposed on the first gate electrode; a second gate electrode, disposed on the second active pattern; as well as a dummy pattern arranged in the peripheral region, the dummy pattern extending in a first direction, Wherein, the dummy pattern and the second gate electrode are arranged in the same layer.

2. The display device according to claim 1, wherein: The second gate electrode extends in the first direction; The second active pattern extends in a second direction crossing the first direction; and The second active pattern at least partially overlaps the second gate electrode in a plan view.

3. The display device according to claim 1, further comprising a first gate line extending in the first direction, in, The second gate electrode is electrically connected to the first gate line through a contact hole penetrating an insulating layer between the second gate electrode and the first gate line.

4. The display device according to claim 3, wherein: The first gate line is disposed between the first gate electrode and the second active pattern.

5. The display device according to claim 1, further comprising: a first sub-pixel and a second sub-pixel, the first sub-pixel including a first sub-pixel circuit, the second sub-pixel including a second sub-pixel circuit, the first sub-pixel and the second sub-pixel being arranged in the display area to be adjacent to each other, The first sub-pixel circuit includes the first active pattern, the first gate electrode, the second active pattern and the second gate electrode, and The first sub-pixel circuit and the second sub-pixel circuit have shapes symmetrical to each other based on a virtual line between the first sub-pixel circuit and the second sub-pixel circuit.

6. The display device according to claim 5, wherein: The second sub-pixel circuit comprises: a third active pattern on the substrate; a third gate electrode, disposed on the third active pattern; a fourth active pattern disposed on the third gate electrode; and a fourth gate electrode, disposed on the fourth active pattern, The second gate electrode and the fourth gate electrode are integrated with each other and include a gate pattern.

7. The display device according to claim 6, wherein: The gate pattern has a shape separated from all other patterns disposed at the same layer as the gate pattern in a plan view.

8. The display device according to claim 6, wherein: Each of the first active pattern and the third active pattern includes a silicon semiconductor material; and Each of the second active pattern and the fourth active pattern includes an oxide semiconductor material.

9. The display device according to claim 1, further comprising: a first power line arranged in the peripheral area and extending in the first direction; as well as The second power line is arranged outside the first power line and extends in the first direction.

10. The display device according to claim 9, wherein: The dummy pattern is electrically connected to the first power line. 11 . The display device according to claim 9 , further comprising an extending portion extending from the second power line in a second direction perpendicular to the first direction.

12. The display device according to claim 11, wherein: The dummy pattern is electrically insulated from the second power line and the extending portion.

13. The display device according to claim 11, wherein: In a plan view, the dummy pattern overlaps the extending portion in a plan view.

14. The display device according to claim 13, wherein: The dummy pattern comprises: a first dummy pattern extending in the first direction; a second dummy pattern spaced apart from the first dummy pattern and extending in the first direction; and a connecting portion, connecting the first dummy pattern to the second dummy pattern, Wherein, the first dummy pattern, the second dummy pattern and the connecting portion are integrated with each other.

15. The display device according to claim 14, wherein: In a plan view, the first dummy pattern is arranged between the display area and the first power line.

16. The display device according to claim 14, wherein: The second dummy pattern overlaps the first power line in a plan view.

17. The display device according to claim 14, wherein: The second dummy pattern overlaps at least some of the extending portions in a plan view.

18. The display device according to claim 11, wherein: The dummy pattern is spaced apart from and does not overlap the extending portion in a plan view.

19. The display device according to claim 18, wherein: The dummy pattern comprises: a first dummy pattern extending in the first direction; second dummy patterns spaced apart from each other in the first direction; and connecting parts, respectively connecting the second dummy patterns to the first dummy patterns, Wherein, the first dummy pattern, the second dummy pattern and the connecting portion are integrated with each other.

20. The display device according to claim 19, wherein In a plan view, each of the second dummy patterns is arranged between two adjacent extending portions.

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