Driving substrate, manufacturing method thereof, display panel and display device

Abstract

The invention provides a driving substrate, a manufacturing method thereof, a display panel and a display device. The driving substrate comprises a first insulating layer, a wire, a second insulating layer, a flat layer, a first electrode and a second electrode. The flat layer is provided with a first via hole, the second insulating layer is provided with a second via hole, the second via hole is communicated with the first via hole, the wire is exposed out of the second via hole, part of the first electrode is arranged in the first via hole and the second via hole, and the first electrode is connected with the wire. The second electrode comprises an electrode body and a plurality of sub-electrodes, every two adjacent sub-electrodes are arranged at intervals to form a gap, the sub-electrodes and part of the electrode body are located in the first via hole, part of the first electrode is located in the gap, and the first electrode is connected with the electrode body and the sub-electrodes. Therefore, the second electrode forms a plurality of gaps at the opening of the second via hole, so that the first electrode can be deposited in the gaps, and the first electrode does not have a breakpoint at the opening of the second via hole.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a driving substrate, a manufacturing method of a driving substrate, a display panel, and a display device. Background Art

[0002] With the rapid development of display technologies, touch display panels have been widely accepted and used by people. For example, touch display panels are used in smart phones, tablet computers, etc. Touch display panels usually adopt in-cell touch technology to integrate a touch panel and a liquid crystal display panel into one, and embed the touch panel function into the liquid crystal display panel, so that the liquid crystal display panel has both the functions of display and touch input sensing.

[0003] Currently, to further simplify the structure of the touch display panel, a common electrode for forming an electric field and a touch electrode for realizing the touch function are connected through traces, so that the common electrode and the touch electrode can each realize their functions in different time periods. Since the traces are not on the same layer as the common electrode and the touch electrode, the common electrode and the touch electrode need to extend into the half-lap holes above the traces, so that the common electrode, the touch electrode and the traces are overlapped. However, the special structure of the half-lap holes easily causes disconnection between the touch electrode and the common electrode.

[0004] Therefore, how to solve the problem that the touch electrode and the common electrode of the touch display panel in the prior art are prone to disconnection in the half-lap holes is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above deficiencies of the prior art, the purpose of the present application is to provide a driving substrate, a manufacturing method of a driving substrate, a display panel, and a display device, aiming to solve the problem that the touch electrode and the common electrode of the touch display panel in the prior art are prone to disconnection in the half-lap holes.

[0006] In a first aspect, an embodiment of the present application provides a driving substrate, which includes a plurality of touch regions arranged in an array. The driving substrate further includes a first insulating layer, a plurality of traces, a second insulating layer, a planarizing layer, a plurality of first electrodes, and a plurality of second electrodes. The second insulating layer covers the plurality of traces to the first insulating layer, and the planarizing layer is disposed on a surface of the second insulating layer facing away from the first insulating layer. The planarizing layer is provided with a plurality of first vias, and the second insulating layer is provided with a plurality of second vias, and one of the second vias communicates with one of the first vias. Part of the traces are exposed from the second vias, and part of the first electrodes are disposed in the first vias and the second vias, and the first electrodes are connected to the traces. One of the second electrodes is located in one of the touch regions. The second electrode includes an electrode body and a plurality of sub-electrodes. The plurality of sub-electrodes are connected to one side of the electrode body, and adjacent two of the sub-electrodes are spaced apart to form at least one gap. The sub-electrodes and part of the electrode body are located in the first via, part of the first electrode is located in the gap, and the first electrode is respectively connected to the electrode body and the plurality of sub-electrodes, so that the second electrode is electrically connected to the trace. The first electrode is configured to emit a touch signal through the trace, and the second electrode is configured to receive a signal for display through the trace.

[0007] In the prior art, the special structure of the half-through hole easily causes disconnection between the touch electrode and the common electrode. In the driving substrate provided by the embodiment of the present application, a plurality of gaps are formed at the opening of the second via for the second electrode, so that the first electrode can be deposited in the gaps, and the first electrode will not have a break point at the opening of the second via.

[0008] In an exemplary embodiment, the width of the gap is the distance between adjacent two sub-electrodes, and is 1 μm to 3 μm.

[0009] In an exemplary embodiment, the length of the gap is the length of the sub-electrode, and is 2 μm to 4 μm.

[0010] In an exemplary embodiment, the electrode body includes at least one connecting surface facing the gap. The connecting surface is respectively connected to the sub-electrodes. The connecting surface is an inclined surface and faces the first via.

[0011] In an exemplary embodiment, the first via includes a first sidewall and a bottom wall, the first sidewall is connected to the bottom wall, and the second via includes a second sidewall, and the second sidewall is respectively connected to the first sidewall and the bottom wall. The plurality of sub-electrodes are disposed on the bottom wall, part of the electrode body is disposed on the first sidewall, and part of the first electrode is disposed on the second sidewall.

[0012] In an exemplary embodiment, the inclination angle of the connection surface relative to the bottom wall is 50 degrees to 80 degrees.

[0013] In an exemplary embodiment, the driving substrate further includes a third insulating layer disposed on the first sidewall, the second sidewall, the surface of the second electrode facing away from the flat layer, and the surface of the flat layer facing away from the second insulating layer.

[0014] In a second aspect, an embodiment of the present application further provides a method for manufacturing a driving substrate. The method for manufacturing the driving substrate is used to form the above-mentioned driving substrate. The method for manufacturing the driving substrate includes: sequentially forming a wiring, a second insulating layer, and a flat layer on a first insulating layer. The second insulating layer covers the wiring to a surface of the first insulating layer, and the flat layer is located on the surface of the second insulating layer facing away from the first insulating layer. A first via hole is formed in the flat layer and a second via hole is formed in the second insulating layer. The first via hole communicates with the second via hole, and a part of the wiring is exposed from the second via hole. A second electrode is formed in the first via hole and on the surface of the flat layer facing away from the second insulating layer. A third insulating layer is formed in the first via hole and the second via hole, wherein a part of the surface of the wiring facing away from the first insulating layer is exposed from the third insulating layer. A first electrode is formed in the first via hole and the second via hole. The first electrode is respectively connected to the second electrode and the wiring.

[0015] In a third aspect, an embodiment of the present application further provides a display panel. The display panel includes a touch control unit and the above-mentioned driving substrate. Each first electrode of the driving substrate is electrically connected to the touch control unit. The first electrode is used to send a touch control signal to the touch control unit through the wiring.

[0016] In summary, the display panel provided by the embodiment of the present application includes a touch control unit and a driving substrate. The driving substrate forms a plurality of gaps at the opening of the second via hole for the second electrode, so that the first electrode can be deposited in the gaps, and the first electrode will not have a break point at the opening of the second via hole.

[0017] In a fourth aspect, an embodiment of the present application further provides a display device. The display device includes a power supply board and the above-mentioned display panel. The power supply board is electrically connected to the display panel, and the power supply board is used to supply power to the display panel.

[0018] In summary, the display device provided by the embodiment of the present application includes a power supply board and a display panel. The display panel includes a touch control unit and a driving substrate. The driving substrate forms a plurality of gaps at the opening of the second via for the second electrode, so that the first electrode can be deposited in the gaps, and there will be no breakpoints at the opening of the second via for the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0020] Figure 1 Schematic diagram of the layer structure of the display device disclosed in the first embodiment of the present application;

[0021] Figure 2 Schematic diagram of the layer structure of the display panel disclosed in the second embodiment of the present application;

[0022] Figure 3 Schematic diagram of the distribution of the touch control area of the driving substrate disclosed in the third embodiment of the present application;

[0023] Figure 4 Schematic diagram of the distribution of the first electrode of the driving substrate disclosed in the third embodiment of the present application;

[0024] Figure 5 Schematic diagram of the layer structure of the driving substrate disclosed in this embodiment;

[0025] Figure 6 For Figure 5 The first structural schematic diagram of the second electrode shown;

[0026] Figure 7 Schematic diagram of the layer structure of the driving substrate in the prior art;

[0027] Figure 8 For Figure 5 The second structural schematic diagram of the second electrode shown;

[0028] Figure 9 For Figure 5 A specific structural schematic diagram of the driving substrate shown;

[0029] Figure 10 Schematic diagram of the process flow of the manufacturing method of the driving substrate disclosed in the fourth embodiment of the present application;

[0030] Figure 11 For Figure 10 The structural schematic diagram corresponding to the formation of step S10 shown;

[0031] Figure 12 The Figure 10 structural schematic diagram corresponding to the formed step S20 shown;

[0032] Figure 13 The Figure 10 structural schematic diagram corresponding to the formed step S30 shown;

[0033] Figure 14 The Figure 10 structural schematic diagram corresponding to the formed step S40 shown;

[0034] Figure 15 The Figure 10 specific process schematic diagram of the manufacturing method of the driving substrate shown;

[0035] Figure 16 The Figure 15 structural schematic diagram corresponding to the formed step S110 shown;

[0036] Figure 17 The Figure 15 structural schematic diagram corresponding to the formed step S120 shown;

[0037] Figure 18 The Figure 15 structural schematic diagram corresponding to the formed step S130 shown;

[0038] Figure 19 The Figure 15 structural schematic diagram corresponding to the formed step S140 shown.

[0039] Explanation of reference numerals:

[0040] 1 - Display device; 10 - Display panel; 11 - Driving substrate; 12 - Liquid crystal layer; 13 - Color filter substrate; 15 - Touch control unit; 30 - Backlight module; 111 - Substrate; 112 - First insulating layer; 113 - Circuit trace; 114 - Second insulating layer; 114a - Second via hole; 114b - Third via hole; 115 - Planarization layer; 115a - First via hole; 115b - Fourth via hole; 116 - Third insulating layer; 117 - First electrode; 118 - Second electrode; 121 - Connection electrode; 122 - Transistor; 123 - Third electrode; 141 - Side surface; 142 - First conductive layer; 143 - Second conductive layer; 144 - Conductive wire; 145 - Bottom surface; 1181 - Electrode body; 1181a - Connection surface; 1182 - Sub - electrode; 1183 - Gap; T - Touch control area; P - Sub - pixel area; a1 - First side wall; a2 - Bottom wall; a3 - Second side wall; a11 - First sub - side wall; a12 - Second sub - side wall; a31 - Third sub - side wall; a32 - Fourth sub - side wall; b1 - Gate; b2 - Active layer; b3 - Source; b4 - Drain; Step S10 - Step S50 - Steps of the manufacturing method of the driving substrate; Step S110 - Step S150 - Steps of the manufacturing method of the driving substrate. Detailed implementation manners

[0041] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0042] The descriptions of the following embodiments refer to the attached drawings, which are used to illustrate specific embodiments in which the present application can be implemented. The serial numbers assigned to the components herein, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meanings. The terms "connection" and "coupling" used in the present application, unless otherwise specified, include both direct and indirect connections (couplings). The directional terms mentioned in the present application, for example, "up", "down", "front", "back", "left", "right", "inside", "outside", "side surface", etc., are only references to the directions in the attached drawings. Therefore, the directional terms used are for better and clearer illustration and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present application.

[0043] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising", "may comprise", "including", or "may include" used in the present application indicate the presence of the corresponding functions, operations, elements, etc. disclosed, and do not limit the presence of one or more other functions, operations, elements, etc. In addition, the term "comprising" or "including" means the presence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and does not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and is intended to cover non-exclusive inclusion. It should also be understood that the meaning of "at least one" described herein is one or more, such as one, two, or three, etc., and the meaning of "a plurality" is at least two, such as two or three, etc., unless otherwise specifically defined.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments, and are not intended to limit this application.

[0045] Please refer to Figure 1 , Figure 1 , which is a schematic diagram of the layer structure of the display device disclosed in the first embodiment of the present application. The display device 1 can be used in electronic devices including but not limited to televisions, smartphones, tablet computers, laptop computers, desktop computers, mobile phones, in-vehicle displays, etc. According to the embodiments of the present application, the specific type of the display device 1 is not particularly limited, and those skilled in the art can design accordingly according to the specific usage requirements of the application of the display device 1, which will not be elaborated herein.

[0046] The display device 1 includes a display panel 10 and a backlight module 30 arranged in a stacked manner. The display panel 10 is disposed on the light-emitting side of the backlight module 30. The backlight module 30 is used to provide backlight, and the display panel 10 is used to display an image under the backlight provided by the backlight module 30.

[0047] In the embodiments of the present application, Figure 1The backlight module 30 shown may be a side-light type backlight module, and the backlight module 30 may also be a direct-lit type backlight module. The display panel 10 may be a display panel of a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in-plane switching (IPS) mode, or a fringe field switching (FFS) mode. This application does not make specific limitations thereto.

[0048] In an exemplary embodiment, the display device 1 may further include other necessary components and constituent parts such as a driving board, a power supply board, a high-voltage board, and a key control board. Those skilled in the art may make corresponding supplements according to the specific type and actual function of the display device 1, which will not be elaborated herein.

[0049] In some embodiments, the display device 1 may further include a processor and a memory. The processor is electrically connected to the display panel 10 and is configured to control the display panel 10 to perform display. The memory is electrically connected to the processor, and the memory is used to store program codes required for the operation of the processor and control the display content of the display panel 10, etc.

[0050] In an exemplary embodiment, the memory may include a volatile memory, such as a random access memory (RAM); the memory may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory (FM), a hard disk drive (HDD), or a solid-state drive (SSD). The memory may also include a combination of the above types of memories.

[0051] In an exemplary embodiment, the processor includes one or more general-purpose processors. Among them, the general-purpose processor may be any type of device capable of processing electronic instructions, including a central processing unit (CPU), a microprocessor, a microcontroller, a main processor, and a controller, etc. The processor is configured to execute various types of digital storage instructions, such as software or firmware programs stored in the memory, which can enable the computing device to provide a wide variety of services.

[0052] Please refer to Figure 2 , Figure 2Schematic diagram of the layer structure of the display panel disclosed in the second embodiment of the present application. The display panel 10 includes a driving substrate 11, a liquid crystal layer 12, and a color filter substrate 13. The driving substrate 11 and the color filter substrate 13 are opposite and spaced apart. The driving substrate 11 is used to form a preset electric field, and the preset electric field is used to drive the liquid crystal molecules in the liquid crystal layer 12 to deflect, so as to change the transmittance of the liquid crystal layer 12. Among them, the driving substrate 11 is also the array substrate of the liquid crystal display panel.

[0053] It should be noted that the driving substrate 11 of the present application can also be applied to an organic light-emitting diode (OLED) display panel, a mini light-emitting diode (Mini LED) display panel, and a micro light-emitting diode (Micro LED) display panel. The present application does not make specific limitations on this.

[0054] Please refer to Figure 3 , Figure 3 Schematic diagram of the distribution of the touch areas of the driving substrate disclosed in the third embodiment of the present application. For convenience of description, it is defined that Figure 3 the length direction of the driving substrate 11 shown is the X-axis direction, the width direction of the driving substrate 11 is the Y-axis direction, and the thickness direction of the driving substrate 11 is the Z-axis direction. The X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other in pairs.

[0055] Specifically, the driving substrate 11 includes a plurality of touch areas T and a plurality of sub-pixel areas P. The plurality of touch areas T are distributed in multiple rows along the X-axis direction and in multiple columns along the Y-axis direction, that is, the plurality of touch areas T are arranged in a multi-row and multi-column array. A plurality of sub-pixel areas P are provided in each touch area T. In one touch area T, the plurality of sub-pixel areas P are distributed in multiple rows along the X-axis direction and in multiple columns along the Y-axis direction, that is, the plurality of sub-pixel areas P are arranged in a multi-row and multi-column array. The sub-pixel area P is used to display an image, and the touch area T is used to implement a touch function.

[0056] Please refer to Figure 3 and Figure 4 , Figure 4Schematic diagram of the distribution of the first electrodes of the driving substrate disclosed in the third embodiment of the present application. The driving substrate 11 further includes a plurality of first electrodes 117 and a plurality of traces 113. The plurality of first electrodes 117 are distributed in multiple rows along the X-axis direction and in multiple columns along the Y-axis direction, that is, the plurality of first electrodes 117 are distributed in a multi-row and multi-column array. One first electrode 117 is disposed within one sub-pixel region P. One trace 113 is electrically connected to one first electrode 117. The display panel 10 further includes a touch control unit 15. Each trace 113 is electrically connected to the touch control unit 15. Each of the first electrodes 117 is electrically connected to the touch control unit 15 through a corresponding trace 113. The first electrodes 117 are configured to send touch signals to the touch control unit 15 through the traces 113, and the touch control unit 15 is configured to determine the position of the touch according to the touch signals.

[0057] Please refer to Figure 5 , Figure 5 Schematic diagram of the layer structure of the driving substrate disclosed in this embodiment. The driving substrate 11 further includes a substrate 111, a first insulating layer 112, a second insulating layer 114, a planarization layer 115, a third insulating layer 116, and a plurality of second electrodes 118. For the convenience of display and description, Figure 5 only one first electrode 117 and one second electrode 118 are shown.

[0058] In the embodiment of the present application, the first insulating layer 112 is disposed on the surface of the substrate 111 facing the Z-axis direction, that is, the first insulating layer 112 is disposed on one side of the substrate 111. The traces 113 and the second insulating layer 114 are both disposed on the surface of the first insulating layer 112 facing away from the substrate 111. The second insulating layer 114 further covers the peripheral side surface of the traces 113 and a part of the surface of the traces 113 facing away from the first insulating layer 112. That is, the second insulating layer 114 covers the traces 113 to the surface of the first insulating layer 112 facing away from the substrate 111. That is to say, the orthographic projection of the traces 113 on the substrate 111 partially coincides with the orthographic projection of the second insulating layer 114 on the substrate 111.

[0059] The planarization layer 115 is disposed on the surface of the second insulating layer 114 facing away from the first insulating layer 112. The planarization layer 115 is provided with a first via 115a penetrating the planarization layer 115 along the Z-axis. The second insulating layer 114 is provided with a second via 114a penetrating the second insulating layer 114 along the Z-axis, and the second via 114a is communicated with the first via 115a. That is, the second via 114a is formed on the bottom wall of the first via 115a. A part of the surface of the traces 113 facing away from the second insulating layer 114 exposes the second via 114a.

[0060] The second electrode 118 is disposed within the first via 115a and on the surface of the planarization layer 115 facing away from the second insulating layer 114, that is, part of the second electrode 118 is disposed within the first via 115a, and part of the second electrode 118 is disposed on the surface of the planarization layer 115 facing away from the second insulating layer 114. The third insulating layer 116 is disposed within the second via 115a and the first via 115a, and the third insulating layer 116 is located on the surface of the second electrode 118 facing away from the planarization layer 115 and on the surface of the planarization layer 115 facing away from the second insulating layer 114. The first electrode 117 is disposed on the surface of the third insulating layer 116 facing away from the planarization layer 115, on the surface of the trace 113 facing away from the first insulating layer 112, and on the surface of the second electrode 118 facing away from the second insulating layer 114. The first electrode 117 extends into the first via 115a and the second via 114a, and the first electrode 117 is connected to the second electrode 118 and the trace 113 respectively. That is, part of the first electrode 117 is disposed on the surface of the third insulating layer 116 facing away from the planarization layer 115, part of the first electrode 117 extends into the first via 115a and the second via 114a, and is disposed on the surface of the trace 113 facing away from the first insulating layer 112 and on the surface of the second electrode 118 facing away from the second insulating layer 114, and is connected to the second electrode 118 and the trace 113 respectively.

[0061] It should be noted that the first via 115a and the second via 114a form a half-overlapping via. Among them, a half-overlapping via means that: a film layer is connected to two other film layers respectively within a hole, and such a hole is called a half-overlapping via. In the present application, the first electrode 117 is connected to the trace 113 and the second electrode 118 respectively within the half-overlapping via.

[0062] The first via 115a includes a first sidewall a1 and a bottom wall a2, and the first sidewall a1 is connected to the bottom wall a2. The second via 114a includes a second sidewall a3, and the second sidewall a3 is connected to the first sidewall a1 and the bottom wall a2 respectively. Among them, the bottom wall a2 is formed by a partial surface of the second insulating layer 114 facing away from the trace 113.

[0063] The second electrode 118 is disposed on the bottom wall a2, the first side wall a1, and the surface of the planar layer 115 facing away from the second insulating layer 114. The third insulating layer 116 is disposed on the first side wall a1 and the second side wall a3, and the third insulating layer 116 covers a part of the second electrode 118. The first electrode 117 is disposed on the third insulating layer 116, on the surface where the trace 113 exposes the second via 114a, and on the second side wall a3, and the first electrode 117 is also connected to the second electrode 118. That is, the third insulating layer 116 and the second electrode 118 are disposed on the first side wall a1, the second electrode 118 is disposed on the bottom wall a2, and the third insulating layer 116 and the first electrode 117 are disposed on the second side wall a3.

[0064] More specifically, the first side wall a1 includes a first sub-side wall a11 and a second sub-side wall a12 that are opposite and spaced apart. The first sub-side wall a11 is connected to the bottom wall a2, and the second sub-side wall a12 is spaced from the bottom wall a2. The second electrode 118 is disposed on the first sub-side wall a1, the third insulating layer 116 is disposed on the surface of the second electrode 118 facing away from the first sub-side wall a1, and the first electrode 117 is disposed on the surface of the third insulating layer 116 facing away from the second electrode 118. The second electrode 118 is disposed on the bottom wall a2, and the first electrode 117 is disposed on the surface of the second electrode 118 facing away from the bottom wall a2.

[0065] The second side wall a3 includes a third sub-side wall a31 and a fourth sub-side wall a32 that are opposite and spaced apart. The third sub-side wall a31 is connected to the bottom wall a2, the fourth sub-side wall a32 is spaced from the bottom wall a2, and the fourth sub-side wall a32 is connected to the second sub-side wall a12. The first electrode 117 is disposed on the third sub-side wall a31, the third insulating layer 116 is disposed on the fourth sub-side wall a32, and the first electrode 117 is disposed on the surface of the third insulating layer 116 facing away from the fourth sub-side wall a32.

[0066] Wherein, the second electrode 118 is electrically connected to the trace 113 through the first electrode 117, and the second electrode 118 is used to receive a signal for display through the trace 113.

[0067] Please refer to Figure 6 , Figure 6 For Figure 5The first structural schematic diagram of the second electrode shown. The second electrode 118 includes an electrode body 1181 and a plurality of sub - electrodes 1182. The plurality of sub - electrodes 1182 are connected to one side of the electrode body 1181, and two adjacent sub - electrodes 1182 are spaced apart to form at least one gap 1183. Among them, a part of the electrode body 1181 is located on the first sub - sidewall a11 and the bottom wall a2, and the plurality of sub - electrodes 1182 are located on the bottom wall a2. A part of the first electrode 117 is located within the gap 1183, and the first electrode 117 is respectively connected to the electrode body 1181 and the plurality of sub - electrodes 1182, so that the second electrode 118 is electrically connected to the trace 113.

[0068] Understandably, please refer to Figure 7 , Figure 7 is a schematic diagram of the layer structure of a driving substrate in the prior art. Since the side surface 141 is relatively steep, that is, the slope of the side surface 141 is large, and the first conductive layer 142 is formed by a deposition process, a break point appears in the first conductive layer 142 at the connection between the bottom surface 145 and the side surface 141, resulting in the second conductive layer 143 not being able to be connected to the wire 144 through the first conductive layer 142. Therefore, in the present application, by forming a plurality of gaps 1183 at the connection between the bottom wall a2 and the second sidewall a3 of the second electrode 118, the first electrode 117 can be deposited within the gap 1183. The first electrode 117 located within the gap 1183 is connected to the second electrode 118, and the first electrode 117 does not have a break point at the second sidewall a3. The second electrode 118 is electrically connected to the trace 113 through the first electrode 117.

[0069] It should be noted that the first electrode 117 and the second electrode 118 operate in different time periods. The time of one - frame display includes a display time period and a touch time period. During the display time period, the second electrode 118 receives a display signal for display through the trace 113. During the touch time period, the first electrode 117 sends a touch signal to the touch unit 15 through the trace 113.

[0070] In a possible implementation manner, the third insulating layer 116 only covers the electrode body 1181, and the third insulating layer 116 does not cover the sub - electrodes 1182.

[0071] In an exemplary implementation manner, as Figure 6 shown, the distance W between two adjacent sub - electrodes 1182, that is, the width of the gap 1183, is 1 um to 3 um. For example, 1 um, 1.3 um, 1.5 um, 1.9 um, 2 um, 2.4 um, 3 um, or other values. The present application does not make specific limitations on this.

[0072] In an exemplary embodiment, the length L of the sub - electrode 1182, that is, the length of the gap 1183, is 2 um to 4 um. For example, 2 um, 2.4 um, 2.7 um, 3 um, 3.5 um, 3.8 um, 4 um, or other values. The present application does not make specific limitations thereto. Wherein, the length of the gap is along the X - axis direction, and the width of the gap is along the Y - axis direction.

[0073] In a possible embodiment, please refer to Figure 8 , Figure 8 is Figure 5 the second structural schematic diagram of the second electrode shown in. The electrode body 1181 includes at least one connecting surface 1181a. The connecting surface 1181a faces the gap 1183, and the connecting surface 1181a is respectively connected to the sub - electrode 1182. It can also be that one connecting surface 1181a is located between two adjacent sub - electrodes 1182, and this connecting surface 1181a is respectively connected to the two adjacent sub - electrodes 1182. The connecting surface 1181a is an inclined surface, and the connecting surface 1181a faces the first via 115a.

[0074] It can be understood that by setting the connecting surface 1181a connected between two adjacent sub - electrodes 1182 as an inclined surface, the contact between the electrode body 1181 and the first electrode 117 is increased, and the connection stability between the electrode body 1181 and the first electrode 117 is improved.

[0075] In an exemplary embodiment, as Figure 8 shown, the inclination angle α of the connecting surface 1181a relative to the bottom wall a2 is 50 degrees to 80 degrees. For example, 50 degrees, 58 degrees, 60 degrees, 65 degrees, 67 degrees, 70 degrees, 72 degrees, 80 degrees, or other values. The present application does not make specific limitations thereto. Wherein, the bottom wall a2 is parallel to the upper surface of the sub - electrode 1182.

[0076] It should be noted that for the convenience of display, Figure 5 only one first electrode 117 and one second electrode 118 are shown. In fact, the numbers of both the first electrode 117 and the second electrode 118 are multiple. One first electrode 117 is located within one touch area T, and one second electrode 118 is located within one touch area T or within one sub - pixel P. The number of the first vias 115a within one touch area T can be one or more, and the number of the second vias 114a within one touch area T can be one or more.

[0077] In a possible embodiment, please refer to Figure 9 , Figure 9 is Figure 5A schematic diagram of a specific structure of the driving substrate shown. The driving substrate 11 is applied to a liquid crystal display panel. The driving substrate 11 further includes a connection electrode 121, a transistor 122, and a third electrode 123. Each transistor 122 includes a gate b1, an active layer b2, a source b3, and a drain b4. The gate b1, the connection electrode 121, and the first insulating layer 112 are disposed on a surface of the substrate 111. The first insulating layer 112 also covers the peripheral side surface of the gate b1 and the surface of the gate b1 facing away from the substrate 111, that is, the first insulating layer 112 covers the gate b1 and the connection electrode 121 to a surface of the substrate 111. The active layer b2 is disposed on the surface of the first insulating layer 112 facing away from the substrate 111, and the positive projection of the active layer b2 in the Z-axis direction coincides at least partially with the positive projection of the gate b1 in the Z-axis direction, that is, the positive projection of the active layer b2 on the substrate 111 coincides at least partially with the positive projection of the gate b1 on the substrate 111. The source b3 and the drain b4 are both disposed on the surface of the first insulating layer 112 facing away from the substrate 111. The source b3 and the drain b4 are opposite and spaced apart along the X-axis direction, and the source b3 and the drain b4 are respectively connected to opposite sides of the active layer b2. The positive projection of a part of the source b3 in the Z-axis direction coincides partially with the positive projection of the gate b1 in the Z-axis direction, and the positive projection of a part of the drain b4 in the Z-axis direction coincides partially with the positive projection of the gate b1 in the Z-axis direction, that is, the positive projections of a part of the source b3 and a part of the drain b4 on the substrate 111 both coincide partially with the positive projection of the gate b1 on the substrate 111. The second insulating layer 114 covers the active layer b2, the source b3, and the drain b4.

[0078] The planarizing layer 115 is further provided with a third via hole 115b penetrating through the planarizing layer 115 along the Z-axis direction. The second insulating layer 114 is further provided with a fourth via hole 114b penetrating through the second insulating layer 114 along the Z-axis direction. The fourth via hole 114b communicates with the third via hole 115b, and the positive projection of the fourth via hole 114b in the Z-axis direction coincides with the positive projection of the third via hole 115b in the Z-axis direction. A part of the source b3 is exposed from the fourth via hole 114b. The third insulating layer 116 is disposed in the third via hole 115b and the fourth via hole 114b, and the third electrode 123 is disposed on the third insulating layer 116, and the third electrode 123 is located in the third via hole 115b and the fourth via hole 114b.

[0079] Among them, the first insulating layer 112 is used to insulate between the gate b1 and the active layer b2, insulate between the gate b1 and the source b3, and insulate between the gate b1 and the drain b4. The source b3 is electrically connected to the active layer b2, and the drain b4 is electrically connected to the active layer b2. The connection electrode 121 can be electrically connected to the gate b1, and the connection electrode 121 can provide a scanning signal to the gate b1. The gate b1 turns on the active layer b2 according to the scanning signal, and then the source b3 and the drain b4 are turned on. The source b3 is electrically connected to the third electrode 123, and the data signal transmitted by the data line (not shown in the figure) is transmitted to the third electrode 123 through the drain b4, the active layer b2, and the source b3 to control the potential of the third electrode 123.

[0080] It should be noted that for the convenience of display, Figure 9 only one connection electrode 121, one transistor 122, and one third electrode 123 are shown. In fact, the numbers of the connection electrodes 121, the transistors 122, and the third electrodes 123 are all multiple. One connection electrode 121 is located in one sub-pixel region P, one transistor 122 is located in one sub-pixel region P, and one third electrode 123 is located in one sub-pixel region P.

[0081] In an exemplary embodiment, the first electrode 117 is a touch electrode, the second electrode 118 is a common electrode, and the third electrode 123 is a pixel electrode. A preset electric field for driving the deflection of the liquid crystal molecules of the liquid crystal layer 12 is formed between the third electrode 123 and the second electrode 118.

[0082] In other embodiments, the driving substrate 11 can also be applied to an OLED display panel or a Micro LED display panel. Among them, the second electrode 118 can be an anode or a cathode electrically connected to the light-emitting element.

[0083] In summary, the driving substrate 11 provided by the embodiment of the present application includes a first insulating layer 112, a wiring 113, a second insulating layer 114, a planarizing layer 115, a first electrode 117, and a second electrode 118. The second insulating layer 114 covers the wiring 113 to a surface of the first insulating layer 112, and the planarizing layer 115 is disposed on a surface of the second insulating layer 114 facing away from the first insulating layer 112. The planarizing layer 115 is provided with a first via 115a penetrating the planarizing layer 115 along the Z axis, and the second insulating layer 114 is provided with a second via 114a penetrating the second insulating layer 114 along the Z axis, and the second via 114a is communicated with the first via 115a, and the wiring 113 is exposed from the second via 114a. The first electrode 117 is disposed in the first via 115a and the second via 114a, and the first electrode 117 is connected to the wiring 113. The second electrode 118 includes an electrode body 1181 and a plurality of sub-electrodes 1182. The plurality of sub-electrodes 1182 are connected to one side of the electrode body 1181, and two adjacent sub-electrodes 1182 are spaced apart to form at least one gap 1183. The sub-electrodes 1182 and a part of the electrode body 1181 are located in the first via 115a. A part of the first electrode 117 is located in the gap 1183, and the first electrode 117 is respectively connected to the electrode body 1181 and the plurality of sub-electrodes 1182. The second electrode 118 is electrically connected to the wiring 113 through the first electrode 117. Therefore, in the present application, by forming a plurality of gaps 1183 at the opening of the second via 114a for the second electrode 118, the first electrode 117 can be deposited in the gap 1183, and the first electrode 117 will not have a break at the opening of the second via 114a.

[0084] Please refer to Figure 10 , Figure 10 which is a schematic flow chart of a manufacturing method of a driving substrate disclosed in the fourth embodiment of the present application. The manufacturing method of the driving substrate is used to form the driving substrate 11 of the third embodiment. For the description of the same parts between the structure involved in the manufacturing method of the driving substrate and the structure of the driving substrate 11, please refer to the relevant description of the driving substrate 11 in the above embodiment, which will not be repeated here. Please refer to Figure 10 , the manufacturing method of the driving substrate 11 specifically includes the following steps.

[0085] Step S10: Provide a substrate 111, and sequentially form a first insulating layer 112, a wiring 113, a second insulating layer 114, and a planarizing layer 115 on the substrate 111. The first insulating layer 112 is located on a surface of the substrate 111, the second insulating layer 114 covers the wiring 113 to a surface of the first insulating layer 112 facing away from the substrate 111, and the planarizing layer 115 is located on a surface of the second insulating layer 114 facing away from the first insulating layer 112.

[0086] Specifically, please refer to Figure 11 , Figure 11 which is Figure 10 a schematic structural diagram corresponding to the formed step S10 as shown. Provide a substrate 111, and form a first insulating layer 112 on one surface of the substrate 111. Through deposition, exposure, etching and stripping processes, form a trace 113 on the surface of the first insulating layer 112 facing away from the substrate 111. Through chemical vapor deposition process, form a second insulating layer 114 on the surface of the first insulating layer 112 facing away from the substrate 111, and the second insulating layer 114 covers the trace 113. Through deposition, exposure and drying processes, form a planarization layer 115 on the surface of the second insulating layer 114 facing away from the first insulating layer 112.

[0087] Step S20: Open a first via 115a in the planarization layer 115 and a second via 114a in the second insulating layer 114. The first via 115a communicates with the second via 114a, and part of the trace 113 is exposed from the second via 114a.

[0088] Please refer to Figure 12 , Figure 12 which is Figure 10 a schematic structural diagram corresponding to the formed step S20 as shown. Open a first via 115a in the planarization layer 115 and a second via 114a in the second insulating layer 114 through an etching process. Wherein, the first via 115a communicates with the second via 114a, and part of the trace 113 is exposed from the second via 114a.

[0089] Step S30: Form a second electrode 118 in the first via 115a and on the surface of the planarization layer 115 facing away from the second insulating layer 114.

[0090] Please refer to Figure 13 , Figure 13 which is Figure 10 a schematic structural diagram corresponding to the formed step S30 as shown. Form a second electrode 118 in the first via 115a and on the surface of the planarization layer 115 facing away from the second insulating layer 114 through deposition, exposure, etching and stripping processes.

[0091] Step S40: Form a third insulating layer 116 in the first via 115a and the second via 114a. Wherein, part of the surface of the trace 113 facing away from the first insulating layer 112 is exposed from the third insulating layer 116.

[0092] Please refer to Figure 14 , Figure 14 which is Figure 10The structural schematic diagram corresponding to the formed step S40 is shown. The third insulating layer 116 is formed in the first via 115a, the second via 114a, on the surface of the planar layer 115 facing away from the second insulating layer 114, and on the surface of the second electrode 118 facing away from the planar layer 115 through deposition, exposure, etching, and stripping processes. Among them, a partial surface of the trace 113 facing away from the first insulating layer 112 exposes the third insulating layer 116, that is, the third insulating layer 116 does not completely cover the trace 113.

[0093] Step S50: Form a first electrode 117 in the first via 115a and the second via 114a. The first electrode 117 is respectively connected to the second electrode 118 and the trace 113.

[0094] Please refer to Figure 5 , the first electrode 117 is formed in the first via 115a, the second via 114a, and on the surface of the third insulating layer 116 facing away from the planar layer 115 through deposition, exposure, etching, and stripping processes. Among them, the first electrode 117 is connected to the second electrode 118 in the first via 115a, and the first electrode 117 is connected to the trace 113 at the second via 114a.

[0095] It can be understood that by forming the first via 115a and the second via 114a in the same process, one etching process is saved, and the cost is reduced. Moreover, by connecting the second electrode 118 and the trace 113 through the first electrode 117, there is no need to open an additional hole and set a conductive element to connect the second electrode 118 and the trace 113, saving the space required for the hole and improving the margin of design and process.

[0096] Please refer to Figure 15 , Figure 15 is Figure 10 a specific process schematic diagram of the manufacturing method of the driving substrate shown, Figure 15 the process schematic diagram shown is used to form Figure 9 the driving substrate shown. Please refer to Figure 15 , the manufacturing method of the driving substrate may specifically include the following steps.

[0097] Step S110: Provide a substrate 111, and sequentially form a gate b1, a connection electrode 121, a first insulating layer 112, an active layer b2, a source electrode b3, a drain electrode b4, a trace 113, a second insulating layer 114, and a planarization layer 115 on the substrate 111. Among them, the first insulating layer 112 covers the gate b1 and the connection electrode 121 to the substrate 111, the second insulating layer 114 covers the source layer b2, the source electrode b3, the drain electrode b4, and the trace 113 to the surface of the first insulating layer 112 facing away from the substrate 111, and the planarization layer 115 is disposed on the surface of the second insulating layer 114 facing away from the first insulating layer 112.

[0098] Specifically, please refer to Figure 16 , Figure 16 is Figure 15 the schematic structural diagram formed corresponding to step S110 shown in. Provide a substrate 111, and form a gate b1 and a connection electrode 121 on a surface of the substrate 111. Form a first insulating layer 112 on the substrate 111, and the first insulating layer 112 covers the gate b1 and the connection electrode 121. Form an active layer b2 on the surface of the first insulating layer 112 facing away from the gate b1. Form a source electrode b3 and a drain electrode b4 on the surface of the first insulating layer 112 facing away from the gate b1 and form a trace 113 on the surface of the first insulating layer 112 facing away from the connection electrode 121. Form a second insulating layer 114 on the first insulating layer 112, and the second insulating layer 114 covers the active layer b2, the source electrode b3, the drain electrode b4, and the trace 113. Form a planarization layer 115 on the surface of the second insulating layer 114 facing away from the first insulating layer 112.

[0099] Step S120: Open a first via 115a and a third via 115b in the planarization layer 115 and open a second via 114a and a fourth via 114b in the second insulating layer 114. The first via 115a communicates with the second via 114a, and a part of the trace 113 is exposed from the second via 114a. The third via 115b communicates with the fourth via 114b, and a part of the source electrode b3 is exposed from the fourth via 114b.

[0100] Specifically, please refer to Figure 17 , Figure 17 is Figure 15 the schematic structural diagram formed corresponding to step S120 shown in. Open the first via 115a and the third via 115b in the planarization layer 115 by an etching process, and open the second via 114a and the fourth via 114b in the second insulating layer 114 by an etching process. Among them, the first via 115a communicates with the second via 114a, and a part of the trace 113 is exposed from the second via 114a. The third via 115b communicates with the fourth via 114b, and a part of the source electrode b3 is exposed from the fourth via 114b.

[0101] Step S130: Form a second electrode 118 in the first via 115a and on a part of the surface of the planarization layer 115 facing away from the second insulating layer 114.

[0102] Specifically, please refer to Figure 18 , Figure 18 which is Figure 15 a schematic diagram of the structure formed corresponding to step S130 shown. The second electrode 118 is formed in the first via 115a and on a part of the surface of the planarization layer 115 facing away from the second insulating layer 114 through deposition, exposure, etching, and stripping processes.

[0103] Step S140: Form a third insulating layer 116 in the first via 115a, the second via 114a, the third via 115b, and the fourth via 114b, wherein parts of the surfaces of the trace 113 and the source b3 facing away from the first insulating layer 112 are exposed from the third insulating layer 116.

[0104] Please refer to Figure 19 , Figure 19 which is Figure 15 a schematic diagram of the structure formed corresponding to step S140 shown. The third insulating layer 116 is formed in the first via 115a, the second via 114a, the third via 115b, the fourth via 114b, on the surface of the second electrode 118 facing away from the planarization layer 115, and on the planarization layer 115 facing away from the second insulating layer 114 through deposition, exposure, etching, and stripping processes. Parts of the surfaces of the trace 113 and the source b3 facing away from the first insulating layer 112 are exposed from the third insulating layer 116, that is, the third insulating layer 116 does not completely cover the trace 113 and the source b3.

[0105] Step S150: Form a first electrode 117 in the first via 115a and the second via 114a, and form a third electrode 123 in the third via 115b and the fourth via 114b. The first electrode 117 is connected to the second electrode 118 and the trace 113 respectively, and the third electrode 123 is connected to the source b3.

[0106] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0107] It should be understood that the application of this application is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of this application. Those of ordinary skill in the art can understand all or part of the processes of implementing the above embodiments, and the equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. A driving substrate, comprising a plurality of touch control areas arranged in an array, characterized in that: The driving substrate further includes a first insulating layer, a plurality of routing wires, a second insulating layer, a flat layer, a plurality of first electrodes, and a plurality of second electrodes, wherein the second insulating layer covers the plurality of routing wires to the first insulating layer, the flat layer is disposed on a surface of the second insulating layer facing away from the first insulating layer, the flat layer is provided with a plurality of first via holes, the second insulating layer is provided with a plurality of second via holes, and one of the second via holes is connected to one of the first via holes, a portion of the routing wires is exposed from the second via holes, a portion of the first electrodes is disposed in the first via holes and the second via holes, and the first electrodes are connected to the routing wires; A second electrode is located in a touch area, the second electrode includes an electrode body and multiple sub-electrodes, the multiple sub-electrodes are connected to one side of the electrode body, and two adjacent sub-electrodes are spaced apart to form at least one gap, the sub-electrode and part of the electrode body are located in the first via hole, part of the first electrode is located in the gap, and the first electrode is respectively connected to the electrode body and the multiple sub-electrodes, so that the second electrode is electrically connected to the wiring, the first electrode is used to send a touch signal through the wiring, and the second electrode is used to receive a display signal through the wiring.

2. The driving substrate according to claim 1, wherein: The width of the gap is the distance between two adjacent sub-electrodes, which is 1 um to 3 um.

3. The driving substrate according to claim 1, wherein: The length of the gap is the length of the sub-electrode, which is 2um to 4um.

4. The driving substrate according to claim 1, wherein: The electrode body includes at least one connection surface, the connection surface faces the gap, the connection surface is respectively connected to the sub-electrodes, the connection surface is an inclined surface, and the connection surface faces the first via hole.

5. The driving substrate according to claim 4, characterized in that: The first via hole includes a first side wall and a bottom wall, the first side wall is connected to the bottom wall, and the second via hole includes a second side wall, the second side wall is respectively connected to the first side wall and the bottom wall; A plurality of the sub-electrodes are disposed on the bottom wall, a portion of the electrode body is disposed on the first side wall, and a portion of the first electrode is disposed on the second side wall.

6. The driving substrate according to claim 5, characterized in that: The inclination angle of the connecting surface relative to the bottom wall is 50 degrees to 80 degrees.

7. The driving substrate according to claim 5, characterized in that: The driving substrate further includes a third insulating layer, which is disposed on the first side wall, the second side wall, a surface of the second electrode facing away from the planar layer, and a surface of the planar layer facing away from the second insulating layer.

8. A method for manufacturing a driving substrate, characterized in that: Used to form the driving substrate according to any one of claims 1 to 7, the manufacturing method of the driving substrate comprising: A wiring, a second insulation layer and a flat layer are sequentially formed on the first insulation layer, wherein the second insulation layer covers the wiring to a surface of the first insulation layer, and the flat layer is located on a surface of the second insulation layer facing away from the first insulation layer; A first via hole is formed in the planar layer and a second via hole is formed in the second insulating layer, wherein the first via hole is connected to the second via hole, and a portion of the wiring is exposed through the second via hole; forming a second electrode in the first via hole and on a surface of the planar layer facing away from the second insulating layer; forming a third insulating layer in the first via hole and the second via hole, wherein a portion of the surface of the trace facing away from the first insulating layer exposes the third insulating layer; A first electrode is formed in the first via hole and the second via hole, and the first electrode is connected to the second electrode and the wiring respectively.

9. A display panel, characterized in that: It comprises a touch control unit and a driving substrate as claimed in any one of claims 1 to 7, wherein each first electrode of the driving substrate is electrically connected to the touch control unit, and the first electrode is used to send a touch signal to the touch control unit through a wiring.

10. A display device, characterized in that: It comprises a power board and the display panel as claimed in claim 9, wherein the power board is electrically connected to the display panel and is used to supply power to the display panel.

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