Silicon-based barrier impurity band detector and preparation method thereof
By using a chemical vapor deposition process to grow a highly doped absorbing layer and selective ion implantation in a silicon-based barrier impurity band detector, the problems of high dark current and low response rate in the prior art are solved, and the stability and reliability of the device are improved.
Patent Information
- Application Number
- CN202510100954.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-27
AI Technical Summary
During the preparation process, existing silicon-based barrier impurity tape detectors have problems such as high dark current, low response rate and difficult bottom filling process, which affects their stability and reliability.
The highly doped thick absorbing layer is epitaxially grown using a chemical vapor deposition process, and dark current is reduced by selective ion implantation to avoid inductively coupled plasma etching to form bare sidewalls.
Improves the response rate and stability of the device, reduces dark current, enhances the sensitivity and reliability of the detector, while simplifying the preparation process and reducing costs and time.
Smart Images
Figure CN120051020A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technology of infrared photodetectors, and specifically refers to a silicon-based blocked impurity band detector and a preparation method thereof. Background Art
[0002] The blocked impurity band detector is developed from the impurity band photoconductive detector, mainly composed of an absorption layer, a blocking layer and an electrode contact layer. It can detect in the wavelength range of 5 - 300um and belongs to the family of mid-infrared and far-infrared detectors. The highly doped absorption layer of the device improves the absorption efficiency, and the high-purity blocking layer is used to suppress the dark current of the device. Because of its characteristics such as high sensitivity, wide detection band, fast response speed, and strong anti-irradiation performance, it is widely used in various space-based and ground-based detection platforms.
[0003] Currently, the preparation of the mesa-type silicon-based blocked impurity band detector mainly adopts processes such as lithography, inductively coupled plasma selective etching and glue removal cleaning, etc., so as to form a physically isolated focal plane array between the photosensitive elements. After the device is etched, the sidewalls of the mesa become new surfaces exposed to the environment, introducing surface states and increasing the dark current. At the same time, there are a large number of micro-channels in the device, which increases the difficulty of the bottom filling process. During the filling process, the glue is affected by the grooves, resulting in holes, which will reduce the reliability of the detector or even cause it to fail. The planar silicon-based blocked impurity band detector usually forms an absorption layer by ion implantation on a high-purity silicon substrate, and the high-purity silicon substrate serves as the blocking layer. The dark current of the device is relatively low, but the ion implantation is usually less than 2um in thickness, resulting in a relatively thin absorption layer, less absorption of incident photons by the device, and a relatively low responsivity. Therefore, it is necessary to study and solve the deficiencies existing in the silicon-based blocked impurity band detector and improve the comprehensive performance of the device. Summary of the Invention
[0004] Aiming at the defects in the prior art, the purpose of the present invention is to provide a silicon-based blocked impurity band detector and a preparation method thereof. The chemical vapor deposition process is used to epitaxially grow a highly doped thick absorption layer, which enhances the absorption of incident photons and improves the responsivity of the device; at the same time, selective ion implantation avoids the formation of exposed sidewalls by inductively coupled plasma etching of the photosensitive elements, reduces the dark current of the device, and improves the stability and sensitivity of the detector.
[0005] A silicon-based blocked impurity band detector provided by the present invention includes: a high-resistance silicon substrate, a negative electrode contact layer, a silicon-doped phosphorus absorption layer, a high-purity silicon blocking layer, a positive electrode contact layer, a V-shaped negative electrode, a positive electrode, a UBM electrode, an indium column, and a silicon readout circuit;
[0006] A negative electrode contact layer, a phosphorus-doped silicon absorption layer, and a high-purity silicon blocking layer are sequentially grown on the surface of the high-resistance silicon substrate; a positive electrode contact layer is formed on the high-purity silicon blocking layer; a positive electrode is evaporated on the positive electrode contact layer, and a V-shaped negative electrode is evaporated on the negative electrode contact layer; a UBM electrode is evaporated on the surfaces of the positive electrode and the negative electrode, and an indium pillar array is grown on the UBM electrode; the other end of the indium pillar is flip-chip interconnected with the silicon readout circuit.
[0007] A method for preparing a silicon-based blocked impurity band detector according to the present invention includes the following steps:
[0008] Step S1: On the surface of the high-resistance silicon substrate, a negative electrode contact layer, a phosphorus-doped silicon absorption layer, and a high-purity silicon blocking layer are epitaxially grown by chemical vapor deposition.
[0009] Step S2: On the high-purity silicon blocking layer, a positive electrode contact layer is formed by selective ion implantation and rapid annealing processes on the photosensitive elements of the chip, and a V-groove is prepared by chemical etching to expose the negative electrode contact layer.
[0010] Step S3: A positive electrode is evaporated on the positive electrode contact layer, and a V-shaped negative electrode is evaporated on the negative electrode contact layer. The positive electrode and the negative electrode are both ohmic contacts through photolithography, electron beam evaporation, and annealing processes.
[0011] Step S4: A UBM electrode is evaporated on the positive electrode and the negative electrode through photolithography and electron beam evaporation processes.
[0012] Step S5: On the UBM electrode, an indium pillar array is grown at corresponding positions through photolithography and thermal evaporation processes.
[0013] Step S6: The back surface of the high-resistance silicon substrate is thinned and polished and separated into individual single chips by dicing. The other end of the indium pillar array is flip-chip interconnected with the silicon readout circuit.
[0014] Preferably, the high-resistance silicon substrate is a silicon wafer with a thickness of 700 μm, a resistivity greater than 20000 Ω·cm, and a clean and flat surface.
[0015] Preferably, the step S2 includes:
[0016] Step S2.1: Spin-coat a photoresist on the high-purity silicon blocking layer, expose and develop it, and remove the residual resist by oxygen plasma; etch a groove by reactive ion etching, clean and remove the residual resist to form a photolithographic alignment mark.
[0017] Step S2.2: Grow a silicon dioxide film by plasma enhanced chemical vapor deposition as an ion implantation mask; spin-coat photoresist on the silicon dioxide mask, expose and develop it, and remove the residual photoresist by oxygen plasma. All areas except the photosensitive elements are covered with photoresist; perform an ion implantation process to implant phosphorus ions into the photosensitive element area. Use acetone and isopropyl alcohol to ultrasonically clean the photoresist on the chip surface after ion implantation respectively, and use rapid thermal annealing at 950 °C for 10 s to repair the lattice damage to form a positive electrode contact layer;
[0018] Step S2.3: Grow a silicon nitride film by plasma enhanced chemical vapor deposition as a mask. Spin-coat photoresist on the silicon nitride surface mask, expose and develop it, and remove the residual photoresist by oxygen plasma. Use reactive ion etching to remove the corresponding areas of silicon nitride and silicon dioxide; after etching, perform an organic cleaning to remove the residual photoresist; prepare a V-groove by chemical wet etching with an 85 °C potassium hydroxide solution to expose the negative electrode contact layer; use hydrofluoric acid to remove the remaining silicon nitride and silicon dioxide masks.
[0019] Preferably, step S3 includes: coating photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing it, and removing the residual photoresist by oxygen plasma; performing an electron beam evaporation process to sequentially deposit titanium, aluminum, nickel, and gold from bottom to top at the electrode holes, with thicknesses of 20 nm, 120 nm, 20 nm, and 100 nm respectively; soaking and peeling off with an organic solvent to form a metal electrode.
[0020] Preferably, step S4 includes: coating photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing it, and removing the residual photoresist by oxygen plasma; performing an electron beam evaporation process to sequentially deposit metal titanium and gold from bottom to top on the electrode, with thicknesses of 20 nm and 100 nm respectively; soaking and peeling off with an organic solvent to form a UBM electrode.
[0021] Preferably, step S5 includes: coating photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing it, and removing the residual photoresist by oxygen plasma; growing indium pillars on the UBM electrode by a thermal evaporation process; soaking and peeling off with an organic solvent to form a 6-um high indium pillar array.
[0022] Preferably, step S6 includes: spin-coating photoresist on the surface of the high-purity silicon barrier layer as a protection, thinning and polishing the back of the high-resistance silicon substrate using a thinning machine and a polishing machine; attaching the high-resistance silicon substrate to a blue film, using a dicing machine to divide it into individual single chips, cleaning the single chips and the readout circuit using acetone and isopropyl alcohol solutions, and using a flip bonder to hybrid interconnect the two by thermal pressing.
[0023] Preferably, the size of the photosensitive element is 30*30 um, the center distance is 45 um, and the pixel array scale is a 128*128 back-illuminated device.
[0024] Preferably, in the ion implantation process of the photosensitive element, the implanted ion is a phosphorus ion, and the implantation dose is 2×10 14 cm -2 . After implantation, rapid thermal annealing at 950 °C is used to repair the lattice damage.
[0025] The present invention adopts the above technical solutions and has the following advantages compared with the prior art:
[0026] 1. Ion implantation is performed on each photosensitive element of the silicon-based blocked impurity band detector, avoiding the formation of exposed sidewalls during inductively coupled plasma etching, reducing the dark current of the device, and improving the stability and sensitivity of the detector;
[0027] 2. Due to the absence of the influence of grooves in the device structure, the glue can flow better during the bottom filling of the device, reducing the generation of holes during the next bottom filling process and improving the reliability of the device;
[0028] 3. In the present invention, the silicon-based blocked impurity band detector adopts a chemical vapor deposition process to epitaxially grow a highly doped thick absorption layer, enhancing the absorption of incident photons and improving the responsivity of the device;
[0029] 4. The process steps such as lithography, inductively coupled plasma etching, and resist stripping and cleaning are reduced, improving the efficiency and saving the preparation cost and time of the device. Description of the Drawings
[0030] By reading the following detailed description of the non-limiting embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present invention will become more apparent:
[0031] Figure 1 It is a schematic diagram of the material structure of a silicon-based blocked impurity band detector related to the present invention;
[0032] Figure 2 It is a flowchart of a preparation method of a silicon-based blocked impurity band detector proposed by the present invention;
[0033] Figure 3 It is a flowchart of a preparation process of a silicon-based blocked impurity band detector proposed by the present invention;
[0034] Figure 4 It is a schematic diagram of the structure of a silicon-based blocked impurity band detector related to the present invention;
[0035] Description of the reference numerals:
[0036] Detailed Embodiments
[0037] The present invention will be described in detail below in conjunction with a specific embodiment where the photosensitive element array is a 128*128 silicon-based blocked impurity band detector. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can be made. These all fall within the protection scope of the present invention.
[0038] As Figures 1 to 4 shown, in this embodiment, the silicon-based blocked impurity band detector consists of a high-resistivity silicon substrate 1, a negative electrode contact layer 2, a silicon phosphorus-doped absorption layer 3, a high-purity silicon blocking layer 4; it also includes a V-shaped negative electrode 5, a positive electrode contact layer 6, a positive electrode 7, a UBM electrode 8, an indium pillar 9, and a silicon readout circuit 10.
[0039] In this embodiment, the processing technology of each layer structure of the silicon-based blocked impurity band detector includes: on the surface of the high-resistivity silicon substrate 1, the negative electrode contact layer 2, the silicon phosphorus-doped absorption layer 3, and the high-purity silicon blocking layer 4 are epitaxially grown by chemical vapor deposition technology; on the high-purity silicon blocking layer 4, the positive electrode contact layer 6 is formed by selective ion implantation and rapid annealing technology for the photosensitive elements of the chip, and the V-shaped groove is prepared by chemical wet etching to expose the negative electrode contact layer 2; the positive electrode 7 and the V-shaped negative electrode 5 are grown by photolithography, electron beam evaporation, and annealing technology, both of which are ohmic contacts; the UBM electrode 8 is grown by photolithography and electron beam evaporation technology; on the UBM electrode 8, an indium pillar 9 array is grown at the corresponding position by photolithography and thermal evaporation technology; on the chip, the other end of the indium pillar 9 is interconnected with the silicon readout circuit 10 by flip-chip bonding to form the silicon-based blocked impurity band detector.
[0040] A silicon-based blocked impurity band detector and its preparation method provided by the present invention include the following steps:
[0041] S1, Select a high-resistivity silicon wafer: The silicon-based blocked impurity band detector in the present invention is a back-illuminated type. A silicon wafer with a thickness of about 700 μm, a resistivity greater than 20000 Ω·cm, and a clean and flat surface is selected as the substrate for material growth.
[0042] S2, Device material growth: On the surface of the high-resistivity silicon substrate 1, a low-resistivity electrode contact layer 2 doped with silicon phosphorus N-type, a high-doped absorption layer 3 with a thickness of 35 μm, and a high-purity silicon blocking layer 4 are epitaxially grown by chemical vapor deposition technology.
[0043] S3, Prepare alignment marks: AZ5214 positive photoresist is spin-coated on the surface of the high-purity blocking layer 4 with a thickness of 1.6 μm, exposed and developed, and the residual photoresist is removed by oxygen plasma; a reaction ion etching (RIE) with a depth of about 200 nm is used, and the residual photoresist is removed by cleaning to form a photolithographic alignment mark.
[0044] S4, Prepare the positive electrode contact layer 6: Grow a silicon dioxide thin film with a thickness of 20 nm as an ion implantation mask by plasma enhanced chemical vapor deposition (PECVD); Spin-coat AZ5214 positive photoresist on the silicon dioxide mask with a thickness of 1.6 μm, expose and develop it, and remove the residual photoresist through oxygen plasma. All areas except the photosensitive elements are covered with photoresist; Ion implantation process, implant phosphorus ions onto the photosensitive element area, and the implantation dose is 2×10 14 cm -2 。
[0045] S5, Rapid annealing: Use acetone and isopropyl alcohol to ultrasonically clean and remove the photoresist on the chip surface after ion implantation, and perform rapid thermal annealing at 950 °C for 10 s to repair lattice damage.
[0046] S6, Prepare the V-groove: Grow a silicon nitride thin film with a thickness of 300 nm as a mask again by plasma enhanced chemical vapor deposition (PECVD); Spin-coat AZ5214 positive photoresist on the silicon nitride surface mask with a thickness of 1.6 μm, expose and develop it, and remove the residual photoresist through oxygen plasma; Use reactive ion etching (RIE) to remove the silicon nitride and silicon dioxide in the corresponding areas; After etching, perform organic cleaning to remove the residual photoresist; Prepare the V-groove by chemical wet etching with a potassium hydroxide solution at 85 °C to expose the negative electrode contact layer; Use hydrofluoric acid to remove the remaining silicon nitride and silicon dioxide masks.
[0047] S7, Evaporate the electrodes: Use the spraying method to coat a 3-μm-thick ROL7133 negative photoresist on the surface of the high-purity barrier layer 4, expose and develop it, and remove the residual photoresist through oxygen plasma; Use electron beam evaporation process to evaporate titanium, aluminum, nickel, and gold from bottom to top at the electrode holes, with thicknesses of 20 nm, 120 nm, 20 nm, and 100 nm respectively; Immerse and strip with organic solvents to form the positive electrode 7 and the V-shaped negative electrode 5.
[0048] S8, Thermal annealing: Perform annealing using an annealing furnace at a temperature of 450 °C for 30 min in a nitrogen atmosphere to form a good ohmic contact with a resistance of about 12 Ω.
[0049] S9, Evaporate the UBM electrode 8: Use the spraying method to coat a 3-μm-thick ROL7133 negative photoresist on the surface of the high-purity barrier layer 4, expose and develop it, and remove the residual photoresist through oxygen plasma; Use electron beam evaporation process to evaporate the metals titanium and gold from bottom to top on the positive electrode 7 and the V-shaped negative electrode 5, with thicknesses of 20 nm and 100 nm respectively; Immerse and strip with organic solvents to form the UBM electrode 8.
[0050] S10, Growing indium pillars 9: Coating a 10-um-thick SPR220 positive photoresist on the surface of the barrier layer 4 by spraying, exposing and developing, and removing the residual photoresist by oxygen plasma; Growing 6-um-high indium pillars on the UBM electrode 8 through a thermal evaporation process; Soaking and cleaning with organic solvents for stripping to form an indium pillar 9 array.
[0051] S11, Thinning and polishing: Spin-coating a 10-um-thick AZ4620 positive photoresist on the surface of the high-purity silicon barrier layer 4 as protection; Thinning and polishing the back surface of the high-resistivity silicon wafer to a thickness of 500 um using a thinning machine and a polishing machine.
[0052] S12, Dicing: Attaching the high-resistivity silicon substrate to the blue film, and using a dicing machine to divide it into individual single chips to prepare for the next flip-chip bonding.
[0053] S13, Flip-chip bonding: Cleaning the single chip and the readout circuit using acetone and isopropyl alcohol solutions, and using a flip-chip bonder to thermally press the individual single chips and the silicon readout circuit 10 for hybrid interconnection to obtain a silicon-based barrier impurity band detector.
[0054] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.
[0055] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Without conflict, the embodiments and features in the embodiments of the present application can be arbitrarily combined with each other.
Claims
1. A silicon-based barrier impurity band detector, characterized in that: The silicon-based barrier impurity band detector comprises: a high-resistance silicon substrate, a negative electrode contact layer, a silicon-doped phosphorus absorption layer, a high-purity silicon barrier layer, a positive electrode contact layer, a V-shaped negative electrode, a positive electrode, a bump metallization (UBM) electrode, an indium column, and a silicon readout circuit; A negative electrode contact layer, a silicon-doped phosphorus absorption layer and a high-purity silicon barrier layer are sequentially grown on the surface of the high-resistance silicon substrate; a positive electrode contact layer is formed on the high-purity silicon barrier layer; a positive electrode is evaporated on the positive electrode contact layer, and a V-shaped negative electrode is evaporated on the negative electrode contact layer; UBM electrodes are evaporated on the surfaces of the positive electrode and the negative electrode, and an indium column array is grown on the UBM electrodes; the other end of the indium column is interconnected with a silicon readout circuit by reverse welding.
2. A method for preparing a silicon-based blocking impurity band detector, characterized in that: The following steps are involved: Step S1: epitaxially growing a negative electrode contact layer, a silicon-doped phosphorus absorption layer and a high-purity silicon barrier layer on the surface of a high-resistance silicon substrate by a chemical vapor deposition process; Step S2: on the high-purity silicon barrier layer, a positive electrode contact layer is formed by selective ion implantation and rapid annealing of the chip photosensitive element, and a V-shaped groove is prepared by etching to expose the negative electrode contact layer; Step S3: evaporating a positive electrode on the positive electrode contact layer, and evaporating a V-shaped negative electrode on the negative electrode contact layer, wherein the positive electrode and the negative electrode are both in ohmic contact through photolithography, electron beam evaporation and annealing processes; Step S4: evaporating UBM electrodes on the positive electrode and the negative electrode by photolithography and electron beam evaporation process; Step S5: growing an indium column array at a corresponding position on the UBM electrode by photolithography and thermal evaporation process; Step S6: The back side of the high-resistance silicon substrate is thinned and polished and separated into individual single chips by dicing. The other end of the indium column array is reversely soldered to the silicon readout circuit for interconnection.
3. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The high-resistance silicon substrate is a silicon wafer with a thickness of 700um, a resistivity greater than 20000Ω·cm, and a clean and flat surface.
4. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The step S2 comprises: Step S2.1: Spin-coating photoresist on the high-purity silicon barrier layer, exposing and developing, and removing residual photoresist by oxygen plasma; using reactive ion etching to etch grooves, cleaning to remove residual photoresist, and forming photolithography alignment marks; Step S2.2: growing a silicon dioxide film as an ion implantation mask by plasma enhanced chemical vapor deposition; spin coating photoresist on the silicon dioxide mask, exposing and developing, and removing residual glue by oxygen plasma, and covering the rest of the area except the photosensitive element with photoresist; ion implantation process, implanting phosphorus ions into the photosensitive element area, using acetone and isopropanol to ultrasonically clean and remove the photoresist on the chip surface after ion implantation, and using 950°C rapid thermal annealing for 10s to repair lattice damage to form a positive electrode contact layer; Step S2.3: Grow a silicon nitride film as a mask by plasma enhanced chemical vapor deposition, spin coat photoresist on the silicon nitride surface mask, expose and develop, remove residual glue by oxygen plasma, and use reactive ion etching to remove silicon nitride and silicon oxide in the corresponding area; after etching, use organic cleaning to remove residual photoresist; prepare a V-shaped groove by chemical wet etching with 85°C potassium hydroxide solution to expose the negative electrode contact layer; use hydrofluoric acid to remove the remaining silicon nitride and silicon oxide masks.
5. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The step S3 comprises: coating a photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing, and removing residual photoresist by oxygen plasma; using an electron beam evaporation process to sequentially deposit titanium, aluminum, nickel, and gold from bottom to top at the electrode hole, with thicknesses of 20 nm, 120 nm, 20 nm, and 100 nm, respectively; and stripping by soaking in an organic solvent to form a metal electrode.
6. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The step S4 includes: coating photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing, and removing residual photoresist by oxygen plasma; depositing metal titanium and gold on the electrode from bottom to top by electron beam evaporation process, with thickness of 20nm and 100nm respectively; and immersing and peeling by organic solvent to form UBM electrode.
7. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The step S5 comprises: coating photoresist on the surface of the high-purity silicon barrier layer by spraying, exposing and developing, and removing residual photoresist by oxygen plasma; growing indium pillars on the UBM electrodes by thermal evaporation; and soaking and stripping by organic solvent to form an indium pillar array with a height of 6 μm.
8. The method for preparing a silicon-based blocking impurity band detector according to claim 2, characterized in that: The step S6 comprises: spin coating photoresist on the surface of the high-purity silicon barrier layer as protection, thinning and polishing the back of the high-resistance silicon substrate by using a thinning machine and a polishing machine; attaching the high-resistance silicon substrate to the blue film, dividing it into independent single chips by using a dicing machine, cleaning the single chip and the readout circuit by using acetone and isopropanol solution, and interconnecting the two by hot pressing using a reverse soldering machine.
9. The method for preparing a silicon-based blocking impurity band detector according to claim 4, characterized in that: The photosensitive element has a size of 30*30um, a center distance of 45um, and a pixel array scale of 128*128 back-incident devices.
10. The method for preparing a silicon-based blocking impurity band detector according to claim 4, characterized in that: The ion implantation process of the photosensitive element is that the implanted ions are phosphorus ions and the implantation dose is 2×10 14 cm -2 After implantation, rapid thermal annealing at 950°C is used to repair lattice damage.